1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_APIC_APIC_H 27 #define _SYS_APIC_APIC_H 28 29 #include <sys/psm_types.h> 30 #include <sys/avintr.h> 31 #include <sys/pci.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #include <sys/psm_common.h> 38 39 #define APIC_PCPLUSMP_NAME "pcplusmp" 40 41 #define APIC_IO_ADDR 0xfec00000 42 #define APIC_LOCAL_ADDR 0xfee00000 43 #define APIC_IO_MEMLEN 0xf 44 #define APIC_LOCAL_MEMLEN 0xfffff 45 46 /* Local Unit ID register */ 47 #define APIC_LID_REG 0x8 48 49 /* I/o Unit Version Register */ 50 #define APIC_VERS_REG 0xc 51 52 /* Task Priority register */ 53 #define APIC_TASK_REG 0x20 54 55 /* EOI register */ 56 #define APIC_EOI_REG 0x2c 57 58 /* Remote Read register */ 59 #define APIC_REMOTE_READ 0x30 60 61 /* Logical Destination register */ 62 #define APIC_DEST_REG 0x34 63 64 /* Destination Format rgister */ 65 #define APIC_FORMAT_REG 0x38 66 67 /* Spurious Interrupt Vector register */ 68 #define APIC_SPUR_INT_REG 0x3c 69 70 /* Error Status Register */ 71 #define APIC_ERROR_STATUS 0xa0 72 73 /* Interrupt Command registers */ 74 #define APIC_INT_CMD1 0xc0 75 #define APIC_INT_CMD2 0xc4 76 77 /* Timer Vector Table register */ 78 #define APIC_LOCAL_TIMER 0xc8 79 80 /* Local Interrupt Vector registers */ 81 #define APIC_CMCI_VECT 0xbc 82 #define APIC_THERM_VECT 0xcc 83 #define APIC_PCINT_VECT 0xd0 84 #define APIC_INT_VECT0 0xd4 85 #define APIC_INT_VECT1 0xd8 86 #define APIC_ERR_VECT 0xdc 87 88 /* IPL for performance counter interrupts */ 89 #define APIC_PCINT_IPL 0xe 90 #define APIC_LVT_MASK 0x10000 /* Mask bit (16) in LVT */ 91 92 /* Initial Count register */ 93 #define APIC_INIT_COUNT 0xe0 94 95 /* Current Count Register */ 96 #define APIC_CURR_COUNT 0xe4 97 #define APIC_CURR_ADD 0x39 /* used for remote read command */ 98 #define CURR_COUNT_OFFSET (sizeof (int32_t) * APIC_CURR_COUNT) 99 100 /* Divider Configuration Register */ 101 #define APIC_DIVIDE_REG 0xf8 102 103 /* Various mode for local APIC. Modes are mutually exclusive */ 104 #define APIC_IS_DISABLED 0x0 105 #define APIC_MODE_NOTSET 0x1 106 #define LOCAL_APIC 0x2 107 #define LOCAL_X2APIC 0x3 108 109 /* x2APIC SELF IPI Reguster */ 110 #define X2APIC_SELF_IPI 0x100 111 112 /* General x2APIC constants used at various places */ 113 #define APIC_SVR 12 114 #define APIC_DIRECTED_EOI 24 115 116 /* IRR register */ 117 #define APIC_IRR_REG 0x80 118 119 /* ISR register */ 120 #define APIC_ISR_REG 0x40 121 122 #define APIC_IO_REG 0x0 123 #define APIC_IO_DATA 0x4 124 #define APIC_IO_EOI 0x10 125 126 /* Bit offset of APIC ID in LID_REG, INT_CMD and in DEST_REG */ 127 #define APIC_ID_BIT_OFFSET 24 128 #define APIC_ICR_ID_BIT_OFFSET 24 129 #define APIC_LDR_ID_BIT_OFFSET 24 130 131 /* 132 * Choose between flat and clustered models by writing the following to the 133 * FORMAT_REG. 82489 DX documentation seemed to suggest that writing 0 will 134 * disable logical destination mode. 135 * Does not seem to be in the docs for local APICs on the processors. 136 */ 137 #define APIC_FLAT_MODEL 0xFFFFFFFFUL 138 #define APIC_CLUSTER_MODEL 0x0FFFFFFF 139 140 /* 141 * The commands which follow are window selectors written to APIC_IO_REG 142 * before data can be read/written from/to APIC_IO_DATA 143 */ 144 145 #define APIC_ID_CMD 0x0 146 #define APIC_VERS_CMD 0x1 147 #define APIC_RDT_CMD 0x10 148 #define APIC_RDT_CMD2 0x11 149 150 #define APIC_INTEGRATED_VERS 0x10 /* 0x10 & above indicates integrated */ 151 #define IOAPIC_VER_82489DX 0x01 /* Version ID: 82489DX External APIC */ 152 153 #define APIC_INT_SPURIOUS -1 154 155 #define APIC_IMCR_P1 0x22 /* int mode conf register port 1 */ 156 #define APIC_IMCR_P2 0x23 /* int mode conf register port 2 */ 157 #define APIC_IMCR_SELECT 0x70 /* select imcr by writing into P1 */ 158 #define APIC_IMCR_PIC 0x0 /* selects PIC mode (8259-> BSP) */ 159 #define APIC_IMCR_APIC 0x1 /* selects APIC mode (8259->APIC) */ 160 161 #define APIC_CT_VECT 0x4ac /* conf table vector */ 162 #define APIC_CT_SIZE 1024 /* conf table size */ 163 164 #define APIC_ID 'MPAT' /* conf table signature */ 165 166 #define VENID_AMD 0x1022 167 #define DEVID_8131_IOAPIC 0x7451 168 #define DEVID_8132_IOAPIC 0x7459 169 170 #define IOAPICS_NODE_NAME "ioapics" 171 #define IOAPICS_CHILD_NAME "ioapic" 172 #define IOAPICS_DEV_TYPE "ioapic" 173 #define IOAPICS_PROP_VENID "vendor-id" 174 #define IOAPICS_PROP_DEVID "device-id" 175 176 #define IS_CLASS_IOAPIC(b, s, p) \ 177 ((b) == PCI_CLASS_PERIPH && (s) == PCI_PERIPH_PIC && \ 178 ((p) == PCI_PERIPH_PIC_IF_IO_APIC || \ 179 (p) == PCI_PERIPH_PIC_IF_IOX_APIC)) 180 181 /* 182 * These macros are used in frequently called routines like 183 * apic_intr_enter(). 184 */ 185 #define X2APIC_WRITE(reg, v) \ 186 wrmsr((REG_X2APIC_BASE_MSR + (reg >> 2)), v) 187 188 #define LOCAL_APIC_WRITE_REG(reg, v) \ 189 apicadr[reg] = v 190 191 /* 192 * MP floating pointer structure defined in Intel MP Spec 1.1 193 */ 194 struct apic_mpfps_hdr { 195 uint32_t mpfps_sig; /* _MP_ (0x5F4D505F) */ 196 uint32_t mpfps_mpct_paddr; /* paddr of MP configuration tbl */ 197 uchar_t mpfps_length; /* in paragraph (16-bytes units) */ 198 uchar_t mpfps_spec_rev; /* version number of MP spec */ 199 uchar_t mpfps_checksum; /* checksum of complete structure */ 200 uchar_t mpfps_featinfo1; /* mp feature info bytes 1 */ 201 uchar_t mpfps_featinfo2; /* mp feature info bytes 2 */ 202 uchar_t mpfps_featinfo3; /* mp feature info bytes 3 */ 203 uchar_t mpfps_featinfo4; /* mp feature info bytes 4 */ 204 uchar_t mpfps_featinfo5; /* mp feature info bytes 5 */ 205 }; 206 207 #define MPFPS_FEATINFO2_IMCRP 0x80 /* IMCRP presence bit */ 208 209 #define APIC_MPS_OEM_ID_LEN 8 210 #define APIC_MPS_PROD_ID_LEN 12 211 212 struct apic_mp_cnf_hdr { 213 uint_t mpcnf_sig; 214 215 uint_t mpcnf_tbl_length: 16, 216 mpcnf_spec: 8, 217 mpcnf_cksum: 8; 218 219 char mpcnf_oem_str[APIC_MPS_OEM_ID_LEN]; 220 221 char mpcnf_prod_str[APIC_MPS_PROD_ID_LEN]; 222 223 uint_t mpcnf_oem_ptr; 224 225 uint_t mpcnf_oem_tbl_size: 16, 226 mpcnf_entry_cnt: 16; 227 228 uint_t mpcnf_local_apic; 229 230 uint_t mpcnf_resv; 231 }; 232 233 struct apic_procent { 234 uint_t proc_entry: 8, 235 proc_apicid: 8, 236 proc_version: 8, 237 proc_cpuflags: 8; 238 239 uint_t proc_stepping: 4, 240 proc_model: 4, 241 proc_family: 4, 242 proc_type: 2, /* undocumented feature */ 243 proc_resv1: 18; 244 245 uint_t proc_feature; 246 247 uint_t proc_resv2; 248 249 uint_t proc_resv3; 250 }; 251 252 /* 253 * proc_cpuflags definitions 254 */ 255 #define CPUFLAGS_EN 1 /* if not set, this processor is unusable */ 256 #define CPUFLAGS_BP 2 /* set if this is the bootstrap processor */ 257 258 259 struct apic_bus { 260 uchar_t bus_entry; 261 uchar_t bus_id; 262 ushort_t bus_str1; 263 uint_t bus_str2; 264 }; 265 266 struct apic_io_entry { 267 uint_t io_entry: 8, 268 io_apicid: 8, 269 io_version: 8, 270 io_flags: 8; 271 272 uint_t io_apic_addr; 273 }; 274 275 #define IOAPIC_FLAGS_EN 0x01 /* this I/O apic is enable or not */ 276 277 #define MAX_IO_APIC 32 /* maximum # of IOAPICs supported */ 278 279 struct apic_io_intr { 280 uint_t intr_entry: 8, 281 intr_type: 8, 282 intr_po: 2, 283 intr_el: 2, 284 intr_resv: 12; 285 286 uint_t intr_busid: 8, 287 intr_irq: 8, 288 intr_destid: 8, 289 intr_destintin: 8; 290 }; 291 292 /* 293 * intr_type definitions 294 */ 295 #define IO_INTR_INT 0x00 296 #define IO_INTR_NMI 0x01 297 #define IO_INTR_SMI 0x02 298 #define IO_INTR_EXTINT 0x03 299 300 /* 301 * destination APIC ID 302 */ 303 #define INTR_ALL_APIC 0xff 304 305 306 /* local vector table */ 307 #define AV_MASK 0x10000 308 309 /* interrupt command register 32-63 */ 310 #define AV_TOALL 0x7fffffff 311 #define AV_HIGH_ORDER 0x40000000 312 #define AV_IM_OFF 0x40000000 313 314 /* interrupt command register 0-31 */ 315 #define AV_DELIV_MODE 0x700 316 317 #define AV_FIXED 0x000 318 #define AV_LOPRI 0x100 319 #define AV_SMI 0x200 320 #define AV_REMOTE 0x300 321 #define AV_NMI 0x400 322 #define AV_RESET 0x500 323 #define AV_STARTUP 0x600 324 #define AV_EXTINT 0x700 325 326 #define AV_PDEST 0x000 327 #define AV_LDEST 0x800 328 329 /* IO & Local APIC Bit Definitions */ 330 #define RDT_VECTOR(x) ((uchar_t)((x) & 0xFF)) 331 #define AV_PENDING 0x1000 332 #define AV_ACTIVE_LOW 0x2000 /* only for integrated APIC */ 333 #define AV_REMOTE_IRR 0x4000 /* IOAPIC RDT-specific */ 334 #define AV_LEVEL 0x8000 335 #define AV_DEASSERT AV_LEVEL 336 #define AV_ASSERT 0xc000 337 338 #define AV_READ_PENDING 0x10000 339 #define AV_REMOTE_STATUS 0x20000 /* 1 = valid, 0 = invalid */ 340 341 #define AV_SH_SELF 0x40000 /* Short hand for self */ 342 #define AV_SH_ALL_INCSELF 0x80000 /* All processors */ 343 #define AV_SH_ALL_EXCSELF 0xc0000 /* All excluding self */ 344 /* spurious interrupt vector register */ 345 #define AV_UNIT_ENABLE 0x100 346 347 /* timer vector table */ 348 #define AV_TIME 0x20000 /* Set timer mode to periodic */ 349 350 #define APIC_MAXVAL 0xffffffffUL 351 #define APIC_TIME_MIN 0x5000 352 #define APIC_TIME_COUNT 0x4000 353 354 /* 355 * Range of the low byte value in apic_tick before starting calibration 356 */ 357 #define APIC_LB_MIN 0x60 358 #define APIC_LB_MAX 0xe0 359 360 #define APIC_MAX_VECTOR 255 361 #define APIC_RESV_VECT 0x00 362 #define APIC_RESV_IRQ 0xfe 363 #define APIC_BASE_VECT 0x20 /* This will come in as interrupt 0 */ 364 #define APIC_AVAIL_VECTOR (APIC_MAX_VECTOR+1-APIC_BASE_VECT) 365 #define APIC_VECTOR_PER_IPL 0x10 /* # of vectors before PRI changes */ 366 #define APIC_VECTOR(ipl) (apic_ipltopri[ipl] | APIC_RESV_VECT) 367 #define APIC_VECTOR_MASK 0x0f 368 #define APIC_HI_PRI_VECTS 2 /* vects reserved for hi pri reqs */ 369 #define APIC_IPL_MASK 0xf0 370 #define APIC_IPL_SHIFT 4 /* >> to get ipl part of vector */ 371 #define APIC_FIRST_FREE_IRQ 0x10 372 #define APIC_MAX_ISA_IRQ 15 373 #define APIC_IPL0 0x0f /* let IDLE_IPL be the lowest */ 374 #define APIC_IDLE_IPL 0x00 375 376 #define APIC_MASK_ALL 0xf0 /* Mask all interrupts */ 377 378 /* spurious interrupt vector */ 379 #define APIC_SPUR_INTR 0xFF 380 381 /* special or reserve vectors */ 382 #define APIC_CHECK_RESERVE_VECTORS(v) \ 383 (((v) == T_FASTTRAP) || ((v) == APIC_SPUR_INTR) || \ 384 ((v) == T_SYSCALLINT) || ((v) == T_DTRACE_RET) || ((v) == T_INT80)) 385 386 /* cmos shutdown code for BIOS */ 387 #define BIOS_SHUTDOWN 0x0a 388 389 /* define the entry types for BIOS information tables as defined in PC+MP */ 390 #define APIC_CPU_ENTRY 0 391 #define APIC_BUS_ENTRY 1 392 #define APIC_IO_ENTRY 2 393 #define APIC_IO_INTR_ENTRY 3 394 #define APIC_LOCAL_INTR_ENTRY 4 395 #define APIC_MPTBL_ADDR (639 * 1024) 396 /* 397 * The MP Floating Point structure could be in 1st 1KB of EBDA or last KB 398 * of system base memory or in ROM between 0xF0000 and 0xFFFFF 399 */ 400 #define MPFPS_RAM_WIN_LEN 1024 401 #define MPFPS_ROM_WIN_START (uint32_t)0xf0000 402 #define MPFPS_ROM_WIN_LEN 0x10000 403 404 #define EISA_LEVEL_CNTL 0x4D0 405 406 /* definitions for apic_irq_table */ 407 #define FREE_INDEX (short)-1 /* empty slot */ 408 #define RESERVE_INDEX (short)-2 /* ipi, softintr, clkintr */ 409 #define ACPI_INDEX (short)-3 /* ACPI */ 410 #define MSI_INDEX (short)-4 /* MSI */ 411 #define MSIX_INDEX (short)-5 /* MSI-X */ 412 #define DEFAULT_INDEX (short)0x7FFF 413 /* biggest positive no. to avoid conflict with actual index */ 414 415 #define APIC_IS_MSI_OR_MSIX_INDEX(index) \ 416 ((index) == MSI_INDEX || (index) == MSIX_INDEX) 417 418 /* 419 * definitions for MSI Address 420 */ 421 #define MSI_ADDR_HDR APIC_LOCAL_ADDR 422 #define MSI_ADDR_DEST_SHIFT 12 /* Destination CPU's apic id */ 423 #define MSI_ADDR_RH_FIXED 0x0 /* Redirection Hint Fixed */ 424 #define MSI_ADDR_RH_LOPRI 0x1 /* Redirection Hint Lowest priority */ 425 #define MSI_ADDR_RH_SHIFT 3 426 #define MSI_ADDR_DM_PHYSICAL 0x0 /* Physical Destination Mode */ 427 #define MSI_ADDR_DM_LOGICAL 0x1 /* Logical Destination Mode */ 428 #define MSI_ADDR_DM_SHIFT 2 429 430 /* 431 * definitions for MSI Data 432 */ 433 #define MSI_DATA_DELIVERY_FIXED 0x0 /* Fixed delivery */ 434 #define MSI_DATA_DELIVERY_LOPRI 0x1 /* Lowest priority delivery */ 435 #define MSI_DATA_DELIVERY_SMI 0x2 436 #define MSI_DATA_DELIVERY_NMI 0x4 437 #define MSI_DATA_DELIVERY_INIT 0x5 438 #define MSI_DATA_DELIVERY_EXTINT 0x7 439 #define MSI_DATA_DELIVERY_SHIFT 8 440 #define MSI_DATA_TM_EDGE 0x0 /* MSI is edge sensitive */ 441 #define MSI_DATA_TM_LEVEL 0x1 /* level sensitive */ 442 #define MSI_DATA_TM_SHIFT 15 443 #define MSI_DATA_LEVEL_DEASSERT 0x0 444 #define MSI_DATA_LEVEL_ASSERT 0x1 /* Edge always assert */ 445 #define MSI_DATA_LEVEL_SHIFT 14 446 447 /* 448 * use to define each irq setup by the apic 449 */ 450 typedef struct apic_irq { 451 short airq_mps_intr_index; /* index into mps interrupt entries */ 452 /* table */ 453 uchar_t airq_intin_no; 454 uchar_t airq_ioapicindex; 455 dev_info_t *airq_dip; /* device corresponding to this interrupt */ 456 /* 457 * IRQ could be shared (in H/W) in which case dip & major will be 458 * for the one that was last added at this level. We cannot keep a 459 * linked list as delspl does not tell us which device has just 460 * been unloaded. For most servers where we are worried about 461 * performance, interrupt should not be shared & should not be 462 * a problem. This does not cause any correctness issue - dip is 463 * used only as an optimisation to avoid going thru all the tables 464 * in translate IRQ (which is always called twice due to brokenness 465 * in the way IPLs are determined for devices). major is used only 466 * to bind interrupts corresponding to the same device on the same 467 * CPU. Not finding major will just cause it to be potentially bound 468 * to another CPU. 469 */ 470 major_t airq_major; /* major number corresponding to the device */ 471 ushort_t airq_rdt_entry; /* level, polarity & trig mode */ 472 uint32_t airq_cpu; /* Which CPU are we bound to ? */ 473 uint32_t airq_temp_cpu; /* Could be diff from cpu due to disable_intr */ 474 uchar_t airq_vector; /* Vector chosen for this irq */ 475 uchar_t airq_share; /* number of interrupts at this irq */ 476 uchar_t airq_share_id; /* id to identify source from irqno */ 477 uchar_t airq_ipl; /* The ipl at which this is handled */ 478 iflag_t airq_iflag; /* interrupt flag */ 479 uchar_t airq_origirq; /* original irq passed in */ 480 uint_t airq_busy; /* How frequently did clock find */ 481 /* us in this */ 482 struct apic_irq *airq_next; /* chain of shared intpts */ 483 } apic_irq_t; 484 485 #define IRQ_USER_BOUND 0x80000000 /* user requested bind if set in airq_cpu */ 486 #define IRQ_UNBOUND (uint32_t)-1 /* set in airq_cpu and airq_temp_cpu */ 487 #define IRQ_UNINIT (uint32_t)-2 /* in airq_temp_cpu till addspl called */ 488 489 /* Macros to help deal with shared interrupts */ 490 #define VIRTIRQ(irqno, share_id) ((irqno) | ((share_id) << 8)) 491 #define IRQINDEX(irq) ((irq) & 0xFF) /* Mask to get irq from virtual irq */ 492 493 typedef struct apic_cpus_info { 494 uint32_t aci_local_id; 495 uchar_t aci_local_ver; 496 uchar_t aci_status; 497 uchar_t aci_redistribute; /* Selected for redistribution */ 498 uint_t aci_busy; /* Number of ticks we were in ISR */ 499 uint_t aci_spur_cnt; /* # of spurious intpts on this cpu */ 500 uint_t aci_ISR_in_progress; /* big enough to hold 1 << MAXIPL */ 501 uchar_t aci_curipl; /* IPL of current ISR */ 502 uchar_t aci_current[MAXIPL]; /* Current IRQ at each IPL */ 503 uint32_t aci_bound; /* # of user requested binds ? */ 504 uint32_t aci_temp_bound; /* # of non user IRQ binds */ 505 uchar_t aci_idle; /* The CPU is idle */ 506 /* 507 * fill to make sure each struct is in seperate cache line. 508 * Or atleast that ISR_in_progress/curipl is not shared with something 509 * that is read/written heavily by another CPU. 510 * Given kmem_alloc guarantees alignment to 8 bytes, having 8 511 * bytes on each side will isolate us in a 16 byte cache line. 512 */ 513 } apic_cpus_info_t; 514 515 #define APIC_CPU_ONLINE 1 516 #define APIC_CPU_INTR_ENABLE 2 517 518 /* 519 * APIC ops to support various flavors of APIC like APIC and x2APIC. 520 */ 521 typedef struct apic_regs_ops { 522 uint64_t (*apic_read)(uint32_t); 523 void (*apic_write)(uint32_t, uint64_t); 524 int (*apic_get_pri)(void); 525 void (*apic_write_task_reg)(uint64_t); 526 void (*apic_write_int_cmd)(uint32_t, uint32_t); 527 void (*apic_send_eoi)(uint32_t); 528 } apic_reg_ops_t; 529 530 /* 531 * Various poweroff methods and ports & bits for them 532 */ 533 #define APIC_POWEROFF_NONE 0 534 #define APIC_POWEROFF_VIA_RTC 1 535 #define APIC_POWEROFF_VIA_ASPEN_BMC 2 536 #define APIC_POWEROFF_VIA_SITKA_BMC 3 537 538 /* For RTC */ 539 #define RTC_REGA 0x0a 540 #define PFR_REG 0x4a /* extended control register */ 541 #define PAB_CBIT 0x08 542 #define WF_FLAG 0x02 543 #define KS_FLAG 0x01 544 #define EXT_BANK 0x10 545 546 /* For Aspen/Drake BMC */ 547 548 #define CC_SMS_GET_STATUS 0x40 549 #define CC_SMS_WR_START 0x41 550 #define CC_SMS_WR_NEXT 0x42 551 #define CC_SMS_WR_END 0x43 552 553 #define MISMIC_DATA_REGISTER 0x0ca9 554 #define MISMIC_CNTL_REGISTER 0x0caa 555 #define MISMIC_FLAG_REGISTER 0x0cab 556 557 #define MISMIC_BUSY_MASK 0x01 558 559 /* For Sitka/Cabrillo BMC */ 560 561 #define SMS_GET_STATUS 0x60 562 #define SMS_WRITE_START 0x61 563 #define SMS_WRITE_END 0x62 564 565 #define SMS_DATA_REGISTER 0x0ca2 566 #define SMS_STATUS_REGISTER 0x0ca3 567 #define SMS_COMMAND_REGISTER 0x0ca3 568 569 #define SMS_IBF_MASK 0x02 570 #define SMS_STATE_MASK 0xc0 571 572 #define SMS_IDLE_STATE 0x00 573 #define SMS_READ_STATE 0x40 574 #define SMS_WRITE_STATE 0x80 575 #define SMS_ERROR_STATE 0xc0 576 577 extern uint32_t ioapic_read(int ioapic_ix, uint32_t reg); 578 extern void ioapic_write(int ioapic_ix, uint32_t reg, uint32_t value); 579 extern void ioapic_write_eoi(int ioapic_ix, uint32_t value); 580 581 /* Macros for reading/writing the IOAPIC RDT entries */ 582 #define READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, ipin) \ 583 ioapic_read(ioapic_ix, APIC_RDT_CMD + (2 * (ipin))) 584 585 #define READ_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapic_ix, ipin) \ 586 ioapic_read(ioapic_ix, APIC_RDT_CMD2 + (2 * (ipin))) 587 588 #define WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, ipin, value) \ 589 ioapic_write(ioapic_ix, APIC_RDT_CMD + (2 * (ipin)), value) 590 591 #define WRITE_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapic_ix, ipin, value) \ 592 ioapic_write(ioapic_ix, APIC_RDT_CMD2 + (2 * (ipin)), value) 593 594 /* Used by PSM_INTR_OP_GET_INTR to return device information. */ 595 typedef struct { 596 uint16_t avgi_req_flags; /* request flags - to kernel */ 597 uint8_t avgi_num_devs; /* # devs on this ino - from kernel */ 598 uint8_t avgi_vector; /* vector */ 599 uint32_t avgi_cpu_id; /* cpu of interrupt - from kernel */ 600 dev_info_t **avgi_dip_list; /* kmem_alloc'ed list of dev_infos. */ 601 /* Contains num_devs elements. */ 602 } apic_get_intr_t; 603 604 /* Masks for avgi_req_flags. */ 605 #define PSMGI_REQ_CPUID 0x1 /* Request CPU ID */ 606 #define PSMGI_REQ_NUM_DEVS 0x2 /* Request num of devices on vector */ 607 #define PSMGI_REQ_VECTOR 0x4 608 #define PSMGI_REQ_GET_DEVS 0x8 /* Request device list */ 609 #define PSMGI_REQ_ALL 0xf /* Request everything */ 610 611 /* Other flags */ 612 #define PSMGI_INTRBY_VEC 0 /* Vec passed. xlate to IRQ needed */ 613 #define PSMGI_INTRBY_IRQ 0x8000 /* IRQ passed. no xlate needed */ 614 #define PSMGI_INTRBY_FLAGS 0x8000 /* Mask for this flag */ 615 616 /* 617 * Use scaled-fixed-point arithmetic to calculate apic ticks. 618 * Round when dividing (by adding half of divisor to dividend) 619 * for one extra bit of precision. 620 */ 621 622 #define SF (1ULL<<20) /* Scaling Factor: scale by 2^20 */ 623 #define APIC_TICKS_TO_NSECS(ticks) ((((int64_t)(ticks) * SF) + \ 624 apic_ticks_per_SFnsecs / 2) / \ 625 apic_ticks_per_SFnsecs); 626 #define APIC_NSECS_TO_TICKS(nsecs) (((int64_t)(nsecs) * \ 627 apic_ticks_per_SFnsecs + (SF/2)) / SF) 628 629 extern int apic_verbose; 630 631 /* Flag definitions for apic_verbose */ 632 #define APIC_VERBOSE_IOAPIC_FLAG 0x00000001 633 #define APIC_VERBOSE_IRQ_FLAG 0x00000002 634 #define APIC_VERBOSE_POWEROFF_FLAG 0x00000004 635 #define APIC_VERBOSE_POWEROFF_PAUSE_FLAG 0x00000008 636 637 638 #define APIC_VERBOSE_IOAPIC(fmt) \ 639 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) \ 640 cmn_err fmt; 641 642 #define APIC_VERBOSE_IRQ(fmt) \ 643 if (apic_verbose & APIC_VERBOSE_IRQ_FLAG) \ 644 cmn_err fmt; 645 646 #define APIC_VERBOSE_POWEROFF(fmt) \ 647 if (apic_verbose & APIC_VERBOSE_POWEROFF_FLAG) \ 648 prom_printf fmt; 649 650 #ifdef DEBUG 651 #define DENT 0x0001 652 extern int apic_debug; 653 /* 654 * set apic_restrict_vector to the # of vectors we want to allow per range 655 * useful in testing shared interrupt logic by setting it to 2 or 3 656 */ 657 extern int apic_restrict_vector; 658 659 #define APIC_DEBUG_MSGBUFSIZE 2048 660 extern int apic_debug_msgbuf[]; 661 extern int apic_debug_msgbufindex; 662 663 /* 664 * Put "int" info into debug buffer. No MP consistency, but light weight. 665 * Good enough for most debugging. 666 */ 667 #define APIC_DEBUG_BUF_PUT(x) \ 668 apic_debug_msgbuf[apic_debug_msgbufindex++] = x; \ 669 if (apic_debug_msgbufindex >= (APIC_DEBUG_MSGBUFSIZE - NCPU)) \ 670 apic_debug_msgbufindex = 0; 671 672 #endif /* DEBUG */ 673 674 extern int apic_error; 675 /* values which apic_error can take. Not catastrophic, but may help debug */ 676 #define APIC_ERR_BOOT_EOI 0x1 677 #define APIC_ERR_GET_IPIVECT_FAIL 0x2 678 #define APIC_ERR_INVALID_INDEX 0x4 679 #define APIC_ERR_MARK_VECTOR_FAIL 0x8 680 #define APIC_ERR_APIC_ERROR 0x40000000 681 #define APIC_ERR_NMI 0x80000000 682 683 /* 684 * ACPI definitions 685 */ 686 /* _PIC method arguments */ 687 #define ACPI_PIC_MODE 0 688 #define ACPI_APIC_MODE 1 689 690 /* APIC error flags we care about */ 691 #define APIC_SEND_CS_ERROR 0x01 692 #define APIC_RECV_CS_ERROR 0x02 693 #define APIC_CS_ERRORS (APIC_SEND_CS_ERROR|APIC_RECV_CS_ERROR) 694 695 /* Maximum number of times to retry reprogramming at apic_intr_exit time */ 696 #define APIC_REPROGRAM_MAX_TRIES 10000 697 698 /* Parameter to ioapic_init_intr(): Should ioapic ints be masked? */ 699 #define IOAPIC_MASK 1 700 #define IOAPIC_NOMASK 0 701 702 #define INTR_ROUND_ROBIN_WITH_AFFINITY 0 703 #define INTR_ROUND_ROBIN 1 704 #define INTR_LOWEST_PRIORITY 2 705 706 707 708 struct ioapic_reprogram_data { 709 boolean_t done; 710 apic_irq_t *irqp; 711 /* The CPU to which the int will be bound */ 712 int bindcpu; 713 /* # times the reprogram timeout was called */ 714 unsigned tries; 715 }; 716 717 /* The irq # is implicit in the array index: */ 718 extern struct ioapic_reprogram_data apic_reprogram_info[]; 719 720 extern void apic_intr_exit(int ipl, int irq); 721 extern void x2apic_intr_exit(int ipl, int irq); 722 extern int apic_probe_common(); 723 extern void apic_init_common(); 724 extern void ioapic_init_intr(); 725 extern void ioapic_disable_redirection(); 726 extern int apic_addspl_common(int irqno, int ipl, int min_ipl, int max_ipl); 727 extern int apic_delspl_common(int irqno, int ipl, int min_ipl, int max_ipl); 728 extern void apic_cleanup_busy(); 729 extern void apic_intr_redistribute(); 730 extern uchar_t apic_xlate_vector(uchar_t vector); 731 extern uchar_t apic_allocate_vector(int ipl, int irq, int pri); 732 extern void apic_free_vector(uchar_t vector); 733 extern int apic_allocate_irq(int irq); 734 extern uint32_t apic_bind_intr(dev_info_t *dip, int irq, uchar_t ioapicid, 735 uchar_t intin); 736 extern int apic_rebind(apic_irq_t *irq_ptr, int bind_cpu, 737 struct ioapic_reprogram_data *drep); 738 extern int apic_rebind_all(apic_irq_t *irq_ptr, int bind_cpu); 739 extern int apic_introp_xlate(dev_info_t *dip, struct intrspec *ispec, int type); 740 extern int apic_intr_ops(dev_info_t *dip, ddi_intr_handle_impl_t *hdlp, 741 psm_intr_op_t intr_op, int *result); 742 extern int apic_state(psm_state_request_t *); 743 extern boolean_t apic_cpu_in_range(int cpu); 744 extern int apic_check_msi_support(); 745 extern apic_irq_t *apic_find_irq(dev_info_t *dip, struct intrspec *ispec, 746 int type); 747 extern int apic_navail_vector(dev_info_t *dip, int pri); 748 extern int apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count, 749 int pri, int behavior); 750 extern int apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count, 751 int pri, int behavior); 752 extern void apic_free_vectors(dev_info_t *dip, int inum, int count, int pri, 753 int type); 754 extern int apic_get_vector_intr_info(int vecirq, 755 apic_get_intr_t *intr_params_p); 756 extern uchar_t apic_find_multi_vectors(int pri, int count); 757 extern int apic_setup_io_intr(void *p, int irq, boolean_t deferred); 758 extern uint32_t *mapin_apic(uint32_t addr, size_t len, int flags); 759 extern uint32_t *mapin_ioapic(uint32_t addr, size_t len, int flags); 760 extern void mapout_apic(caddr_t addr, size_t len); 761 extern void mapout_ioapic(caddr_t addr, size_t len); 762 extern uchar_t apic_modify_vector(uchar_t vector, int irq); 763 extern void apic_pci_msi_unconfigure(dev_info_t *rdip, int type, int inum); 764 extern void apic_pci_msi_disable_mode(dev_info_t *rdip, int type); 765 extern void apic_pci_msi_enable_mode(dev_info_t *rdip, int type, int inum); 766 extern void apic_pci_msi_enable_vector(dev_info_t *dip, int type, int inum, 767 int vector, int count, int target_apic_id); 768 extern char *apic_get_apic_type(); 769 extern uint16_t apic_get_apic_version(); 770 extern void x2apic_send_ipi(); 771 extern void apic_ret(); 772 extern int apic_detect_x2apic(); 773 extern void apic_enable_x2apic(); 774 extern void apic_change_eoi(); 775 extern void apic_send_EOI(uint32_t); 776 extern void apic_send_directed_EOI(uint32_t); 777 778 extern volatile uint32_t *apicadr; /* virtual addr of local APIC */ 779 extern int apic_forceload; 780 extern apic_cpus_info_t *apic_cpus; 781 #ifdef _MACHDEP 782 extern cpuset_t apic_cpumask; 783 #endif 784 extern uint_t apic_picinit_called; 785 extern uchar_t apic_ipltopri[MAXIPL+1]; 786 extern uchar_t apic_vector_to_irq[APIC_MAX_VECTOR+1]; 787 extern int apic_max_device_irq; 788 extern int apic_min_device_irq; 789 extern apic_irq_t *apic_irq_table[APIC_MAX_VECTOR+1]; 790 extern volatile uint32_t *apicioadr[MAX_IO_APIC]; 791 extern uchar_t apic_io_id[MAX_IO_APIC]; 792 extern lock_t apic_ioapic_lock; 793 extern uint32_t apic_physaddr[MAX_IO_APIC]; 794 extern kmutex_t airq_mutex; 795 extern int apic_first_avail_irq; 796 extern uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL]; 797 extern int apic_imcrp; 798 extern int apic_revector_pending; 799 extern char apic_level_intr[APIC_MAX_VECTOR+1]; 800 extern uchar_t apic_resv_vector[MAXIPL+1]; 801 extern int apic_sample_factor_redistribution; 802 extern int apic_int_busy_mark; 803 extern int apic_int_free_mark; 804 extern int apic_diff_for_redistribution; 805 extern int apic_poweroff_method; 806 extern int apic_enable_acpi; 807 extern int apic_nproc; 808 extern int apic_next_bind_cpu; 809 extern int apic_redistribute_sample_interval; 810 extern int apic_multi_msi_enable; 811 extern int apic_multi_msi_max; 812 extern int apic_msix_max; 813 extern int apic_sci_vect; 814 extern uchar_t apic_ipls[]; 815 extern apic_reg_ops_t *apic_reg_ops; 816 extern int apic_mode; 817 extern int apic_direct_EOI; 818 extern void x2apic_update_psm(); 819 820 821 #ifdef __cplusplus 822 } 823 #endif 824 825 #endif /* _SYS_APIC_APIC_H */ 826