1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_APIC_APIC_H 27 #define _SYS_APIC_APIC_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #include <sys/psm_types.h> 32 #include <sys/avintr.h> 33 #include <sys/pci.h> 34 35 #ifdef __cplusplus 36 extern "C" { 37 #endif 38 39 #include <sys/psm_common.h> 40 41 #define APIC_IO_ADDR 0xfec00000 42 #define APIC_LOCAL_ADDR 0xfee00000 43 #define APIC_IO_MEMLEN 0xf 44 #define APIC_LOCAL_MEMLEN 0xfffff 45 46 /* Local Unit ID register */ 47 #define APIC_LID_REG 0x8 48 49 /* I/o Unit Version Register */ 50 #define APIC_VERS_REG 0xc 51 52 /* Task Priority register */ 53 #define APIC_TASK_REG 0x20 54 55 /* EOI register */ 56 #define APIC_EOI_REG 0x2c 57 58 /* Remote Read register */ 59 #define APIC_REMOTE_READ 0x30 60 61 /* Logical Destination register */ 62 #define APIC_DEST_REG 0x34 63 64 /* Destination Format rgister */ 65 #define APIC_FORMAT_REG 0x38 66 67 /* Spurious Interrupt Vector register */ 68 #define APIC_SPUR_INT_REG 0x3c 69 70 /* Error Status Register */ 71 #define APIC_ERROR_STATUS 0xa0 72 73 /* Interrupt Command registers */ 74 #define APIC_INT_CMD1 0xc0 75 #define APIC_INT_CMD2 0xc4 76 77 /* Timer Vector Table register */ 78 #define APIC_LOCAL_TIMER 0xc8 79 80 /* Local Interrupt Vector registers */ 81 #define APIC_PCINT_VECT 0xd0 82 #define APIC_INT_VECT0 0xd4 83 #define APIC_INT_VECT1 0xd8 84 #define APIC_ERR_VECT 0xdc 85 86 /* IPL for performance counter interrupts */ 87 #define APIC_PCINT_IPL 0xe 88 #define APIC_LVT_MASK 0x10000 /* Mask bit (16) in LVT */ 89 90 /* Initial Count register */ 91 #define APIC_INIT_COUNT 0xe0 92 93 /* Current Count Register */ 94 #define APIC_CURR_COUNT 0xe4 95 #define APIC_CURR_ADD 0x39 /* used for remote read command */ 96 #define CURR_COUNT_OFFSET (sizeof (int32_t) * APIC_CURR_COUNT) 97 98 /* Divider Configuration Register */ 99 #define APIC_DIVIDE_REG 0xf8 100 101 /* IRR register */ 102 #define APIC_IRR_REG 0x80 103 104 /* ISR register */ 105 #define APIC_ISR_REG 0x40 106 107 #define APIC_IO_REG 0x0 108 #define APIC_IO_DATA 0x4 109 110 /* Bit offset of APIC ID in LID_REG, INT_CMD and in DEST_REG */ 111 #define APIC_ID_BIT_OFFSET 24 112 #define APIC_ICR_ID_BIT_OFFSET 24 113 #define APIC_LDR_ID_BIT_OFFSET 24 114 115 /* 116 * Choose between flat and clustered models by writing the following to the 117 * FORMAT_REG. 82489 DX documentation seemed to suggest that writing 0 will 118 * disable logical destination mode. 119 * Does not seem to be in the docs for local APICs on the processors. 120 */ 121 #define APIC_FLAT_MODEL 0xFFFFFFFFUL 122 #define APIC_CLUSTER_MODEL 0x0FFFFFFF 123 124 /* 125 * The commands which follow are window selectors written to APIC_IO_REG 126 * before data can be read/written from/to APIC_IO_DATA 127 */ 128 129 #define APIC_ID_CMD 0x0 130 #define APIC_VERS_CMD 0x1 131 #define APIC_RDT_CMD 0x10 132 #define APIC_RDT_CMD2 0x11 133 134 #define APIC_INTEGRATED_VERS 0x10 /* 0x10 & above indicates integrated */ 135 #define IOAPIC_VER_82489DX 0x01 /* Version ID: 82489DX External APIC */ 136 137 #define APIC_INT_SPURIOUS -1 138 139 #define APIC_IMCR_P1 0x22 /* int mode conf register port 1 */ 140 #define APIC_IMCR_P2 0x23 /* int mode conf register port 2 */ 141 #define APIC_IMCR_SELECT 0x70 /* select imcr by writing into P1 */ 142 #define APIC_IMCR_PIC 0x0 /* selects PIC mode (8259-> BSP) */ 143 #define APIC_IMCR_APIC 0x1 /* selects APIC mode (8259->APIC) */ 144 145 #define APIC_CT_VECT 0x4ac /* conf table vector */ 146 #define APIC_CT_SIZE 1024 /* conf table size */ 147 148 #define APIC_ID 'MPAT' /* conf table signature */ 149 150 #define VENID_AMD 0x1022 151 #define DEVID_8131_IOAPIC 0x7451 152 #define DEVID_8132_IOAPIC 0x7459 153 154 #define IOAPICS_NODE_NAME "ioapics" 155 #define IOAPICS_CHILD_NAME "ioapic" 156 #define IOAPICS_DEV_TYPE "ioapic" 157 #define IOAPICS_PROP_VENID "vendor-id" 158 #define IOAPICS_PROP_DEVID "device-id" 159 160 #define IS_CLASS_IOAPIC(b, s, p) \ 161 ((b) == PCI_CLASS_PERIPH && (s) == PCI_PERIPH_PIC && \ 162 ((p) == PCI_PERIPH_PIC_IF_IO_APIC || \ 163 (p) == PCI_PERIPH_PIC_IF_IOX_APIC)) 164 165 166 /* 167 * MP floating pointer structure defined in Intel MP Spec 1.1 168 */ 169 struct apic_mpfps_hdr { 170 uint32_t mpfps_sig; /* _MP_ (0x5F4D505F) */ 171 uint32_t mpfps_mpct_paddr; /* paddr of MP configuration tbl */ 172 uchar_t mpfps_length; /* in paragraph (16-bytes units) */ 173 uchar_t mpfps_spec_rev; /* version number of MP spec */ 174 uchar_t mpfps_checksum; /* checksum of complete structure */ 175 uchar_t mpfps_featinfo1; /* mp feature info bytes 1 */ 176 uchar_t mpfps_featinfo2; /* mp feature info bytes 2 */ 177 uchar_t mpfps_featinfo3; /* mp feature info bytes 3 */ 178 uchar_t mpfps_featinfo4; /* mp feature info bytes 4 */ 179 uchar_t mpfps_featinfo5; /* mp feature info bytes 5 */ 180 }; 181 182 #define MPFPS_FEATINFO2_IMCRP 0x80 /* IMCRP presence bit */ 183 184 #define APIC_MPS_OEM_ID_LEN 8 185 #define APIC_MPS_PROD_ID_LEN 12 186 187 struct apic_mp_cnf_hdr { 188 uint_t mpcnf_sig; 189 190 uint_t mpcnf_tbl_length: 16, 191 mpcnf_spec: 8, 192 mpcnf_cksum: 8; 193 194 char mpcnf_oem_str[APIC_MPS_OEM_ID_LEN]; 195 196 char mpcnf_prod_str[APIC_MPS_PROD_ID_LEN]; 197 198 uint_t mpcnf_oem_ptr; 199 200 uint_t mpcnf_oem_tbl_size: 16, 201 mpcnf_entry_cnt: 16; 202 203 uint_t mpcnf_local_apic; 204 205 uint_t mpcnf_resv; 206 }; 207 208 struct apic_procent { 209 uint_t proc_entry: 8, 210 proc_apicid: 8, 211 proc_version: 8, 212 proc_cpuflags: 8; 213 214 uint_t proc_stepping: 4, 215 proc_model: 4, 216 proc_family: 4, 217 proc_type: 2, /* undocumented feature */ 218 proc_resv1: 18; 219 220 uint_t proc_feature; 221 222 uint_t proc_resv2; 223 224 uint_t proc_resv3; 225 }; 226 227 /* 228 * proc_cpuflags definitions 229 */ 230 #define CPUFLAGS_EN 1 /* if not set, this processor is unusable */ 231 #define CPUFLAGS_BP 2 /* set if this is the bootstrap processor */ 232 233 234 struct apic_bus { 235 uchar_t bus_entry; 236 uchar_t bus_id; 237 ushort_t bus_str1; 238 uint_t bus_str2; 239 }; 240 241 struct apic_io_entry { 242 uint_t io_entry: 8, 243 io_apicid: 8, 244 io_version: 8, 245 io_flags: 8; 246 247 uint_t io_apic_addr; 248 }; 249 250 #define IOAPIC_FLAGS_EN 0x01 /* this I/O apic is enable or not */ 251 252 #define MAX_IO_APIC 32 /* maximum # of IOAPICs supported */ 253 254 struct apic_io_intr { 255 uint_t intr_entry: 8, 256 intr_type: 8, 257 intr_po: 2, 258 intr_el: 2, 259 intr_resv: 12; 260 261 uint_t intr_busid: 8, 262 intr_irq: 8, 263 intr_destid: 8, 264 intr_destintin: 8; 265 }; 266 267 /* 268 * intr_type definitions 269 */ 270 #define IO_INTR_INT 0x00 271 #define IO_INTR_NMI 0x01 272 #define IO_INTR_SMI 0x02 273 #define IO_INTR_EXTINT 0x03 274 275 /* 276 * destination APIC ID 277 */ 278 #define INTR_ALL_APIC 0xff 279 280 281 /* local vector table */ 282 #define AV_MASK 0x10000 283 284 /* interrupt command register 32-63 */ 285 #define AV_TOALL 0x7fffffff 286 #define AV_HIGH_ORDER 0x40000000 287 #define AV_IM_OFF 0x40000000 288 289 /* interrupt command register 0-31 */ 290 #define AV_FIXED 0x000 291 #define AV_LOPRI 0x100 292 #define AV_REMOTE 0x300 293 #define AV_NMI 0x400 294 #define AV_RESET 0x500 295 #define AV_STARTUP 0x600 296 #define AV_EXTINT 0x700 297 298 #define AV_PDEST 0x000 299 #define AV_LDEST 0x800 300 301 /* IO & Local APIC Bit Definitions */ 302 #define RDT_VECTOR(x) ((uchar_t)((x) & 0xFF)) 303 #define AV_PENDING 0x1000 304 #define AV_ACTIVE_LOW 0x2000 /* only for integrated APIC */ 305 #define AV_REMOTE_IRR 0x4000 /* IOAPIC RDT-specific */ 306 #define AV_LEVEL 0x8000 307 #define AV_DEASSERT AV_LEVEL 308 #define AV_ASSERT 0xc000 309 310 #define AV_READ_PENDING 0x10000 311 #define AV_REMOTE_STATUS 0x20000 /* 1 = valid, 0 = invalid */ 312 313 #define AV_SH_SELF 0x40000 /* Short hand for self */ 314 #define AV_SH_ALL_INCSELF 0x80000 /* All processors */ 315 #define AV_SH_ALL_EXCSELF 0xc0000 /* All excluding self */ 316 /* spurious interrupt vector register */ 317 #define AV_UNIT_ENABLE 0x100 318 319 /* timer vector table */ 320 #define AV_TIME 0x20000 /* Set timer mode to periodic */ 321 322 #define APIC_MAXVAL 0xffffffffUL 323 #define APIC_TIME_MIN 0x5000 324 #define APIC_TIME_COUNT 0x4000 325 326 /* 327 * Range of the low byte value in apic_tick before starting calibration 328 */ 329 #define APIC_LB_MIN 0x60 330 #define APIC_LB_MAX 0xe0 331 332 #define APIC_MAX_VECTOR 255 333 #define APIC_RESV_VECT 0x00 334 #define APIC_RESV_IRQ 0xfe 335 #define APIC_BASE_VECT 0x20 /* This will come in as interrupt 0 */ 336 #define APIC_AVAIL_VECTOR (APIC_MAX_VECTOR+1-APIC_BASE_VECT) 337 #define APIC_VECTOR_PER_IPL 0x10 /* # of vectors before PRI changes */ 338 #define APIC_VECTOR(ipl) (apic_ipltopri[ipl] | APIC_RESV_VECT) 339 #define APIC_VECTOR_MASK 0x0f 340 #define APIC_HI_PRI_VECTS 2 /* vects reserved for hi pri reqs */ 341 #define APIC_IPL_MASK 0xf0 342 #define APIC_IPL_SHIFT 4 /* >> to get ipl part of vector */ 343 #define APIC_FIRST_FREE_IRQ 0x10 344 #define APIC_MAX_ISA_IRQ 15 345 #define APIC_IPL0 0x0f /* let IDLE_IPL be the lowest */ 346 #define APIC_IDLE_IPL 0x00 347 348 #define APIC_MASK_ALL 0xf0 /* Mask all interrupts */ 349 350 /* spurious interrupt vector */ 351 #define APIC_SPUR_INTR 0xFF 352 353 /* special or reserve vectors */ 354 #define APIC_CHECK_RESERVE_VECTORS(v) \ 355 ((v == T_FASTTRAP) || (v == APIC_SPUR_INTR) || (v == T_SYSCALLINT) || \ 356 (v == T_DTRACE_RET) || (v == T_INT80)) 357 358 /* cmos shutdown code for BIOS */ 359 #define BIOS_SHUTDOWN 0x0a 360 361 /* define the entry types for BIOS information tables as defined in PC+MP */ 362 #define APIC_CPU_ENTRY 0 363 #define APIC_BUS_ENTRY 1 364 #define APIC_IO_ENTRY 2 365 #define APIC_IO_INTR_ENTRY 3 366 #define APIC_LOCAL_INTR_ENTRY 4 367 #define APIC_MPTBL_ADDR (639 * 1024) 368 /* 369 * The MP Floating Point structure could be in 1st 1KB of EBDA or last KB 370 * of system base memory or in ROM between 0xF0000 and 0xFFFFF 371 */ 372 #define MPFPS_RAM_WIN_LEN 1024 373 #define MPFPS_ROM_WIN_START (uint32_t)0xf0000 374 #define MPFPS_ROM_WIN_LEN 0x10000 375 376 #define EISA_LEVEL_CNTL 0x4D0 377 378 /* definitions for apic_irq_table */ 379 #define FREE_INDEX (short)-1 /* empty slot */ 380 #define RESERVE_INDEX (short)-2 /* ipi, softintr, clkintr */ 381 #define ACPI_INDEX (short)-3 /* ACPI */ 382 #define MSI_INDEX (short)-4 /* MSI */ 383 #define MSIX_INDEX (short)-5 /* MSI-X */ 384 #define DEFAULT_INDEX (short)0x7FFF 385 /* biggest positive no. to avoid conflict with actual index */ 386 387 #define APIC_IS_MSI_OR_MSIX_INDEX(index) \ 388 ((index) == MSI_INDEX || (index) == MSIX_INDEX) 389 390 /* 391 * definitions for MSI Address 392 */ 393 #define MSI_ADDR_HDR APIC_LOCAL_ADDR 394 #define MSI_ADDR_DEST_SHIFT 12 /* Destination CPU's apic id */ 395 #define MSI_ADDR_RH_FIXED 0x0 /* Redirection Hint Fixed */ 396 #define MSI_ADDR_RH_LOPRI 0x1 /* Redirection Hint Lowest priority */ 397 #define MSI_ADDR_RH_SHIFT 3 398 #define MSI_ADDR_DM_PHYSICAL 0x0 /* Physical Destination Mode */ 399 #define MSI_ADDR_DM_LOGICAL 0x1 /* Logical Destination Mode */ 400 #define MSI_ADDR_DM_SHIFT 2 401 402 /* 403 * definitions for MSI Data 404 */ 405 #define MSI_DATA_DELIVERY_FIXED 0x0 /* Fixed delivery */ 406 #define MSI_DATA_DELIVERY_LOPRI 0x1 /* Lowest priority delivery */ 407 #define MSI_DATA_DELIVERY_SMI 0x2 408 #define MSI_DATA_DELIVERY_NMI 0x4 409 #define MSI_DATA_DELIVERY_INIT 0x5 410 #define MSI_DATA_DELIVERY_EXTINT 0x7 411 #define MSI_DATA_DELIVERY_SHIFT 8 412 #define MSI_DATA_TM_EDGE 0x0 /* MSI is edge sensitive */ 413 #define MSI_DATA_TM_LEVEL 0x1 /* level sensitive */ 414 #define MSI_DATA_TM_SHIFT 15 415 #define MSI_DATA_LEVEL_DEASSERT 0x0 416 #define MSI_DATA_LEVEL_ASSERT 0x1 /* Edge always assert */ 417 #define MSI_DATA_LEVEL_SHIFT 14 418 419 /* 420 * use to define each irq setup by the apic 421 */ 422 typedef struct apic_irq { 423 short airq_mps_intr_index; /* index into mps interrupt entries */ 424 /* table */ 425 uchar_t airq_intin_no; 426 uchar_t airq_ioapicindex; 427 dev_info_t *airq_dip; /* device corresponding to this interrupt */ 428 /* 429 * IRQ could be shared (in H/W) in which case dip & major will be 430 * for the one that was last added at this level. We cannot keep a 431 * linked list as delspl does not tell us which device has just 432 * been unloaded. For most servers where we are worried about 433 * performance, interrupt should not be shared & should not be 434 * a problem. This does not cause any correctness issue - dip is 435 * used only as an optimisation to avoid going thru all the tables 436 * in translate IRQ (which is always called twice due to brokenness 437 * in the way IPLs are determined for devices). major is used only 438 * to bind interrupts corresponding to the same device on the same 439 * CPU. Not finding major will just cause it to be potentially bound 440 * to another CPU. 441 */ 442 major_t airq_major; /* major number corresponding to the device */ 443 ushort_t airq_rdt_entry; /* level, polarity & trig mode */ 444 uchar_t airq_cpu; /* Which CPU are we bound to ? */ 445 uchar_t airq_temp_cpu; /* Could be diff from cpu due to disable_intr */ 446 uchar_t airq_vector; /* Vector chosen for this irq */ 447 uchar_t airq_share; /* number of interrupts at this irq */ 448 uchar_t airq_share_id; /* id to identify source from irqno */ 449 uchar_t airq_ipl; /* The ipl at which this is handled */ 450 iflag_t airq_iflag; /* interrupt flag */ 451 uchar_t airq_origirq; /* original irq passed in */ 452 uint_t airq_busy; /* How frequently did clock find */ 453 /* us in this */ 454 struct apic_irq *airq_next; /* chain of shared intpts */ 455 } apic_irq_t; 456 457 #define IRQ_USER_BOUND 0x80 /* user requested bind if set in airq_cpu */ 458 #define IRQ_UNBOUND (uchar_t)-1 /* set in airq_cpu and airq_temp_cpu */ 459 #define IRQ_UNINIT (uchar_t)-2 /* in airq_temp_cpu till addspl called */ 460 461 /* Macros to help deal with shared interrupts */ 462 #define VIRTIRQ(irqno, share_id) ((irqno) | ((share_id) << 8)) 463 #define IRQINDEX(irq) ((irq) & 0xFF) /* Mask to get irq from virtual irq */ 464 465 typedef struct apic_cpus_info { 466 uchar_t aci_local_id; 467 uchar_t aci_local_ver; 468 uchar_t aci_status; 469 uchar_t aci_redistribute; /* Selected for redistribution */ 470 uint_t aci_busy; /* Number of ticks we were in ISR */ 471 uint_t aci_spur_cnt; /* # of spurious intpts on this cpu */ 472 uint_t aci_ISR_in_progress; /* big enough to hold 1 << MAXIPL */ 473 uchar_t aci_curipl; /* IPL of current ISR */ 474 uchar_t aci_current[MAXIPL]; /* Current IRQ at each IPL */ 475 uint32_t aci_bound; /* # of user requested binds ? */ 476 uint32_t aci_temp_bound; /* # of non user IRQ binds */ 477 uchar_t aci_idle; /* The CPU is idle */ 478 /* 479 * fill to make sure each struct is in seperate cache line. 480 * Or atleast that ISR_in_progress/curipl is not shared with something 481 * that is read/written heavily by another CPU. 482 * Given kmem_alloc guarantees alignment to 8 bytes, having 8 483 * bytes on each side will isolate us in a 16 byte cache line. 484 */ 485 } apic_cpus_info_t; 486 487 #define APIC_CPU_ONLINE 1 488 #define APIC_CPU_INTR_ENABLE 2 489 490 /* 491 * Various poweroff methods and ports & bits for them 492 */ 493 #define APIC_POWEROFF_NONE 0 494 #define APIC_POWEROFF_VIA_RTC 1 495 #define APIC_POWEROFF_VIA_ASPEN_BMC 2 496 #define APIC_POWEROFF_VIA_SITKA_BMC 3 497 498 /* For RTC */ 499 #define RTC_REGA 0x0a 500 #define PFR_REG 0x4a /* extended control register */ 501 #define PAB_CBIT 0x08 502 #define WF_FLAG 0x02 503 #define KS_FLAG 0x01 504 #define EXT_BANK 0x10 505 506 /* For Aspen/Drake BMC */ 507 508 #define CC_SMS_GET_STATUS 0x40 509 #define CC_SMS_WR_START 0x41 510 #define CC_SMS_WR_NEXT 0x42 511 #define CC_SMS_WR_END 0x43 512 513 #define MISMIC_DATA_REGISTER 0x0ca9 514 #define MISMIC_CNTL_REGISTER 0x0caa 515 #define MISMIC_FLAG_REGISTER 0x0cab 516 517 #define MISMIC_BUSY_MASK 0x01 518 519 /* For Sitka/Cabrillo BMC */ 520 521 #define SMS_GET_STATUS 0x60 522 #define SMS_WRITE_START 0x61 523 #define SMS_WRITE_END 0x62 524 525 #define SMS_DATA_REGISTER 0x0ca2 526 #define SMS_STATUS_REGISTER 0x0ca3 527 #define SMS_COMMAND_REGISTER 0x0ca3 528 529 #define SMS_IBF_MASK 0x02 530 #define SMS_STATE_MASK 0xc0 531 532 #define SMS_IDLE_STATE 0x00 533 #define SMS_READ_STATE 0x40 534 #define SMS_WRITE_STATE 0x80 535 #define SMS_ERROR_STATE 0xc0 536 537 extern uint32_t ioapic_read(int ioapic_ix, uint32_t reg); 538 extern void ioapic_write(int ioapic_ix, uint32_t reg, uint32_t value); 539 540 /* Macros for reading/writing the IOAPIC RDT entries */ 541 #define READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, ipin) \ 542 ioapic_read(ioapic_ix, APIC_RDT_CMD + (2 * (ipin))) 543 544 #define READ_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapic_ix, ipin) \ 545 ioapic_read(ioapic_ix, APIC_RDT_CMD2 + (2 * (ipin))) 546 547 #define WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, ipin, value) \ 548 ioapic_write(ioapic_ix, APIC_RDT_CMD + (2 * (ipin)), value) 549 550 #define WRITE_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapic_ix, ipin, value) \ 551 ioapic_write(ioapic_ix, APIC_RDT_CMD2 + (2 * (ipin)), value) 552 553 /* Used by PSM_INTR_OP_GET_INTR to return device information. */ 554 typedef struct { 555 uint16_t avgi_req_flags; /* request flags - to kernel */ 556 uint8_t avgi_num_devs; /* # devs on this ino - from kernel */ 557 uint8_t avgi_vector; /* vector */ 558 uint32_t avgi_cpu_id; /* cpu of interrupt - from kernel */ 559 dev_info_t **avgi_dip_list; /* kmem_alloc'ed list of dev_infos. */ 560 /* Contains num_devs elements. */ 561 } apic_get_intr_t; 562 563 /* Masks for avgi_req_flags. */ 564 #define PSMGI_REQ_CPUID 0x1 /* Request CPU ID */ 565 #define PSMGI_REQ_NUM_DEVS 0x2 /* Request num of devices on vector */ 566 #define PSMGI_REQ_VECTOR 0x4 567 #define PSMGI_REQ_GET_DEVS 0x8 /* Request device list */ 568 #define PSMGI_REQ_ALL 0xf /* Request everything */ 569 570 /* Other flags */ 571 #define PSMGI_INTRBY_VEC 0 /* Vec passed. xlate to IRQ needed */ 572 #define PSMGI_INTRBY_IRQ 0x8000 /* IRQ passed. no xlate needed */ 573 #define PSMGI_INTRBY_FLAGS 0x8000 /* Mask for this flag */ 574 575 /* 576 * Use scaled-fixed-point arithmetic to calculate apic ticks. 577 * Round when dividing (by adding half of divisor to dividend) 578 * for one extra bit of precision. 579 */ 580 581 #define SF (1ULL<<20) /* Scaling Factor: scale by 2^20 */ 582 #define APIC_TICKS_TO_NSECS(ticks) ((((int64_t)(ticks) * SF) + \ 583 apic_ticks_per_SFnsecs / 2) / \ 584 apic_ticks_per_SFnsecs); 585 #define APIC_NSECS_TO_TICKS(nsecs) (((int64_t)(nsecs) * \ 586 apic_ticks_per_SFnsecs + (SF/2)) / SF) 587 588 extern int apic_verbose; 589 590 /* Flag definitions for apic_verbose */ 591 #define APIC_VERBOSE_IOAPIC_FLAG 0x00000001 592 #define APIC_VERBOSE_IRQ_FLAG 0x00000002 593 #define APIC_VERBOSE_POWEROFF_FLAG 0x00000004 594 #define APIC_VERBOSE_POWEROFF_PAUSE_FLAG 0x00000008 595 596 597 #define APIC_VERBOSE_IOAPIC(fmt) \ 598 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) \ 599 cmn_err fmt; 600 601 #define APIC_VERBOSE_IRQ(fmt) \ 602 if (apic_verbose & APIC_VERBOSE_IRQ_FLAG) \ 603 cmn_err fmt; 604 605 #define APIC_VERBOSE_POWEROFF(fmt) \ 606 if (apic_verbose & APIC_VERBOSE_POWEROFF_FLAG) \ 607 prom_printf fmt; 608 609 #ifdef DEBUG 610 #define DENT 0x0001 611 extern int apic_debug; 612 /* 613 * set apic_restrict_vector to the # of vectors we want to allow per range 614 * useful in testing shared interrupt logic by setting it to 2 or 3 615 */ 616 extern int apic_restrict_vector; 617 618 #define APIC_DEBUG_MSGBUFSIZE 2048 619 extern int apic_debug_msgbuf[]; 620 extern int apic_debug_msgbufindex; 621 622 /* 623 * Put "int" info into debug buffer. No MP consistency, but light weight. 624 * Good enough for most debugging. 625 */ 626 #define APIC_DEBUG_BUF_PUT(x) \ 627 apic_debug_msgbuf[apic_debug_msgbufindex++] = x; \ 628 if (apic_debug_msgbufindex >= (APIC_DEBUG_MSGBUFSIZE - NCPU)) \ 629 apic_debug_msgbufindex = 0; 630 631 #endif /* DEBUG */ 632 633 extern int apic_error; 634 /* values which apic_error can take. Not catastrophic, but may help debug */ 635 #define APIC_ERR_BOOT_EOI 0x1 636 #define APIC_ERR_GET_IPIVECT_FAIL 0x2 637 #define APIC_ERR_INVALID_INDEX 0x4 638 #define APIC_ERR_MARK_VECTOR_FAIL 0x8 639 #define APIC_ERR_APIC_ERROR 0x40000000 640 #define APIC_ERR_NMI 0x80000000 641 642 /* 643 * ACPI definitions 644 */ 645 /* _PIC method arguments */ 646 #define ACPI_PIC_MODE 0 647 #define ACPI_APIC_MODE 1 648 649 /* APIC error flags we care about */ 650 #define APIC_SEND_CS_ERROR 0x01 651 #define APIC_RECV_CS_ERROR 0x02 652 #define APIC_CS_ERRORS (APIC_SEND_CS_ERROR|APIC_RECV_CS_ERROR) 653 654 /* Maximum number of times to retry reprogramming at apic_intr_exit time */ 655 #define APIC_REPROGRAM_MAX_TRIES 10000 656 657 /* Parameter to ioapic_init_intr(): Should ioapic ints be masked? */ 658 #define IOAPIC_MASK 1 659 #define IOAPIC_NOMASK 0 660 661 #define INTR_ROUND_ROBIN_WITH_AFFINITY 0 662 #define INTR_ROUND_ROBIN 1 663 #define INTR_LOWEST_PRIORITY 2 664 665 666 667 struct ioapic_reprogram_data { 668 boolean_t done; 669 apic_irq_t *irqp; 670 /* The CPU to which the int will be bound */ 671 int bindcpu; 672 /* # times the reprogram timeout was called */ 673 unsigned tries; 674 }; 675 676 /* The irq # is implicit in the array index: */ 677 extern struct ioapic_reprogram_data apic_reprogram_info[]; 678 679 extern void apic_intr_exit(int ipl, int irq); 680 extern int apic_probe_common(); 681 extern void apic_init_common(); 682 extern void ioapic_init_intr(); 683 extern void ioapic_disable_redirection(); 684 extern int apic_addspl_common(int irqno, int ipl, int min_ipl, int max_ipl); 685 extern int apic_delspl_common(int irqno, int ipl, int min_ipl, int max_ipl); 686 extern void apic_cleanup_busy(); 687 extern void apic_intr_redistribute(); 688 extern uchar_t apic_xlate_vector(uchar_t vector); 689 extern uchar_t apic_allocate_vector(int ipl, int irq, int pri); 690 extern void apic_free_vector(uchar_t vector); 691 extern int apic_allocate_irq(int irq); 692 extern uchar_t apic_bind_intr(dev_info_t *dip, int irq, uchar_t ioapicid, 693 uchar_t intin); 694 extern int apic_rebind(apic_irq_t *irq_ptr, int bind_cpu, 695 struct ioapic_reprogram_data *drep); 696 extern int apic_rebind_all(apic_irq_t *irq_ptr, int bind_cpu); 697 extern int apic_introp_xlate(dev_info_t *dip, struct intrspec *ispec, int type); 698 extern int apic_intr_ops(dev_info_t *dip, ddi_intr_handle_impl_t *hdlp, 699 psm_intr_op_t intr_op, int *result); 700 extern boolean_t apic_cpu_in_range(int cpu); 701 extern int apic_check_msi_support(); 702 extern apic_irq_t *apic_find_irq(dev_info_t *dip, struct intrspec *ispec, 703 int type); 704 extern int apic_navail_vector(dev_info_t *dip, int pri); 705 extern int apic_alloc_vectors(dev_info_t *dip, int inum, int count, int pri, 706 int type, int behavior); 707 extern void apic_free_vectors(dev_info_t *dip, int inum, int count, int pri, 708 int type); 709 extern int apic_get_vector_intr_info(int vecirq, 710 apic_get_intr_t *intr_params_p); 711 extern uchar_t apic_find_multi_vectors(int pri, int count); 712 extern int apic_setup_io_intr(void *p, int irq, boolean_t deferred); 713 extern uint32_t *mapin_apic(uint32_t addr, size_t len, int flags); 714 extern uint32_t *mapin_ioapic(uint32_t addr, size_t len, int flags); 715 extern void mapout_apic(caddr_t addr, size_t len); 716 extern void mapout_ioapic(caddr_t addr, size_t len); 717 extern uchar_t apic_modify_vector(uchar_t vector, int irq); 718 extern int apic_pci_msi_unconfigure(dev_info_t *rdip, int type, int inum); 719 extern int apic_pci_msi_disable_mode(dev_info_t *rdip, int type, int inum); 720 extern int apic_pci_msi_enable_mode(dev_info_t *rdip, int type, int inum); 721 722 extern volatile uint32_t *apicadr; /* virtual addr of local APIC */ 723 extern int apic_forceload; 724 extern apic_cpus_info_t *apic_cpus; 725 #ifdef _MACHDEP 726 extern cpuset_t apic_cpumask; 727 #endif 728 extern uint_t apic_flag; 729 extern uchar_t apic_ipltopri[MAXIPL+1]; 730 extern uchar_t apic_vector_to_irq[APIC_MAX_VECTOR+1]; 731 extern int apic_max_device_irq; 732 extern int apic_min_device_irq; 733 extern apic_irq_t *apic_irq_table[APIC_MAX_VECTOR+1]; 734 extern volatile uint32_t *apicioadr[MAX_IO_APIC]; 735 extern uchar_t apic_io_id[MAX_IO_APIC]; 736 extern lock_t apic_ioapic_lock; 737 extern uint32_t apic_physaddr[MAX_IO_APIC]; 738 extern kmutex_t airq_mutex; 739 extern int apic_first_avail_irq; 740 extern uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL]; 741 extern int apic_imcrp; 742 extern int apic_revector_pending; 743 extern char apic_level_intr[APIC_MAX_VECTOR+1]; 744 extern uchar_t apic_resv_vector[MAXIPL+1]; 745 extern int apic_sample_factor_redistribution; 746 extern int apic_int_busy_mark; 747 extern int apic_int_free_mark; 748 extern int apic_diff_for_redistribution; 749 extern int apic_poweroff_method; 750 extern int apic_enable_acpi; 751 extern int apic_nproc; 752 extern int apic_next_bind_cpu; 753 extern int apic_redistribute_sample_interval; 754 extern int apic_multi_msi_enable; 755 extern int apic_multi_msi_max; 756 extern int apic_sci_vect; 757 extern uchar_t apic_ipls[]; 758 759 760 #ifdef __cplusplus 761 } 762 #endif 763 764 #endif /* _SYS_APIC_APIC_H */ 765