1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/thread.h> 31 #include <sys/cpuvar.h> 32 #include <sys/t_lock.h> 33 #include <sys/param.h> 34 #include <sys/proc.h> 35 #include <sys/disp.h> 36 #include <sys/class.h> 37 #include <sys/cmn_err.h> 38 #include <sys/debug.h> 39 #include <sys/asm_linkage.h> 40 #include <sys/x_call.h> 41 #include <sys/systm.h> 42 #include <sys/var.h> 43 #include <sys/vtrace.h> 44 #include <vm/hat.h> 45 #include <vm/as.h> 46 #include <vm/seg_kmem.h> 47 #include <vm/seg_kp.h> 48 #include <sys/segments.h> 49 #include <sys/kmem.h> 50 #include <sys/stack.h> 51 #include <sys/smp_impldefs.h> 52 #include <sys/x86_archext.h> 53 #include <sys/machsystm.h> 54 #include <sys/traptrace.h> 55 #include <sys/clock.h> 56 #include <sys/cpc_impl.h> 57 #include <sys/pg.h> 58 #include <sys/cmt.h> 59 #include <sys/dtrace.h> 60 #include <sys/archsystm.h> 61 #include <sys/fp.h> 62 #include <sys/reboot.h> 63 #include <sys/kdi_machimpl.h> 64 #include <vm/hat_i86.h> 65 #include <sys/memnode.h> 66 #include <sys/pci_cfgspace.h> 67 #include <sys/mach_mmu.h> 68 #include <sys/sysmacros.h> 69 #include <sys/cpu_module.h> 70 71 struct cpu cpus[1]; /* CPU data */ 72 struct cpu *cpu[NCPU] = {&cpus[0]}; /* pointers to all CPUs */ 73 cpu_core_t cpu_core[NCPU]; /* cpu_core structures */ 74 75 /* 76 * Useful for disabling MP bring-up on a MP capable system. 77 */ 78 int use_mp = 1; 79 80 /* 81 * to be set by a PSM to indicate what cpus 82 * are sitting around on the system. 83 */ 84 cpuset_t mp_cpus; 85 86 /* 87 * This variable is used by the hat layer to decide whether or not 88 * critical sections are needed to prevent race conditions. For sun4m, 89 * this variable is set once enough MP initialization has been done in 90 * order to allow cross calls. 91 */ 92 int flushes_require_xcalls; 93 cpuset_t cpu_ready_set = 1; 94 95 static void mp_startup(void); 96 97 static void cpu_sep_enable(void); 98 static void cpu_sep_disable(void); 99 static void cpu_asysc_enable(void); 100 static void cpu_asysc_disable(void); 101 102 extern int tsc_gethrtime_enable; 103 104 /* 105 * Init CPU info - get CPU type info for processor_info system call. 106 */ 107 void 108 init_cpu_info(struct cpu *cp) 109 { 110 processor_info_t *pi = &cp->cpu_type_info; 111 char buf[CPU_IDSTRLEN]; 112 113 /* 114 * Get clock-frequency property for the CPU. 115 */ 116 pi->pi_clock = cpu_freq; 117 118 (void) strcpy(pi->pi_processor_type, "i386"); 119 if (fpu_exists) 120 (void) strcpy(pi->pi_fputypes, "i387 compatible"); 121 122 (void) cpuid_getidstr(cp, buf, sizeof (buf)); 123 124 cp->cpu_idstr = kmem_alloc(strlen(buf) + 1, KM_SLEEP); 125 (void) strcpy(cp->cpu_idstr, buf); 126 127 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_idstr); 128 129 (void) cpuid_getbrandstr(cp, buf, sizeof (buf)); 130 cp->cpu_brandstr = kmem_alloc(strlen(buf) + 1, KM_SLEEP); 131 (void) strcpy(cp->cpu_brandstr, buf); 132 133 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_brandstr); 134 } 135 136 /* 137 * Configure syscall support on this CPU. 138 */ 139 /*ARGSUSED*/ 140 static void 141 init_cpu_syscall(struct cpu *cp) 142 { 143 kpreempt_disable(); 144 145 #if defined(__amd64) 146 if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) { 147 148 #if !defined(__lint) 149 /* 150 * The syscall instruction imposes a certain ordering on 151 * segment selectors, so we double-check that ordering 152 * here. 153 */ 154 ASSERT(KDS_SEL == KCS_SEL + 8); 155 ASSERT(UDS_SEL == U32CS_SEL + 8); 156 ASSERT(UCS_SEL == U32CS_SEL + 16); 157 #endif 158 /* 159 * Turn syscall/sysret extensions on. 160 */ 161 cpu_asysc_enable(); 162 163 /* 164 * Program the magic registers .. 165 */ 166 wrmsr(MSR_AMD_STAR, 167 ((uint64_t)(U32CS_SEL << 16 | KCS_SEL)) << 32); 168 wrmsr(MSR_AMD_LSTAR, (uint64_t)(uintptr_t)sys_syscall); 169 wrmsr(MSR_AMD_CSTAR, (uint64_t)(uintptr_t)sys_syscall32); 170 171 /* 172 * This list of flags is masked off the incoming 173 * %rfl when we enter the kernel. 174 */ 175 wrmsr(MSR_AMD_SFMASK, (uint64_t)(uintptr_t)(PS_IE | PS_T)); 176 } 177 #endif 178 179 /* 180 * On 32-bit kernels, we use sysenter/sysexit because it's too 181 * hard to use syscall/sysret, and it is more portable anyway. 182 * 183 * On 64-bit kernels on Nocona machines, the 32-bit syscall 184 * variant isn't available to 32-bit applications, but sysenter is. 185 */ 186 if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) { 187 188 #if !defined(__lint) 189 /* 190 * The sysenter instruction imposes a certain ordering on 191 * segment selectors, so we double-check that ordering 192 * here. See "sysenter" in Intel document 245471-012, "IA-32 193 * Intel Architecture Software Developer's Manual Volume 2: 194 * Instruction Set Reference" 195 */ 196 ASSERT(KDS_SEL == KCS_SEL + 8); 197 198 ASSERT32(UCS_SEL == ((KCS_SEL + 16) | 3)); 199 ASSERT32(UDS_SEL == UCS_SEL + 8); 200 201 ASSERT64(U32CS_SEL == ((KCS_SEL + 16) | 3)); 202 ASSERT64(UDS_SEL == U32CS_SEL + 8); 203 #endif 204 205 cpu_sep_enable(); 206 207 /* 208 * resume() sets this value to the base of the threads stack 209 * via a context handler. 210 */ 211 wrmsr(MSR_INTC_SEP_ESP, 0); 212 wrmsr(MSR_INTC_SEP_EIP, (uint64_t)(uintptr_t)sys_sysenter); 213 } 214 215 kpreempt_enable(); 216 } 217 218 /* 219 * Multiprocessor initialization. 220 * 221 * Allocate and initialize the cpu structure, TRAPTRACE buffer, and the 222 * startup and idle threads for the specified CPU. 223 */ 224 struct cpu * 225 mp_startup_init(int cpun) 226 { 227 struct cpu *cp; 228 kthread_id_t tp; 229 caddr_t sp; 230 proc_t *procp; 231 extern void idle(); 232 233 #ifdef TRAPTRACE 234 trap_trace_ctl_t *ttc = &trap_trace_ctl[cpun]; 235 #endif 236 237 ASSERT(cpun < NCPU && cpu[cpun] == NULL); 238 239 cp = kmem_zalloc(sizeof (*cp), KM_SLEEP); 240 if (x86_feature & X86_MWAIT) 241 cp->cpu_m.mcpu_mwait = mach_alloc_mwait(CPU); 242 243 procp = curthread->t_procp; 244 245 mutex_enter(&cpu_lock); 246 /* 247 * Initialize the dispatcher first. 248 */ 249 disp_cpu_init(cp); 250 mutex_exit(&cpu_lock); 251 252 cpu_vm_data_init(cp); 253 254 /* 255 * Allocate and initialize the startup thread for this CPU. 256 * Interrupt and process switch stacks get allocated later 257 * when the CPU starts running. 258 */ 259 tp = thread_create(NULL, 0, NULL, NULL, 0, procp, 260 TS_STOPPED, maxclsyspri); 261 262 /* 263 * Set state to TS_ONPROC since this thread will start running 264 * as soon as the CPU comes online. 265 * 266 * All the other fields of the thread structure are setup by 267 * thread_create(). 268 */ 269 THREAD_ONPROC(tp, cp); 270 tp->t_preempt = 1; 271 tp->t_bound_cpu = cp; 272 tp->t_affinitycnt = 1; 273 tp->t_cpu = cp; 274 tp->t_disp_queue = cp->cpu_disp; 275 276 /* 277 * Setup thread to start in mp_startup. 278 */ 279 sp = tp->t_stk; 280 tp->t_pc = (uintptr_t)mp_startup; 281 tp->t_sp = (uintptr_t)(sp - MINFRAME); 282 #if defined(__amd64) 283 tp->t_sp -= STACK_ENTRY_ALIGN; /* fake a call */ 284 #endif 285 286 cp->cpu_id = cpun; 287 cp->cpu_self = cp; 288 cp->cpu_thread = tp; 289 cp->cpu_lwp = NULL; 290 cp->cpu_dispthread = tp; 291 cp->cpu_dispatch_pri = DISP_PRIO(tp); 292 293 /* 294 * cpu_base_spl must be set explicitly here to prevent any blocking 295 * operations in mp_startup from causing the spl of the cpu to drop 296 * to 0 (allowing device interrupts before we're ready) in resume(). 297 * cpu_base_spl MUST remain at LOCK_LEVEL until the cpu is CPU_READY. 298 * As an extra bit of security on DEBUG kernels, this is enforced with 299 * an assertion in mp_startup() -- before cpu_base_spl is set to its 300 * proper value. 301 */ 302 cp->cpu_base_spl = ipltospl(LOCK_LEVEL); 303 304 /* 305 * Now, initialize per-CPU idle thread for this CPU. 306 */ 307 tp = thread_create(NULL, PAGESIZE, idle, NULL, 0, procp, TS_ONPROC, -1); 308 309 cp->cpu_idle_thread = tp; 310 311 tp->t_preempt = 1; 312 tp->t_bound_cpu = cp; 313 tp->t_affinitycnt = 1; 314 tp->t_cpu = cp; 315 tp->t_disp_queue = cp->cpu_disp; 316 317 /* 318 * Bootstrap the CPU's PG data 319 */ 320 pg_cpu_bootstrap(cp); 321 322 /* 323 * Perform CPC initialization on the new CPU. 324 */ 325 kcpc_hw_init(cp); 326 327 /* 328 * Allocate virtual addresses for cpu_caddr1 and cpu_caddr2 329 * for each CPU. 330 */ 331 setup_vaddr_for_ppcopy(cp); 332 333 /* 334 * Allocate page for new GDT and initialize from current GDT. 335 */ 336 #if !defined(__lint) 337 ASSERT((sizeof (*cp->cpu_gdt) * NGDT) <= PAGESIZE); 338 #endif 339 cp->cpu_m.mcpu_gdt = kmem_zalloc(PAGESIZE, KM_SLEEP); 340 bcopy(CPU->cpu_m.mcpu_gdt, cp->cpu_m.mcpu_gdt, 341 (sizeof (*cp->cpu_m.mcpu_gdt) * NGDT)); 342 343 #if defined(__i386) 344 /* 345 * setup kernel %gs. 346 */ 347 set_usegd(&cp->cpu_gdt[GDT_GS], cp, sizeof (struct cpu) -1, SDT_MEMRWA, 348 SEL_KPL, 0, 1); 349 #endif 350 351 /* 352 * If we have more than one node, each cpu gets a copy of IDT 353 * local to its node. If this is a Pentium box, we use cpu 0's 354 * IDT. cpu 0's IDT has been made read-only to workaround the 355 * cmpxchgl register bug 356 */ 357 if (system_hardware.hd_nodes && x86_type != X86_TYPE_P5) { 358 struct machcpu *mcpu = &cp->cpu_m; 359 360 mcpu->mcpu_idt = kmem_alloc(sizeof (idt0), KM_SLEEP); 361 bcopy(idt0, mcpu->mcpu_idt, sizeof (idt0)); 362 } else { 363 cp->cpu_m.mcpu_idt = CPU->cpu_m.mcpu_idt; 364 } 365 366 /* 367 * Get interrupt priority data from cpu 0. 368 */ 369 cp->cpu_pri_data = CPU->cpu_pri_data; 370 371 /* 372 * alloc space for cpuid info 373 */ 374 cpuid_alloc_space(cp); 375 376 hat_cpu_online(cp); 377 378 #ifdef TRAPTRACE 379 /* 380 * If this is a TRAPTRACE kernel, allocate TRAPTRACE buffers 381 */ 382 ttc->ttc_first = (uintptr_t)kmem_zalloc(trap_trace_bufsize, KM_SLEEP); 383 ttc->ttc_next = ttc->ttc_first; 384 ttc->ttc_limit = ttc->ttc_first + trap_trace_bufsize; 385 #endif 386 /* 387 * Record that we have another CPU. 388 */ 389 mutex_enter(&cpu_lock); 390 /* 391 * Initialize the interrupt threads for this CPU 392 */ 393 cpu_intr_alloc(cp, NINTR_THREADS); 394 /* 395 * Add CPU to list of available CPUs. It'll be on the active list 396 * after mp_startup(). 397 */ 398 cpu_add_unit(cp); 399 mutex_exit(&cpu_lock); 400 401 return (cp); 402 } 403 404 /* 405 * Undo what was done in mp_startup_init 406 */ 407 static void 408 mp_startup_fini(struct cpu *cp, int error) 409 { 410 mutex_enter(&cpu_lock); 411 412 /* 413 * Remove the CPU from the list of available CPUs. 414 */ 415 cpu_del_unit(cp->cpu_id); 416 417 if (error == ETIMEDOUT) { 418 /* 419 * The cpu was started, but never *seemed* to run any 420 * code in the kernel; it's probably off spinning in its 421 * own private world, though with potential references to 422 * our kmem-allocated IDTs and GDTs (for example). 423 * 424 * Worse still, it may actually wake up some time later, 425 * so rather than guess what it might or might not do, we 426 * leave the fundamental data structures intact. 427 */ 428 cp->cpu_flags = 0; 429 mutex_exit(&cpu_lock); 430 return; 431 } 432 433 /* 434 * At this point, the only threads bound to this CPU should 435 * special per-cpu threads: it's idle thread, it's pause threads, 436 * and it's interrupt threads. Clean these up. 437 */ 438 cpu_destroy_bound_threads(cp); 439 cp->cpu_idle_thread = NULL; 440 441 /* 442 * Free the interrupt stack. 443 */ 444 segkp_release(segkp, 445 cp->cpu_intr_stack - (INTR_STACK_SIZE - SA(MINFRAME))); 446 447 mutex_exit(&cpu_lock); 448 449 #ifdef TRAPTRACE 450 /* 451 * Discard the trap trace buffer 452 */ 453 { 454 trap_trace_ctl_t *ttc = &trap_trace_ctl[cp->cpu_id]; 455 456 kmem_free((void *)ttc->ttc_first, trap_trace_bufsize); 457 ttc->ttc_first = NULL; 458 } 459 #endif 460 461 hat_cpu_offline(cp); 462 463 cpuid_free_space(cp); 464 465 if (cp->cpu_m.mcpu_idt != CPU->cpu_m.mcpu_idt) 466 kmem_free(cp->cpu_m.mcpu_idt, sizeof (idt0)); 467 cp->cpu_m.mcpu_idt = NULL; 468 469 kmem_free(cp->cpu_m.mcpu_gdt, PAGESIZE); 470 cp->cpu_m.mcpu_gdt = NULL; 471 472 teardown_vaddr_for_ppcopy(cp); 473 474 kcpc_hw_fini(cp); 475 476 cp->cpu_dispthread = NULL; 477 cp->cpu_thread = NULL; /* discarded by cpu_destroy_bound_threads() */ 478 479 cpu_vm_data_destroy(cp); 480 481 mutex_enter(&cpu_lock); 482 disp_cpu_fini(cp); 483 mutex_exit(&cpu_lock); 484 485 kmem_free(cp, sizeof (*cp)); 486 } 487 488 /* 489 * Apply workarounds for known errata, and warn about those that are absent. 490 * 491 * System vendors occasionally create configurations which contain different 492 * revisions of the CPUs that are almost but not exactly the same. At the 493 * time of writing, this meant that their clock rates were the same, their 494 * feature sets were the same, but the required workaround were -not- 495 * necessarily the same. So, this routine is invoked on -every- CPU soon 496 * after starting to make sure that the resulting system contains the most 497 * pessimal set of workarounds needed to cope with *any* of the CPUs in the 498 * system. 499 * 500 * workaround_errata is invoked early in mlsetup() for CPU 0, and in 501 * mp_startup() for all slave CPUs. Slaves process workaround_errata prior 502 * to acknowledging their readiness to the master, so this routine will 503 * never be executed by multiple CPUs in parallel, thus making updates to 504 * global data safe. 505 * 506 * These workarounds are based on Rev 3.57 of the Revision Guide for 507 * AMD Athlon(tm) 64 and AMD Opteron(tm) Processors, August 2005. 508 */ 509 510 #if defined(OPTERON_ERRATUM_88) 511 int opteron_erratum_88; /* if non-zero -> at least one cpu has it */ 512 #endif 513 514 #if defined(OPTERON_ERRATUM_91) 515 int opteron_erratum_91; /* if non-zero -> at least one cpu has it */ 516 #endif 517 518 #if defined(OPTERON_ERRATUM_93) 519 int opteron_erratum_93; /* if non-zero -> at least one cpu has it */ 520 #endif 521 522 #if defined(OPTERON_ERRATUM_95) 523 int opteron_erratum_95; /* if non-zero -> at least one cpu has it */ 524 #endif 525 526 #if defined(OPTERON_ERRATUM_100) 527 int opteron_erratum_100; /* if non-zero -> at least one cpu has it */ 528 #endif 529 530 #if defined(OPTERON_ERRATUM_108) 531 int opteron_erratum_108; /* if non-zero -> at least one cpu has it */ 532 #endif 533 534 #if defined(OPTERON_ERRATUM_109) 535 int opteron_erratum_109; /* if non-zero -> at least one cpu has it */ 536 #endif 537 538 #if defined(OPTERON_ERRATUM_121) 539 int opteron_erratum_121; /* if non-zero -> at least one cpu has it */ 540 #endif 541 542 #if defined(OPTERON_ERRATUM_122) 543 int opteron_erratum_122; /* if non-zero -> at least one cpu has it */ 544 #endif 545 546 #if defined(OPTERON_ERRATUM_123) 547 int opteron_erratum_123; /* if non-zero -> at least one cpu has it */ 548 #endif 549 550 #if defined(OPTERON_ERRATUM_131) 551 int opteron_erratum_131; /* if non-zero -> at least one cpu has it */ 552 #endif 553 554 #if defined(OPTERON_WORKAROUND_6336786) 555 int opteron_workaround_6336786; /* non-zero -> WA relevant and applied */ 556 int opteron_workaround_6336786_UP = 0; /* Not needed for UP */ 557 #endif 558 559 #if defined(OPTERON_WORKAROUND_6323525) 560 int opteron_workaround_6323525; /* if non-zero -> at least one cpu has it */ 561 #endif 562 563 static void 564 workaround_warning(cpu_t *cp, uint_t erratum) 565 { 566 cmn_err(CE_WARN, "cpu%d: no workaround for erratum %u", 567 cp->cpu_id, erratum); 568 } 569 570 static void 571 workaround_applied(uint_t erratum) 572 { 573 if (erratum > 1000000) 574 cmn_err(CE_CONT, "?workaround applied for cpu issue #%d\n", 575 erratum); 576 else 577 cmn_err(CE_CONT, "?workaround applied for cpu erratum #%d\n", 578 erratum); 579 } 580 581 static void 582 msr_warning(cpu_t *cp, const char *rw, uint_t msr, int error) 583 { 584 cmn_err(CE_WARN, "cpu%d: couldn't %smsr 0x%x, error %d", 585 cp->cpu_id, rw, msr, error); 586 } 587 588 uint_t 589 workaround_errata(struct cpu *cpu) 590 { 591 uint_t missing = 0; 592 593 ASSERT(cpu == CPU); 594 595 /*LINTED*/ 596 if (cpuid_opteron_erratum(cpu, 88) > 0) { 597 /* 598 * SWAPGS May Fail To Read Correct GS Base 599 */ 600 #if defined(OPTERON_ERRATUM_88) 601 /* 602 * The workaround is an mfence in the relevant assembler code 603 */ 604 opteron_erratum_88++; 605 #else 606 workaround_warning(cpu, 88); 607 missing++; 608 #endif 609 } 610 611 if (cpuid_opteron_erratum(cpu, 91) > 0) { 612 /* 613 * Software Prefetches May Report A Page Fault 614 */ 615 #if defined(OPTERON_ERRATUM_91) 616 /* 617 * fix is in trap.c 618 */ 619 opteron_erratum_91++; 620 #else 621 workaround_warning(cpu, 91); 622 missing++; 623 #endif 624 } 625 626 if (cpuid_opteron_erratum(cpu, 93) > 0) { 627 /* 628 * RSM Auto-Halt Restart Returns to Incorrect RIP 629 */ 630 #if defined(OPTERON_ERRATUM_93) 631 /* 632 * fix is in trap.c 633 */ 634 opteron_erratum_93++; 635 #else 636 workaround_warning(cpu, 93); 637 missing++; 638 #endif 639 } 640 641 /*LINTED*/ 642 if (cpuid_opteron_erratum(cpu, 95) > 0) { 643 /* 644 * RET Instruction May Return to Incorrect EIP 645 */ 646 #if defined(OPTERON_ERRATUM_95) 647 #if defined(_LP64) 648 /* 649 * Workaround this by ensuring that 32-bit user code and 650 * 64-bit kernel code never occupy the same address 651 * range mod 4G. 652 */ 653 if (_userlimit32 > 0xc0000000ul) 654 *(uintptr_t *)&_userlimit32 = 0xc0000000ul; 655 656 /*LINTED*/ 657 ASSERT((uint32_t)COREHEAP_BASE == 0xc0000000u); 658 opteron_erratum_95++; 659 #endif /* _LP64 */ 660 #else 661 workaround_warning(cpu, 95); 662 missing++; 663 #endif 664 } 665 666 if (cpuid_opteron_erratum(cpu, 100) > 0) { 667 /* 668 * Compatibility Mode Branches Transfer to Illegal Address 669 */ 670 #if defined(OPTERON_ERRATUM_100) 671 /* 672 * fix is in trap.c 673 */ 674 opteron_erratum_100++; 675 #else 676 workaround_warning(cpu, 100); 677 missing++; 678 #endif 679 } 680 681 /*LINTED*/ 682 if (cpuid_opteron_erratum(cpu, 108) > 0) { 683 /* 684 * CPUID Instruction May Return Incorrect Model Number In 685 * Some Processors 686 */ 687 #if defined(OPTERON_ERRATUM_108) 688 /* 689 * (Our cpuid-handling code corrects the model number on 690 * those processors) 691 */ 692 #else 693 workaround_warning(cpu, 108); 694 missing++; 695 #endif 696 } 697 698 /*LINTED*/ 699 if (cpuid_opteron_erratum(cpu, 109) > 0) do { 700 /* 701 * Certain Reverse REP MOVS May Produce Unpredictable Behaviour 702 */ 703 #if defined(OPTERON_ERRATUM_109) 704 /* 705 * The "workaround" is to print a warning to upgrade the BIOS 706 */ 707 uint64_t value; 708 const uint_t msr = MSR_AMD_PATCHLEVEL; 709 int err; 710 711 if ((err = checked_rdmsr(msr, &value)) != 0) { 712 msr_warning(cpu, "rd", msr, err); 713 workaround_warning(cpu, 109); 714 missing++; 715 } 716 if (value == 0) 717 opteron_erratum_109++; 718 #else 719 workaround_warning(cpu, 109); 720 missing++; 721 #endif 722 /*CONSTANTCONDITION*/ 723 } while (0); 724 725 /*LINTED*/ 726 if (cpuid_opteron_erratum(cpu, 121) > 0) { 727 /* 728 * Sequential Execution Across Non_Canonical Boundary Caused 729 * Processor Hang 730 */ 731 #if defined(OPTERON_ERRATUM_121) 732 #if defined(_LP64) 733 /* 734 * Erratum 121 is only present in long (64 bit) mode. 735 * Workaround is to include the page immediately before the 736 * va hole to eliminate the possibility of system hangs due to 737 * sequential execution across the va hole boundary. 738 */ 739 if (opteron_erratum_121) 740 opteron_erratum_121++; 741 else { 742 if (hole_start) { 743 hole_start -= PAGESIZE; 744 } else { 745 /* 746 * hole_start not yet initialized by 747 * mmu_init. Initialize hole_start 748 * with value to be subtracted. 749 */ 750 hole_start = PAGESIZE; 751 } 752 opteron_erratum_121++; 753 } 754 #endif /* _LP64 */ 755 #else 756 workaround_warning(cpu, 121); 757 missing++; 758 #endif 759 } 760 761 /*LINTED*/ 762 if (cpuid_opteron_erratum(cpu, 122) > 0) do { 763 /* 764 * TLB Flush Filter May Cause Coherency Problem in 765 * Multiprocessor Systems 766 */ 767 #if defined(OPTERON_ERRATUM_122) 768 uint64_t value; 769 const uint_t msr = MSR_AMD_HWCR; 770 int error; 771 772 /* 773 * Erratum 122 is only present in MP configurations (multi-core 774 * or multi-processor). 775 */ 776 if (!opteron_erratum_122 && lgrp_plat_node_cnt == 1 && 777 cpuid_get_ncpu_per_chip(cpu) == 1) 778 break; 779 780 /* disable TLB Flush Filter */ 781 782 if ((error = checked_rdmsr(msr, &value)) != 0) { 783 msr_warning(cpu, "rd", msr, error); 784 workaround_warning(cpu, 122); 785 missing++; 786 } else { 787 value |= (uint64_t)AMD_HWCR_FFDIS; 788 if ((error = checked_wrmsr(msr, value)) != 0) { 789 msr_warning(cpu, "wr", msr, error); 790 workaround_warning(cpu, 122); 791 missing++; 792 } 793 } 794 opteron_erratum_122++; 795 #else 796 workaround_warning(cpu, 122); 797 missing++; 798 #endif 799 /*CONSTANTCONDITION*/ 800 } while (0); 801 802 /*LINTED*/ 803 if (cpuid_opteron_erratum(cpu, 123) > 0) do { 804 /* 805 * Bypassed Reads May Cause Data Corruption of System Hang in 806 * Dual Core Processors 807 */ 808 #if defined(OPTERON_ERRATUM_123) 809 uint64_t value; 810 const uint_t msr = MSR_AMD_PATCHLEVEL; 811 int err; 812 813 /* 814 * Erratum 123 applies only to multi-core cpus. 815 */ 816 if (cpuid_get_ncpu_per_chip(cpu) < 2) 817 break; 818 819 /* 820 * The "workaround" is to print a warning to upgrade the BIOS 821 */ 822 if ((err = checked_rdmsr(msr, &value)) != 0) { 823 msr_warning(cpu, "rd", msr, err); 824 workaround_warning(cpu, 123); 825 missing++; 826 } 827 if (value == 0) 828 opteron_erratum_123++; 829 #else 830 workaround_warning(cpu, 123); 831 missing++; 832 833 #endif 834 /*CONSTANTCONDITION*/ 835 } while (0); 836 837 /*LINTED*/ 838 if (cpuid_opteron_erratum(cpu, 131) > 0) do { 839 /* 840 * Multiprocessor Systems with Four or More Cores May Deadlock 841 * Waiting for a Probe Response 842 */ 843 #if defined(OPTERON_ERRATUM_131) 844 uint64_t nbcfg; 845 const uint_t msr = MSR_AMD_NB_CFG; 846 const uint64_t wabits = 847 AMD_NB_CFG_SRQ_HEARTBEAT | AMD_NB_CFG_SRQ_SPR; 848 int error; 849 850 /* 851 * Erratum 131 applies to any system with four or more cores. 852 */ 853 if (opteron_erratum_131) 854 break; 855 856 if (lgrp_plat_node_cnt * cpuid_get_ncpu_per_chip(cpu) < 4) 857 break; 858 859 /* 860 * Print a warning if neither of the workarounds for 861 * erratum 131 is present. 862 */ 863 if ((error = checked_rdmsr(msr, &nbcfg)) != 0) { 864 msr_warning(cpu, "rd", msr, error); 865 workaround_warning(cpu, 131); 866 missing++; 867 } else if ((nbcfg & wabits) == 0) { 868 opteron_erratum_131++; 869 } else { 870 /* cannot have both workarounds set */ 871 ASSERT((nbcfg & wabits) != wabits); 872 } 873 #else 874 workaround_warning(cpu, 131); 875 missing++; 876 #endif 877 /*CONSTANTCONDITION*/ 878 } while (0); 879 880 /* 881 * This isn't really an erratum, but for convenience the 882 * detection/workaround code lives here and in cpuid_opteron_erratum. 883 */ 884 if (cpuid_opteron_erratum(cpu, 6336786) > 0) { 885 #if defined(OPTERON_WORKAROUND_6336786) 886 /* 887 * Disable C1-Clock ramping on multi-core/multi-processor 888 * K8 platforms to guard against TSC drift. 889 */ 890 if (opteron_workaround_6336786) { 891 opteron_workaround_6336786++; 892 } else if ((lgrp_plat_node_cnt * 893 cpuid_get_ncpu_per_chip(cpu) > 1) || 894 opteron_workaround_6336786_UP) { 895 int node; 896 uint8_t data; 897 898 for (node = 0; node < lgrp_plat_node_cnt; node++) { 899 /* 900 * Clear PMM7[1:0] (function 3, offset 0x87) 901 * Northbridge device is the node id + 24. 902 */ 903 data = pci_getb_func(0, node + 24, 3, 0x87); 904 data &= 0xFC; 905 pci_putb_func(0, node + 24, 3, 0x87, data); 906 } 907 opteron_workaround_6336786++; 908 } 909 #else 910 workaround_warning(cpu, 6336786); 911 missing++; 912 #endif 913 } 914 915 /*LINTED*/ 916 /* 917 * Mutex primitives don't work as expected. 918 */ 919 if (cpuid_opteron_erratum(cpu, 6323525) > 0) { 920 #if defined(OPTERON_WORKAROUND_6323525) 921 /* 922 * This problem only occurs with 2 or more cores. If bit in 923 * MSR_BU_CFG set, then not applicable. The workaround 924 * is to patch the semaphone routines with the lfence 925 * instruction to provide necessary load memory barrier with 926 * possible subsequent read-modify-write ops. 927 * 928 * It is too early in boot to call the patch routine so 929 * set erratum variable to be done in startup_end(). 930 */ 931 if (opteron_workaround_6323525) { 932 opteron_workaround_6323525++; 933 } else if ((x86_feature & X86_SSE2) && ((lgrp_plat_node_cnt * 934 cpuid_get_ncpu_per_chip(cpu)) > 1)) { 935 if ((xrdmsr(MSR_BU_CFG) & 0x02) == 0) 936 opteron_workaround_6323525++; 937 } 938 #else 939 workaround_warning(cpu, 6323525); 940 missing++; 941 #endif 942 } 943 944 return (missing); 945 } 946 947 void 948 workaround_errata_end() 949 { 950 #if defined(OPTERON_ERRATUM_88) 951 if (opteron_erratum_88) 952 workaround_applied(88); 953 #endif 954 #if defined(OPTERON_ERRATUM_91) 955 if (opteron_erratum_91) 956 workaround_applied(91); 957 #endif 958 #if defined(OPTERON_ERRATUM_93) 959 if (opteron_erratum_93) 960 workaround_applied(93); 961 #endif 962 #if defined(OPTERON_ERRATUM_95) 963 if (opteron_erratum_95) 964 workaround_applied(95); 965 #endif 966 #if defined(OPTERON_ERRATUM_100) 967 if (opteron_erratum_100) 968 workaround_applied(100); 969 #endif 970 #if defined(OPTERON_ERRATUM_108) 971 if (opteron_erratum_108) 972 workaround_applied(108); 973 #endif 974 #if defined(OPTERON_ERRATUM_109) 975 if (opteron_erratum_109) { 976 cmn_err(CE_WARN, 977 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 978 " processor\nerratum 109 was not detected; updating your" 979 " system's BIOS to a version\ncontaining this" 980 " microcode patch is HIGHLY recommended or erroneous" 981 " system\noperation may occur.\n"); 982 } 983 #endif 984 #if defined(OPTERON_ERRATUM_121) 985 if (opteron_erratum_121) 986 workaround_applied(121); 987 #endif 988 #if defined(OPTERON_ERRATUM_122) 989 if (opteron_erratum_122) 990 workaround_applied(122); 991 #endif 992 #if defined(OPTERON_ERRATUM_123) 993 if (opteron_erratum_123) { 994 cmn_err(CE_WARN, 995 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 996 " processor\nerratum 123 was not detected; updating your" 997 " system's BIOS to a version\ncontaining this" 998 " microcode patch is HIGHLY recommended or erroneous" 999 " system\noperation may occur.\n"); 1000 } 1001 #endif 1002 #if defined(OPTERON_ERRATUM_131) 1003 if (opteron_erratum_131) { 1004 cmn_err(CE_WARN, 1005 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 1006 " processor\nerratum 131 was not detected; updating your" 1007 " system's BIOS to a version\ncontaining this" 1008 " microcode patch is HIGHLY recommended or erroneous" 1009 " system\noperation may occur.\n"); 1010 } 1011 #endif 1012 #if defined(OPTERON_WORKAROUND_6336786) 1013 if (opteron_workaround_6336786) 1014 workaround_applied(6336786); 1015 #endif 1016 #if defined(OPTERON_WORKAROUND_6323525) 1017 if (opteron_workaround_6323525) 1018 workaround_applied(6323525); 1019 #endif 1020 } 1021 1022 static cpuset_t procset; 1023 1024 /* 1025 * Start a single cpu, assuming that the kernel context is available 1026 * to successfully start another cpu. 1027 * 1028 * (For example, real mode code is mapped into the right place 1029 * in memory and is ready to be run.) 1030 */ 1031 int 1032 start_cpu(processorid_t who) 1033 { 1034 void *ctx; 1035 cpu_t *cp; 1036 int delays; 1037 int error = 0; 1038 1039 ASSERT(who != 0); 1040 1041 /* 1042 * Check if there's at least a Mbyte of kmem available 1043 * before attempting to start the cpu. 1044 */ 1045 if (kmem_avail() < 1024 * 1024) { 1046 /* 1047 * Kick off a reap in case that helps us with 1048 * later attempts .. 1049 */ 1050 kmem_reap(); 1051 return (ENOMEM); 1052 } 1053 1054 cp = mp_startup_init(who); 1055 if ((ctx = mach_cpucontext_alloc(cp)) == NULL || 1056 (error = mach_cpu_start(cp, ctx)) != 0) { 1057 1058 /* 1059 * Something went wrong before we even started it 1060 */ 1061 if (ctx) 1062 cmn_err(CE_WARN, 1063 "cpu%d: failed to start error %d", 1064 cp->cpu_id, error); 1065 else 1066 cmn_err(CE_WARN, 1067 "cpu%d: failed to allocate context", cp->cpu_id); 1068 1069 if (ctx) 1070 mach_cpucontext_free(cp, ctx, error); 1071 else 1072 error = EAGAIN; /* hmm. */ 1073 mp_startup_fini(cp, error); 1074 return (error); 1075 } 1076 1077 for (delays = 0; !CPU_IN_SET(procset, who); delays++) { 1078 if (delays == 500) { 1079 /* 1080 * After five seconds, things are probably looking 1081 * a bit bleak - explain the hang. 1082 */ 1083 cmn_err(CE_NOTE, "cpu%d: started, " 1084 "but not running in the kernel yet", who); 1085 } else if (delays > 2000) { 1086 /* 1087 * We waited at least 20 seconds, bail .. 1088 */ 1089 error = ETIMEDOUT; 1090 cmn_err(CE_WARN, "cpu%d: timed out", who); 1091 mach_cpucontext_free(cp, ctx, error); 1092 mp_startup_fini(cp, error); 1093 return (error); 1094 } 1095 1096 /* 1097 * wait at least 10ms, then check again.. 1098 */ 1099 delay(USEC_TO_TICK_ROUNDUP(10000)); 1100 } 1101 1102 mach_cpucontext_free(cp, ctx, 0); 1103 1104 if (tsc_gethrtime_enable) 1105 tsc_sync_master(who); 1106 1107 if (dtrace_cpu_init != NULL) { 1108 /* 1109 * DTrace CPU initialization expects cpu_lock to be held. 1110 */ 1111 mutex_enter(&cpu_lock); 1112 (*dtrace_cpu_init)(who); 1113 mutex_exit(&cpu_lock); 1114 } 1115 1116 while (!CPU_IN_SET(cpu_ready_set, who)) 1117 delay(1); 1118 1119 return (0); 1120 } 1121 1122 1123 /*ARGSUSED*/ 1124 void 1125 start_other_cpus(int cprboot) 1126 { 1127 uint_t who; 1128 uint_t skipped = 0; 1129 uint_t bootcpuid = 0; 1130 1131 /* 1132 * Initialize our own cpu_info. 1133 */ 1134 init_cpu_info(CPU); 1135 1136 /* 1137 * Initialize our syscall handlers 1138 */ 1139 init_cpu_syscall(CPU); 1140 1141 /* 1142 * Take the boot cpu out of the mp_cpus set because we know 1143 * it's already running. Add it to the cpu_ready_set for 1144 * precisely the same reason. 1145 */ 1146 CPUSET_DEL(mp_cpus, bootcpuid); 1147 CPUSET_ADD(cpu_ready_set, bootcpuid); 1148 1149 /* 1150 * if only 1 cpu or not using MP, skip the rest of this 1151 */ 1152 if (CPUSET_ISNULL(mp_cpus) || use_mp == 0) { 1153 if (use_mp == 0) 1154 cmn_err(CE_CONT, "?***** Not in MP mode\n"); 1155 goto done; 1156 } 1157 1158 /* 1159 * perform such initialization as is needed 1160 * to be able to take CPUs on- and off-line. 1161 */ 1162 cpu_pause_init(); 1163 1164 xc_init(); /* initialize processor crosscalls */ 1165 1166 if (mach_cpucontext_init() != 0) 1167 goto done; 1168 1169 flushes_require_xcalls = 1; 1170 1171 /* 1172 * We lock our affinity to the master CPU to ensure that all slave CPUs 1173 * do their TSC syncs with the same CPU. 1174 */ 1175 affinity_set(CPU_CURRENT); 1176 1177 for (who = 0; who < NCPU; who++) { 1178 1179 if (!CPU_IN_SET(mp_cpus, who)) 1180 continue; 1181 ASSERT(who != bootcpuid); 1182 if (ncpus >= max_ncpus) { 1183 skipped = who; 1184 continue; 1185 } 1186 if (start_cpu(who) != 0) 1187 CPUSET_DEL(mp_cpus, who); 1188 } 1189 1190 affinity_clear(); 1191 1192 if (skipped) { 1193 cmn_err(CE_NOTE, 1194 "System detected %d cpus, but " 1195 "only %d cpu(s) were enabled during boot.", 1196 skipped + 1, ncpus); 1197 cmn_err(CE_NOTE, 1198 "Use \"boot-ncpus\" parameter to enable more CPU(s). " 1199 "See eeprom(1M)."); 1200 } 1201 1202 done: 1203 workaround_errata_end(); 1204 mach_cpucontext_fini(); 1205 1206 cmi_post_mpstartup(); 1207 } 1208 1209 /* 1210 * Dummy functions - no i86pc platforms support dynamic cpu allocation. 1211 */ 1212 /*ARGSUSED*/ 1213 int 1214 mp_cpu_configure(int cpuid) 1215 { 1216 return (ENOTSUP); /* not supported */ 1217 } 1218 1219 /*ARGSUSED*/ 1220 int 1221 mp_cpu_unconfigure(int cpuid) 1222 { 1223 return (ENOTSUP); /* not supported */ 1224 } 1225 1226 /* 1227 * Startup function for 'other' CPUs (besides boot cpu). 1228 * Called from real_mode_start. 1229 * 1230 * WARNING: until CPU_READY is set, mp_startup and routines called by 1231 * mp_startup should not call routines (e.g. kmem_free) that could call 1232 * hat_unload which requires CPU_READY to be set. 1233 */ 1234 void 1235 mp_startup(void) 1236 { 1237 struct cpu *cp = CPU; 1238 uint_t new_x86_feature; 1239 1240 /* 1241 * We need to get TSC on this proc synced (i.e., any delta 1242 * from cpu0 accounted for) as soon as we can, because many 1243 * many things use gethrtime/pc_gethrestime, including 1244 * interrupts, cmn_err, etc. 1245 */ 1246 1247 /* Let cpu0 continue into tsc_sync_master() */ 1248 CPUSET_ATOMIC_ADD(procset, cp->cpu_id); 1249 1250 if (tsc_gethrtime_enable) 1251 tsc_sync_slave(); 1252 1253 /* 1254 * Once this was done from assembly, but it's safer here; if 1255 * it blocks, we need to be able to swtch() to and from, and 1256 * since we get here by calling t_pc, we need to do that call 1257 * before swtch() overwrites it. 1258 */ 1259 1260 (void) (*ap_mlsetup)(); 1261 1262 new_x86_feature = cpuid_pass1(cp); 1263 1264 /* 1265 * We need to Sync MTRR with cpu0's MTRR. We have to do 1266 * this with interrupts disabled. 1267 */ 1268 if (x86_feature & X86_MTRR) 1269 mtrr_sync(); 1270 1271 /* 1272 * Set up TSC_AUX to contain the cpuid for this processor 1273 * for the rdtscp instruction. 1274 */ 1275 if (x86_feature & X86_TSCP) 1276 (void) wrmsr(MSR_AMD_TSCAUX, cp->cpu_id); 1277 1278 /* 1279 * Initialize this CPU's syscall handlers 1280 */ 1281 init_cpu_syscall(cp); 1282 1283 /* 1284 * Enable interrupts with spl set to LOCK_LEVEL. LOCK_LEVEL is the 1285 * highest level at which a routine is permitted to block on 1286 * an adaptive mutex (allows for cpu poke interrupt in case 1287 * the cpu is blocked on a mutex and halts). Setting LOCK_LEVEL blocks 1288 * device interrupts that may end up in the hat layer issuing cross 1289 * calls before CPU_READY is set. 1290 */ 1291 splx(ipltospl(LOCK_LEVEL)); 1292 sti(); 1293 1294 /* 1295 * Do a sanity check to make sure this new CPU is a sane thing 1296 * to add to the collection of processors running this system. 1297 * 1298 * XXX Clearly this needs to get more sophisticated, if x86 1299 * systems start to get built out of heterogenous CPUs; as is 1300 * likely to happen once the number of processors in a configuration 1301 * gets large enough. 1302 */ 1303 if ((x86_feature & new_x86_feature) != x86_feature) { 1304 cmn_err(CE_CONT, "?cpu%d: %b\n", 1305 cp->cpu_id, new_x86_feature, FMT_X86_FEATURE); 1306 cmn_err(CE_WARN, "cpu%d feature mismatch", cp->cpu_id); 1307 } 1308 1309 /* 1310 * We do not support cpus with mixed monitor/mwait support if the 1311 * boot cpu supports monitor/mwait. 1312 */ 1313 if ((x86_feature & ~new_x86_feature) & X86_MWAIT) 1314 panic("unsupported mixed cpu monitor/mwait support detected"); 1315 1316 /* 1317 * We could be more sophisticated here, and just mark the CPU 1318 * as "faulted" but at this point we'll opt for the easier 1319 * answer of dieing horribly. Provided the boot cpu is ok, 1320 * the system can be recovered by booting with use_mp set to zero. 1321 */ 1322 if (workaround_errata(cp) != 0) 1323 panic("critical workaround(s) missing for cpu%d", cp->cpu_id); 1324 1325 cpuid_pass2(cp); 1326 cpuid_pass3(cp); 1327 (void) cpuid_pass4(cp); 1328 1329 init_cpu_info(cp); 1330 1331 mutex_enter(&cpu_lock); 1332 /* 1333 * Processor group initialization for this CPU is dependent on the 1334 * cpuid probing, which must be done in the context of the current 1335 * CPU. 1336 */ 1337 pghw_physid_create(cp); 1338 pg_cpu_init(cp); 1339 pg_cmt_cpu_startup(cp); 1340 1341 cp->cpu_flags |= CPU_RUNNING | CPU_READY | CPU_ENABLE | CPU_EXISTS; 1342 cpu_add_active(cp); 1343 1344 if (dtrace_cpu_init != NULL) { 1345 (*dtrace_cpu_init)(cp->cpu_id); 1346 } 1347 1348 mutex_exit(&cpu_lock); 1349 1350 /* 1351 * Enable preemption here so that contention for any locks acquired 1352 * later in mp_startup may be preempted if the thread owning those 1353 * locks is continously executing on other CPUs (for example, this 1354 * CPU must be preemptible to allow other CPUs to pause it during their 1355 * startup phases). It's safe to enable preemption here because the 1356 * CPU state is pretty-much fully constructed. 1357 */ 1358 curthread->t_preempt = 0; 1359 1360 add_cpunode2devtree(cp->cpu_id, cp->cpu_m.mcpu_cpi); 1361 1362 /* The base spl should still be at LOCK LEVEL here */ 1363 ASSERT(cp->cpu_base_spl == ipltospl(LOCK_LEVEL)); 1364 set_base_spl(); /* Restore the spl to its proper value */ 1365 1366 (void) spl0(); /* enable interrupts */ 1367 1368 /* 1369 * Set up the CPU module for this CPU. This can't be done before 1370 * this CPU is made CPU_READY, because we may (in heterogeneous systems) 1371 * need to go load another CPU module. The act of attempting to load 1372 * a module may trigger a cross-call, which will ASSERT unless this 1373 * cpu is CPU_READY. 1374 */ 1375 cmi_init(); 1376 1377 if (x86_feature & X86_MCA) 1378 cmi_mca_init(); 1379 1380 if (boothowto & RB_DEBUG) 1381 kdi_cpu_init(); 1382 1383 /* 1384 * Setting the bit in cpu_ready_set must be the last operation in 1385 * processor initialization; the boot CPU will continue to boot once 1386 * it sees this bit set for all active CPUs. 1387 */ 1388 CPUSET_ATOMIC_ADD(cpu_ready_set, cp->cpu_id); 1389 1390 /* 1391 * Because mp_startup() gets fired off after init() starts, we 1392 * can't use the '?' trick to do 'boot -v' printing - so we 1393 * always direct the 'cpu .. online' messages to the log. 1394 */ 1395 cmn_err(CE_CONT, "!cpu%d initialization complete - online\n", 1396 cp->cpu_id); 1397 1398 /* 1399 * Now we are done with the startup thread, so free it up. 1400 */ 1401 thread_exit(); 1402 panic("mp_startup: cannot return"); 1403 /*NOTREACHED*/ 1404 } 1405 1406 1407 /* 1408 * Start CPU on user request. 1409 */ 1410 /* ARGSUSED */ 1411 int 1412 mp_cpu_start(struct cpu *cp) 1413 { 1414 ASSERT(MUTEX_HELD(&cpu_lock)); 1415 return (0); 1416 } 1417 1418 /* 1419 * Stop CPU on user request. 1420 */ 1421 /* ARGSUSED */ 1422 int 1423 mp_cpu_stop(struct cpu *cp) 1424 { 1425 extern int cbe_psm_timer_mode; 1426 ASSERT(MUTEX_HELD(&cpu_lock)); 1427 1428 /* 1429 * If TIMER_PERIODIC mode is used, CPU0 is the one running it; 1430 * can't stop it. (This is true only for machines with no TSC.) 1431 */ 1432 1433 if ((cbe_psm_timer_mode == TIMER_PERIODIC) && (cp->cpu_id == 0)) 1434 return (1); 1435 1436 return (0); 1437 } 1438 1439 /* 1440 * Take the specified CPU out of participation in interrupts. 1441 */ 1442 int 1443 cpu_disable_intr(struct cpu *cp) 1444 { 1445 if (psm_disable_intr(cp->cpu_id) != DDI_SUCCESS) 1446 return (EBUSY); 1447 1448 cp->cpu_flags &= ~CPU_ENABLE; 1449 return (0); 1450 } 1451 1452 /* 1453 * Allow the specified CPU to participate in interrupts. 1454 */ 1455 void 1456 cpu_enable_intr(struct cpu *cp) 1457 { 1458 ASSERT(MUTEX_HELD(&cpu_lock)); 1459 cp->cpu_flags |= CPU_ENABLE; 1460 psm_enable_intr(cp->cpu_id); 1461 } 1462 1463 1464 1465 void 1466 mp_cpu_faulted_enter(struct cpu *cp) 1467 { 1468 cmi_faulted_enter(cp); 1469 } 1470 1471 void 1472 mp_cpu_faulted_exit(struct cpu *cp) 1473 { 1474 cmi_faulted_exit(cp); 1475 } 1476 1477 /* 1478 * The following two routines are used as context operators on threads belonging 1479 * to processes with a private LDT (see sysi86). Due to the rarity of such 1480 * processes, these routines are currently written for best code readability and 1481 * organization rather than speed. We could avoid checking x86_feature at every 1482 * context switch by installing different context ops, depending on the 1483 * x86_feature flags, at LDT creation time -- one for each combination of fast 1484 * syscall feature flags. 1485 */ 1486 1487 /*ARGSUSED*/ 1488 void 1489 cpu_fast_syscall_disable(void *arg) 1490 { 1491 if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) 1492 cpu_sep_disable(); 1493 if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) 1494 cpu_asysc_disable(); 1495 } 1496 1497 /*ARGSUSED*/ 1498 void 1499 cpu_fast_syscall_enable(void *arg) 1500 { 1501 if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) 1502 cpu_sep_enable(); 1503 if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) 1504 cpu_asysc_enable(); 1505 } 1506 1507 static void 1508 cpu_sep_enable(void) 1509 { 1510 ASSERT(x86_feature & X86_SEP); 1511 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 1512 1513 wrmsr(MSR_INTC_SEP_CS, (uint64_t)(uintptr_t)KCS_SEL); 1514 } 1515 1516 static void 1517 cpu_sep_disable(void) 1518 { 1519 ASSERT(x86_feature & X86_SEP); 1520 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 1521 1522 /* 1523 * Setting the SYSENTER_CS_MSR register to 0 causes software executing 1524 * the sysenter or sysexit instruction to trigger a #gp fault. 1525 */ 1526 wrmsr(MSR_INTC_SEP_CS, 0); 1527 } 1528 1529 static void 1530 cpu_asysc_enable(void) 1531 { 1532 ASSERT(x86_feature & X86_ASYSC); 1533 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 1534 1535 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) | 1536 (uint64_t)(uintptr_t)AMD_EFER_SCE); 1537 } 1538 1539 static void 1540 cpu_asysc_disable(void) 1541 { 1542 ASSERT(x86_feature & X86_ASYSC); 1543 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 1544 1545 /* 1546 * Turn off the SCE (syscall enable) bit in the EFER register. Software 1547 * executing syscall or sysret with this bit off will incur a #ud trap. 1548 */ 1549 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) & 1550 ~((uint64_t)(uintptr_t)AMD_EFER_SCE)); 1551 } 1552