1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/sysmacros.h> 30 #include <sys/disp.h> 31 #include <sys/promif.h> 32 #include <sys/clock.h> 33 #include <sys/cpuvar.h> 34 #include <sys/stack.h> 35 #include <vm/as.h> 36 #include <vm/hat.h> 37 #include <sys/reboot.h> 38 #include <sys/avintr.h> 39 #include <sys/vtrace.h> 40 #include <sys/proc.h> 41 #include <sys/thread.h> 42 #include <sys/cpupart.h> 43 #include <sys/pset.h> 44 #include <sys/copyops.h> 45 #include <sys/pg.h> 46 #include <sys/disp.h> 47 #include <sys/debug.h> 48 #include <sys/sunddi.h> 49 #include <sys/x86_archext.h> 50 #include <sys/privregs.h> 51 #include <sys/machsystm.h> 52 #include <sys/ontrap.h> 53 #include <sys/bootconf.h> 54 #include <sys/kdi_machimpl.h> 55 #include <sys/archsystm.h> 56 #include <sys/promif.h> 57 #include <sys/bootconf.h> 58 #include <sys/kobj.h> 59 #include <sys/kobj_lex.h> 60 #include <sys/pci_cfgspace.h> 61 #ifdef __xpv 62 #include <sys/hypervisor.h> 63 #endif 64 65 /* 66 * some globals for patching the result of cpuid 67 * to solve problems w/ creative cpu vendors 68 */ 69 70 extern uint32_t cpuid_feature_ecx_include; 71 extern uint32_t cpuid_feature_ecx_exclude; 72 extern uint32_t cpuid_feature_edx_include; 73 extern uint32_t cpuid_feature_edx_exclude; 74 75 /* 76 * Dummy spl priority masks 77 */ 78 static unsigned char dummy_cpu_pri[MAXIPL + 1] = { 79 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 80 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf 81 }; 82 83 84 static uint32_t 85 bootprop_getval(char *name) 86 { 87 char prop[32]; 88 u_longlong_t ll; 89 extern struct bootops *bootops; 90 if ((BOP_GETPROPLEN(bootops, name) > sizeof (prop)) || 91 (BOP_GETPROP(bootops, name, prop) < 0) || 92 (kobj_getvalue(prop, &ll) == -1)) 93 return (0); 94 return ((uint32_t)ll); 95 } 96 97 /* 98 * Setup routine called right before main(). Interposing this function 99 * before main() allows us to call it in a machine-independent fashion. 100 */ 101 void 102 mlsetup(struct regs *rp) 103 { 104 extern struct classfuncs sys_classfuncs; 105 extern disp_t cpu0_disp; 106 extern char t0stack[]; 107 int boot_ncpus; 108 #if !defined(__xpv) 109 extern int xpv_is_hvm; 110 #endif 111 112 ASSERT_STACK_ALIGNED(); 113 114 /* 115 * initialize cpu_self 116 */ 117 cpu[0]->cpu_self = cpu[0]; 118 119 #if defined(__xpv) 120 /* 121 * Point at the hypervisor's virtual cpu structure 122 */ 123 cpu[0]->cpu_m.mcpu_vcpu_info = &HYPERVISOR_shared_info->vcpu_info[0]; 124 #endif 125 126 /* 127 * Set up dummy cpu_pri_data values till psm spl code is 128 * installed. This allows splx() to work on amd64. 129 */ 130 131 cpu[0]->cpu_pri_data = dummy_cpu_pri; 132 133 /* 134 * check if we've got special bits to clear or set 135 * when checking cpu features 136 */ 137 138 cpuid_feature_ecx_include = 139 bootprop_getval("cpuid_feature_ecx_include"); 140 cpuid_feature_ecx_exclude = 141 bootprop_getval("cpuid_feature_ecx_exclude"); 142 cpuid_feature_edx_include = 143 bootprop_getval("cpuid_feature_edx_include"); 144 cpuid_feature_edx_exclude = 145 bootprop_getval("cpuid_feature_edx_exclude"); 146 147 /* 148 * The first lightweight pass (pass0) through the cpuid data 149 * was done in locore before mlsetup was called. Do the next 150 * pass in C code. 151 * 152 * The x86_feature bits are set here on the basis of the capabilities 153 * of the boot CPU. Note that if we choose to support CPUs that have 154 * different feature sets (at which point we would almost certainly 155 * want to set the feature bits to correspond to the feature 156 * minimum) this value may be altered. 157 */ 158 x86_feature = cpuid_pass1(cpu[0]); 159 160 /* 161 * Initialize idt0, gdt0, ldt0_default, ktss0 and dftss. 162 */ 163 init_desctbls(); 164 165 #if !defined(__xpv) 166 167 /* 168 * Patch the tsc_read routine with appropriate set of instructions, 169 * depending on the processor family and architecure, to read the 170 * time-stamp counter while ensuring no out-of-order execution. 171 * Patch it while the kernel text is still writable. 172 * 173 * Note: tsc_read is not patched for intel processors whose family 174 * is >6 and for amd whose family >f (in case they don't support rdtscp 175 * instruction, unlikely). By default tsc_read will use cpuid for 176 * serialization in such cases. The following code needs to be 177 * revisited if intel processors of family >= f retains the 178 * instruction serialization nature of mfence instruction. 179 * Note: tsc_read is not patched for x86 processors which do 180 * not support "mfence". By default tsc_read will use cpuid for 181 * serialization in such cases. 182 * 183 * The Xen hypervisor does not correctly report whether rdtscp is 184 * supported or not, so we must assume that it is not. 185 */ 186 if (xpv_is_hvm == 0 && (x86_feature & X86_TSCP)) 187 patch_tsc_read(X86_HAVE_TSCP); 188 else if (cpuid_getvendor(CPU) == X86_VENDOR_AMD && 189 cpuid_getfamily(CPU) <= 0xf && (x86_feature & X86_SSE2) != 0) 190 patch_tsc_read(X86_TSC_MFENCE); 191 else if (cpuid_getvendor(CPU) == X86_VENDOR_Intel && 192 cpuid_getfamily(CPU) <= 6 && (x86_feature & X86_SSE2) != 0) 193 patch_tsc_read(X86_TSC_MFENCE); 194 195 #endif /* !__xpv */ 196 197 #if defined(__i386) && !defined(__xpv) 198 /* 199 * Some i386 processors do not implement the rdtsc instruction, 200 * or at least they do not implement it correctly. Patch them to 201 * return 0. 202 */ 203 if ((x86_feature & X86_TSC) == 0) 204 patch_tsc_read(X86_NO_TSC); 205 #endif /* __i386 && !__xpv */ 206 207 #if !defined(__xpv) 208 /* XXPV what, if anything, should be dorked with here under xen? */ 209 210 /* 211 * While we're thinking about the TSC, let's set up %cr4 so that 212 * userland can issue rdtsc, and initialize the TSC_AUX value 213 * (the cpuid) for the rdtscp instruction on appropriately 214 * capable hardware. 215 */ 216 if (x86_feature & X86_TSC) 217 setcr4(getcr4() & ~CR4_TSD); 218 219 if (x86_feature & X86_TSCP) 220 (void) wrmsr(MSR_AMD_TSCAUX, 0); 221 222 if (x86_feature & X86_DE) 223 setcr4(getcr4() | CR4_DE); 224 #endif /* __xpv */ 225 226 /* 227 * initialize t0 228 */ 229 t0.t_stk = (caddr_t)rp - MINFRAME; 230 t0.t_stkbase = t0stack; 231 t0.t_pri = maxclsyspri - 3; 232 t0.t_schedflag = TS_LOAD | TS_DONT_SWAP; 233 t0.t_procp = &p0; 234 t0.t_plockp = &p0lock.pl_lock; 235 t0.t_lwp = &lwp0; 236 t0.t_forw = &t0; 237 t0.t_back = &t0; 238 t0.t_next = &t0; 239 t0.t_prev = &t0; 240 t0.t_cpu = cpu[0]; 241 t0.t_disp_queue = &cpu0_disp; 242 t0.t_bind_cpu = PBIND_NONE; 243 t0.t_bind_pset = PS_NONE; 244 t0.t_cpupart = &cp_default; 245 t0.t_clfuncs = &sys_classfuncs.thread; 246 t0.t_copyops = NULL; 247 THREAD_ONPROC(&t0, CPU); 248 249 lwp0.lwp_thread = &t0; 250 lwp0.lwp_regs = (void *)rp; 251 lwp0.lwp_procp = &p0; 252 t0.t_tid = p0.p_lwpcnt = p0.p_lwprcnt = p0.p_lwpid = 1; 253 254 p0.p_exec = NULL; 255 p0.p_stat = SRUN; 256 p0.p_flag = SSYS; 257 p0.p_tlist = &t0; 258 p0.p_stksize = 2*PAGESIZE; 259 p0.p_stkpageszc = 0; 260 p0.p_as = &kas; 261 p0.p_lockp = &p0lock; 262 p0.p_brkpageszc = 0; 263 p0.p_t1_lgrpid = LGRP_NONE; 264 p0.p_tr_lgrpid = LGRP_NONE; 265 sigorset(&p0.p_ignore, &ignoredefault); 266 267 CPU->cpu_thread = &t0; 268 bzero(&cpu0_disp, sizeof (disp_t)); 269 CPU->cpu_disp = &cpu0_disp; 270 CPU->cpu_disp->disp_cpu = CPU; 271 CPU->cpu_dispthread = &t0; 272 CPU->cpu_idle_thread = &t0; 273 CPU->cpu_flags = CPU_READY | CPU_RUNNING | CPU_EXISTS | CPU_ENABLE; 274 CPU->cpu_dispatch_pri = t0.t_pri; 275 276 CPU->cpu_id = 0; 277 278 CPU->cpu_pri = 12; /* initial PIL for the boot CPU */ 279 280 /* 281 * The kernel doesn't use LDTs unless a process explicitly requests one. 282 */ 283 p0.p_ldt_desc = null_sdesc; 284 285 /* 286 * Initialize thread/cpu microstate accounting 287 */ 288 init_mstate(&t0, LMS_SYSTEM); 289 init_cpu_mstate(CPU, CMS_SYSTEM); 290 291 /* 292 * Initialize lists of available and active CPUs. 293 */ 294 cpu_list_init(CPU); 295 296 /* 297 * Now that we have taken over the GDT, IDT and have initialized 298 * active CPU list it's time to inform kmdb if present. 299 */ 300 if (boothowto & RB_DEBUG) 301 kdi_idt_sync(); 302 303 /* 304 * If requested (boot -d) drop into kmdb. 305 * 306 * This must be done after cpu_list_init() on the 64-bit kernel 307 * since taking a trap requires that we re-compute gsbase based 308 * on the cpu list. 309 */ 310 if (boothowto & RB_DEBUGENTER) 311 kmdb_enter(); 312 313 cpu_vm_data_init(CPU); 314 315 /* lgrp_init() needs PCI config space access */ 316 #if defined(__xpv) 317 if (DOMAIN_IS_INITDOMAIN(xen_info)) 318 pci_cfgspace_init(); 319 #else 320 pci_cfgspace_init(); 321 #endif 322 323 /* 324 * Initialize the lgrp framework 325 */ 326 lgrp_init(); 327 328 rp->r_fp = 0; /* terminate kernel stack traces! */ 329 330 prom_init("kernel", (void *)NULL); 331 332 boot_ncpus = bootprop_getval("boot-ncpus"); 333 334 if (boot_ncpus <= 0 || boot_ncpus > NCPU) 335 boot_ncpus = NCPU; 336 337 max_ncpus = boot_max_ncpus = boot_ncpus; 338 339 if (boothowto & RB_HALT) { 340 prom_printf("unix: kernel halted by -h flag\n"); 341 prom_enter_mon(); 342 } 343 344 ASSERT_STACK_ALIGNED(); 345 346 #if !defined(__xpv) 347 /* 348 * Fill out cpu_ucode_info. Update microcode if necessary. 349 */ 350 ucode_check(CPU); 351 #endif 352 353 if (workaround_errata(CPU) != 0) 354 panic("critical workaround(s) missing for boot cpu"); 355 } 356 357 358 void 359 mach_modpath(char *path, const char *filename) 360 { 361 /* 362 * Construct the directory path from the filename. 363 */ 364 365 int len; 366 char *p; 367 const char isastr[] = "/amd64"; 368 size_t isalen = strlen(isastr); 369 370 if ((p = strrchr(filename, '/')) == NULL) 371 return; 372 373 while (p > filename && *(p - 1) == '/') 374 p--; /* remove trailing '/' characters */ 375 if (p == filename) 376 p++; /* so "/" -is- the modpath in this case */ 377 378 /* 379 * Remove optional isa-dependent directory name - the module 380 * subsystem will put this back again (!) 381 */ 382 len = p - filename; 383 if (len > isalen && 384 strncmp(&filename[len - isalen], isastr, isalen) == 0) 385 p -= isalen; 386 387 /* 388 * "/platform/mumblefrotz" + " " + MOD_DEFPATH 389 */ 390 len += (p - filename) + 1 + strlen(MOD_DEFPATH) + 1; 391 (void) strncpy(path, filename, p - filename); 392 } 393