1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <sys/types.h> 27 #include <sys/sysmacros.h> 28 #include <sys/disp.h> 29 #include <sys/promif.h> 30 #include <sys/clock.h> 31 #include <sys/cpuvar.h> 32 #include <sys/stack.h> 33 #include <vm/as.h> 34 #include <vm/hat.h> 35 #include <sys/reboot.h> 36 #include <sys/avintr.h> 37 #include <sys/vtrace.h> 38 #include <sys/proc.h> 39 #include <sys/thread.h> 40 #include <sys/cpupart.h> 41 #include <sys/pset.h> 42 #include <sys/copyops.h> 43 #include <sys/pg.h> 44 #include <sys/disp.h> 45 #include <sys/debug.h> 46 #include <sys/sunddi.h> 47 #include <sys/x86_archext.h> 48 #include <sys/privregs.h> 49 #include <sys/machsystm.h> 50 #include <sys/ontrap.h> 51 #include <sys/bootconf.h> 52 #include <sys/kdi_machimpl.h> 53 #include <sys/archsystm.h> 54 #include <sys/promif.h> 55 #include <sys/bootconf.h> 56 #include <sys/pci_cfgspace.h> 57 #ifdef __xpv 58 #include <sys/hypervisor.h> 59 #else 60 #include <sys/xpv_support.h> 61 #endif 62 63 /* 64 * some globals for patching the result of cpuid 65 * to solve problems w/ creative cpu vendors 66 */ 67 68 extern uint32_t cpuid_feature_ecx_include; 69 extern uint32_t cpuid_feature_ecx_exclude; 70 extern uint32_t cpuid_feature_edx_include; 71 extern uint32_t cpuid_feature_edx_exclude; 72 73 /* 74 * Dummy spl priority masks 75 */ 76 static unsigned char dummy_cpu_pri[MAXIPL + 1] = { 77 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 78 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf 79 }; 80 81 82 /* 83 * Setup routine called right before main(). Interposing this function 84 * before main() allows us to call it in a machine-independent fashion. 85 */ 86 void 87 mlsetup(struct regs *rp) 88 { 89 u_longlong_t prop_value; 90 extern struct classfuncs sys_classfuncs; 91 extern disp_t cpu0_disp; 92 extern char t0stack[]; 93 94 ASSERT_STACK_ALIGNED(); 95 96 /* 97 * initialize cpu_self 98 */ 99 cpu[0]->cpu_self = cpu[0]; 100 101 #if defined(__xpv) 102 /* 103 * Point at the hypervisor's virtual cpu structure 104 */ 105 cpu[0]->cpu_m.mcpu_vcpu_info = &HYPERVISOR_shared_info->vcpu_info[0]; 106 #endif 107 108 /* 109 * Set up dummy cpu_pri_data values till psm spl code is 110 * installed. This allows splx() to work on amd64. 111 */ 112 113 cpu[0]->cpu_pri_data = dummy_cpu_pri; 114 115 /* 116 * check if we've got special bits to clear or set 117 * when checking cpu features 118 */ 119 120 if (bootprop_getval("cpuid_feature_ecx_include", &prop_value) != 0) 121 cpuid_feature_ecx_include = 0; 122 else 123 cpuid_feature_ecx_include = (uint32_t)prop_value; 124 125 if (bootprop_getval("cpuid_feature_ecx_exclude", &prop_value) != 0) 126 cpuid_feature_ecx_exclude = 0; 127 else 128 cpuid_feature_ecx_exclude = (uint32_t)prop_value; 129 130 if (bootprop_getval("cpuid_feature_edx_include", &prop_value) != 0) 131 cpuid_feature_edx_include = 0; 132 else 133 cpuid_feature_edx_include = (uint32_t)prop_value; 134 135 if (bootprop_getval("cpuid_feature_edx_exclude", &prop_value) != 0) 136 cpuid_feature_edx_exclude = 0; 137 else 138 cpuid_feature_edx_exclude = (uint32_t)prop_value; 139 140 /* 141 * The first lightweight pass (pass0) through the cpuid data 142 * was done in locore before mlsetup was called. Do the next 143 * pass in C code. 144 * 145 * The x86_feature bits are set here on the basis of the capabilities 146 * of the boot CPU. Note that if we choose to support CPUs that have 147 * different feature sets (at which point we would almost certainly 148 * want to set the feature bits to correspond to the feature 149 * minimum) this value may be altered. 150 */ 151 x86_feature = cpuid_pass1(cpu[0]); 152 153 /* 154 * Initialize idt0, gdt0, ldt0_default, ktss0 and dftss. 155 */ 156 init_desctbls(); 157 158 #if !defined(__xpv) 159 160 if (get_hwenv() == HW_XEN_HVM) 161 xen_hvm_init(); 162 163 /* 164 * Patch the tsc_read routine with appropriate set of instructions, 165 * depending on the processor family and architecure, to read the 166 * time-stamp counter while ensuring no out-of-order execution. 167 * Patch it while the kernel text is still writable. 168 * 169 * Note: tsc_read is not patched for intel processors whose family 170 * is >6 and for amd whose family >f (in case they don't support rdtscp 171 * instruction, unlikely). By default tsc_read will use cpuid for 172 * serialization in such cases. The following code needs to be 173 * revisited if intel processors of family >= f retains the 174 * instruction serialization nature of mfence instruction. 175 * Note: tsc_read is not patched for x86 processors which do 176 * not support "mfence". By default tsc_read will use cpuid for 177 * serialization in such cases. 178 * 179 * The Xen hypervisor does not correctly report whether rdtscp is 180 * supported or not, so we must assume that it is not. 181 */ 182 if (get_hwenv() != HW_XEN_HVM && (x86_feature & X86_TSCP)) 183 patch_tsc_read(X86_HAVE_TSCP); 184 else if (cpuid_getvendor(CPU) == X86_VENDOR_AMD && 185 cpuid_getfamily(CPU) <= 0xf && (x86_feature & X86_SSE2) != 0) 186 patch_tsc_read(X86_TSC_MFENCE); 187 else if (cpuid_getvendor(CPU) == X86_VENDOR_Intel && 188 cpuid_getfamily(CPU) <= 6 && (x86_feature & X86_SSE2) != 0) 189 patch_tsc_read(X86_TSC_LFENCE); 190 191 #endif /* !__xpv */ 192 193 #if defined(__i386) && !defined(__xpv) 194 /* 195 * Some i386 processors do not implement the rdtsc instruction, 196 * or at least they do not implement it correctly. Patch them to 197 * return 0. 198 */ 199 if ((x86_feature & X86_TSC) == 0) 200 patch_tsc_read(X86_NO_TSC); 201 #endif /* __i386 && !__xpv */ 202 203 #if defined(__amd64) && !defined(__xpv) 204 patch_memops(cpuid_getvendor(CPU)); 205 #endif /* __amd64 && !__xpv */ 206 207 #if !defined(__xpv) 208 /* XXPV what, if anything, should be dorked with here under xen? */ 209 210 /* 211 * While we're thinking about the TSC, let's set up %cr4 so that 212 * userland can issue rdtsc, and initialize the TSC_AUX value 213 * (the cpuid) for the rdtscp instruction on appropriately 214 * capable hardware. 215 */ 216 if (x86_feature & X86_TSC) 217 setcr4(getcr4() & ~CR4_TSD); 218 219 if (x86_feature & X86_TSCP) 220 (void) wrmsr(MSR_AMD_TSCAUX, 0); 221 222 if (x86_feature & X86_DE) 223 setcr4(getcr4() | CR4_DE); 224 #endif /* __xpv */ 225 226 /* 227 * initialize t0 228 */ 229 t0.t_stk = (caddr_t)rp - MINFRAME; 230 t0.t_stkbase = t0stack; 231 t0.t_pri = maxclsyspri - 3; 232 t0.t_schedflag = TS_LOAD | TS_DONT_SWAP; 233 t0.t_procp = &p0; 234 t0.t_plockp = &p0lock.pl_lock; 235 t0.t_lwp = &lwp0; 236 t0.t_forw = &t0; 237 t0.t_back = &t0; 238 t0.t_next = &t0; 239 t0.t_prev = &t0; 240 t0.t_cpu = cpu[0]; 241 t0.t_disp_queue = &cpu0_disp; 242 t0.t_bind_cpu = PBIND_NONE; 243 t0.t_bind_pset = PS_NONE; 244 t0.t_bindflag = (uchar_t)default_binding_mode; 245 t0.t_cpupart = &cp_default; 246 t0.t_clfuncs = &sys_classfuncs.thread; 247 t0.t_copyops = NULL; 248 THREAD_ONPROC(&t0, CPU); 249 250 lwp0.lwp_thread = &t0; 251 lwp0.lwp_regs = (void *)rp; 252 lwp0.lwp_procp = &p0; 253 t0.t_tid = p0.p_lwpcnt = p0.p_lwprcnt = p0.p_lwpid = 1; 254 255 p0.p_exec = NULL; 256 p0.p_stat = SRUN; 257 p0.p_flag = SSYS; 258 p0.p_tlist = &t0; 259 p0.p_stksize = 2*PAGESIZE; 260 p0.p_stkpageszc = 0; 261 p0.p_as = &kas; 262 p0.p_lockp = &p0lock; 263 p0.p_brkpageszc = 0; 264 p0.p_t1_lgrpid = LGRP_NONE; 265 p0.p_tr_lgrpid = LGRP_NONE; 266 sigorset(&p0.p_ignore, &ignoredefault); 267 268 CPU->cpu_thread = &t0; 269 bzero(&cpu0_disp, sizeof (disp_t)); 270 CPU->cpu_disp = &cpu0_disp; 271 CPU->cpu_disp->disp_cpu = CPU; 272 CPU->cpu_dispthread = &t0; 273 CPU->cpu_idle_thread = &t0; 274 CPU->cpu_flags = CPU_READY | CPU_RUNNING | CPU_EXISTS | CPU_ENABLE; 275 CPU->cpu_dispatch_pri = t0.t_pri; 276 277 CPU->cpu_id = 0; 278 279 CPU->cpu_pri = 12; /* initial PIL for the boot CPU */ 280 281 /* 282 * The kernel doesn't use LDTs unless a process explicitly requests one. 283 */ 284 p0.p_ldt_desc = null_sdesc; 285 286 /* 287 * Initialize thread/cpu microstate accounting 288 */ 289 init_mstate(&t0, LMS_SYSTEM); 290 init_cpu_mstate(CPU, CMS_SYSTEM); 291 292 /* 293 * Initialize lists of available and active CPUs. 294 */ 295 cpu_list_init(CPU); 296 297 pg_cpu_bootstrap(CPU); 298 299 /* 300 * Now that we have taken over the GDT, IDT and have initialized 301 * active CPU list it's time to inform kmdb if present. 302 */ 303 if (boothowto & RB_DEBUG) 304 kdi_idt_sync(); 305 306 /* 307 * If requested (boot -d) drop into kmdb. 308 * 309 * This must be done after cpu_list_init() on the 64-bit kernel 310 * since taking a trap requires that we re-compute gsbase based 311 * on the cpu list. 312 */ 313 if (boothowto & RB_DEBUGENTER) 314 kmdb_enter(); 315 316 cpu_vm_data_init(CPU); 317 318 /* lgrp_init() needs PCI config space access */ 319 #if defined(__xpv) 320 if (DOMAIN_IS_INITDOMAIN(xen_info)) 321 pci_cfgspace_init(); 322 #else 323 pci_cfgspace_init(); 324 #endif 325 326 rp->r_fp = 0; /* terminate kernel stack traces! */ 327 328 prom_init("kernel", (void *)NULL); 329 330 if (bootprop_getval("boot-ncpus", &prop_value) != 0) 331 boot_ncpus = NCPU; 332 else { 333 boot_ncpus = (int)prop_value; 334 if (boot_ncpus <= 0 || boot_ncpus > NCPU) 335 boot_ncpus = NCPU; 336 } 337 338 max_ncpus = boot_max_ncpus = boot_ncpus; 339 340 /* 341 * Initialize the lgrp framework 342 */ 343 lgrp_init(); 344 345 if (boothowto & RB_HALT) { 346 prom_printf("unix: kernel halted by -h flag\n"); 347 prom_enter_mon(); 348 } 349 350 ASSERT_STACK_ALIGNED(); 351 352 /* 353 * Fill out cpu_ucode_info. Update microcode if necessary. 354 */ 355 ucode_check(CPU); 356 357 if (workaround_errata(CPU) != 0) 358 panic("critical workaround(s) missing for boot cpu"); 359 } 360 361 362 void 363 mach_modpath(char *path, const char *filename) 364 { 365 /* 366 * Construct the directory path from the filename. 367 */ 368 369 int len; 370 char *p; 371 const char isastr[] = "/amd64"; 372 size_t isalen = strlen(isastr); 373 374 if ((p = strrchr(filename, '/')) == NULL) 375 return; 376 377 while (p > filename && *(p - 1) == '/') 378 p--; /* remove trailing '/' characters */ 379 if (p == filename) 380 p++; /* so "/" -is- the modpath in this case */ 381 382 /* 383 * Remove optional isa-dependent directory name - the module 384 * subsystem will put this back again (!) 385 */ 386 len = p - filename; 387 if (len > isalen && 388 strncmp(&filename[len - isalen], isastr, isalen) == 0) 389 p -= isalen; 390 391 /* 392 * "/platform/mumblefrotz" + " " + MOD_DEFPATH 393 */ 394 len += (p - filename) + 1 + strlen(MOD_DEFPATH) + 1; 395 (void) strncpy(path, filename, p - filename); 396 } 397