1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved. 23 * Copyright (c) 2011 by Delphix. All rights reserved. 24 * Copyright 2013 Nexenta Systems, Inc. All rights reserved. 25 * Copyright 2014 Josef "Jeff" Sipek <jeffpc@josefsipek.net> 26 */ 27 /* 28 * Copyright (c) 2010, Intel Corporation. 29 * All rights reserved. 30 */ 31 /* 32 * Portions Copyright 2009 Advanced Micro Devices, Inc. 33 */ 34 /* 35 * Copyright 2016 Joyent, Inc. 36 */ 37 /* 38 * Various routines to handle identification 39 * and classification of x86 processors. 40 */ 41 42 #include <sys/types.h> 43 #include <sys/archsystm.h> 44 #include <sys/x86_archext.h> 45 #include <sys/kmem.h> 46 #include <sys/systm.h> 47 #include <sys/cmn_err.h> 48 #include <sys/sunddi.h> 49 #include <sys/sunndi.h> 50 #include <sys/cpuvar.h> 51 #include <sys/processor.h> 52 #include <sys/sysmacros.h> 53 #include <sys/pg.h> 54 #include <sys/fp.h> 55 #include <sys/controlregs.h> 56 #include <sys/bitmap.h> 57 #include <sys/auxv_386.h> 58 #include <sys/memnode.h> 59 #include <sys/pci_cfgspace.h> 60 #include <sys/comm_page.h> 61 #include <sys/tsc.h> 62 63 #ifdef __xpv 64 #include <sys/hypervisor.h> 65 #else 66 #include <sys/ontrap.h> 67 #endif 68 69 /* 70 * Pass 0 of cpuid feature analysis happens in locore. It contains special code 71 * to recognize Cyrix processors that are not cpuid-compliant, and to deal with 72 * them accordingly. For most modern processors, feature detection occurs here 73 * in pass 1. 74 * 75 * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup() 76 * for the boot CPU and does the basic analysis that the early kernel needs. 77 * x86_featureset is set based on the return value of cpuid_pass1() of the boot 78 * CPU. 79 * 80 * Pass 1 includes: 81 * 82 * o Determining vendor/model/family/stepping and setting x86_type and 83 * x86_vendor accordingly. 84 * o Processing the feature flags returned by the cpuid instruction while 85 * applying any workarounds or tricks for the specific processor. 86 * o Mapping the feature flags into Solaris feature bits (X86_*). 87 * o Processing extended feature flags if supported by the processor, 88 * again while applying specific processor knowledge. 89 * o Determining the CMT characteristics of the system. 90 * 91 * Pass 1 is done on non-boot CPUs during their initialization and the results 92 * are used only as a meager attempt at ensuring that all processors within the 93 * system support the same features. 94 * 95 * Pass 2 of cpuid feature analysis happens just at the beginning 96 * of startup(). It just copies in and corrects the remainder 97 * of the cpuid data we depend on: standard cpuid functions that we didn't 98 * need for pass1 feature analysis, and extended cpuid functions beyond the 99 * simple feature processing done in pass1. 100 * 101 * Pass 3 of cpuid analysis is invoked after basic kernel services; in 102 * particular kernel memory allocation has been made available. It creates a 103 * readable brand string based on the data collected in the first two passes. 104 * 105 * Pass 4 of cpuid analysis is invoked after post_startup() when all 106 * the support infrastructure for various hardware features has been 107 * initialized. It determines which processor features will be reported 108 * to userland via the aux vector. 109 * 110 * All passes are executed on all CPUs, but only the boot CPU determines what 111 * features the kernel will use. 112 * 113 * Much of the worst junk in this file is for the support of processors 114 * that didn't really implement the cpuid instruction properly. 115 * 116 * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon, 117 * the pass numbers. Accordingly, changes to the pass code may require changes 118 * to the accessor code. 119 */ 120 121 uint_t x86_vendor = X86_VENDOR_IntelClone; 122 uint_t x86_type = X86_TYPE_OTHER; 123 uint_t x86_clflush_size = 0; 124 125 uint_t pentiumpro_bug4046376; 126 127 uchar_t x86_featureset[BT_SIZEOFMAP(NUM_X86_FEATURES)]; 128 129 static char *x86_feature_names[NUM_X86_FEATURES] = { 130 "lgpg", 131 "tsc", 132 "msr", 133 "mtrr", 134 "pge", 135 "de", 136 "cmov", 137 "mmx", 138 "mca", 139 "pae", 140 "cv8", 141 "pat", 142 "sep", 143 "sse", 144 "sse2", 145 "htt", 146 "asysc", 147 "nx", 148 "sse3", 149 "cx16", 150 "cmp", 151 "tscp", 152 "mwait", 153 "sse4a", 154 "cpuid", 155 "ssse3", 156 "sse4_1", 157 "sse4_2", 158 "1gpg", 159 "clfsh", 160 "64", 161 "aes", 162 "pclmulqdq", 163 "xsave", 164 "avx", 165 "vmx", 166 "svm", 167 "topoext", 168 "f16c", 169 "rdrand", 170 "x2apic", 171 "avx2", 172 "bmi1", 173 "bmi2", 174 "fma", 175 "smep", 176 "adx", 177 "rdseed", 178 "amd_pcec" 179 }; 180 181 boolean_t 182 is_x86_feature(void *featureset, uint_t feature) 183 { 184 ASSERT(feature < NUM_X86_FEATURES); 185 return (BT_TEST((ulong_t *)featureset, feature)); 186 } 187 188 void 189 add_x86_feature(void *featureset, uint_t feature) 190 { 191 ASSERT(feature < NUM_X86_FEATURES); 192 BT_SET((ulong_t *)featureset, feature); 193 } 194 195 void 196 remove_x86_feature(void *featureset, uint_t feature) 197 { 198 ASSERT(feature < NUM_X86_FEATURES); 199 BT_CLEAR((ulong_t *)featureset, feature); 200 } 201 202 boolean_t 203 compare_x86_featureset(void *setA, void *setB) 204 { 205 /* 206 * We assume that the unused bits of the bitmap are always zero. 207 */ 208 if (memcmp(setA, setB, BT_SIZEOFMAP(NUM_X86_FEATURES)) == 0) { 209 return (B_TRUE); 210 } else { 211 return (B_FALSE); 212 } 213 } 214 215 void 216 print_x86_featureset(void *featureset) 217 { 218 uint_t i; 219 220 for (i = 0; i < NUM_X86_FEATURES; i++) { 221 if (is_x86_feature(featureset, i)) { 222 cmn_err(CE_CONT, "?x86_feature: %s\n", 223 x86_feature_names[i]); 224 } 225 } 226 } 227 228 static size_t xsave_state_size = 0; 229 uint64_t xsave_bv_all = (XFEATURE_LEGACY_FP | XFEATURE_SSE); 230 boolean_t xsave_force_disable = B_FALSE; 231 232 /* 233 * This is set to platform type we are running on. 234 */ 235 static int platform_type = -1; 236 237 #if !defined(__xpv) 238 /* 239 * Variable to patch if hypervisor platform detection needs to be 240 * disabled (e.g. platform_type will always be HW_NATIVE if this is 0). 241 */ 242 int enable_platform_detection = 1; 243 #endif 244 245 /* 246 * monitor/mwait info. 247 * 248 * size_actual and buf_actual are the real address and size allocated to get 249 * proper mwait_buf alignement. buf_actual and size_actual should be passed 250 * to kmem_free(). Currently kmem_alloc() and mwait happen to both use 251 * processor cache-line alignment, but this is not guarantied in the furture. 252 */ 253 struct mwait_info { 254 size_t mon_min; /* min size to avoid missed wakeups */ 255 size_t mon_max; /* size to avoid false wakeups */ 256 size_t size_actual; /* size actually allocated */ 257 void *buf_actual; /* memory actually allocated */ 258 uint32_t support; /* processor support of monitor/mwait */ 259 }; 260 261 /* 262 * xsave/xrestor info. 263 * 264 * This structure contains HW feature bits and size of the xsave save area. 265 * Note: the kernel will use the maximum size required for all hardware 266 * features. It is not optimize for potential memory savings if features at 267 * the end of the save area are not enabled. 268 */ 269 struct xsave_info { 270 uint32_t xsav_hw_features_low; /* Supported HW features */ 271 uint32_t xsav_hw_features_high; /* Supported HW features */ 272 size_t xsav_max_size; /* max size save area for HW features */ 273 size_t ymm_size; /* AVX: size of ymm save area */ 274 size_t ymm_offset; /* AVX: offset for ymm save area */ 275 }; 276 277 278 /* 279 * These constants determine how many of the elements of the 280 * cpuid we cache in the cpuid_info data structure; the 281 * remaining elements are accessible via the cpuid instruction. 282 */ 283 284 #define NMAX_CPI_STD 8 /* eax = 0 .. 7 */ 285 #define NMAX_CPI_EXTD 0x1f /* eax = 0x80000000 .. 0x8000001e */ 286 287 /* 288 * Some terminology needs to be explained: 289 * - Socket: Something that can be plugged into a motherboard. 290 * - Package: Same as socket 291 * - Chip: Same as socket. Note that AMD's documentation uses term "chip" 292 * differently: there, chip is the same as processor node (below) 293 * - Processor node: Some AMD processors have more than one 294 * "subprocessor" embedded in a package. These subprocessors (nodes) 295 * are fully-functional processors themselves with cores, caches, 296 * memory controllers, PCI configuration spaces. They are connected 297 * inside the package with Hypertransport links. On single-node 298 * processors, processor node is equivalent to chip/socket/package. 299 * - Compute Unit: Some AMD processors pair cores in "compute units" that 300 * share the FPU and the I$ and L2 caches. 301 */ 302 303 struct cpuid_info { 304 uint_t cpi_pass; /* last pass completed */ 305 /* 306 * standard function information 307 */ 308 uint_t cpi_maxeax; /* fn 0: %eax */ 309 char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */ 310 uint_t cpi_vendor; /* enum of cpi_vendorstr */ 311 312 uint_t cpi_family; /* fn 1: extended family */ 313 uint_t cpi_model; /* fn 1: extended model */ 314 uint_t cpi_step; /* fn 1: stepping */ 315 chipid_t cpi_chipid; /* fn 1: %ebx: Intel: chip # */ 316 /* AMD: package/socket # */ 317 uint_t cpi_brandid; /* fn 1: %ebx: brand ID */ 318 int cpi_clogid; /* fn 1: %ebx: thread # */ 319 uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */ 320 uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */ 321 uint_t cpi_ncache; /* fn 2: number of elements */ 322 uint_t cpi_ncpu_shr_last_cache; /* fn 4: %eax: ncpus sharing cache */ 323 id_t cpi_last_lvl_cacheid; /* fn 4: %eax: derived cache id */ 324 uint_t cpi_std_4_size; /* fn 4: number of fn 4 elements */ 325 struct cpuid_regs **cpi_std_4; /* fn 4: %ecx == 0 .. fn4_size */ 326 struct cpuid_regs cpi_std[NMAX_CPI_STD]; /* 0 .. 7 */ 327 /* 328 * extended function information 329 */ 330 uint_t cpi_xmaxeax; /* fn 0x80000000: %eax */ 331 char cpi_brandstr[49]; /* fn 0x8000000[234] */ 332 uint8_t cpi_pabits; /* fn 0x80000006: %eax */ 333 uint8_t cpi_vabits; /* fn 0x80000006: %eax */ 334 struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x800000XX */ 335 336 id_t cpi_coreid; /* same coreid => strands share core */ 337 int cpi_pkgcoreid; /* core number within single package */ 338 uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */ 339 /* Intel: fn 4: %eax[31-26] */ 340 /* 341 * supported feature information 342 */ 343 uint32_t cpi_support[6]; 344 #define STD_EDX_FEATURES 0 345 #define AMD_EDX_FEATURES 1 346 #define TM_EDX_FEATURES 2 347 #define STD_ECX_FEATURES 3 348 #define AMD_ECX_FEATURES 4 349 #define STD_EBX_FEATURES 5 350 /* 351 * Synthesized information, where known. 352 */ 353 uint32_t cpi_chiprev; /* See X86_CHIPREV_* in x86_archext.h */ 354 const char *cpi_chiprevstr; /* May be NULL if chiprev unknown */ 355 uint32_t cpi_socket; /* Chip package/socket type */ 356 357 struct mwait_info cpi_mwait; /* fn 5: monitor/mwait info */ 358 uint32_t cpi_apicid; 359 uint_t cpi_procnodeid; /* AMD: nodeID on HT, Intel: chipid */ 360 uint_t cpi_procnodes_per_pkg; /* AMD: # of nodes in the package */ 361 /* Intel: 1 */ 362 uint_t cpi_compunitid; /* AMD: ComputeUnit ID, Intel: coreid */ 363 uint_t cpi_cores_per_compunit; /* AMD: # of cores in the ComputeUnit */ 364 365 struct xsave_info cpi_xsave; /* fn D: xsave/xrestor info */ 366 }; 367 368 369 static struct cpuid_info cpuid_info0; 370 371 /* 372 * These bit fields are defined by the Intel Application Note AP-485 373 * "Intel Processor Identification and the CPUID Instruction" 374 */ 375 #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20) 376 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16) 377 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12) 378 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8) 379 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0) 380 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4) 381 382 #define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx) 383 #define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx) 384 #define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx) 385 #define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx) 386 #define CPI_FEATURES_7_0_EBX(cpi) ((cpi)->cpi_std[7].cp_ebx) 387 388 #define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0) 389 #define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7) 390 #define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16) 391 #define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24) 392 393 #define CPI_MAXEAX_MAX 0x100 /* sanity control */ 394 #define CPI_XMAXEAX_MAX 0x80000100 395 #define CPI_FN4_ECX_MAX 0x20 /* sanity: max fn 4 levels */ 396 #define CPI_FNB_ECX_MAX 0x20 /* sanity: max fn B levels */ 397 398 /* 399 * Function 4 (Deterministic Cache Parameters) macros 400 * Defined by Intel Application Note AP-485 401 */ 402 #define CPI_NUM_CORES(regs) BITX((regs)->cp_eax, 31, 26) 403 #define CPI_NTHR_SHR_CACHE(regs) BITX((regs)->cp_eax, 25, 14) 404 #define CPI_FULL_ASSOC_CACHE(regs) BITX((regs)->cp_eax, 9, 9) 405 #define CPI_SELF_INIT_CACHE(regs) BITX((regs)->cp_eax, 8, 8) 406 #define CPI_CACHE_LVL(regs) BITX((regs)->cp_eax, 7, 5) 407 #define CPI_CACHE_TYPE(regs) BITX((regs)->cp_eax, 4, 0) 408 #define CPI_CPU_LEVEL_TYPE(regs) BITX((regs)->cp_ecx, 15, 8) 409 410 #define CPI_CACHE_WAYS(regs) BITX((regs)->cp_ebx, 31, 22) 411 #define CPI_CACHE_PARTS(regs) BITX((regs)->cp_ebx, 21, 12) 412 #define CPI_CACHE_COH_LN_SZ(regs) BITX((regs)->cp_ebx, 11, 0) 413 414 #define CPI_CACHE_SETS(regs) BITX((regs)->cp_ecx, 31, 0) 415 416 #define CPI_PREFCH_STRIDE(regs) BITX((regs)->cp_edx, 9, 0) 417 418 419 /* 420 * A couple of shorthand macros to identify "later" P6-family chips 421 * like the Pentium M and Core. First, the "older" P6-based stuff 422 * (loosely defined as "pre-Pentium-4"): 423 * P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon 424 */ 425 426 #define IS_LEGACY_P6(cpi) ( \ 427 cpi->cpi_family == 6 && \ 428 (cpi->cpi_model == 1 || \ 429 cpi->cpi_model == 3 || \ 430 cpi->cpi_model == 5 || \ 431 cpi->cpi_model == 6 || \ 432 cpi->cpi_model == 7 || \ 433 cpi->cpi_model == 8 || \ 434 cpi->cpi_model == 0xA || \ 435 cpi->cpi_model == 0xB) \ 436 ) 437 438 /* A "new F6" is everything with family 6 that's not the above */ 439 #define IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi)) 440 441 /* Extended family/model support */ 442 #define IS_EXTENDED_MODEL_INTEL(cpi) (cpi->cpi_family == 0x6 || \ 443 cpi->cpi_family >= 0xf) 444 445 /* 446 * Info for monitor/mwait idle loop. 447 * 448 * See cpuid section of "Intel 64 and IA-32 Architectures Software Developer's 449 * Manual Volume 2A: Instruction Set Reference, A-M" #25366-022US, November 450 * 2006. 451 * See MONITOR/MWAIT section of "AMD64 Architecture Programmer's Manual 452 * Documentation Updates" #33633, Rev 2.05, December 2006. 453 */ 454 #define MWAIT_SUPPORT (0x00000001) /* mwait supported */ 455 #define MWAIT_EXTENSIONS (0x00000002) /* extenstion supported */ 456 #define MWAIT_ECX_INT_ENABLE (0x00000004) /* ecx 1 extension supported */ 457 #define MWAIT_SUPPORTED(cpi) ((cpi)->cpi_std[1].cp_ecx & CPUID_INTC_ECX_MON) 458 #define MWAIT_INT_ENABLE(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x2) 459 #define MWAIT_EXTENSION(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x1) 460 #define MWAIT_SIZE_MIN(cpi) BITX((cpi)->cpi_std[5].cp_eax, 15, 0) 461 #define MWAIT_SIZE_MAX(cpi) BITX((cpi)->cpi_std[5].cp_ebx, 15, 0) 462 /* 463 * Number of sub-cstates for a given c-state. 464 */ 465 #define MWAIT_NUM_SUBC_STATES(cpi, c_state) \ 466 BITX((cpi)->cpi_std[5].cp_edx, c_state + 3, c_state) 467 468 /* 469 * XSAVE leaf 0xD enumeration 470 */ 471 #define CPUID_LEAFD_2_YMM_OFFSET 576 472 #define CPUID_LEAFD_2_YMM_SIZE 256 473 474 /* 475 * Functions we consune from cpuid_subr.c; don't publish these in a header 476 * file to try and keep people using the expected cpuid_* interfaces. 477 */ 478 extern uint32_t _cpuid_skt(uint_t, uint_t, uint_t, uint_t); 479 extern const char *_cpuid_sktstr(uint_t, uint_t, uint_t, uint_t); 480 extern uint32_t _cpuid_chiprev(uint_t, uint_t, uint_t, uint_t); 481 extern const char *_cpuid_chiprevstr(uint_t, uint_t, uint_t, uint_t); 482 extern uint_t _cpuid_vendorstr_to_vendorcode(char *); 483 484 /* 485 * Apply up various platform-dependent restrictions where the 486 * underlying platform restrictions mean the CPU can be marked 487 * as less capable than its cpuid instruction would imply. 488 */ 489 #if defined(__xpv) 490 static void 491 platform_cpuid_mangle(uint_t vendor, uint32_t eax, struct cpuid_regs *cp) 492 { 493 switch (eax) { 494 case 1: { 495 uint32_t mcamask = DOMAIN_IS_INITDOMAIN(xen_info) ? 496 0 : CPUID_INTC_EDX_MCA; 497 cp->cp_edx &= 498 ~(mcamask | 499 CPUID_INTC_EDX_PSE | 500 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE | 501 CPUID_INTC_EDX_SEP | CPUID_INTC_EDX_MTRR | 502 CPUID_INTC_EDX_PGE | CPUID_INTC_EDX_PAT | 503 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP | 504 CPUID_INTC_EDX_PSE36 | CPUID_INTC_EDX_HTT); 505 break; 506 } 507 508 case 0x80000001: 509 cp->cp_edx &= 510 ~(CPUID_AMD_EDX_PSE | 511 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE | 512 CPUID_AMD_EDX_MTRR | CPUID_AMD_EDX_PGE | 513 CPUID_AMD_EDX_PAT | CPUID_AMD_EDX_PSE36 | 514 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP | 515 CPUID_AMD_EDX_TSCP); 516 cp->cp_ecx &= ~CPUID_AMD_ECX_CMP_LGCY; 517 break; 518 default: 519 break; 520 } 521 522 switch (vendor) { 523 case X86_VENDOR_Intel: 524 switch (eax) { 525 case 4: 526 /* 527 * Zero out the (ncores-per-chip - 1) field 528 */ 529 cp->cp_eax &= 0x03fffffff; 530 break; 531 default: 532 break; 533 } 534 break; 535 case X86_VENDOR_AMD: 536 switch (eax) { 537 538 case 0x80000001: 539 cp->cp_ecx &= ~CPUID_AMD_ECX_CR8D; 540 break; 541 542 case 0x80000008: 543 /* 544 * Zero out the (ncores-per-chip - 1) field 545 */ 546 cp->cp_ecx &= 0xffffff00; 547 break; 548 default: 549 break; 550 } 551 break; 552 default: 553 break; 554 } 555 } 556 #else 557 #define platform_cpuid_mangle(vendor, eax, cp) /* nothing */ 558 #endif 559 560 /* 561 * Some undocumented ways of patching the results of the cpuid 562 * instruction to permit running Solaris 10 on future cpus that 563 * we don't currently support. Could be set to non-zero values 564 * via settings in eeprom. 565 */ 566 567 uint32_t cpuid_feature_ecx_include; 568 uint32_t cpuid_feature_ecx_exclude; 569 uint32_t cpuid_feature_edx_include; 570 uint32_t cpuid_feature_edx_exclude; 571 572 /* 573 * Allocate space for mcpu_cpi in the machcpu structure for all non-boot CPUs. 574 */ 575 void 576 cpuid_alloc_space(cpu_t *cpu) 577 { 578 /* 579 * By convention, cpu0 is the boot cpu, which is set up 580 * before memory allocation is available. All other cpus get 581 * their cpuid_info struct allocated here. 582 */ 583 ASSERT(cpu->cpu_id != 0); 584 ASSERT(cpu->cpu_m.mcpu_cpi == NULL); 585 cpu->cpu_m.mcpu_cpi = 586 kmem_zalloc(sizeof (*cpu->cpu_m.mcpu_cpi), KM_SLEEP); 587 } 588 589 void 590 cpuid_free_space(cpu_t *cpu) 591 { 592 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 593 int i; 594 595 ASSERT(cpi != NULL); 596 ASSERT(cpi != &cpuid_info0); 597 598 /* 599 * Free up any function 4 related dynamic storage 600 */ 601 for (i = 1; i < cpi->cpi_std_4_size; i++) 602 kmem_free(cpi->cpi_std_4[i], sizeof (struct cpuid_regs)); 603 if (cpi->cpi_std_4_size > 0) 604 kmem_free(cpi->cpi_std_4, 605 cpi->cpi_std_4_size * sizeof (struct cpuid_regs *)); 606 607 kmem_free(cpi, sizeof (*cpi)); 608 cpu->cpu_m.mcpu_cpi = NULL; 609 } 610 611 #if !defined(__xpv) 612 /* 613 * Determine the type of the underlying platform. This is used to customize 614 * initialization of various subsystems (e.g. TSC). determine_platform() must 615 * only ever be called once to prevent two processors from seeing different 616 * values of platform_type. Must be called before cpuid_pass1(), the earliest 617 * consumer to execute (uses _cpuid_chiprev --> synth_amd_info --> get_hwenv). 618 */ 619 void 620 determine_platform(void) 621 { 622 struct cpuid_regs cp; 623 uint32_t base; 624 uint32_t regs[4]; 625 char *hvstr = (char *)regs; 626 627 ASSERT(platform_type == -1); 628 629 platform_type = HW_NATIVE; 630 631 if (!enable_platform_detection) 632 return; 633 634 /* 635 * If Hypervisor CPUID bit is set, try to determine hypervisor 636 * vendor signature, and set platform type accordingly. 637 * 638 * References: 639 * http://lkml.org/lkml/2008/10/1/246 640 * http://kb.vmware.com/kb/1009458 641 */ 642 cp.cp_eax = 0x1; 643 (void) __cpuid_insn(&cp); 644 if ((cp.cp_ecx & CPUID_INTC_ECX_HV) != 0) { 645 cp.cp_eax = 0x40000000; 646 (void) __cpuid_insn(&cp); 647 regs[0] = cp.cp_ebx; 648 regs[1] = cp.cp_ecx; 649 regs[2] = cp.cp_edx; 650 regs[3] = 0; 651 if (strcmp(hvstr, HVSIG_XEN_HVM) == 0) { 652 platform_type = HW_XEN_HVM; 653 return; 654 } 655 if (strcmp(hvstr, HVSIG_VMWARE) == 0) { 656 platform_type = HW_VMWARE; 657 return; 658 } 659 if (strcmp(hvstr, HVSIG_KVM) == 0) { 660 platform_type = HW_KVM; 661 return; 662 } 663 if (strcmp(hvstr, HVSIG_MICROSOFT) == 0) 664 platform_type = HW_MICROSOFT; 665 } else { 666 /* 667 * Check older VMware hardware versions. VMware hypervisor is 668 * detected by performing an IN operation to VMware hypervisor 669 * port and checking that value returned in %ebx is VMware 670 * hypervisor magic value. 671 * 672 * References: http://kb.vmware.com/kb/1009458 673 */ 674 vmware_port(VMWARE_HVCMD_GETVERSION, regs); 675 if (regs[1] == VMWARE_HVMAGIC) { 676 platform_type = HW_VMWARE; 677 return; 678 } 679 } 680 681 /* 682 * Check Xen hypervisor. In a fully virtualized domain, 683 * Xen's pseudo-cpuid function returns a string representing the 684 * Xen signature in %ebx, %ecx, and %edx. %eax contains the maximum 685 * supported cpuid function. We need at least a (base + 2) leaf value 686 * to do what we want to do. Try different base values, since the 687 * hypervisor might use a different one depending on whether Hyper-V 688 * emulation is switched on by default or not. 689 */ 690 for (base = 0x40000000; base < 0x40010000; base += 0x100) { 691 cp.cp_eax = base; 692 (void) __cpuid_insn(&cp); 693 regs[0] = cp.cp_ebx; 694 regs[1] = cp.cp_ecx; 695 regs[2] = cp.cp_edx; 696 regs[3] = 0; 697 if (strcmp(hvstr, HVSIG_XEN_HVM) == 0 && 698 cp.cp_eax >= (base + 2)) { 699 platform_type &= ~HW_NATIVE; 700 platform_type |= HW_XEN_HVM; 701 return; 702 } 703 } 704 } 705 706 int 707 get_hwenv(void) 708 { 709 ASSERT(platform_type != -1); 710 return (platform_type); 711 } 712 713 int 714 is_controldom(void) 715 { 716 return (0); 717 } 718 719 #else 720 721 int 722 get_hwenv(void) 723 { 724 return (HW_XEN_PV); 725 } 726 727 int 728 is_controldom(void) 729 { 730 return (DOMAIN_IS_INITDOMAIN(xen_info)); 731 } 732 733 #endif /* __xpv */ 734 735 static void 736 cpuid_intel_getids(cpu_t *cpu, void *feature) 737 { 738 uint_t i; 739 uint_t chipid_shift = 0; 740 uint_t coreid_shift = 0; 741 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 742 743 for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1) 744 chipid_shift++; 745 746 cpi->cpi_chipid = cpi->cpi_apicid >> chipid_shift; 747 cpi->cpi_clogid = cpi->cpi_apicid & ((1 << chipid_shift) - 1); 748 749 if (is_x86_feature(feature, X86FSET_CMP)) { 750 /* 751 * Multi-core (and possibly multi-threaded) 752 * processors. 753 */ 754 uint_t ncpu_per_core; 755 if (cpi->cpi_ncore_per_chip == 1) 756 ncpu_per_core = cpi->cpi_ncpu_per_chip; 757 else if (cpi->cpi_ncore_per_chip > 1) 758 ncpu_per_core = cpi->cpi_ncpu_per_chip / 759 cpi->cpi_ncore_per_chip; 760 /* 761 * 8bit APIC IDs on dual core Pentiums 762 * look like this: 763 * 764 * +-----------------------+------+------+ 765 * | Physical Package ID | MC | HT | 766 * +-----------------------+------+------+ 767 * <------- chipid --------> 768 * <------- coreid ---------------> 769 * <--- clogid --> 770 * <------> 771 * pkgcoreid 772 * 773 * Where the number of bits necessary to 774 * represent MC and HT fields together equals 775 * to the minimum number of bits necessary to 776 * store the value of cpi->cpi_ncpu_per_chip. 777 * Of those bits, the MC part uses the number 778 * of bits necessary to store the value of 779 * cpi->cpi_ncore_per_chip. 780 */ 781 for (i = 1; i < ncpu_per_core; i <<= 1) 782 coreid_shift++; 783 cpi->cpi_coreid = cpi->cpi_apicid >> coreid_shift; 784 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift; 785 } else if (is_x86_feature(feature, X86FSET_HTT)) { 786 /* 787 * Single-core multi-threaded processors. 788 */ 789 cpi->cpi_coreid = cpi->cpi_chipid; 790 cpi->cpi_pkgcoreid = 0; 791 } 792 cpi->cpi_procnodeid = cpi->cpi_chipid; 793 cpi->cpi_compunitid = cpi->cpi_coreid; 794 } 795 796 static void 797 cpuid_amd_getids(cpu_t *cpu) 798 { 799 int i, first_half, coreidsz; 800 uint32_t nb_caps_reg; 801 uint_t node2_1; 802 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 803 struct cpuid_regs *cp; 804 805 /* 806 * AMD CMP chips currently have a single thread per core. 807 * 808 * Since no two cpus share a core we must assign a distinct coreid 809 * per cpu, and we do this by using the cpu_id. This scheme does not, 810 * however, guarantee that sibling cores of a chip will have sequential 811 * coreids starting at a multiple of the number of cores per chip - 812 * that is usually the case, but if the ACPI MADT table is presented 813 * in a different order then we need to perform a few more gymnastics 814 * for the pkgcoreid. 815 * 816 * All processors in the system have the same number of enabled 817 * cores. Cores within a processor are always numbered sequentially 818 * from 0 regardless of how many or which are disabled, and there 819 * is no way for operating system to discover the real core id when some 820 * are disabled. 821 * 822 * In family 0x15, the cores come in pairs called compute units. They 823 * share I$ and L2 caches and the FPU. Enumeration of this feature is 824 * simplified by the new topology extensions CPUID leaf, indicated by 825 * the X86 feature X86FSET_TOPOEXT. 826 */ 827 828 cpi->cpi_coreid = cpu->cpu_id; 829 cpi->cpi_compunitid = cpu->cpu_id; 830 831 if (cpi->cpi_xmaxeax >= 0x80000008) { 832 833 coreidsz = BITX((cpi)->cpi_extd[8].cp_ecx, 15, 12); 834 835 /* 836 * In AMD parlance chip is really a node while Solaris 837 * sees chip as equivalent to socket/package. 838 */ 839 cpi->cpi_ncore_per_chip = 840 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1; 841 if (coreidsz == 0) { 842 /* Use legacy method */ 843 for (i = 1; i < cpi->cpi_ncore_per_chip; i <<= 1) 844 coreidsz++; 845 if (coreidsz == 0) 846 coreidsz = 1; 847 } 848 } else { 849 /* Assume single-core part */ 850 cpi->cpi_ncore_per_chip = 1; 851 coreidsz = 1; 852 } 853 854 cpi->cpi_clogid = cpi->cpi_pkgcoreid = 855 cpi->cpi_apicid & ((1<<coreidsz) - 1); 856 cpi->cpi_ncpu_per_chip = cpi->cpi_ncore_per_chip; 857 858 /* Get node ID, compute unit ID */ 859 if (is_x86_feature(x86_featureset, X86FSET_TOPOEXT) && 860 cpi->cpi_xmaxeax >= 0x8000001e) { 861 cp = &cpi->cpi_extd[0x1e]; 862 cp->cp_eax = 0x8000001e; 863 (void) __cpuid_insn(cp); 864 865 cpi->cpi_procnodes_per_pkg = BITX(cp->cp_ecx, 10, 8) + 1; 866 cpi->cpi_procnodeid = BITX(cp->cp_ecx, 7, 0); 867 cpi->cpi_cores_per_compunit = BITX(cp->cp_ebx, 15, 8) + 1; 868 cpi->cpi_compunitid = BITX(cp->cp_ebx, 7, 0) 869 + (cpi->cpi_ncore_per_chip / cpi->cpi_cores_per_compunit) 870 * (cpi->cpi_procnodeid / cpi->cpi_procnodes_per_pkg); 871 } else if (cpi->cpi_family == 0xf || cpi->cpi_family >= 0x11) { 872 cpi->cpi_procnodeid = (cpi->cpi_apicid >> coreidsz) & 7; 873 } else if (cpi->cpi_family == 0x10) { 874 /* 875 * See if we are a multi-node processor. 876 * All processors in the system have the same number of nodes 877 */ 878 nb_caps_reg = pci_getl_func(0, 24, 3, 0xe8); 879 if ((cpi->cpi_model < 8) || BITX(nb_caps_reg, 29, 29) == 0) { 880 /* Single-node */ 881 cpi->cpi_procnodeid = BITX(cpi->cpi_apicid, 5, 882 coreidsz); 883 } else { 884 885 /* 886 * Multi-node revision D (2 nodes per package 887 * are supported) 888 */ 889 cpi->cpi_procnodes_per_pkg = 2; 890 891 first_half = (cpi->cpi_pkgcoreid <= 892 (cpi->cpi_ncore_per_chip/2 - 1)); 893 894 if (cpi->cpi_apicid == cpi->cpi_pkgcoreid) { 895 /* We are BSP */ 896 cpi->cpi_procnodeid = (first_half ? 0 : 1); 897 } else { 898 899 /* We are AP */ 900 /* NodeId[2:1] bits to use for reading F3xe8 */ 901 node2_1 = BITX(cpi->cpi_apicid, 5, 4) << 1; 902 903 nb_caps_reg = 904 pci_getl_func(0, 24 + node2_1, 3, 0xe8); 905 906 /* 907 * Check IntNodeNum bit (31:30, but bit 31 is 908 * always 0 on dual-node processors) 909 */ 910 if (BITX(nb_caps_reg, 30, 30) == 0) 911 cpi->cpi_procnodeid = node2_1 + 912 !first_half; 913 else 914 cpi->cpi_procnodeid = node2_1 + 915 first_half; 916 } 917 } 918 } else { 919 cpi->cpi_procnodeid = 0; 920 } 921 922 cpi->cpi_chipid = 923 cpi->cpi_procnodeid / cpi->cpi_procnodes_per_pkg; 924 } 925 926 /* 927 * Setup XFeature_Enabled_Mask register. Required by xsave feature. 928 */ 929 void 930 setup_xfem(void) 931 { 932 uint64_t flags = XFEATURE_LEGACY_FP; 933 934 ASSERT(is_x86_feature(x86_featureset, X86FSET_XSAVE)); 935 936 if (is_x86_feature(x86_featureset, X86FSET_SSE)) 937 flags |= XFEATURE_SSE; 938 939 if (is_x86_feature(x86_featureset, X86FSET_AVX)) 940 flags |= XFEATURE_AVX; 941 942 set_xcr(XFEATURE_ENABLED_MASK, flags); 943 944 xsave_bv_all = flags; 945 } 946 947 void 948 cpuid_pass1(cpu_t *cpu, uchar_t *featureset) 949 { 950 uint32_t mask_ecx, mask_edx; 951 struct cpuid_info *cpi; 952 struct cpuid_regs *cp; 953 int xcpuid; 954 #if !defined(__xpv) 955 extern int idle_cpu_prefer_mwait; 956 #endif 957 958 /* 959 * Space statically allocated for BSP, ensure pointer is set 960 */ 961 if (cpu->cpu_id == 0) { 962 if (cpu->cpu_m.mcpu_cpi == NULL) 963 cpu->cpu_m.mcpu_cpi = &cpuid_info0; 964 } 965 966 add_x86_feature(featureset, X86FSET_CPUID); 967 968 cpi = cpu->cpu_m.mcpu_cpi; 969 ASSERT(cpi != NULL); 970 cp = &cpi->cpi_std[0]; 971 cp->cp_eax = 0; 972 cpi->cpi_maxeax = __cpuid_insn(cp); 973 { 974 uint32_t *iptr = (uint32_t *)cpi->cpi_vendorstr; 975 *iptr++ = cp->cp_ebx; 976 *iptr++ = cp->cp_edx; 977 *iptr++ = cp->cp_ecx; 978 *(char *)&cpi->cpi_vendorstr[12] = '\0'; 979 } 980 981 cpi->cpi_vendor = _cpuid_vendorstr_to_vendorcode(cpi->cpi_vendorstr); 982 x86_vendor = cpi->cpi_vendor; /* for compatibility */ 983 984 /* 985 * Limit the range in case of weird hardware 986 */ 987 if (cpi->cpi_maxeax > CPI_MAXEAX_MAX) 988 cpi->cpi_maxeax = CPI_MAXEAX_MAX; 989 if (cpi->cpi_maxeax < 1) 990 goto pass1_done; 991 992 cp = &cpi->cpi_std[1]; 993 cp->cp_eax = 1; 994 (void) __cpuid_insn(cp); 995 996 /* 997 * Extract identifying constants for easy access. 998 */ 999 cpi->cpi_model = CPI_MODEL(cpi); 1000 cpi->cpi_family = CPI_FAMILY(cpi); 1001 1002 if (cpi->cpi_family == 0xf) 1003 cpi->cpi_family += CPI_FAMILY_XTD(cpi); 1004 1005 /* 1006 * Beware: AMD uses "extended model" iff base *FAMILY* == 0xf. 1007 * Intel, and presumably everyone else, uses model == 0xf, as 1008 * one would expect (max value means possible overflow). Sigh. 1009 */ 1010 1011 switch (cpi->cpi_vendor) { 1012 case X86_VENDOR_Intel: 1013 if (IS_EXTENDED_MODEL_INTEL(cpi)) 1014 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 1015 break; 1016 case X86_VENDOR_AMD: 1017 if (CPI_FAMILY(cpi) == 0xf) 1018 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 1019 break; 1020 default: 1021 if (cpi->cpi_model == 0xf) 1022 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 1023 break; 1024 } 1025 1026 cpi->cpi_step = CPI_STEP(cpi); 1027 cpi->cpi_brandid = CPI_BRANDID(cpi); 1028 1029 /* 1030 * *default* assumptions: 1031 * - believe %edx feature word 1032 * - ignore %ecx feature word 1033 * - 32-bit virtual and physical addressing 1034 */ 1035 mask_edx = 0xffffffff; 1036 mask_ecx = 0; 1037 1038 cpi->cpi_pabits = cpi->cpi_vabits = 32; 1039 1040 switch (cpi->cpi_vendor) { 1041 case X86_VENDOR_Intel: 1042 if (cpi->cpi_family == 5) 1043 x86_type = X86_TYPE_P5; 1044 else if (IS_LEGACY_P6(cpi)) { 1045 x86_type = X86_TYPE_P6; 1046 pentiumpro_bug4046376 = 1; 1047 /* 1048 * Clear the SEP bit when it was set erroneously 1049 */ 1050 if (cpi->cpi_model < 3 && cpi->cpi_step < 3) 1051 cp->cp_edx &= ~CPUID_INTC_EDX_SEP; 1052 } else if (IS_NEW_F6(cpi) || cpi->cpi_family == 0xf) { 1053 x86_type = X86_TYPE_P4; 1054 /* 1055 * We don't currently depend on any of the %ecx 1056 * features until Prescott, so we'll only check 1057 * this from P4 onwards. We might want to revisit 1058 * that idea later. 1059 */ 1060 mask_ecx = 0xffffffff; 1061 } else if (cpi->cpi_family > 0xf) 1062 mask_ecx = 0xffffffff; 1063 /* 1064 * We don't support MONITOR/MWAIT if leaf 5 is not available 1065 * to obtain the monitor linesize. 1066 */ 1067 if (cpi->cpi_maxeax < 5) 1068 mask_ecx &= ~CPUID_INTC_ECX_MON; 1069 break; 1070 case X86_VENDOR_IntelClone: 1071 default: 1072 break; 1073 case X86_VENDOR_AMD: 1074 #if defined(OPTERON_ERRATUM_108) 1075 if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) { 1076 cp->cp_eax = (0xf0f & cp->cp_eax) | 0xc0; 1077 cpi->cpi_model = 0xc; 1078 } else 1079 #endif 1080 if (cpi->cpi_family == 5) { 1081 /* 1082 * AMD K5 and K6 1083 * 1084 * These CPUs have an incomplete implementation 1085 * of MCA/MCE which we mask away. 1086 */ 1087 mask_edx &= ~(CPUID_INTC_EDX_MCE | CPUID_INTC_EDX_MCA); 1088 1089 /* 1090 * Model 0 uses the wrong (APIC) bit 1091 * to indicate PGE. Fix it here. 1092 */ 1093 if (cpi->cpi_model == 0) { 1094 if (cp->cp_edx & 0x200) { 1095 cp->cp_edx &= ~0x200; 1096 cp->cp_edx |= CPUID_INTC_EDX_PGE; 1097 } 1098 } 1099 1100 /* 1101 * Early models had problems w/ MMX; disable. 1102 */ 1103 if (cpi->cpi_model < 6) 1104 mask_edx &= ~CPUID_INTC_EDX_MMX; 1105 } 1106 1107 /* 1108 * For newer families, SSE3 and CX16, at least, are valid; 1109 * enable all 1110 */ 1111 if (cpi->cpi_family >= 0xf) 1112 mask_ecx = 0xffffffff; 1113 /* 1114 * We don't support MONITOR/MWAIT if leaf 5 is not available 1115 * to obtain the monitor linesize. 1116 */ 1117 if (cpi->cpi_maxeax < 5) 1118 mask_ecx &= ~CPUID_INTC_ECX_MON; 1119 1120 #if !defined(__xpv) 1121 /* 1122 * Do not use MONITOR/MWAIT to halt in the idle loop on any AMD 1123 * processors. AMD does not intend MWAIT to be used in the cpu 1124 * idle loop on current and future processors. 10h and future 1125 * AMD processors use more power in MWAIT than HLT. 1126 * Pre-family-10h Opterons do not have the MWAIT instruction. 1127 */ 1128 idle_cpu_prefer_mwait = 0; 1129 #endif 1130 1131 break; 1132 case X86_VENDOR_TM: 1133 /* 1134 * workaround the NT workaround in CMS 4.1 1135 */ 1136 if (cpi->cpi_family == 5 && cpi->cpi_model == 4 && 1137 (cpi->cpi_step == 2 || cpi->cpi_step == 3)) 1138 cp->cp_edx |= CPUID_INTC_EDX_CX8; 1139 break; 1140 case X86_VENDOR_Centaur: 1141 /* 1142 * workaround the NT workarounds again 1143 */ 1144 if (cpi->cpi_family == 6) 1145 cp->cp_edx |= CPUID_INTC_EDX_CX8; 1146 break; 1147 case X86_VENDOR_Cyrix: 1148 /* 1149 * We rely heavily on the probing in locore 1150 * to actually figure out what parts, if any, 1151 * of the Cyrix cpuid instruction to believe. 1152 */ 1153 switch (x86_type) { 1154 case X86_TYPE_CYRIX_486: 1155 mask_edx = 0; 1156 break; 1157 case X86_TYPE_CYRIX_6x86: 1158 mask_edx = 0; 1159 break; 1160 case X86_TYPE_CYRIX_6x86L: 1161 mask_edx = 1162 CPUID_INTC_EDX_DE | 1163 CPUID_INTC_EDX_CX8; 1164 break; 1165 case X86_TYPE_CYRIX_6x86MX: 1166 mask_edx = 1167 CPUID_INTC_EDX_DE | 1168 CPUID_INTC_EDX_MSR | 1169 CPUID_INTC_EDX_CX8 | 1170 CPUID_INTC_EDX_PGE | 1171 CPUID_INTC_EDX_CMOV | 1172 CPUID_INTC_EDX_MMX; 1173 break; 1174 case X86_TYPE_CYRIX_GXm: 1175 mask_edx = 1176 CPUID_INTC_EDX_MSR | 1177 CPUID_INTC_EDX_CX8 | 1178 CPUID_INTC_EDX_CMOV | 1179 CPUID_INTC_EDX_MMX; 1180 break; 1181 case X86_TYPE_CYRIX_MediaGX: 1182 break; 1183 case X86_TYPE_CYRIX_MII: 1184 case X86_TYPE_VIA_CYRIX_III: 1185 mask_edx = 1186 CPUID_INTC_EDX_DE | 1187 CPUID_INTC_EDX_TSC | 1188 CPUID_INTC_EDX_MSR | 1189 CPUID_INTC_EDX_CX8 | 1190 CPUID_INTC_EDX_PGE | 1191 CPUID_INTC_EDX_CMOV | 1192 CPUID_INTC_EDX_MMX; 1193 break; 1194 default: 1195 break; 1196 } 1197 break; 1198 } 1199 1200 #if defined(__xpv) 1201 /* 1202 * Do not support MONITOR/MWAIT under a hypervisor 1203 */ 1204 mask_ecx &= ~CPUID_INTC_ECX_MON; 1205 /* 1206 * Do not support XSAVE under a hypervisor for now 1207 */ 1208 xsave_force_disable = B_TRUE; 1209 1210 #endif /* __xpv */ 1211 1212 if (xsave_force_disable) { 1213 mask_ecx &= ~CPUID_INTC_ECX_XSAVE; 1214 mask_ecx &= ~CPUID_INTC_ECX_AVX; 1215 mask_ecx &= ~CPUID_INTC_ECX_F16C; 1216 mask_ecx &= ~CPUID_INTC_ECX_FMA; 1217 } 1218 1219 /* 1220 * Now we've figured out the masks that determine 1221 * which bits we choose to believe, apply the masks 1222 * to the feature words, then map the kernel's view 1223 * of these feature words into its feature word. 1224 */ 1225 cp->cp_edx &= mask_edx; 1226 cp->cp_ecx &= mask_ecx; 1227 1228 /* 1229 * apply any platform restrictions (we don't call this 1230 * immediately after __cpuid_insn here, because we need the 1231 * workarounds applied above first) 1232 */ 1233 platform_cpuid_mangle(cpi->cpi_vendor, 1, cp); 1234 1235 /* 1236 * In addition to ecx and edx, Intel is storing a bunch of instruction 1237 * set extensions in leaf 7's ebx. 1238 */ 1239 if (cpi->cpi_vendor == X86_VENDOR_Intel && cpi->cpi_maxeax >= 7) { 1240 struct cpuid_regs *ecp; 1241 ecp = &cpi->cpi_std[7]; 1242 ecp->cp_eax = 7; 1243 ecp->cp_ecx = 0; 1244 (void) __cpuid_insn(ecp); 1245 /* 1246 * If XSAVE has been disabled, just ignore all of the AVX 1247 * dependent flags here. 1248 */ 1249 if (xsave_force_disable) { 1250 ecp->cp_ebx &= ~CPUID_INTC_EBX_7_0_BMI1; 1251 ecp->cp_ebx &= ~CPUID_INTC_EBX_7_0_BMI2; 1252 ecp->cp_ebx &= ~CPUID_INTC_EBX_7_0_AVX2; 1253 } 1254 1255 if (ecp->cp_ebx & CPUID_INTC_EBX_7_0_SMEP) 1256 add_x86_feature(featureset, X86FSET_SMEP); 1257 1258 if (ecp->cp_ebx & CPUID_INTC_EBX_7_0_RDSEED) 1259 add_x86_feature(featureset, X86FSET_RDSEED); 1260 1261 if (ecp->cp_ebx & CPUID_INTC_EBX_7_0_ADX) 1262 add_x86_feature(featureset, X86FSET_ADX); 1263 } 1264 1265 /* 1266 * fold in overrides from the "eeprom" mechanism 1267 */ 1268 cp->cp_edx |= cpuid_feature_edx_include; 1269 cp->cp_edx &= ~cpuid_feature_edx_exclude; 1270 1271 cp->cp_ecx |= cpuid_feature_ecx_include; 1272 cp->cp_ecx &= ~cpuid_feature_ecx_exclude; 1273 1274 if (cp->cp_edx & CPUID_INTC_EDX_PSE) { 1275 add_x86_feature(featureset, X86FSET_LARGEPAGE); 1276 } 1277 if (cp->cp_edx & CPUID_INTC_EDX_TSC) { 1278 add_x86_feature(featureset, X86FSET_TSC); 1279 } 1280 if (cp->cp_edx & CPUID_INTC_EDX_MSR) { 1281 add_x86_feature(featureset, X86FSET_MSR); 1282 } 1283 if (cp->cp_edx & CPUID_INTC_EDX_MTRR) { 1284 add_x86_feature(featureset, X86FSET_MTRR); 1285 } 1286 if (cp->cp_edx & CPUID_INTC_EDX_PGE) { 1287 add_x86_feature(featureset, X86FSET_PGE); 1288 } 1289 if (cp->cp_edx & CPUID_INTC_EDX_CMOV) { 1290 add_x86_feature(featureset, X86FSET_CMOV); 1291 } 1292 if (cp->cp_edx & CPUID_INTC_EDX_MMX) { 1293 add_x86_feature(featureset, X86FSET_MMX); 1294 } 1295 if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 && 1296 (cp->cp_edx & CPUID_INTC_EDX_MCA) != 0) { 1297 add_x86_feature(featureset, X86FSET_MCA); 1298 } 1299 if (cp->cp_edx & CPUID_INTC_EDX_PAE) { 1300 add_x86_feature(featureset, X86FSET_PAE); 1301 } 1302 if (cp->cp_edx & CPUID_INTC_EDX_CX8) { 1303 add_x86_feature(featureset, X86FSET_CX8); 1304 } 1305 if (cp->cp_ecx & CPUID_INTC_ECX_CX16) { 1306 add_x86_feature(featureset, X86FSET_CX16); 1307 } 1308 if (cp->cp_edx & CPUID_INTC_EDX_PAT) { 1309 add_x86_feature(featureset, X86FSET_PAT); 1310 } 1311 if (cp->cp_edx & CPUID_INTC_EDX_SEP) { 1312 add_x86_feature(featureset, X86FSET_SEP); 1313 } 1314 if (cp->cp_edx & CPUID_INTC_EDX_FXSR) { 1315 /* 1316 * In our implementation, fxsave/fxrstor 1317 * are prerequisites before we'll even 1318 * try and do SSE things. 1319 */ 1320 if (cp->cp_edx & CPUID_INTC_EDX_SSE) { 1321 add_x86_feature(featureset, X86FSET_SSE); 1322 } 1323 if (cp->cp_edx & CPUID_INTC_EDX_SSE2) { 1324 add_x86_feature(featureset, X86FSET_SSE2); 1325 } 1326 if (cp->cp_ecx & CPUID_INTC_ECX_SSE3) { 1327 add_x86_feature(featureset, X86FSET_SSE3); 1328 } 1329 if (cp->cp_ecx & CPUID_INTC_ECX_SSSE3) { 1330 add_x86_feature(featureset, X86FSET_SSSE3); 1331 } 1332 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_1) { 1333 add_x86_feature(featureset, X86FSET_SSE4_1); 1334 } 1335 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_2) { 1336 add_x86_feature(featureset, X86FSET_SSE4_2); 1337 } 1338 if (cp->cp_ecx & CPUID_INTC_ECX_AES) { 1339 add_x86_feature(featureset, X86FSET_AES); 1340 } 1341 if (cp->cp_ecx & CPUID_INTC_ECX_PCLMULQDQ) { 1342 add_x86_feature(featureset, X86FSET_PCLMULQDQ); 1343 } 1344 1345 if (cp->cp_ecx & CPUID_INTC_ECX_XSAVE) { 1346 add_x86_feature(featureset, X86FSET_XSAVE); 1347 1348 /* We only test AVX when there is XSAVE */ 1349 if (cp->cp_ecx & CPUID_INTC_ECX_AVX) { 1350 add_x86_feature(featureset, 1351 X86FSET_AVX); 1352 1353 /* 1354 * Intel says we can't check these without also 1355 * checking AVX. 1356 */ 1357 if (cp->cp_ecx & CPUID_INTC_ECX_F16C) 1358 add_x86_feature(featureset, 1359 X86FSET_F16C); 1360 1361 if (cp->cp_ecx & CPUID_INTC_ECX_FMA) 1362 add_x86_feature(featureset, 1363 X86FSET_FMA); 1364 1365 if (cpi->cpi_std[7].cp_ebx & 1366 CPUID_INTC_EBX_7_0_BMI1) 1367 add_x86_feature(featureset, 1368 X86FSET_BMI1); 1369 1370 if (cpi->cpi_std[7].cp_ebx & 1371 CPUID_INTC_EBX_7_0_BMI2) 1372 add_x86_feature(featureset, 1373 X86FSET_BMI2); 1374 1375 if (cpi->cpi_std[7].cp_ebx & 1376 CPUID_INTC_EBX_7_0_AVX2) 1377 add_x86_feature(featureset, 1378 X86FSET_AVX2); 1379 } 1380 } 1381 } 1382 if (cp->cp_ecx & CPUID_INTC_ECX_X2APIC) { 1383 add_x86_feature(featureset, X86FSET_X2APIC); 1384 } 1385 if (cp->cp_edx & CPUID_INTC_EDX_DE) { 1386 add_x86_feature(featureset, X86FSET_DE); 1387 } 1388 #if !defined(__xpv) 1389 if (cp->cp_ecx & CPUID_INTC_ECX_MON) { 1390 1391 /* 1392 * We require the CLFLUSH instruction for erratum workaround 1393 * to use MONITOR/MWAIT. 1394 */ 1395 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) { 1396 cpi->cpi_mwait.support |= MWAIT_SUPPORT; 1397 add_x86_feature(featureset, X86FSET_MWAIT); 1398 } else { 1399 extern int idle_cpu_assert_cflush_monitor; 1400 1401 /* 1402 * All processors we are aware of which have 1403 * MONITOR/MWAIT also have CLFLUSH. 1404 */ 1405 if (idle_cpu_assert_cflush_monitor) { 1406 ASSERT((cp->cp_ecx & CPUID_INTC_ECX_MON) && 1407 (cp->cp_edx & CPUID_INTC_EDX_CLFSH)); 1408 } 1409 } 1410 } 1411 #endif /* __xpv */ 1412 1413 if (cp->cp_ecx & CPUID_INTC_ECX_VMX) { 1414 add_x86_feature(featureset, X86FSET_VMX); 1415 } 1416 1417 if (cp->cp_ecx & CPUID_INTC_ECX_RDRAND) 1418 add_x86_feature(featureset, X86FSET_RDRAND); 1419 1420 /* 1421 * Only need it first time, rest of the cpus would follow suit. 1422 * we only capture this for the bootcpu. 1423 */ 1424 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) { 1425 add_x86_feature(featureset, X86FSET_CLFSH); 1426 x86_clflush_size = (BITX(cp->cp_ebx, 15, 8) * 8); 1427 } 1428 if (is_x86_feature(featureset, X86FSET_PAE)) 1429 cpi->cpi_pabits = 36; 1430 1431 /* 1432 * Hyperthreading configuration is slightly tricky on Intel 1433 * and pure clones, and even trickier on AMD. 1434 * 1435 * (AMD chose to set the HTT bit on their CMP processors, 1436 * even though they're not actually hyperthreaded. Thus it 1437 * takes a bit more work to figure out what's really going 1438 * on ... see the handling of the CMP_LGCY bit below) 1439 */ 1440 if (cp->cp_edx & CPUID_INTC_EDX_HTT) { 1441 cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi); 1442 if (cpi->cpi_ncpu_per_chip > 1) 1443 add_x86_feature(featureset, X86FSET_HTT); 1444 } else { 1445 cpi->cpi_ncpu_per_chip = 1; 1446 } 1447 1448 /* 1449 * Work on the "extended" feature information, doing 1450 * some basic initialization for cpuid_pass2() 1451 */ 1452 xcpuid = 0; 1453 switch (cpi->cpi_vendor) { 1454 case X86_VENDOR_Intel: 1455 if (IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf) 1456 xcpuid++; 1457 break; 1458 case X86_VENDOR_AMD: 1459 if (cpi->cpi_family > 5 || 1460 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 1461 xcpuid++; 1462 break; 1463 case X86_VENDOR_Cyrix: 1464 /* 1465 * Only these Cyrix CPUs are -known- to support 1466 * extended cpuid operations. 1467 */ 1468 if (x86_type == X86_TYPE_VIA_CYRIX_III || 1469 x86_type == X86_TYPE_CYRIX_GXm) 1470 xcpuid++; 1471 break; 1472 case X86_VENDOR_Centaur: 1473 case X86_VENDOR_TM: 1474 default: 1475 xcpuid++; 1476 break; 1477 } 1478 1479 if (xcpuid) { 1480 cp = &cpi->cpi_extd[0]; 1481 cp->cp_eax = 0x80000000; 1482 cpi->cpi_xmaxeax = __cpuid_insn(cp); 1483 } 1484 1485 if (cpi->cpi_xmaxeax & 0x80000000) { 1486 1487 if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX) 1488 cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX; 1489 1490 switch (cpi->cpi_vendor) { 1491 case X86_VENDOR_Intel: 1492 case X86_VENDOR_AMD: 1493 if (cpi->cpi_xmaxeax < 0x80000001) 1494 break; 1495 cp = &cpi->cpi_extd[1]; 1496 cp->cp_eax = 0x80000001; 1497 (void) __cpuid_insn(cp); 1498 1499 if (cpi->cpi_vendor == X86_VENDOR_AMD && 1500 cpi->cpi_family == 5 && 1501 cpi->cpi_model == 6 && 1502 cpi->cpi_step == 6) { 1503 /* 1504 * K6 model 6 uses bit 10 to indicate SYSC 1505 * Later models use bit 11. Fix it here. 1506 */ 1507 if (cp->cp_edx & 0x400) { 1508 cp->cp_edx &= ~0x400; 1509 cp->cp_edx |= CPUID_AMD_EDX_SYSC; 1510 } 1511 } 1512 1513 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000001, cp); 1514 1515 /* 1516 * Compute the additions to the kernel's feature word. 1517 */ 1518 if (cp->cp_edx & CPUID_AMD_EDX_NX) { 1519 add_x86_feature(featureset, X86FSET_NX); 1520 } 1521 1522 /* 1523 * Regardless whether or not we boot 64-bit, 1524 * we should have a way to identify whether 1525 * the CPU is capable of running 64-bit. 1526 */ 1527 if (cp->cp_edx & CPUID_AMD_EDX_LM) { 1528 add_x86_feature(featureset, X86FSET_64); 1529 } 1530 1531 #if defined(__amd64) 1532 /* 1 GB large page - enable only for 64 bit kernel */ 1533 if (cp->cp_edx & CPUID_AMD_EDX_1GPG) { 1534 add_x86_feature(featureset, X86FSET_1GPG); 1535 } 1536 #endif 1537 1538 if ((cpi->cpi_vendor == X86_VENDOR_AMD) && 1539 (cpi->cpi_std[1].cp_edx & CPUID_INTC_EDX_FXSR) && 1540 (cp->cp_ecx & CPUID_AMD_ECX_SSE4A)) { 1541 add_x86_feature(featureset, X86FSET_SSE4A); 1542 } 1543 1544 /* 1545 * If both the HTT and CMP_LGCY bits are set, 1546 * then we're not actually HyperThreaded. Read 1547 * "AMD CPUID Specification" for more details. 1548 */ 1549 if (cpi->cpi_vendor == X86_VENDOR_AMD && 1550 is_x86_feature(featureset, X86FSET_HTT) && 1551 (cp->cp_ecx & CPUID_AMD_ECX_CMP_LGCY)) { 1552 remove_x86_feature(featureset, X86FSET_HTT); 1553 add_x86_feature(featureset, X86FSET_CMP); 1554 } 1555 #if defined(__amd64) 1556 /* 1557 * It's really tricky to support syscall/sysret in 1558 * the i386 kernel; we rely on sysenter/sysexit 1559 * instead. In the amd64 kernel, things are -way- 1560 * better. 1561 */ 1562 if (cp->cp_edx & CPUID_AMD_EDX_SYSC) { 1563 add_x86_feature(featureset, X86FSET_ASYSC); 1564 } 1565 1566 /* 1567 * While we're thinking about system calls, note 1568 * that AMD processors don't support sysenter 1569 * in long mode at all, so don't try to program them. 1570 */ 1571 if (x86_vendor == X86_VENDOR_AMD) { 1572 remove_x86_feature(featureset, X86FSET_SEP); 1573 } 1574 #endif 1575 if (cp->cp_edx & CPUID_AMD_EDX_TSCP) { 1576 add_x86_feature(featureset, X86FSET_TSCP); 1577 } 1578 1579 if (cp->cp_ecx & CPUID_AMD_ECX_SVM) { 1580 add_x86_feature(featureset, X86FSET_SVM); 1581 } 1582 1583 if (cp->cp_ecx & CPUID_AMD_ECX_TOPOEXT) { 1584 add_x86_feature(featureset, X86FSET_TOPOEXT); 1585 } 1586 1587 if (cp->cp_ecx & CPUID_AMD_ECX_PCEC) { 1588 add_x86_feature(featureset, X86FSET_AMD_PCEC); 1589 } 1590 break; 1591 default: 1592 break; 1593 } 1594 1595 /* 1596 * Get CPUID data about processor cores and hyperthreads. 1597 */ 1598 switch (cpi->cpi_vendor) { 1599 case X86_VENDOR_Intel: 1600 if (cpi->cpi_maxeax >= 4) { 1601 cp = &cpi->cpi_std[4]; 1602 cp->cp_eax = 4; 1603 cp->cp_ecx = 0; 1604 (void) __cpuid_insn(cp); 1605 platform_cpuid_mangle(cpi->cpi_vendor, 4, cp); 1606 } 1607 /*FALLTHROUGH*/ 1608 case X86_VENDOR_AMD: 1609 if (cpi->cpi_xmaxeax < 0x80000008) 1610 break; 1611 cp = &cpi->cpi_extd[8]; 1612 cp->cp_eax = 0x80000008; 1613 (void) __cpuid_insn(cp); 1614 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000008, cp); 1615 1616 /* 1617 * Virtual and physical address limits from 1618 * cpuid override previously guessed values. 1619 */ 1620 cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0); 1621 cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8); 1622 break; 1623 default: 1624 break; 1625 } 1626 1627 /* 1628 * Derive the number of cores per chip 1629 */ 1630 switch (cpi->cpi_vendor) { 1631 case X86_VENDOR_Intel: 1632 if (cpi->cpi_maxeax < 4) { 1633 cpi->cpi_ncore_per_chip = 1; 1634 break; 1635 } else { 1636 cpi->cpi_ncore_per_chip = 1637 BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1; 1638 } 1639 break; 1640 case X86_VENDOR_AMD: 1641 if (cpi->cpi_xmaxeax < 0x80000008) { 1642 cpi->cpi_ncore_per_chip = 1; 1643 break; 1644 } else { 1645 /* 1646 * On family 0xf cpuid fn 2 ECX[7:0] "NC" is 1647 * 1 less than the number of physical cores on 1648 * the chip. In family 0x10 this value can 1649 * be affected by "downcoring" - it reflects 1650 * 1 less than the number of cores actually 1651 * enabled on this node. 1652 */ 1653 cpi->cpi_ncore_per_chip = 1654 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1; 1655 } 1656 break; 1657 default: 1658 cpi->cpi_ncore_per_chip = 1; 1659 break; 1660 } 1661 1662 /* 1663 * Get CPUID data about TSC Invariance in Deep C-State. 1664 */ 1665 switch (cpi->cpi_vendor) { 1666 case X86_VENDOR_Intel: 1667 if (cpi->cpi_maxeax >= 7) { 1668 cp = &cpi->cpi_extd[7]; 1669 cp->cp_eax = 0x80000007; 1670 cp->cp_ecx = 0; 1671 (void) __cpuid_insn(cp); 1672 } 1673 break; 1674 default: 1675 break; 1676 } 1677 } else { 1678 cpi->cpi_ncore_per_chip = 1; 1679 } 1680 1681 /* 1682 * If more than one core, then this processor is CMP. 1683 */ 1684 if (cpi->cpi_ncore_per_chip > 1) { 1685 add_x86_feature(featureset, X86FSET_CMP); 1686 } 1687 1688 /* 1689 * If the number of cores is the same as the number 1690 * of CPUs, then we cannot have HyperThreading. 1691 */ 1692 if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip) { 1693 remove_x86_feature(featureset, X86FSET_HTT); 1694 } 1695 1696 cpi->cpi_apicid = CPI_APIC_ID(cpi); 1697 cpi->cpi_procnodes_per_pkg = 1; 1698 cpi->cpi_cores_per_compunit = 1; 1699 if (is_x86_feature(featureset, X86FSET_HTT) == B_FALSE && 1700 is_x86_feature(featureset, X86FSET_CMP) == B_FALSE) { 1701 /* 1702 * Single-core single-threaded processors. 1703 */ 1704 cpi->cpi_chipid = -1; 1705 cpi->cpi_clogid = 0; 1706 cpi->cpi_coreid = cpu->cpu_id; 1707 cpi->cpi_pkgcoreid = 0; 1708 if (cpi->cpi_vendor == X86_VENDOR_AMD) 1709 cpi->cpi_procnodeid = BITX(cpi->cpi_apicid, 3, 0); 1710 else 1711 cpi->cpi_procnodeid = cpi->cpi_chipid; 1712 } else if (cpi->cpi_ncpu_per_chip > 1) { 1713 if (cpi->cpi_vendor == X86_VENDOR_Intel) 1714 cpuid_intel_getids(cpu, featureset); 1715 else if (cpi->cpi_vendor == X86_VENDOR_AMD) 1716 cpuid_amd_getids(cpu); 1717 else { 1718 /* 1719 * All other processors are currently 1720 * assumed to have single cores. 1721 */ 1722 cpi->cpi_coreid = cpi->cpi_chipid; 1723 cpi->cpi_pkgcoreid = 0; 1724 cpi->cpi_procnodeid = cpi->cpi_chipid; 1725 cpi->cpi_compunitid = cpi->cpi_chipid; 1726 } 1727 } 1728 1729 /* 1730 * Synthesize chip "revision" and socket type 1731 */ 1732 cpi->cpi_chiprev = _cpuid_chiprev(cpi->cpi_vendor, cpi->cpi_family, 1733 cpi->cpi_model, cpi->cpi_step); 1734 cpi->cpi_chiprevstr = _cpuid_chiprevstr(cpi->cpi_vendor, 1735 cpi->cpi_family, cpi->cpi_model, cpi->cpi_step); 1736 cpi->cpi_socket = _cpuid_skt(cpi->cpi_vendor, cpi->cpi_family, 1737 cpi->cpi_model, cpi->cpi_step); 1738 1739 pass1_done: 1740 cpi->cpi_pass = 1; 1741 } 1742 1743 /* 1744 * Make copies of the cpuid table entries we depend on, in 1745 * part for ease of parsing now, in part so that we have only 1746 * one place to correct any of it, in part for ease of 1747 * later export to userland, and in part so we can look at 1748 * this stuff in a crash dump. 1749 */ 1750 1751 /*ARGSUSED*/ 1752 void 1753 cpuid_pass2(cpu_t *cpu) 1754 { 1755 uint_t n, nmax; 1756 int i; 1757 struct cpuid_regs *cp; 1758 uint8_t *dp; 1759 uint32_t *iptr; 1760 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1761 1762 ASSERT(cpi->cpi_pass == 1); 1763 1764 if (cpi->cpi_maxeax < 1) 1765 goto pass2_done; 1766 1767 if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD) 1768 nmax = NMAX_CPI_STD; 1769 /* 1770 * (We already handled n == 0 and n == 1 in pass 1) 1771 */ 1772 for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) { 1773 cp->cp_eax = n; 1774 1775 /* 1776 * CPUID function 4 expects %ecx to be initialized 1777 * with an index which indicates which cache to return 1778 * information about. The OS is expected to call function 4 1779 * with %ecx set to 0, 1, 2, ... until it returns with 1780 * EAX[4:0] set to 0, which indicates there are no more 1781 * caches. 1782 * 1783 * Here, populate cpi_std[4] with the information returned by 1784 * function 4 when %ecx == 0, and do the rest in cpuid_pass3() 1785 * when dynamic memory allocation becomes available. 1786 * 1787 * Note: we need to explicitly initialize %ecx here, since 1788 * function 4 may have been previously invoked. 1789 */ 1790 if (n == 4) 1791 cp->cp_ecx = 0; 1792 1793 (void) __cpuid_insn(cp); 1794 platform_cpuid_mangle(cpi->cpi_vendor, n, cp); 1795 switch (n) { 1796 case 2: 1797 /* 1798 * "the lower 8 bits of the %eax register 1799 * contain a value that identifies the number 1800 * of times the cpuid [instruction] has to be 1801 * executed to obtain a complete image of the 1802 * processor's caching systems." 1803 * 1804 * How *do* they make this stuff up? 1805 */ 1806 cpi->cpi_ncache = sizeof (*cp) * 1807 BITX(cp->cp_eax, 7, 0); 1808 if (cpi->cpi_ncache == 0) 1809 break; 1810 cpi->cpi_ncache--; /* skip count byte */ 1811 1812 /* 1813 * Well, for now, rather than attempt to implement 1814 * this slightly dubious algorithm, we just look 1815 * at the first 15 .. 1816 */ 1817 if (cpi->cpi_ncache > (sizeof (*cp) - 1)) 1818 cpi->cpi_ncache = sizeof (*cp) - 1; 1819 1820 dp = cpi->cpi_cacheinfo; 1821 if (BITX(cp->cp_eax, 31, 31) == 0) { 1822 uint8_t *p = (void *)&cp->cp_eax; 1823 for (i = 1; i < 4; i++) 1824 if (p[i] != 0) 1825 *dp++ = p[i]; 1826 } 1827 if (BITX(cp->cp_ebx, 31, 31) == 0) { 1828 uint8_t *p = (void *)&cp->cp_ebx; 1829 for (i = 0; i < 4; i++) 1830 if (p[i] != 0) 1831 *dp++ = p[i]; 1832 } 1833 if (BITX(cp->cp_ecx, 31, 31) == 0) { 1834 uint8_t *p = (void *)&cp->cp_ecx; 1835 for (i = 0; i < 4; i++) 1836 if (p[i] != 0) 1837 *dp++ = p[i]; 1838 } 1839 if (BITX(cp->cp_edx, 31, 31) == 0) { 1840 uint8_t *p = (void *)&cp->cp_edx; 1841 for (i = 0; i < 4; i++) 1842 if (p[i] != 0) 1843 *dp++ = p[i]; 1844 } 1845 break; 1846 1847 case 3: /* Processor serial number, if PSN supported */ 1848 break; 1849 1850 case 4: /* Deterministic cache parameters */ 1851 break; 1852 1853 case 5: /* Monitor/Mwait parameters */ 1854 { 1855 size_t mwait_size; 1856 1857 /* 1858 * check cpi_mwait.support which was set in cpuid_pass1 1859 */ 1860 if (!(cpi->cpi_mwait.support & MWAIT_SUPPORT)) 1861 break; 1862 1863 /* 1864 * Protect ourself from insane mwait line size. 1865 * Workaround for incomplete hardware emulator(s). 1866 */ 1867 mwait_size = (size_t)MWAIT_SIZE_MAX(cpi); 1868 if (mwait_size < sizeof (uint32_t) || 1869 !ISP2(mwait_size)) { 1870 #if DEBUG 1871 cmn_err(CE_NOTE, "Cannot handle cpu %d mwait " 1872 "size %ld", cpu->cpu_id, (long)mwait_size); 1873 #endif 1874 break; 1875 } 1876 1877 cpi->cpi_mwait.mon_min = (size_t)MWAIT_SIZE_MIN(cpi); 1878 cpi->cpi_mwait.mon_max = mwait_size; 1879 if (MWAIT_EXTENSION(cpi)) { 1880 cpi->cpi_mwait.support |= MWAIT_EXTENSIONS; 1881 if (MWAIT_INT_ENABLE(cpi)) 1882 cpi->cpi_mwait.support |= 1883 MWAIT_ECX_INT_ENABLE; 1884 } 1885 break; 1886 } 1887 default: 1888 break; 1889 } 1890 } 1891 1892 if (cpi->cpi_maxeax >= 0xB && cpi->cpi_vendor == X86_VENDOR_Intel) { 1893 struct cpuid_regs regs; 1894 1895 cp = ®s; 1896 cp->cp_eax = 0xB; 1897 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0; 1898 1899 (void) __cpuid_insn(cp); 1900 1901 /* 1902 * Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero, which 1903 * indicates that the extended topology enumeration leaf is 1904 * available. 1905 */ 1906 if (cp->cp_ebx) { 1907 uint32_t x2apic_id; 1908 uint_t coreid_shift = 0; 1909 uint_t ncpu_per_core = 1; 1910 uint_t chipid_shift = 0; 1911 uint_t ncpu_per_chip = 1; 1912 uint_t i; 1913 uint_t level; 1914 1915 for (i = 0; i < CPI_FNB_ECX_MAX; i++) { 1916 cp->cp_eax = 0xB; 1917 cp->cp_ecx = i; 1918 1919 (void) __cpuid_insn(cp); 1920 level = CPI_CPU_LEVEL_TYPE(cp); 1921 1922 if (level == 1) { 1923 x2apic_id = cp->cp_edx; 1924 coreid_shift = BITX(cp->cp_eax, 4, 0); 1925 ncpu_per_core = BITX(cp->cp_ebx, 15, 0); 1926 } else if (level == 2) { 1927 x2apic_id = cp->cp_edx; 1928 chipid_shift = BITX(cp->cp_eax, 4, 0); 1929 ncpu_per_chip = BITX(cp->cp_ebx, 15, 0); 1930 } 1931 } 1932 1933 cpi->cpi_apicid = x2apic_id; 1934 cpi->cpi_ncpu_per_chip = ncpu_per_chip; 1935 cpi->cpi_ncore_per_chip = ncpu_per_chip / 1936 ncpu_per_core; 1937 cpi->cpi_chipid = x2apic_id >> chipid_shift; 1938 cpi->cpi_clogid = x2apic_id & ((1 << chipid_shift) - 1); 1939 cpi->cpi_coreid = x2apic_id >> coreid_shift; 1940 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift; 1941 } 1942 1943 /* Make cp NULL so that we don't stumble on others */ 1944 cp = NULL; 1945 } 1946 1947 /* 1948 * XSAVE enumeration 1949 */ 1950 if (cpi->cpi_maxeax >= 0xD) { 1951 struct cpuid_regs regs; 1952 boolean_t cpuid_d_valid = B_TRUE; 1953 1954 cp = ®s; 1955 cp->cp_eax = 0xD; 1956 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0; 1957 1958 (void) __cpuid_insn(cp); 1959 1960 /* 1961 * Sanity checks for debug 1962 */ 1963 if ((cp->cp_eax & XFEATURE_LEGACY_FP) == 0 || 1964 (cp->cp_eax & XFEATURE_SSE) == 0) { 1965 cpuid_d_valid = B_FALSE; 1966 } 1967 1968 cpi->cpi_xsave.xsav_hw_features_low = cp->cp_eax; 1969 cpi->cpi_xsave.xsav_hw_features_high = cp->cp_edx; 1970 cpi->cpi_xsave.xsav_max_size = cp->cp_ecx; 1971 1972 /* 1973 * If the hw supports AVX, get the size and offset in the save 1974 * area for the ymm state. 1975 */ 1976 if (cpi->cpi_xsave.xsav_hw_features_low & XFEATURE_AVX) { 1977 cp->cp_eax = 0xD; 1978 cp->cp_ecx = 2; 1979 cp->cp_edx = cp->cp_ebx = 0; 1980 1981 (void) __cpuid_insn(cp); 1982 1983 if (cp->cp_ebx != CPUID_LEAFD_2_YMM_OFFSET || 1984 cp->cp_eax != CPUID_LEAFD_2_YMM_SIZE) { 1985 cpuid_d_valid = B_FALSE; 1986 } 1987 1988 cpi->cpi_xsave.ymm_size = cp->cp_eax; 1989 cpi->cpi_xsave.ymm_offset = cp->cp_ebx; 1990 } 1991 1992 if (is_x86_feature(x86_featureset, X86FSET_XSAVE)) { 1993 xsave_state_size = 0; 1994 } else if (cpuid_d_valid) { 1995 xsave_state_size = cpi->cpi_xsave.xsav_max_size; 1996 } else { 1997 /* Broken CPUID 0xD, probably in HVM */ 1998 cmn_err(CE_WARN, "cpu%d: CPUID.0xD returns invalid " 1999 "value: hw_low = %d, hw_high = %d, xsave_size = %d" 2000 ", ymm_size = %d, ymm_offset = %d\n", 2001 cpu->cpu_id, cpi->cpi_xsave.xsav_hw_features_low, 2002 cpi->cpi_xsave.xsav_hw_features_high, 2003 (int)cpi->cpi_xsave.xsav_max_size, 2004 (int)cpi->cpi_xsave.ymm_size, 2005 (int)cpi->cpi_xsave.ymm_offset); 2006 2007 if (xsave_state_size != 0) { 2008 /* 2009 * This must be a non-boot CPU. We cannot 2010 * continue, because boot cpu has already 2011 * enabled XSAVE. 2012 */ 2013 ASSERT(cpu->cpu_id != 0); 2014 cmn_err(CE_PANIC, "cpu%d: we have already " 2015 "enabled XSAVE on boot cpu, cannot " 2016 "continue.", cpu->cpu_id); 2017 } else { 2018 /* 2019 * If we reached here on the boot CPU, it's also 2020 * almost certain that we'll reach here on the 2021 * non-boot CPUs. When we're here on a boot CPU 2022 * we should disable the feature, on a non-boot 2023 * CPU we need to confirm that we have. 2024 */ 2025 if (cpu->cpu_id == 0) { 2026 remove_x86_feature(x86_featureset, 2027 X86FSET_XSAVE); 2028 remove_x86_feature(x86_featureset, 2029 X86FSET_AVX); 2030 remove_x86_feature(x86_featureset, 2031 X86FSET_F16C); 2032 remove_x86_feature(x86_featureset, 2033 X86FSET_BMI1); 2034 remove_x86_feature(x86_featureset, 2035 X86FSET_BMI2); 2036 remove_x86_feature(x86_featureset, 2037 X86FSET_FMA); 2038 remove_x86_feature(x86_featureset, 2039 X86FSET_AVX2); 2040 CPI_FEATURES_ECX(cpi) &= 2041 ~CPUID_INTC_ECX_XSAVE; 2042 CPI_FEATURES_ECX(cpi) &= 2043 ~CPUID_INTC_ECX_AVX; 2044 CPI_FEATURES_ECX(cpi) &= 2045 ~CPUID_INTC_ECX_F16C; 2046 CPI_FEATURES_ECX(cpi) &= 2047 ~CPUID_INTC_ECX_FMA; 2048 CPI_FEATURES_7_0_EBX(cpi) &= 2049 ~CPUID_INTC_EBX_7_0_BMI1; 2050 CPI_FEATURES_7_0_EBX(cpi) &= 2051 ~CPUID_INTC_EBX_7_0_BMI2; 2052 CPI_FEATURES_7_0_EBX(cpi) &= 2053 ~CPUID_INTC_EBX_7_0_AVX2; 2054 xsave_force_disable = B_TRUE; 2055 } else { 2056 VERIFY(is_x86_feature(x86_featureset, 2057 X86FSET_XSAVE) == B_FALSE); 2058 } 2059 } 2060 } 2061 } 2062 2063 2064 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) 2065 goto pass2_done; 2066 2067 if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD) 2068 nmax = NMAX_CPI_EXTD; 2069 /* 2070 * Copy the extended properties, fixing them as we go. 2071 * (We already handled n == 0 and n == 1 in pass 1) 2072 */ 2073 iptr = (void *)cpi->cpi_brandstr; 2074 for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) { 2075 cp->cp_eax = 0x80000000 + n; 2076 (void) __cpuid_insn(cp); 2077 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000000 + n, cp); 2078 switch (n) { 2079 case 2: 2080 case 3: 2081 case 4: 2082 /* 2083 * Extract the brand string 2084 */ 2085 *iptr++ = cp->cp_eax; 2086 *iptr++ = cp->cp_ebx; 2087 *iptr++ = cp->cp_ecx; 2088 *iptr++ = cp->cp_edx; 2089 break; 2090 case 5: 2091 switch (cpi->cpi_vendor) { 2092 case X86_VENDOR_AMD: 2093 /* 2094 * The Athlon and Duron were the first 2095 * parts to report the sizes of the 2096 * TLB for large pages. Before then, 2097 * we don't trust the data. 2098 */ 2099 if (cpi->cpi_family < 6 || 2100 (cpi->cpi_family == 6 && 2101 cpi->cpi_model < 1)) 2102 cp->cp_eax = 0; 2103 break; 2104 default: 2105 break; 2106 } 2107 break; 2108 case 6: 2109 switch (cpi->cpi_vendor) { 2110 case X86_VENDOR_AMD: 2111 /* 2112 * The Athlon and Duron were the first 2113 * AMD parts with L2 TLB's. 2114 * Before then, don't trust the data. 2115 */ 2116 if (cpi->cpi_family < 6 || 2117 cpi->cpi_family == 6 && 2118 cpi->cpi_model < 1) 2119 cp->cp_eax = cp->cp_ebx = 0; 2120 /* 2121 * AMD Duron rev A0 reports L2 2122 * cache size incorrectly as 1K 2123 * when it is really 64K 2124 */ 2125 if (cpi->cpi_family == 6 && 2126 cpi->cpi_model == 3 && 2127 cpi->cpi_step == 0) { 2128 cp->cp_ecx &= 0xffff; 2129 cp->cp_ecx |= 0x400000; 2130 } 2131 break; 2132 case X86_VENDOR_Cyrix: /* VIA C3 */ 2133 /* 2134 * VIA C3 processors are a bit messed 2135 * up w.r.t. encoding cache sizes in %ecx 2136 */ 2137 if (cpi->cpi_family != 6) 2138 break; 2139 /* 2140 * model 7 and 8 were incorrectly encoded 2141 * 2142 * xxx is model 8 really broken? 2143 */ 2144 if (cpi->cpi_model == 7 || 2145 cpi->cpi_model == 8) 2146 cp->cp_ecx = 2147 BITX(cp->cp_ecx, 31, 24) << 16 | 2148 BITX(cp->cp_ecx, 23, 16) << 12 | 2149 BITX(cp->cp_ecx, 15, 8) << 8 | 2150 BITX(cp->cp_ecx, 7, 0); 2151 /* 2152 * model 9 stepping 1 has wrong associativity 2153 */ 2154 if (cpi->cpi_model == 9 && cpi->cpi_step == 1) 2155 cp->cp_ecx |= 8 << 12; 2156 break; 2157 case X86_VENDOR_Intel: 2158 /* 2159 * Extended L2 Cache features function. 2160 * First appeared on Prescott. 2161 */ 2162 default: 2163 break; 2164 } 2165 break; 2166 default: 2167 break; 2168 } 2169 } 2170 2171 pass2_done: 2172 cpi->cpi_pass = 2; 2173 } 2174 2175 static const char * 2176 intel_cpubrand(const struct cpuid_info *cpi) 2177 { 2178 int i; 2179 2180 if (!is_x86_feature(x86_featureset, X86FSET_CPUID) || 2181 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 2182 return ("i486"); 2183 2184 switch (cpi->cpi_family) { 2185 case 5: 2186 return ("Intel Pentium(r)"); 2187 case 6: 2188 switch (cpi->cpi_model) { 2189 uint_t celeron, xeon; 2190 const struct cpuid_regs *cp; 2191 case 0: 2192 case 1: 2193 case 2: 2194 return ("Intel Pentium(r) Pro"); 2195 case 3: 2196 case 4: 2197 return ("Intel Pentium(r) II"); 2198 case 6: 2199 return ("Intel Celeron(r)"); 2200 case 5: 2201 case 7: 2202 celeron = xeon = 0; 2203 cp = &cpi->cpi_std[2]; /* cache info */ 2204 2205 for (i = 1; i < 4; i++) { 2206 uint_t tmp; 2207 2208 tmp = (cp->cp_eax >> (8 * i)) & 0xff; 2209 if (tmp == 0x40) 2210 celeron++; 2211 if (tmp >= 0x44 && tmp <= 0x45) 2212 xeon++; 2213 } 2214 2215 for (i = 0; i < 2; i++) { 2216 uint_t tmp; 2217 2218 tmp = (cp->cp_ebx >> (8 * i)) & 0xff; 2219 if (tmp == 0x40) 2220 celeron++; 2221 else if (tmp >= 0x44 && tmp <= 0x45) 2222 xeon++; 2223 } 2224 2225 for (i = 0; i < 4; i++) { 2226 uint_t tmp; 2227 2228 tmp = (cp->cp_ecx >> (8 * i)) & 0xff; 2229 if (tmp == 0x40) 2230 celeron++; 2231 else if (tmp >= 0x44 && tmp <= 0x45) 2232 xeon++; 2233 } 2234 2235 for (i = 0; i < 4; i++) { 2236 uint_t tmp; 2237 2238 tmp = (cp->cp_edx >> (8 * i)) & 0xff; 2239 if (tmp == 0x40) 2240 celeron++; 2241 else if (tmp >= 0x44 && tmp <= 0x45) 2242 xeon++; 2243 } 2244 2245 if (celeron) 2246 return ("Intel Celeron(r)"); 2247 if (xeon) 2248 return (cpi->cpi_model == 5 ? 2249 "Intel Pentium(r) II Xeon(tm)" : 2250 "Intel Pentium(r) III Xeon(tm)"); 2251 return (cpi->cpi_model == 5 ? 2252 "Intel Pentium(r) II or Pentium(r) II Xeon(tm)" : 2253 "Intel Pentium(r) III or Pentium(r) III Xeon(tm)"); 2254 default: 2255 break; 2256 } 2257 default: 2258 break; 2259 } 2260 2261 /* BrandID is present if the field is nonzero */ 2262 if (cpi->cpi_brandid != 0) { 2263 static const struct { 2264 uint_t bt_bid; 2265 const char *bt_str; 2266 } brand_tbl[] = { 2267 { 0x1, "Intel(r) Celeron(r)" }, 2268 { 0x2, "Intel(r) Pentium(r) III" }, 2269 { 0x3, "Intel(r) Pentium(r) III Xeon(tm)" }, 2270 { 0x4, "Intel(r) Pentium(r) III" }, 2271 { 0x6, "Mobile Intel(r) Pentium(r) III" }, 2272 { 0x7, "Mobile Intel(r) Celeron(r)" }, 2273 { 0x8, "Intel(r) Pentium(r) 4" }, 2274 { 0x9, "Intel(r) Pentium(r) 4" }, 2275 { 0xa, "Intel(r) Celeron(r)" }, 2276 { 0xb, "Intel(r) Xeon(tm)" }, 2277 { 0xc, "Intel(r) Xeon(tm) MP" }, 2278 { 0xe, "Mobile Intel(r) Pentium(r) 4" }, 2279 { 0xf, "Mobile Intel(r) Celeron(r)" }, 2280 { 0x11, "Mobile Genuine Intel(r)" }, 2281 { 0x12, "Intel(r) Celeron(r) M" }, 2282 { 0x13, "Mobile Intel(r) Celeron(r)" }, 2283 { 0x14, "Intel(r) Celeron(r)" }, 2284 { 0x15, "Mobile Genuine Intel(r)" }, 2285 { 0x16, "Intel(r) Pentium(r) M" }, 2286 { 0x17, "Mobile Intel(r) Celeron(r)" } 2287 }; 2288 uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]); 2289 uint_t sgn; 2290 2291 sgn = (cpi->cpi_family << 8) | 2292 (cpi->cpi_model << 4) | cpi->cpi_step; 2293 2294 for (i = 0; i < btblmax; i++) 2295 if (brand_tbl[i].bt_bid == cpi->cpi_brandid) 2296 break; 2297 if (i < btblmax) { 2298 if (sgn == 0x6b1 && cpi->cpi_brandid == 3) 2299 return ("Intel(r) Celeron(r)"); 2300 if (sgn < 0xf13 && cpi->cpi_brandid == 0xb) 2301 return ("Intel(r) Xeon(tm) MP"); 2302 if (sgn < 0xf13 && cpi->cpi_brandid == 0xe) 2303 return ("Intel(r) Xeon(tm)"); 2304 return (brand_tbl[i].bt_str); 2305 } 2306 } 2307 2308 return (NULL); 2309 } 2310 2311 static const char * 2312 amd_cpubrand(const struct cpuid_info *cpi) 2313 { 2314 if (!is_x86_feature(x86_featureset, X86FSET_CPUID) || 2315 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 2316 return ("i486 compatible"); 2317 2318 switch (cpi->cpi_family) { 2319 case 5: 2320 switch (cpi->cpi_model) { 2321 case 0: 2322 case 1: 2323 case 2: 2324 case 3: 2325 case 4: 2326 case 5: 2327 return ("AMD-K5(r)"); 2328 case 6: 2329 case 7: 2330 return ("AMD-K6(r)"); 2331 case 8: 2332 return ("AMD-K6(r)-2"); 2333 case 9: 2334 return ("AMD-K6(r)-III"); 2335 default: 2336 return ("AMD (family 5)"); 2337 } 2338 case 6: 2339 switch (cpi->cpi_model) { 2340 case 1: 2341 return ("AMD-K7(tm)"); 2342 case 0: 2343 case 2: 2344 case 4: 2345 return ("AMD Athlon(tm)"); 2346 case 3: 2347 case 7: 2348 return ("AMD Duron(tm)"); 2349 case 6: 2350 case 8: 2351 case 10: 2352 /* 2353 * Use the L2 cache size to distinguish 2354 */ 2355 return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ? 2356 "AMD Athlon(tm)" : "AMD Duron(tm)"); 2357 default: 2358 return ("AMD (family 6)"); 2359 } 2360 default: 2361 break; 2362 } 2363 2364 if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 && 2365 cpi->cpi_brandid != 0) { 2366 switch (BITX(cpi->cpi_brandid, 7, 5)) { 2367 case 3: 2368 return ("AMD Opteron(tm) UP 1xx"); 2369 case 4: 2370 return ("AMD Opteron(tm) DP 2xx"); 2371 case 5: 2372 return ("AMD Opteron(tm) MP 8xx"); 2373 default: 2374 return ("AMD Opteron(tm)"); 2375 } 2376 } 2377 2378 return (NULL); 2379 } 2380 2381 static const char * 2382 cyrix_cpubrand(struct cpuid_info *cpi, uint_t type) 2383 { 2384 if (!is_x86_feature(x86_featureset, X86FSET_CPUID) || 2385 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5 || 2386 type == X86_TYPE_CYRIX_486) 2387 return ("i486 compatible"); 2388 2389 switch (type) { 2390 case X86_TYPE_CYRIX_6x86: 2391 return ("Cyrix 6x86"); 2392 case X86_TYPE_CYRIX_6x86L: 2393 return ("Cyrix 6x86L"); 2394 case X86_TYPE_CYRIX_6x86MX: 2395 return ("Cyrix 6x86MX"); 2396 case X86_TYPE_CYRIX_GXm: 2397 return ("Cyrix GXm"); 2398 case X86_TYPE_CYRIX_MediaGX: 2399 return ("Cyrix MediaGX"); 2400 case X86_TYPE_CYRIX_MII: 2401 return ("Cyrix M2"); 2402 case X86_TYPE_VIA_CYRIX_III: 2403 return ("VIA Cyrix M3"); 2404 default: 2405 /* 2406 * Have another wild guess .. 2407 */ 2408 if (cpi->cpi_family == 4 && cpi->cpi_model == 9) 2409 return ("Cyrix 5x86"); 2410 else if (cpi->cpi_family == 5) { 2411 switch (cpi->cpi_model) { 2412 case 2: 2413 return ("Cyrix 6x86"); /* Cyrix M1 */ 2414 case 4: 2415 return ("Cyrix MediaGX"); 2416 default: 2417 break; 2418 } 2419 } else if (cpi->cpi_family == 6) { 2420 switch (cpi->cpi_model) { 2421 case 0: 2422 return ("Cyrix 6x86MX"); /* Cyrix M2? */ 2423 case 5: 2424 case 6: 2425 case 7: 2426 case 8: 2427 case 9: 2428 return ("VIA C3"); 2429 default: 2430 break; 2431 } 2432 } 2433 break; 2434 } 2435 return (NULL); 2436 } 2437 2438 /* 2439 * This only gets called in the case that the CPU extended 2440 * feature brand string (0x80000002, 0x80000003, 0x80000004) 2441 * aren't available, or contain null bytes for some reason. 2442 */ 2443 static void 2444 fabricate_brandstr(struct cpuid_info *cpi) 2445 { 2446 const char *brand = NULL; 2447 2448 switch (cpi->cpi_vendor) { 2449 case X86_VENDOR_Intel: 2450 brand = intel_cpubrand(cpi); 2451 break; 2452 case X86_VENDOR_AMD: 2453 brand = amd_cpubrand(cpi); 2454 break; 2455 case X86_VENDOR_Cyrix: 2456 brand = cyrix_cpubrand(cpi, x86_type); 2457 break; 2458 case X86_VENDOR_NexGen: 2459 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 2460 brand = "NexGen Nx586"; 2461 break; 2462 case X86_VENDOR_Centaur: 2463 if (cpi->cpi_family == 5) 2464 switch (cpi->cpi_model) { 2465 case 4: 2466 brand = "Centaur C6"; 2467 break; 2468 case 8: 2469 brand = "Centaur C2"; 2470 break; 2471 case 9: 2472 brand = "Centaur C3"; 2473 break; 2474 default: 2475 break; 2476 } 2477 break; 2478 case X86_VENDOR_Rise: 2479 if (cpi->cpi_family == 5 && 2480 (cpi->cpi_model == 0 || cpi->cpi_model == 2)) 2481 brand = "Rise mP6"; 2482 break; 2483 case X86_VENDOR_SiS: 2484 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 2485 brand = "SiS 55x"; 2486 break; 2487 case X86_VENDOR_TM: 2488 if (cpi->cpi_family == 5 && cpi->cpi_model == 4) 2489 brand = "Transmeta Crusoe TM3x00 or TM5x00"; 2490 break; 2491 case X86_VENDOR_NSC: 2492 case X86_VENDOR_UMC: 2493 default: 2494 break; 2495 } 2496 if (brand) { 2497 (void) strcpy((char *)cpi->cpi_brandstr, brand); 2498 return; 2499 } 2500 2501 /* 2502 * If all else fails ... 2503 */ 2504 (void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr), 2505 "%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family, 2506 cpi->cpi_model, cpi->cpi_step); 2507 } 2508 2509 /* 2510 * This routine is called just after kernel memory allocation 2511 * becomes available on cpu0, and as part of mp_startup() on 2512 * the other cpus. 2513 * 2514 * Fixup the brand string, and collect any information from cpuid 2515 * that requires dynamically allocated storage to represent. 2516 */ 2517 /*ARGSUSED*/ 2518 void 2519 cpuid_pass3(cpu_t *cpu) 2520 { 2521 int i, max, shft, level, size; 2522 struct cpuid_regs regs; 2523 struct cpuid_regs *cp; 2524 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2525 2526 ASSERT(cpi->cpi_pass == 2); 2527 2528 /* 2529 * Function 4: Deterministic cache parameters 2530 * 2531 * Take this opportunity to detect the number of threads 2532 * sharing the last level cache, and construct a corresponding 2533 * cache id. The respective cpuid_info members are initialized 2534 * to the default case of "no last level cache sharing". 2535 */ 2536 cpi->cpi_ncpu_shr_last_cache = 1; 2537 cpi->cpi_last_lvl_cacheid = cpu->cpu_id; 2538 2539 if (cpi->cpi_maxeax >= 4 && cpi->cpi_vendor == X86_VENDOR_Intel) { 2540 2541 /* 2542 * Find the # of elements (size) returned by fn 4, and along 2543 * the way detect last level cache sharing details. 2544 */ 2545 bzero(®s, sizeof (regs)); 2546 cp = ®s; 2547 for (i = 0, max = 0; i < CPI_FN4_ECX_MAX; i++) { 2548 cp->cp_eax = 4; 2549 cp->cp_ecx = i; 2550 2551 (void) __cpuid_insn(cp); 2552 2553 if (CPI_CACHE_TYPE(cp) == 0) 2554 break; 2555 level = CPI_CACHE_LVL(cp); 2556 if (level > max) { 2557 max = level; 2558 cpi->cpi_ncpu_shr_last_cache = 2559 CPI_NTHR_SHR_CACHE(cp) + 1; 2560 } 2561 } 2562 cpi->cpi_std_4_size = size = i; 2563 2564 /* 2565 * Allocate the cpi_std_4 array. The first element 2566 * references the regs for fn 4, %ecx == 0, which 2567 * cpuid_pass2() stashed in cpi->cpi_std[4]. 2568 */ 2569 if (size > 0) { 2570 cpi->cpi_std_4 = 2571 kmem_alloc(size * sizeof (cp), KM_SLEEP); 2572 cpi->cpi_std_4[0] = &cpi->cpi_std[4]; 2573 2574 /* 2575 * Allocate storage to hold the additional regs 2576 * for function 4, %ecx == 1 .. cpi_std_4_size. 2577 * 2578 * The regs for fn 4, %ecx == 0 has already 2579 * been allocated as indicated above. 2580 */ 2581 for (i = 1; i < size; i++) { 2582 cp = cpi->cpi_std_4[i] = 2583 kmem_zalloc(sizeof (regs), KM_SLEEP); 2584 cp->cp_eax = 4; 2585 cp->cp_ecx = i; 2586 2587 (void) __cpuid_insn(cp); 2588 } 2589 } 2590 /* 2591 * Determine the number of bits needed to represent 2592 * the number of CPUs sharing the last level cache. 2593 * 2594 * Shift off that number of bits from the APIC id to 2595 * derive the cache id. 2596 */ 2597 shft = 0; 2598 for (i = 1; i < cpi->cpi_ncpu_shr_last_cache; i <<= 1) 2599 shft++; 2600 cpi->cpi_last_lvl_cacheid = cpi->cpi_apicid >> shft; 2601 } 2602 2603 /* 2604 * Now fixup the brand string 2605 */ 2606 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) { 2607 fabricate_brandstr(cpi); 2608 } else { 2609 2610 /* 2611 * If we successfully extracted a brand string from the cpuid 2612 * instruction, clean it up by removing leading spaces and 2613 * similar junk. 2614 */ 2615 if (cpi->cpi_brandstr[0]) { 2616 size_t maxlen = sizeof (cpi->cpi_brandstr); 2617 char *src, *dst; 2618 2619 dst = src = (char *)cpi->cpi_brandstr; 2620 src[maxlen - 1] = '\0'; 2621 /* 2622 * strip leading spaces 2623 */ 2624 while (*src == ' ') 2625 src++; 2626 /* 2627 * Remove any 'Genuine' or "Authentic" prefixes 2628 */ 2629 if (strncmp(src, "Genuine ", 8) == 0) 2630 src += 8; 2631 if (strncmp(src, "Authentic ", 10) == 0) 2632 src += 10; 2633 2634 /* 2635 * Now do an in-place copy. 2636 * Map (R) to (r) and (TM) to (tm). 2637 * The era of teletypes is long gone, and there's 2638 * -really- no need to shout. 2639 */ 2640 while (*src != '\0') { 2641 if (src[0] == '(') { 2642 if (strncmp(src + 1, "R)", 2) == 0) { 2643 (void) strncpy(dst, "(r)", 3); 2644 src += 3; 2645 dst += 3; 2646 continue; 2647 } 2648 if (strncmp(src + 1, "TM)", 3) == 0) { 2649 (void) strncpy(dst, "(tm)", 4); 2650 src += 4; 2651 dst += 4; 2652 continue; 2653 } 2654 } 2655 *dst++ = *src++; 2656 } 2657 *dst = '\0'; 2658 2659 /* 2660 * Finally, remove any trailing spaces 2661 */ 2662 while (--dst > cpi->cpi_brandstr) 2663 if (*dst == ' ') 2664 *dst = '\0'; 2665 else 2666 break; 2667 } else 2668 fabricate_brandstr(cpi); 2669 } 2670 cpi->cpi_pass = 3; 2671 } 2672 2673 /* 2674 * This routine is called out of bind_hwcap() much later in the life 2675 * of the kernel (post_startup()). The job of this routine is to resolve 2676 * the hardware feature support and kernel support for those features into 2677 * what we're actually going to tell applications via the aux vector. 2678 */ 2679 void 2680 cpuid_pass4(cpu_t *cpu, uint_t *hwcap_out) 2681 { 2682 struct cpuid_info *cpi; 2683 uint_t hwcap_flags = 0, hwcap_flags_2 = 0; 2684 2685 if (cpu == NULL) 2686 cpu = CPU; 2687 cpi = cpu->cpu_m.mcpu_cpi; 2688 2689 ASSERT(cpi->cpi_pass == 3); 2690 2691 if (cpi->cpi_maxeax >= 1) { 2692 uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES]; 2693 uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES]; 2694 uint32_t *ebx = &cpi->cpi_support[STD_EBX_FEATURES]; 2695 2696 *edx = CPI_FEATURES_EDX(cpi); 2697 *ecx = CPI_FEATURES_ECX(cpi); 2698 *ebx = CPI_FEATURES_7_0_EBX(cpi); 2699 2700 /* 2701 * [these require explicit kernel support] 2702 */ 2703 if (!is_x86_feature(x86_featureset, X86FSET_SEP)) 2704 *edx &= ~CPUID_INTC_EDX_SEP; 2705 2706 if (!is_x86_feature(x86_featureset, X86FSET_SSE)) 2707 *edx &= ~(CPUID_INTC_EDX_FXSR|CPUID_INTC_EDX_SSE); 2708 if (!is_x86_feature(x86_featureset, X86FSET_SSE2)) 2709 *edx &= ~CPUID_INTC_EDX_SSE2; 2710 2711 if (!is_x86_feature(x86_featureset, X86FSET_HTT)) 2712 *edx &= ~CPUID_INTC_EDX_HTT; 2713 2714 if (!is_x86_feature(x86_featureset, X86FSET_SSE3)) 2715 *ecx &= ~CPUID_INTC_ECX_SSE3; 2716 2717 if (!is_x86_feature(x86_featureset, X86FSET_SSSE3)) 2718 *ecx &= ~CPUID_INTC_ECX_SSSE3; 2719 if (!is_x86_feature(x86_featureset, X86FSET_SSE4_1)) 2720 *ecx &= ~CPUID_INTC_ECX_SSE4_1; 2721 if (!is_x86_feature(x86_featureset, X86FSET_SSE4_2)) 2722 *ecx &= ~CPUID_INTC_ECX_SSE4_2; 2723 if (!is_x86_feature(x86_featureset, X86FSET_AES)) 2724 *ecx &= ~CPUID_INTC_ECX_AES; 2725 if (!is_x86_feature(x86_featureset, X86FSET_PCLMULQDQ)) 2726 *ecx &= ~CPUID_INTC_ECX_PCLMULQDQ; 2727 if (!is_x86_feature(x86_featureset, X86FSET_XSAVE)) 2728 *ecx &= ~(CPUID_INTC_ECX_XSAVE | 2729 CPUID_INTC_ECX_OSXSAVE); 2730 if (!is_x86_feature(x86_featureset, X86FSET_AVX)) 2731 *ecx &= ~CPUID_INTC_ECX_AVX; 2732 if (!is_x86_feature(x86_featureset, X86FSET_F16C)) 2733 *ecx &= ~CPUID_INTC_ECX_F16C; 2734 if (!is_x86_feature(x86_featureset, X86FSET_FMA)) 2735 *ecx &= ~CPUID_INTC_ECX_FMA; 2736 if (!is_x86_feature(x86_featureset, X86FSET_BMI1)) 2737 *ebx &= ~CPUID_INTC_EBX_7_0_BMI1; 2738 if (!is_x86_feature(x86_featureset, X86FSET_BMI2)) 2739 *ebx &= ~CPUID_INTC_EBX_7_0_BMI2; 2740 if (!is_x86_feature(x86_featureset, X86FSET_AVX2)) 2741 *ebx &= ~CPUID_INTC_EBX_7_0_AVX2; 2742 if (!is_x86_feature(x86_featureset, X86FSET_RDSEED)) 2743 *ebx &= ~CPUID_INTC_EBX_7_0_RDSEED; 2744 if (!is_x86_feature(x86_featureset, X86FSET_ADX)) 2745 *ebx &= ~CPUID_INTC_EBX_7_0_ADX; 2746 2747 /* 2748 * [no explicit support required beyond x87 fp context] 2749 */ 2750 if (!fpu_exists) 2751 *edx &= ~(CPUID_INTC_EDX_FPU | CPUID_INTC_EDX_MMX); 2752 2753 /* 2754 * Now map the supported feature vector to things that we 2755 * think userland will care about. 2756 */ 2757 if (*edx & CPUID_INTC_EDX_SEP) 2758 hwcap_flags |= AV_386_SEP; 2759 if (*edx & CPUID_INTC_EDX_SSE) 2760 hwcap_flags |= AV_386_FXSR | AV_386_SSE; 2761 if (*edx & CPUID_INTC_EDX_SSE2) 2762 hwcap_flags |= AV_386_SSE2; 2763 if (*ecx & CPUID_INTC_ECX_SSE3) 2764 hwcap_flags |= AV_386_SSE3; 2765 if (*ecx & CPUID_INTC_ECX_SSSE3) 2766 hwcap_flags |= AV_386_SSSE3; 2767 if (*ecx & CPUID_INTC_ECX_SSE4_1) 2768 hwcap_flags |= AV_386_SSE4_1; 2769 if (*ecx & CPUID_INTC_ECX_SSE4_2) 2770 hwcap_flags |= AV_386_SSE4_2; 2771 if (*ecx & CPUID_INTC_ECX_MOVBE) 2772 hwcap_flags |= AV_386_MOVBE; 2773 if (*ecx & CPUID_INTC_ECX_AES) 2774 hwcap_flags |= AV_386_AES; 2775 if (*ecx & CPUID_INTC_ECX_PCLMULQDQ) 2776 hwcap_flags |= AV_386_PCLMULQDQ; 2777 if ((*ecx & CPUID_INTC_ECX_XSAVE) && 2778 (*ecx & CPUID_INTC_ECX_OSXSAVE)) { 2779 hwcap_flags |= AV_386_XSAVE; 2780 2781 if (*ecx & CPUID_INTC_ECX_AVX) { 2782 hwcap_flags |= AV_386_AVX; 2783 if (*ecx & CPUID_INTC_ECX_F16C) 2784 hwcap_flags_2 |= AV_386_2_F16C; 2785 if (*ecx & CPUID_INTC_ECX_FMA) 2786 hwcap_flags_2 |= AV_386_2_FMA; 2787 if (*ebx & CPUID_INTC_EBX_7_0_BMI1) 2788 hwcap_flags_2 |= AV_386_2_BMI1; 2789 if (*ebx & CPUID_INTC_EBX_7_0_BMI2) 2790 hwcap_flags_2 |= AV_386_2_BMI2; 2791 if (*ebx & CPUID_INTC_EBX_7_0_AVX2) 2792 hwcap_flags_2 |= AV_386_2_AVX2; 2793 } 2794 } 2795 if (*ecx & CPUID_INTC_ECX_VMX) 2796 hwcap_flags |= AV_386_VMX; 2797 if (*ecx & CPUID_INTC_ECX_POPCNT) 2798 hwcap_flags |= AV_386_POPCNT; 2799 if (*edx & CPUID_INTC_EDX_FPU) 2800 hwcap_flags |= AV_386_FPU; 2801 if (*edx & CPUID_INTC_EDX_MMX) 2802 hwcap_flags |= AV_386_MMX; 2803 2804 if (*edx & CPUID_INTC_EDX_TSC) 2805 hwcap_flags |= AV_386_TSC; 2806 if (*edx & CPUID_INTC_EDX_CX8) 2807 hwcap_flags |= AV_386_CX8; 2808 if (*edx & CPUID_INTC_EDX_CMOV) 2809 hwcap_flags |= AV_386_CMOV; 2810 if (*ecx & CPUID_INTC_ECX_CX16) 2811 hwcap_flags |= AV_386_CX16; 2812 2813 if (*ecx & CPUID_INTC_ECX_RDRAND) 2814 hwcap_flags_2 |= AV_386_2_RDRAND; 2815 if (*ebx & CPUID_INTC_EBX_7_0_ADX) 2816 hwcap_flags_2 |= AV_386_2_ADX; 2817 if (*ebx & CPUID_INTC_EBX_7_0_RDSEED) 2818 hwcap_flags_2 |= AV_386_2_RDSEED; 2819 if (*ebx & CPUID_INTC_EBX_7_0_SHA) 2820 hwcap_flags_2 |= AV_386_2_SHA; 2821 2822 } 2823 2824 if (cpi->cpi_xmaxeax < 0x80000001) 2825 goto pass4_done; 2826 2827 switch (cpi->cpi_vendor) { 2828 struct cpuid_regs cp; 2829 uint32_t *edx, *ecx; 2830 2831 case X86_VENDOR_Intel: 2832 /* 2833 * Seems like Intel duplicated what we necessary 2834 * here to make the initial crop of 64-bit OS's work. 2835 * Hopefully, those are the only "extended" bits 2836 * they'll add. 2837 */ 2838 /*FALLTHROUGH*/ 2839 2840 case X86_VENDOR_AMD: 2841 edx = &cpi->cpi_support[AMD_EDX_FEATURES]; 2842 ecx = &cpi->cpi_support[AMD_ECX_FEATURES]; 2843 2844 *edx = CPI_FEATURES_XTD_EDX(cpi); 2845 *ecx = CPI_FEATURES_XTD_ECX(cpi); 2846 2847 /* 2848 * [these features require explicit kernel support] 2849 */ 2850 switch (cpi->cpi_vendor) { 2851 case X86_VENDOR_Intel: 2852 if (!is_x86_feature(x86_featureset, X86FSET_TSCP)) 2853 *edx &= ~CPUID_AMD_EDX_TSCP; 2854 break; 2855 2856 case X86_VENDOR_AMD: 2857 if (!is_x86_feature(x86_featureset, X86FSET_TSCP)) 2858 *edx &= ~CPUID_AMD_EDX_TSCP; 2859 if (!is_x86_feature(x86_featureset, X86FSET_SSE4A)) 2860 *ecx &= ~CPUID_AMD_ECX_SSE4A; 2861 break; 2862 2863 default: 2864 break; 2865 } 2866 2867 /* 2868 * [no explicit support required beyond 2869 * x87 fp context and exception handlers] 2870 */ 2871 if (!fpu_exists) 2872 *edx &= ~(CPUID_AMD_EDX_MMXamd | 2873 CPUID_AMD_EDX_3DNow | CPUID_AMD_EDX_3DNowx); 2874 2875 if (!is_x86_feature(x86_featureset, X86FSET_NX)) 2876 *edx &= ~CPUID_AMD_EDX_NX; 2877 #if !defined(__amd64) 2878 *edx &= ~CPUID_AMD_EDX_LM; 2879 #endif 2880 /* 2881 * Now map the supported feature vector to 2882 * things that we think userland will care about. 2883 */ 2884 #if defined(__amd64) 2885 if (*edx & CPUID_AMD_EDX_SYSC) 2886 hwcap_flags |= AV_386_AMD_SYSC; 2887 #endif 2888 if (*edx & CPUID_AMD_EDX_MMXamd) 2889 hwcap_flags |= AV_386_AMD_MMX; 2890 if (*edx & CPUID_AMD_EDX_3DNow) 2891 hwcap_flags |= AV_386_AMD_3DNow; 2892 if (*edx & CPUID_AMD_EDX_3DNowx) 2893 hwcap_flags |= AV_386_AMD_3DNowx; 2894 if (*ecx & CPUID_AMD_ECX_SVM) 2895 hwcap_flags |= AV_386_AMD_SVM; 2896 2897 switch (cpi->cpi_vendor) { 2898 case X86_VENDOR_AMD: 2899 if (*edx & CPUID_AMD_EDX_TSCP) 2900 hwcap_flags |= AV_386_TSCP; 2901 if (*ecx & CPUID_AMD_ECX_AHF64) 2902 hwcap_flags |= AV_386_AHF; 2903 if (*ecx & CPUID_AMD_ECX_SSE4A) 2904 hwcap_flags |= AV_386_AMD_SSE4A; 2905 if (*ecx & CPUID_AMD_ECX_LZCNT) 2906 hwcap_flags |= AV_386_AMD_LZCNT; 2907 break; 2908 2909 case X86_VENDOR_Intel: 2910 if (*edx & CPUID_AMD_EDX_TSCP) 2911 hwcap_flags |= AV_386_TSCP; 2912 /* 2913 * Aarrgh. 2914 * Intel uses a different bit in the same word. 2915 */ 2916 if (*ecx & CPUID_INTC_ECX_AHF64) 2917 hwcap_flags |= AV_386_AHF; 2918 break; 2919 2920 default: 2921 break; 2922 } 2923 break; 2924 2925 case X86_VENDOR_TM: 2926 cp.cp_eax = 0x80860001; 2927 (void) __cpuid_insn(&cp); 2928 cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx; 2929 break; 2930 2931 default: 2932 break; 2933 } 2934 2935 pass4_done: 2936 cpi->cpi_pass = 4; 2937 if (hwcap_out != NULL) { 2938 hwcap_out[0] = hwcap_flags; 2939 hwcap_out[1] = hwcap_flags_2; 2940 } 2941 } 2942 2943 2944 /* 2945 * Simulate the cpuid instruction using the data we previously 2946 * captured about this CPU. We try our best to return the truth 2947 * about the hardware, independently of kernel support. 2948 */ 2949 uint32_t 2950 cpuid_insn(cpu_t *cpu, struct cpuid_regs *cp) 2951 { 2952 struct cpuid_info *cpi; 2953 struct cpuid_regs *xcp; 2954 2955 if (cpu == NULL) 2956 cpu = CPU; 2957 cpi = cpu->cpu_m.mcpu_cpi; 2958 2959 ASSERT(cpuid_checkpass(cpu, 3)); 2960 2961 /* 2962 * CPUID data is cached in two separate places: cpi_std for standard 2963 * CPUID functions, and cpi_extd for extended CPUID functions. 2964 */ 2965 if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD) 2966 xcp = &cpi->cpi_std[cp->cp_eax]; 2967 else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax && 2968 cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD) 2969 xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000]; 2970 else 2971 /* 2972 * The caller is asking for data from an input parameter which 2973 * the kernel has not cached. In this case we go fetch from 2974 * the hardware and return the data directly to the user. 2975 */ 2976 return (__cpuid_insn(cp)); 2977 2978 cp->cp_eax = xcp->cp_eax; 2979 cp->cp_ebx = xcp->cp_ebx; 2980 cp->cp_ecx = xcp->cp_ecx; 2981 cp->cp_edx = xcp->cp_edx; 2982 return (cp->cp_eax); 2983 } 2984 2985 int 2986 cpuid_checkpass(cpu_t *cpu, int pass) 2987 { 2988 return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL && 2989 cpu->cpu_m.mcpu_cpi->cpi_pass >= pass); 2990 } 2991 2992 int 2993 cpuid_getbrandstr(cpu_t *cpu, char *s, size_t n) 2994 { 2995 ASSERT(cpuid_checkpass(cpu, 3)); 2996 2997 return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr)); 2998 } 2999 3000 int 3001 cpuid_is_cmt(cpu_t *cpu) 3002 { 3003 if (cpu == NULL) 3004 cpu = CPU; 3005 3006 ASSERT(cpuid_checkpass(cpu, 1)); 3007 3008 return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0); 3009 } 3010 3011 /* 3012 * AMD and Intel both implement the 64-bit variant of the syscall 3013 * instruction (syscallq), so if there's -any- support for syscall, 3014 * cpuid currently says "yes, we support this". 3015 * 3016 * However, Intel decided to -not- implement the 32-bit variant of the 3017 * syscall instruction, so we provide a predicate to allow our caller 3018 * to test that subtlety here. 3019 * 3020 * XXPV Currently, 32-bit syscall instructions don't work via the hypervisor, 3021 * even in the case where the hardware would in fact support it. 3022 */ 3023 /*ARGSUSED*/ 3024 int 3025 cpuid_syscall32_insn(cpu_t *cpu) 3026 { 3027 ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1)); 3028 3029 #if !defined(__xpv) 3030 if (cpu == NULL) 3031 cpu = CPU; 3032 3033 /*CSTYLED*/ 3034 { 3035 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 3036 3037 if (cpi->cpi_vendor == X86_VENDOR_AMD && 3038 cpi->cpi_xmaxeax >= 0x80000001 && 3039 (CPI_FEATURES_XTD_EDX(cpi) & CPUID_AMD_EDX_SYSC)) 3040 return (1); 3041 } 3042 #endif 3043 return (0); 3044 } 3045 3046 int 3047 cpuid_getidstr(cpu_t *cpu, char *s, size_t n) 3048 { 3049 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 3050 3051 static const char fmt[] = 3052 "x86 (%s %X family %d model %d step %d clock %d MHz)"; 3053 static const char fmt_ht[] = 3054 "x86 (chipid 0x%x %s %X family %d model %d step %d clock %d MHz)"; 3055 3056 ASSERT(cpuid_checkpass(cpu, 1)); 3057 3058 if (cpuid_is_cmt(cpu)) 3059 return (snprintf(s, n, fmt_ht, cpi->cpi_chipid, 3060 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, 3061 cpi->cpi_family, cpi->cpi_model, 3062 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 3063 return (snprintf(s, n, fmt, 3064 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, 3065 cpi->cpi_family, cpi->cpi_model, 3066 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 3067 } 3068 3069 const char * 3070 cpuid_getvendorstr(cpu_t *cpu) 3071 { 3072 ASSERT(cpuid_checkpass(cpu, 1)); 3073 return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr); 3074 } 3075 3076 uint_t 3077 cpuid_getvendor(cpu_t *cpu) 3078 { 3079 ASSERT(cpuid_checkpass(cpu, 1)); 3080 return (cpu->cpu_m.mcpu_cpi->cpi_vendor); 3081 } 3082 3083 uint_t 3084 cpuid_getfamily(cpu_t *cpu) 3085 { 3086 ASSERT(cpuid_checkpass(cpu, 1)); 3087 return (cpu->cpu_m.mcpu_cpi->cpi_family); 3088 } 3089 3090 uint_t 3091 cpuid_getmodel(cpu_t *cpu) 3092 { 3093 ASSERT(cpuid_checkpass(cpu, 1)); 3094 return (cpu->cpu_m.mcpu_cpi->cpi_model); 3095 } 3096 3097 uint_t 3098 cpuid_get_ncpu_per_chip(cpu_t *cpu) 3099 { 3100 ASSERT(cpuid_checkpass(cpu, 1)); 3101 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip); 3102 } 3103 3104 uint_t 3105 cpuid_get_ncore_per_chip(cpu_t *cpu) 3106 { 3107 ASSERT(cpuid_checkpass(cpu, 1)); 3108 return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip); 3109 } 3110 3111 uint_t 3112 cpuid_get_ncpu_sharing_last_cache(cpu_t *cpu) 3113 { 3114 ASSERT(cpuid_checkpass(cpu, 2)); 3115 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_shr_last_cache); 3116 } 3117 3118 id_t 3119 cpuid_get_last_lvl_cacheid(cpu_t *cpu) 3120 { 3121 ASSERT(cpuid_checkpass(cpu, 2)); 3122 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid); 3123 } 3124 3125 uint_t 3126 cpuid_getstep(cpu_t *cpu) 3127 { 3128 ASSERT(cpuid_checkpass(cpu, 1)); 3129 return (cpu->cpu_m.mcpu_cpi->cpi_step); 3130 } 3131 3132 uint_t 3133 cpuid_getsig(struct cpu *cpu) 3134 { 3135 ASSERT(cpuid_checkpass(cpu, 1)); 3136 return (cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_eax); 3137 } 3138 3139 uint32_t 3140 cpuid_getchiprev(struct cpu *cpu) 3141 { 3142 ASSERT(cpuid_checkpass(cpu, 1)); 3143 return (cpu->cpu_m.mcpu_cpi->cpi_chiprev); 3144 } 3145 3146 const char * 3147 cpuid_getchiprevstr(struct cpu *cpu) 3148 { 3149 ASSERT(cpuid_checkpass(cpu, 1)); 3150 return (cpu->cpu_m.mcpu_cpi->cpi_chiprevstr); 3151 } 3152 3153 uint32_t 3154 cpuid_getsockettype(struct cpu *cpu) 3155 { 3156 ASSERT(cpuid_checkpass(cpu, 1)); 3157 return (cpu->cpu_m.mcpu_cpi->cpi_socket); 3158 } 3159 3160 const char * 3161 cpuid_getsocketstr(cpu_t *cpu) 3162 { 3163 static const char *socketstr = NULL; 3164 struct cpuid_info *cpi; 3165 3166 ASSERT(cpuid_checkpass(cpu, 1)); 3167 cpi = cpu->cpu_m.mcpu_cpi; 3168 3169 /* Assume that socket types are the same across the system */ 3170 if (socketstr == NULL) 3171 socketstr = _cpuid_sktstr(cpi->cpi_vendor, cpi->cpi_family, 3172 cpi->cpi_model, cpi->cpi_step); 3173 3174 3175 return (socketstr); 3176 } 3177 3178 int 3179 cpuid_get_chipid(cpu_t *cpu) 3180 { 3181 ASSERT(cpuid_checkpass(cpu, 1)); 3182 3183 if (cpuid_is_cmt(cpu)) 3184 return (cpu->cpu_m.mcpu_cpi->cpi_chipid); 3185 return (cpu->cpu_id); 3186 } 3187 3188 id_t 3189 cpuid_get_coreid(cpu_t *cpu) 3190 { 3191 ASSERT(cpuid_checkpass(cpu, 1)); 3192 return (cpu->cpu_m.mcpu_cpi->cpi_coreid); 3193 } 3194 3195 int 3196 cpuid_get_pkgcoreid(cpu_t *cpu) 3197 { 3198 ASSERT(cpuid_checkpass(cpu, 1)); 3199 return (cpu->cpu_m.mcpu_cpi->cpi_pkgcoreid); 3200 } 3201 3202 int 3203 cpuid_get_clogid(cpu_t *cpu) 3204 { 3205 ASSERT(cpuid_checkpass(cpu, 1)); 3206 return (cpu->cpu_m.mcpu_cpi->cpi_clogid); 3207 } 3208 3209 int 3210 cpuid_get_cacheid(cpu_t *cpu) 3211 { 3212 ASSERT(cpuid_checkpass(cpu, 1)); 3213 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid); 3214 } 3215 3216 uint_t 3217 cpuid_get_procnodeid(cpu_t *cpu) 3218 { 3219 ASSERT(cpuid_checkpass(cpu, 1)); 3220 return (cpu->cpu_m.mcpu_cpi->cpi_procnodeid); 3221 } 3222 3223 uint_t 3224 cpuid_get_procnodes_per_pkg(cpu_t *cpu) 3225 { 3226 ASSERT(cpuid_checkpass(cpu, 1)); 3227 return (cpu->cpu_m.mcpu_cpi->cpi_procnodes_per_pkg); 3228 } 3229 3230 uint_t 3231 cpuid_get_compunitid(cpu_t *cpu) 3232 { 3233 ASSERT(cpuid_checkpass(cpu, 1)); 3234 return (cpu->cpu_m.mcpu_cpi->cpi_compunitid); 3235 } 3236 3237 uint_t 3238 cpuid_get_cores_per_compunit(cpu_t *cpu) 3239 { 3240 ASSERT(cpuid_checkpass(cpu, 1)); 3241 return (cpu->cpu_m.mcpu_cpi->cpi_cores_per_compunit); 3242 } 3243 3244 /*ARGSUSED*/ 3245 int 3246 cpuid_have_cr8access(cpu_t *cpu) 3247 { 3248 #if defined(__amd64) 3249 return (1); 3250 #else 3251 struct cpuid_info *cpi; 3252 3253 ASSERT(cpu != NULL); 3254 cpi = cpu->cpu_m.mcpu_cpi; 3255 if (cpi->cpi_vendor == X86_VENDOR_AMD && cpi->cpi_maxeax >= 1 && 3256 (CPI_FEATURES_XTD_ECX(cpi) & CPUID_AMD_ECX_CR8D) != 0) 3257 return (1); 3258 return (0); 3259 #endif 3260 } 3261 3262 uint32_t 3263 cpuid_get_apicid(cpu_t *cpu) 3264 { 3265 ASSERT(cpuid_checkpass(cpu, 1)); 3266 if (cpu->cpu_m.mcpu_cpi->cpi_maxeax < 1) { 3267 return (UINT32_MAX); 3268 } else { 3269 return (cpu->cpu_m.mcpu_cpi->cpi_apicid); 3270 } 3271 } 3272 3273 void 3274 cpuid_get_addrsize(cpu_t *cpu, uint_t *pabits, uint_t *vabits) 3275 { 3276 struct cpuid_info *cpi; 3277 3278 if (cpu == NULL) 3279 cpu = CPU; 3280 cpi = cpu->cpu_m.mcpu_cpi; 3281 3282 ASSERT(cpuid_checkpass(cpu, 1)); 3283 3284 if (pabits) 3285 *pabits = cpi->cpi_pabits; 3286 if (vabits) 3287 *vabits = cpi->cpi_vabits; 3288 } 3289 3290 /* 3291 * Returns the number of data TLB entries for a corresponding 3292 * pagesize. If it can't be computed, or isn't known, the 3293 * routine returns zero. If you ask about an architecturally 3294 * impossible pagesize, the routine will panic (so that the 3295 * hat implementor knows that things are inconsistent.) 3296 */ 3297 uint_t 3298 cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize) 3299 { 3300 struct cpuid_info *cpi; 3301 uint_t dtlb_nent = 0; 3302 3303 if (cpu == NULL) 3304 cpu = CPU; 3305 cpi = cpu->cpu_m.mcpu_cpi; 3306 3307 ASSERT(cpuid_checkpass(cpu, 1)); 3308 3309 /* 3310 * Check the L2 TLB info 3311 */ 3312 if (cpi->cpi_xmaxeax >= 0x80000006) { 3313 struct cpuid_regs *cp = &cpi->cpi_extd[6]; 3314 3315 switch (pagesize) { 3316 3317 case 4 * 1024: 3318 /* 3319 * All zero in the top 16 bits of the register 3320 * indicates a unified TLB. Size is in low 16 bits. 3321 */ 3322 if ((cp->cp_ebx & 0xffff0000) == 0) 3323 dtlb_nent = cp->cp_ebx & 0x0000ffff; 3324 else 3325 dtlb_nent = BITX(cp->cp_ebx, 27, 16); 3326 break; 3327 3328 case 2 * 1024 * 1024: 3329 if ((cp->cp_eax & 0xffff0000) == 0) 3330 dtlb_nent = cp->cp_eax & 0x0000ffff; 3331 else 3332 dtlb_nent = BITX(cp->cp_eax, 27, 16); 3333 break; 3334 3335 default: 3336 panic("unknown L2 pagesize"); 3337 /*NOTREACHED*/ 3338 } 3339 } 3340 3341 if (dtlb_nent != 0) 3342 return (dtlb_nent); 3343 3344 /* 3345 * No L2 TLB support for this size, try L1. 3346 */ 3347 if (cpi->cpi_xmaxeax >= 0x80000005) { 3348 struct cpuid_regs *cp = &cpi->cpi_extd[5]; 3349 3350 switch (pagesize) { 3351 case 4 * 1024: 3352 dtlb_nent = BITX(cp->cp_ebx, 23, 16); 3353 break; 3354 case 2 * 1024 * 1024: 3355 dtlb_nent = BITX(cp->cp_eax, 23, 16); 3356 break; 3357 default: 3358 panic("unknown L1 d-TLB pagesize"); 3359 /*NOTREACHED*/ 3360 } 3361 } 3362 3363 return (dtlb_nent); 3364 } 3365 3366 /* 3367 * Return 0 if the erratum is not present or not applicable, positive 3368 * if it is, and negative if the status of the erratum is unknown. 3369 * 3370 * See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm) 3371 * Processors" #25759, Rev 3.57, August 2005 3372 */ 3373 int 3374 cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum) 3375 { 3376 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 3377 uint_t eax; 3378 3379 /* 3380 * Bail out if this CPU isn't an AMD CPU, or if it's 3381 * a legacy (32-bit) AMD CPU. 3382 */ 3383 if (cpi->cpi_vendor != X86_VENDOR_AMD || 3384 cpi->cpi_family == 4 || cpi->cpi_family == 5 || 3385 cpi->cpi_family == 6) 3386 3387 return (0); 3388 3389 eax = cpi->cpi_std[1].cp_eax; 3390 3391 #define SH_B0(eax) (eax == 0xf40 || eax == 0xf50) 3392 #define SH_B3(eax) (eax == 0xf51) 3393 #define B(eax) (SH_B0(eax) || SH_B3(eax)) 3394 3395 #define SH_C0(eax) (eax == 0xf48 || eax == 0xf58) 3396 3397 #define SH_CG(eax) (eax == 0xf4a || eax == 0xf5a || eax == 0xf7a) 3398 #define DH_CG(eax) (eax == 0xfc0 || eax == 0xfe0 || eax == 0xff0) 3399 #define CH_CG(eax) (eax == 0xf82 || eax == 0xfb2) 3400 #define CG(eax) (SH_CG(eax) || DH_CG(eax) || CH_CG(eax)) 3401 3402 #define SH_D0(eax) (eax == 0x10f40 || eax == 0x10f50 || eax == 0x10f70) 3403 #define DH_D0(eax) (eax == 0x10fc0 || eax == 0x10ff0) 3404 #define CH_D0(eax) (eax == 0x10f80 || eax == 0x10fb0) 3405 #define D0(eax) (SH_D0(eax) || DH_D0(eax) || CH_D0(eax)) 3406 3407 #define SH_E0(eax) (eax == 0x20f50 || eax == 0x20f40 || eax == 0x20f70) 3408 #define JH_E1(eax) (eax == 0x20f10) /* JH8_E0 had 0x20f30 */ 3409 #define DH_E3(eax) (eax == 0x20fc0 || eax == 0x20ff0) 3410 #define SH_E4(eax) (eax == 0x20f51 || eax == 0x20f71) 3411 #define BH_E4(eax) (eax == 0x20fb1) 3412 #define SH_E5(eax) (eax == 0x20f42) 3413 #define DH_E6(eax) (eax == 0x20ff2 || eax == 0x20fc2) 3414 #define JH_E6(eax) (eax == 0x20f12 || eax == 0x20f32) 3415 #define EX(eax) (SH_E0(eax) || JH_E1(eax) || DH_E3(eax) || \ 3416 SH_E4(eax) || BH_E4(eax) || SH_E5(eax) || \ 3417 DH_E6(eax) || JH_E6(eax)) 3418 3419 #define DR_AX(eax) (eax == 0x100f00 || eax == 0x100f01 || eax == 0x100f02) 3420 #define DR_B0(eax) (eax == 0x100f20) 3421 #define DR_B1(eax) (eax == 0x100f21) 3422 #define DR_BA(eax) (eax == 0x100f2a) 3423 #define DR_B2(eax) (eax == 0x100f22) 3424 #define DR_B3(eax) (eax == 0x100f23) 3425 #define RB_C0(eax) (eax == 0x100f40) 3426 3427 switch (erratum) { 3428 case 1: 3429 return (cpi->cpi_family < 0x10); 3430 case 51: /* what does the asterisk mean? */ 3431 return (B(eax) || SH_C0(eax) || CG(eax)); 3432 case 52: 3433 return (B(eax)); 3434 case 57: 3435 return (cpi->cpi_family <= 0x11); 3436 case 58: 3437 return (B(eax)); 3438 case 60: 3439 return (cpi->cpi_family <= 0x11); 3440 case 61: 3441 case 62: 3442 case 63: 3443 case 64: 3444 case 65: 3445 case 66: 3446 case 68: 3447 case 69: 3448 case 70: 3449 case 71: 3450 return (B(eax)); 3451 case 72: 3452 return (SH_B0(eax)); 3453 case 74: 3454 return (B(eax)); 3455 case 75: 3456 return (cpi->cpi_family < 0x10); 3457 case 76: 3458 return (B(eax)); 3459 case 77: 3460 return (cpi->cpi_family <= 0x11); 3461 case 78: 3462 return (B(eax) || SH_C0(eax)); 3463 case 79: 3464 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 3465 case 80: 3466 case 81: 3467 case 82: 3468 return (B(eax)); 3469 case 83: 3470 return (B(eax) || SH_C0(eax) || CG(eax)); 3471 case 85: 3472 return (cpi->cpi_family < 0x10); 3473 case 86: 3474 return (SH_C0(eax) || CG(eax)); 3475 case 88: 3476 #if !defined(__amd64) 3477 return (0); 3478 #else 3479 return (B(eax) || SH_C0(eax)); 3480 #endif 3481 case 89: 3482 return (cpi->cpi_family < 0x10); 3483 case 90: 3484 return (B(eax) || SH_C0(eax) || CG(eax)); 3485 case 91: 3486 case 92: 3487 return (B(eax) || SH_C0(eax)); 3488 case 93: 3489 return (SH_C0(eax)); 3490 case 94: 3491 return (B(eax) || SH_C0(eax) || CG(eax)); 3492 case 95: 3493 #if !defined(__amd64) 3494 return (0); 3495 #else 3496 return (B(eax) || SH_C0(eax)); 3497 #endif 3498 case 96: 3499 return (B(eax) || SH_C0(eax) || CG(eax)); 3500 case 97: 3501 case 98: 3502 return (SH_C0(eax) || CG(eax)); 3503 case 99: 3504 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 3505 case 100: 3506 return (B(eax) || SH_C0(eax)); 3507 case 101: 3508 case 103: 3509 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 3510 case 104: 3511 return (SH_C0(eax) || CG(eax) || D0(eax)); 3512 case 105: 3513 case 106: 3514 case 107: 3515 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 3516 case 108: 3517 return (DH_CG(eax)); 3518 case 109: 3519 return (SH_C0(eax) || CG(eax) || D0(eax)); 3520 case 110: 3521 return (D0(eax) || EX(eax)); 3522 case 111: 3523 return (CG(eax)); 3524 case 112: 3525 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 3526 case 113: 3527 return (eax == 0x20fc0); 3528 case 114: 3529 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 3530 case 115: 3531 return (SH_E0(eax) || JH_E1(eax)); 3532 case 116: 3533 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 3534 case 117: 3535 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 3536 case 118: 3537 return (SH_E0(eax) || JH_E1(eax) || SH_E4(eax) || BH_E4(eax) || 3538 JH_E6(eax)); 3539 case 121: 3540 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 3541 case 122: 3542 return (cpi->cpi_family < 0x10 || cpi->cpi_family == 0x11); 3543 case 123: 3544 return (JH_E1(eax) || BH_E4(eax) || JH_E6(eax)); 3545 case 131: 3546 return (cpi->cpi_family < 0x10); 3547 case 6336786: 3548 /* 3549 * Test for AdvPowerMgmtInfo.TscPStateInvariant 3550 * if this is a K8 family or newer processor 3551 */ 3552 if (CPI_FAMILY(cpi) == 0xf) { 3553 struct cpuid_regs regs; 3554 regs.cp_eax = 0x80000007; 3555 (void) __cpuid_insn(®s); 3556 return (!(regs.cp_edx & 0x100)); 3557 } 3558 return (0); 3559 case 6323525: 3560 return (((((eax >> 12) & 0xff00) + (eax & 0xf00)) | 3561 (((eax >> 4) & 0xf) | ((eax >> 12) & 0xf0))) < 0xf40); 3562 3563 case 6671130: 3564 /* 3565 * check for processors (pre-Shanghai) that do not provide 3566 * optimal management of 1gb ptes in its tlb. 3567 */ 3568 return (cpi->cpi_family == 0x10 && cpi->cpi_model < 4); 3569 3570 case 298: 3571 return (DR_AX(eax) || DR_B0(eax) || DR_B1(eax) || DR_BA(eax) || 3572 DR_B2(eax) || RB_C0(eax)); 3573 3574 case 721: 3575 #if defined(__amd64) 3576 return (cpi->cpi_family == 0x10 || cpi->cpi_family == 0x12); 3577 #else 3578 return (0); 3579 #endif 3580 3581 default: 3582 return (-1); 3583 3584 } 3585 } 3586 3587 /* 3588 * Determine if specified erratum is present via OSVW (OS Visible Workaround). 3589 * Return 1 if erratum is present, 0 if not present and -1 if indeterminate. 3590 */ 3591 int 3592 osvw_opteron_erratum(cpu_t *cpu, uint_t erratum) 3593 { 3594 struct cpuid_info *cpi; 3595 uint_t osvwid; 3596 static int osvwfeature = -1; 3597 uint64_t osvwlength; 3598 3599 3600 cpi = cpu->cpu_m.mcpu_cpi; 3601 3602 /* confirm OSVW supported */ 3603 if (osvwfeature == -1) { 3604 osvwfeature = cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW; 3605 } else { 3606 /* assert that osvw feature setting is consistent on all cpus */ 3607 ASSERT(osvwfeature == 3608 (cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW)); 3609 } 3610 if (!osvwfeature) 3611 return (-1); 3612 3613 osvwlength = rdmsr(MSR_AMD_OSVW_ID_LEN) & OSVW_ID_LEN_MASK; 3614 3615 switch (erratum) { 3616 case 298: /* osvwid is 0 */ 3617 osvwid = 0; 3618 if (osvwlength <= (uint64_t)osvwid) { 3619 /* osvwid 0 is unknown */ 3620 return (-1); 3621 } 3622 3623 /* 3624 * Check the OSVW STATUS MSR to determine the state 3625 * of the erratum where: 3626 * 0 - fixed by HW 3627 * 1 - BIOS has applied the workaround when BIOS 3628 * workaround is available. (Or for other errata, 3629 * OS workaround is required.) 3630 * For a value of 1, caller will confirm that the 3631 * erratum 298 workaround has indeed been applied by BIOS. 3632 * 3633 * A 1 may be set in cpus that have a HW fix 3634 * in a mixed cpu system. Regarding erratum 298: 3635 * In a multiprocessor platform, the workaround above 3636 * should be applied to all processors regardless of 3637 * silicon revision when an affected processor is 3638 * present. 3639 */ 3640 3641 return (rdmsr(MSR_AMD_OSVW_STATUS + 3642 (osvwid / OSVW_ID_CNT_PER_MSR)) & 3643 (1ULL << (osvwid % OSVW_ID_CNT_PER_MSR))); 3644 3645 default: 3646 return (-1); 3647 } 3648 } 3649 3650 static const char assoc_str[] = "associativity"; 3651 static const char line_str[] = "line-size"; 3652 static const char size_str[] = "size"; 3653 3654 static void 3655 add_cache_prop(dev_info_t *devi, const char *label, const char *type, 3656 uint32_t val) 3657 { 3658 char buf[128]; 3659 3660 /* 3661 * ndi_prop_update_int() is used because it is desirable for 3662 * DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set. 3663 */ 3664 if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf)) 3665 (void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val); 3666 } 3667 3668 /* 3669 * Intel-style cache/tlb description 3670 * 3671 * Standard cpuid level 2 gives a randomly ordered 3672 * selection of tags that index into a table that describes 3673 * cache and tlb properties. 3674 */ 3675 3676 static const char l1_icache_str[] = "l1-icache"; 3677 static const char l1_dcache_str[] = "l1-dcache"; 3678 static const char l2_cache_str[] = "l2-cache"; 3679 static const char l3_cache_str[] = "l3-cache"; 3680 static const char itlb4k_str[] = "itlb-4K"; 3681 static const char dtlb4k_str[] = "dtlb-4K"; 3682 static const char itlb2M_str[] = "itlb-2M"; 3683 static const char itlb4M_str[] = "itlb-4M"; 3684 static const char dtlb4M_str[] = "dtlb-4M"; 3685 static const char dtlb24_str[] = "dtlb0-2M-4M"; 3686 static const char itlb424_str[] = "itlb-4K-2M-4M"; 3687 static const char itlb24_str[] = "itlb-2M-4M"; 3688 static const char dtlb44_str[] = "dtlb-4K-4M"; 3689 static const char sl1_dcache_str[] = "sectored-l1-dcache"; 3690 static const char sl2_cache_str[] = "sectored-l2-cache"; 3691 static const char itrace_str[] = "itrace-cache"; 3692 static const char sl3_cache_str[] = "sectored-l3-cache"; 3693 static const char sh_l2_tlb4k_str[] = "shared-l2-tlb-4k"; 3694 3695 static const struct cachetab { 3696 uint8_t ct_code; 3697 uint8_t ct_assoc; 3698 uint16_t ct_line_size; 3699 size_t ct_size; 3700 const char *ct_label; 3701 } intel_ctab[] = { 3702 /* 3703 * maintain descending order! 3704 * 3705 * Codes ignored - Reason 3706 * ---------------------- 3707 * 40H - intel_cpuid_4_cache_info() disambiguates l2/l3 cache 3708 * f0H/f1H - Currently we do not interpret prefetch size by design 3709 */ 3710 { 0xe4, 16, 64, 8*1024*1024, l3_cache_str}, 3711 { 0xe3, 16, 64, 4*1024*1024, l3_cache_str}, 3712 { 0xe2, 16, 64, 2*1024*1024, l3_cache_str}, 3713 { 0xde, 12, 64, 6*1024*1024, l3_cache_str}, 3714 { 0xdd, 12, 64, 3*1024*1024, l3_cache_str}, 3715 { 0xdc, 12, 64, ((1*1024*1024)+(512*1024)), l3_cache_str}, 3716 { 0xd8, 8, 64, 4*1024*1024, l3_cache_str}, 3717 { 0xd7, 8, 64, 2*1024*1024, l3_cache_str}, 3718 { 0xd6, 8, 64, 1*1024*1024, l3_cache_str}, 3719 { 0xd2, 4, 64, 2*1024*1024, l3_cache_str}, 3720 { 0xd1, 4, 64, 1*1024*1024, l3_cache_str}, 3721 { 0xd0, 4, 64, 512*1024, l3_cache_str}, 3722 { 0xca, 4, 0, 512, sh_l2_tlb4k_str}, 3723 { 0xc0, 4, 0, 8, dtlb44_str }, 3724 { 0xba, 4, 0, 64, dtlb4k_str }, 3725 { 0xb4, 4, 0, 256, dtlb4k_str }, 3726 { 0xb3, 4, 0, 128, dtlb4k_str }, 3727 { 0xb2, 4, 0, 64, itlb4k_str }, 3728 { 0xb0, 4, 0, 128, itlb4k_str }, 3729 { 0x87, 8, 64, 1024*1024, l2_cache_str}, 3730 { 0x86, 4, 64, 512*1024, l2_cache_str}, 3731 { 0x85, 8, 32, 2*1024*1024, l2_cache_str}, 3732 { 0x84, 8, 32, 1024*1024, l2_cache_str}, 3733 { 0x83, 8, 32, 512*1024, l2_cache_str}, 3734 { 0x82, 8, 32, 256*1024, l2_cache_str}, 3735 { 0x80, 8, 64, 512*1024, l2_cache_str}, 3736 { 0x7f, 2, 64, 512*1024, l2_cache_str}, 3737 { 0x7d, 8, 64, 2*1024*1024, sl2_cache_str}, 3738 { 0x7c, 8, 64, 1024*1024, sl2_cache_str}, 3739 { 0x7b, 8, 64, 512*1024, sl2_cache_str}, 3740 { 0x7a, 8, 64, 256*1024, sl2_cache_str}, 3741 { 0x79, 8, 64, 128*1024, sl2_cache_str}, 3742 { 0x78, 8, 64, 1024*1024, l2_cache_str}, 3743 { 0x73, 8, 0, 64*1024, itrace_str}, 3744 { 0x72, 8, 0, 32*1024, itrace_str}, 3745 { 0x71, 8, 0, 16*1024, itrace_str}, 3746 { 0x70, 8, 0, 12*1024, itrace_str}, 3747 { 0x68, 4, 64, 32*1024, sl1_dcache_str}, 3748 { 0x67, 4, 64, 16*1024, sl1_dcache_str}, 3749 { 0x66, 4, 64, 8*1024, sl1_dcache_str}, 3750 { 0x60, 8, 64, 16*1024, sl1_dcache_str}, 3751 { 0x5d, 0, 0, 256, dtlb44_str}, 3752 { 0x5c, 0, 0, 128, dtlb44_str}, 3753 { 0x5b, 0, 0, 64, dtlb44_str}, 3754 { 0x5a, 4, 0, 32, dtlb24_str}, 3755 { 0x59, 0, 0, 16, dtlb4k_str}, 3756 { 0x57, 4, 0, 16, dtlb4k_str}, 3757 { 0x56, 4, 0, 16, dtlb4M_str}, 3758 { 0x55, 0, 0, 7, itlb24_str}, 3759 { 0x52, 0, 0, 256, itlb424_str}, 3760 { 0x51, 0, 0, 128, itlb424_str}, 3761 { 0x50, 0, 0, 64, itlb424_str}, 3762 { 0x4f, 0, 0, 32, itlb4k_str}, 3763 { 0x4e, 24, 64, 6*1024*1024, l2_cache_str}, 3764 { 0x4d, 16, 64, 16*1024*1024, l3_cache_str}, 3765 { 0x4c, 12, 64, 12*1024*1024, l3_cache_str}, 3766 { 0x4b, 16, 64, 8*1024*1024, l3_cache_str}, 3767 { 0x4a, 12, 64, 6*1024*1024, l3_cache_str}, 3768 { 0x49, 16, 64, 4*1024*1024, l3_cache_str}, 3769 { 0x48, 12, 64, 3*1024*1024, l2_cache_str}, 3770 { 0x47, 8, 64, 8*1024*1024, l3_cache_str}, 3771 { 0x46, 4, 64, 4*1024*1024, l3_cache_str}, 3772 { 0x45, 4, 32, 2*1024*1024, l2_cache_str}, 3773 { 0x44, 4, 32, 1024*1024, l2_cache_str}, 3774 { 0x43, 4, 32, 512*1024, l2_cache_str}, 3775 { 0x42, 4, 32, 256*1024, l2_cache_str}, 3776 { 0x41, 4, 32, 128*1024, l2_cache_str}, 3777 { 0x3e, 4, 64, 512*1024, sl2_cache_str}, 3778 { 0x3d, 6, 64, 384*1024, sl2_cache_str}, 3779 { 0x3c, 4, 64, 256*1024, sl2_cache_str}, 3780 { 0x3b, 2, 64, 128*1024, sl2_cache_str}, 3781 { 0x3a, 6, 64, 192*1024, sl2_cache_str}, 3782 { 0x39, 4, 64, 128*1024, sl2_cache_str}, 3783 { 0x30, 8, 64, 32*1024, l1_icache_str}, 3784 { 0x2c, 8, 64, 32*1024, l1_dcache_str}, 3785 { 0x29, 8, 64, 4096*1024, sl3_cache_str}, 3786 { 0x25, 8, 64, 2048*1024, sl3_cache_str}, 3787 { 0x23, 8, 64, 1024*1024, sl3_cache_str}, 3788 { 0x22, 4, 64, 512*1024, sl3_cache_str}, 3789 { 0x0e, 6, 64, 24*1024, l1_dcache_str}, 3790 { 0x0d, 4, 32, 16*1024, l1_dcache_str}, 3791 { 0x0c, 4, 32, 16*1024, l1_dcache_str}, 3792 { 0x0b, 4, 0, 4, itlb4M_str}, 3793 { 0x0a, 2, 32, 8*1024, l1_dcache_str}, 3794 { 0x08, 4, 32, 16*1024, l1_icache_str}, 3795 { 0x06, 4, 32, 8*1024, l1_icache_str}, 3796 { 0x05, 4, 0, 32, dtlb4M_str}, 3797 { 0x04, 4, 0, 8, dtlb4M_str}, 3798 { 0x03, 4, 0, 64, dtlb4k_str}, 3799 { 0x02, 4, 0, 2, itlb4M_str}, 3800 { 0x01, 4, 0, 32, itlb4k_str}, 3801 { 0 } 3802 }; 3803 3804 static const struct cachetab cyrix_ctab[] = { 3805 { 0x70, 4, 0, 32, "tlb-4K" }, 3806 { 0x80, 4, 16, 16*1024, "l1-cache" }, 3807 { 0 } 3808 }; 3809 3810 /* 3811 * Search a cache table for a matching entry 3812 */ 3813 static const struct cachetab * 3814 find_cacheent(const struct cachetab *ct, uint_t code) 3815 { 3816 if (code != 0) { 3817 for (; ct->ct_code != 0; ct++) 3818 if (ct->ct_code <= code) 3819 break; 3820 if (ct->ct_code == code) 3821 return (ct); 3822 } 3823 return (NULL); 3824 } 3825 3826 /* 3827 * Populate cachetab entry with L2 or L3 cache-information using 3828 * cpuid function 4. This function is called from intel_walk_cacheinfo() 3829 * when descriptor 0x49 is encountered. It returns 0 if no such cache 3830 * information is found. 3831 */ 3832 static int 3833 intel_cpuid_4_cache_info(struct cachetab *ct, struct cpuid_info *cpi) 3834 { 3835 uint32_t level, i; 3836 int ret = 0; 3837 3838 for (i = 0; i < cpi->cpi_std_4_size; i++) { 3839 level = CPI_CACHE_LVL(cpi->cpi_std_4[i]); 3840 3841 if (level == 2 || level == 3) { 3842 ct->ct_assoc = CPI_CACHE_WAYS(cpi->cpi_std_4[i]) + 1; 3843 ct->ct_line_size = 3844 CPI_CACHE_COH_LN_SZ(cpi->cpi_std_4[i]) + 1; 3845 ct->ct_size = ct->ct_assoc * 3846 (CPI_CACHE_PARTS(cpi->cpi_std_4[i]) + 1) * 3847 ct->ct_line_size * 3848 (cpi->cpi_std_4[i]->cp_ecx + 1); 3849 3850 if (level == 2) { 3851 ct->ct_label = l2_cache_str; 3852 } else if (level == 3) { 3853 ct->ct_label = l3_cache_str; 3854 } 3855 ret = 1; 3856 } 3857 } 3858 3859 return (ret); 3860 } 3861 3862 /* 3863 * Walk the cacheinfo descriptor, applying 'func' to every valid element 3864 * The walk is terminated if the walker returns non-zero. 3865 */ 3866 static void 3867 intel_walk_cacheinfo(struct cpuid_info *cpi, 3868 void *arg, int (*func)(void *, const struct cachetab *)) 3869 { 3870 const struct cachetab *ct; 3871 struct cachetab des_49_ct, des_b1_ct; 3872 uint8_t *dp; 3873 int i; 3874 3875 if ((dp = cpi->cpi_cacheinfo) == NULL) 3876 return; 3877 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { 3878 /* 3879 * For overloaded descriptor 0x49 we use cpuid function 4 3880 * if supported by the current processor, to create 3881 * cache information. 3882 * For overloaded descriptor 0xb1 we use X86_PAE flag 3883 * to disambiguate the cache information. 3884 */ 3885 if (*dp == 0x49 && cpi->cpi_maxeax >= 0x4 && 3886 intel_cpuid_4_cache_info(&des_49_ct, cpi) == 1) { 3887 ct = &des_49_ct; 3888 } else if (*dp == 0xb1) { 3889 des_b1_ct.ct_code = 0xb1; 3890 des_b1_ct.ct_assoc = 4; 3891 des_b1_ct.ct_line_size = 0; 3892 if (is_x86_feature(x86_featureset, X86FSET_PAE)) { 3893 des_b1_ct.ct_size = 8; 3894 des_b1_ct.ct_label = itlb2M_str; 3895 } else { 3896 des_b1_ct.ct_size = 4; 3897 des_b1_ct.ct_label = itlb4M_str; 3898 } 3899 ct = &des_b1_ct; 3900 } else { 3901 if ((ct = find_cacheent(intel_ctab, *dp)) == NULL) { 3902 continue; 3903 } 3904 } 3905 3906 if (func(arg, ct) != 0) { 3907 break; 3908 } 3909 } 3910 } 3911 3912 /* 3913 * (Like the Intel one, except for Cyrix CPUs) 3914 */ 3915 static void 3916 cyrix_walk_cacheinfo(struct cpuid_info *cpi, 3917 void *arg, int (*func)(void *, const struct cachetab *)) 3918 { 3919 const struct cachetab *ct; 3920 uint8_t *dp; 3921 int i; 3922 3923 if ((dp = cpi->cpi_cacheinfo) == NULL) 3924 return; 3925 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { 3926 /* 3927 * Search Cyrix-specific descriptor table first .. 3928 */ 3929 if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) { 3930 if (func(arg, ct) != 0) 3931 break; 3932 continue; 3933 } 3934 /* 3935 * .. else fall back to the Intel one 3936 */ 3937 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { 3938 if (func(arg, ct) != 0) 3939 break; 3940 continue; 3941 } 3942 } 3943 } 3944 3945 /* 3946 * A cacheinfo walker that adds associativity, line-size, and size properties 3947 * to the devinfo node it is passed as an argument. 3948 */ 3949 static int 3950 add_cacheent_props(void *arg, const struct cachetab *ct) 3951 { 3952 dev_info_t *devi = arg; 3953 3954 add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc); 3955 if (ct->ct_line_size != 0) 3956 add_cache_prop(devi, ct->ct_label, line_str, 3957 ct->ct_line_size); 3958 add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size); 3959 return (0); 3960 } 3961 3962 3963 static const char fully_assoc[] = "fully-associative?"; 3964 3965 /* 3966 * AMD style cache/tlb description 3967 * 3968 * Extended functions 5 and 6 directly describe properties of 3969 * tlbs and various cache levels. 3970 */ 3971 static void 3972 add_amd_assoc(dev_info_t *devi, const char *label, uint_t assoc) 3973 { 3974 switch (assoc) { 3975 case 0: /* reserved; ignore */ 3976 break; 3977 default: 3978 add_cache_prop(devi, label, assoc_str, assoc); 3979 break; 3980 case 0xff: 3981 add_cache_prop(devi, label, fully_assoc, 1); 3982 break; 3983 } 3984 } 3985 3986 static void 3987 add_amd_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 3988 { 3989 if (size == 0) 3990 return; 3991 add_cache_prop(devi, label, size_str, size); 3992 add_amd_assoc(devi, label, assoc); 3993 } 3994 3995 static void 3996 add_amd_cache(dev_info_t *devi, const char *label, 3997 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 3998 { 3999 if (size == 0 || line_size == 0) 4000 return; 4001 add_amd_assoc(devi, label, assoc); 4002 /* 4003 * Most AMD parts have a sectored cache. Multiple cache lines are 4004 * associated with each tag. A sector consists of all cache lines 4005 * associated with a tag. For example, the AMD K6-III has a sector 4006 * size of 2 cache lines per tag. 4007 */ 4008 if (lines_per_tag != 0) 4009 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 4010 add_cache_prop(devi, label, line_str, line_size); 4011 add_cache_prop(devi, label, size_str, size * 1024); 4012 } 4013 4014 static void 4015 add_amd_l2_assoc(dev_info_t *devi, const char *label, uint_t assoc) 4016 { 4017 switch (assoc) { 4018 case 0: /* off */ 4019 break; 4020 case 1: 4021 case 2: 4022 case 4: 4023 add_cache_prop(devi, label, assoc_str, assoc); 4024 break; 4025 case 6: 4026 add_cache_prop(devi, label, assoc_str, 8); 4027 break; 4028 case 8: 4029 add_cache_prop(devi, label, assoc_str, 16); 4030 break; 4031 case 0xf: 4032 add_cache_prop(devi, label, fully_assoc, 1); 4033 break; 4034 default: /* reserved; ignore */ 4035 break; 4036 } 4037 } 4038 4039 static void 4040 add_amd_l2_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 4041 { 4042 if (size == 0 || assoc == 0) 4043 return; 4044 add_amd_l2_assoc(devi, label, assoc); 4045 add_cache_prop(devi, label, size_str, size); 4046 } 4047 4048 static void 4049 add_amd_l2_cache(dev_info_t *devi, const char *label, 4050 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 4051 { 4052 if (size == 0 || assoc == 0 || line_size == 0) 4053 return; 4054 add_amd_l2_assoc(devi, label, assoc); 4055 if (lines_per_tag != 0) 4056 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 4057 add_cache_prop(devi, label, line_str, line_size); 4058 add_cache_prop(devi, label, size_str, size * 1024); 4059 } 4060 4061 static void 4062 amd_cache_info(struct cpuid_info *cpi, dev_info_t *devi) 4063 { 4064 struct cpuid_regs *cp; 4065 4066 if (cpi->cpi_xmaxeax < 0x80000005) 4067 return; 4068 cp = &cpi->cpi_extd[5]; 4069 4070 /* 4071 * 4M/2M L1 TLB configuration 4072 * 4073 * We report the size for 2M pages because AMD uses two 4074 * TLB entries for one 4M page. 4075 */ 4076 add_amd_tlb(devi, "dtlb-2M", 4077 BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16)); 4078 add_amd_tlb(devi, "itlb-2M", 4079 BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0)); 4080 4081 /* 4082 * 4K L1 TLB configuration 4083 */ 4084 4085 switch (cpi->cpi_vendor) { 4086 uint_t nentries; 4087 case X86_VENDOR_TM: 4088 if (cpi->cpi_family >= 5) { 4089 /* 4090 * Crusoe processors have 256 TLB entries, but 4091 * cpuid data format constrains them to only 4092 * reporting 255 of them. 4093 */ 4094 if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255) 4095 nentries = 256; 4096 /* 4097 * Crusoe processors also have a unified TLB 4098 */ 4099 add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24), 4100 nentries); 4101 break; 4102 } 4103 /*FALLTHROUGH*/ 4104 default: 4105 add_amd_tlb(devi, itlb4k_str, 4106 BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16)); 4107 add_amd_tlb(devi, dtlb4k_str, 4108 BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0)); 4109 break; 4110 } 4111 4112 /* 4113 * data L1 cache configuration 4114 */ 4115 4116 add_amd_cache(devi, l1_dcache_str, 4117 BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16), 4118 BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0)); 4119 4120 /* 4121 * code L1 cache configuration 4122 */ 4123 4124 add_amd_cache(devi, l1_icache_str, 4125 BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16), 4126 BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0)); 4127 4128 if (cpi->cpi_xmaxeax < 0x80000006) 4129 return; 4130 cp = &cpi->cpi_extd[6]; 4131 4132 /* Check for a unified L2 TLB for large pages */ 4133 4134 if (BITX(cp->cp_eax, 31, 16) == 0) 4135 add_amd_l2_tlb(devi, "l2-tlb-2M", 4136 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 4137 else { 4138 add_amd_l2_tlb(devi, "l2-dtlb-2M", 4139 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 4140 add_amd_l2_tlb(devi, "l2-itlb-2M", 4141 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 4142 } 4143 4144 /* Check for a unified L2 TLB for 4K pages */ 4145 4146 if (BITX(cp->cp_ebx, 31, 16) == 0) { 4147 add_amd_l2_tlb(devi, "l2-tlb-4K", 4148 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 4149 } else { 4150 add_amd_l2_tlb(devi, "l2-dtlb-4K", 4151 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 4152 add_amd_l2_tlb(devi, "l2-itlb-4K", 4153 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 4154 } 4155 4156 add_amd_l2_cache(devi, l2_cache_str, 4157 BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12), 4158 BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0)); 4159 } 4160 4161 /* 4162 * There are two basic ways that the x86 world describes it cache 4163 * and tlb architecture - Intel's way and AMD's way. 4164 * 4165 * Return which flavor of cache architecture we should use 4166 */ 4167 static int 4168 x86_which_cacheinfo(struct cpuid_info *cpi) 4169 { 4170 switch (cpi->cpi_vendor) { 4171 case X86_VENDOR_Intel: 4172 if (cpi->cpi_maxeax >= 2) 4173 return (X86_VENDOR_Intel); 4174 break; 4175 case X86_VENDOR_AMD: 4176 /* 4177 * The K5 model 1 was the first part from AMD that reported 4178 * cache sizes via extended cpuid functions. 4179 */ 4180 if (cpi->cpi_family > 5 || 4181 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 4182 return (X86_VENDOR_AMD); 4183 break; 4184 case X86_VENDOR_TM: 4185 if (cpi->cpi_family >= 5) 4186 return (X86_VENDOR_AMD); 4187 /*FALLTHROUGH*/ 4188 default: 4189 /* 4190 * If they have extended CPU data for 0x80000005 4191 * then we assume they have AMD-format cache 4192 * information. 4193 * 4194 * If not, and the vendor happens to be Cyrix, 4195 * then try our-Cyrix specific handler. 4196 * 4197 * If we're not Cyrix, then assume we're using Intel's 4198 * table-driven format instead. 4199 */ 4200 if (cpi->cpi_xmaxeax >= 0x80000005) 4201 return (X86_VENDOR_AMD); 4202 else if (cpi->cpi_vendor == X86_VENDOR_Cyrix) 4203 return (X86_VENDOR_Cyrix); 4204 else if (cpi->cpi_maxeax >= 2) 4205 return (X86_VENDOR_Intel); 4206 break; 4207 } 4208 return (-1); 4209 } 4210 4211 void 4212 cpuid_set_cpu_properties(void *dip, processorid_t cpu_id, 4213 struct cpuid_info *cpi) 4214 { 4215 dev_info_t *cpu_devi; 4216 int create; 4217 4218 cpu_devi = (dev_info_t *)dip; 4219 4220 /* device_type */ 4221 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 4222 "device_type", "cpu"); 4223 4224 /* reg */ 4225 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4226 "reg", cpu_id); 4227 4228 /* cpu-mhz, and clock-frequency */ 4229 if (cpu_freq > 0) { 4230 long long mul; 4231 4232 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4233 "cpu-mhz", cpu_freq); 4234 if ((mul = cpu_freq * 1000000LL) <= INT_MAX) 4235 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4236 "clock-frequency", (int)mul); 4237 } 4238 4239 if (!is_x86_feature(x86_featureset, X86FSET_CPUID)) { 4240 return; 4241 } 4242 4243 /* vendor-id */ 4244 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 4245 "vendor-id", cpi->cpi_vendorstr); 4246 4247 if (cpi->cpi_maxeax == 0) { 4248 return; 4249 } 4250 4251 /* 4252 * family, model, and step 4253 */ 4254 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4255 "family", CPI_FAMILY(cpi)); 4256 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4257 "cpu-model", CPI_MODEL(cpi)); 4258 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4259 "stepping-id", CPI_STEP(cpi)); 4260 4261 /* type */ 4262 switch (cpi->cpi_vendor) { 4263 case X86_VENDOR_Intel: 4264 create = 1; 4265 break; 4266 default: 4267 create = 0; 4268 break; 4269 } 4270 if (create) 4271 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4272 "type", CPI_TYPE(cpi)); 4273 4274 /* ext-family */ 4275 switch (cpi->cpi_vendor) { 4276 case X86_VENDOR_Intel: 4277 case X86_VENDOR_AMD: 4278 create = cpi->cpi_family >= 0xf; 4279 break; 4280 default: 4281 create = 0; 4282 break; 4283 } 4284 if (create) 4285 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4286 "ext-family", CPI_FAMILY_XTD(cpi)); 4287 4288 /* ext-model */ 4289 switch (cpi->cpi_vendor) { 4290 case X86_VENDOR_Intel: 4291 create = IS_EXTENDED_MODEL_INTEL(cpi); 4292 break; 4293 case X86_VENDOR_AMD: 4294 create = CPI_FAMILY(cpi) == 0xf; 4295 break; 4296 default: 4297 create = 0; 4298 break; 4299 } 4300 if (create) 4301 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4302 "ext-model", CPI_MODEL_XTD(cpi)); 4303 4304 /* generation */ 4305 switch (cpi->cpi_vendor) { 4306 case X86_VENDOR_AMD: 4307 /* 4308 * AMD K5 model 1 was the first part to support this 4309 */ 4310 create = cpi->cpi_xmaxeax >= 0x80000001; 4311 break; 4312 default: 4313 create = 0; 4314 break; 4315 } 4316 if (create) 4317 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4318 "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8)); 4319 4320 /* brand-id */ 4321 switch (cpi->cpi_vendor) { 4322 case X86_VENDOR_Intel: 4323 /* 4324 * brand id first appeared on Pentium III Xeon model 8, 4325 * and Celeron model 8 processors and Opteron 4326 */ 4327 create = cpi->cpi_family > 6 || 4328 (cpi->cpi_family == 6 && cpi->cpi_model >= 8); 4329 break; 4330 case X86_VENDOR_AMD: 4331 create = cpi->cpi_family >= 0xf; 4332 break; 4333 default: 4334 create = 0; 4335 break; 4336 } 4337 if (create && cpi->cpi_brandid != 0) { 4338 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4339 "brand-id", cpi->cpi_brandid); 4340 } 4341 4342 /* chunks, and apic-id */ 4343 switch (cpi->cpi_vendor) { 4344 /* 4345 * first available on Pentium IV and Opteron (K8) 4346 */ 4347 case X86_VENDOR_Intel: 4348 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 4349 break; 4350 case X86_VENDOR_AMD: 4351 create = cpi->cpi_family >= 0xf; 4352 break; 4353 default: 4354 create = 0; 4355 break; 4356 } 4357 if (create) { 4358 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4359 "chunks", CPI_CHUNKS(cpi)); 4360 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4361 "apic-id", cpi->cpi_apicid); 4362 if (cpi->cpi_chipid >= 0) { 4363 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4364 "chip#", cpi->cpi_chipid); 4365 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4366 "clog#", cpi->cpi_clogid); 4367 } 4368 } 4369 4370 /* cpuid-features */ 4371 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4372 "cpuid-features", CPI_FEATURES_EDX(cpi)); 4373 4374 4375 /* cpuid-features-ecx */ 4376 switch (cpi->cpi_vendor) { 4377 case X86_VENDOR_Intel: 4378 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 4379 break; 4380 case X86_VENDOR_AMD: 4381 create = cpi->cpi_family >= 0xf; 4382 break; 4383 default: 4384 create = 0; 4385 break; 4386 } 4387 if (create) 4388 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4389 "cpuid-features-ecx", CPI_FEATURES_ECX(cpi)); 4390 4391 /* ext-cpuid-features */ 4392 switch (cpi->cpi_vendor) { 4393 case X86_VENDOR_Intel: 4394 case X86_VENDOR_AMD: 4395 case X86_VENDOR_Cyrix: 4396 case X86_VENDOR_TM: 4397 case X86_VENDOR_Centaur: 4398 create = cpi->cpi_xmaxeax >= 0x80000001; 4399 break; 4400 default: 4401 create = 0; 4402 break; 4403 } 4404 if (create) { 4405 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4406 "ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi)); 4407 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4408 "ext-cpuid-features-ecx", CPI_FEATURES_XTD_ECX(cpi)); 4409 } 4410 4411 /* 4412 * Brand String first appeared in Intel Pentium IV, AMD K5 4413 * model 1, and Cyrix GXm. On earlier models we try and 4414 * simulate something similar .. so this string should always 4415 * same -something- about the processor, however lame. 4416 */ 4417 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 4418 "brand-string", cpi->cpi_brandstr); 4419 4420 /* 4421 * Finally, cache and tlb information 4422 */ 4423 switch (x86_which_cacheinfo(cpi)) { 4424 case X86_VENDOR_Intel: 4425 intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 4426 break; 4427 case X86_VENDOR_Cyrix: 4428 cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 4429 break; 4430 case X86_VENDOR_AMD: 4431 amd_cache_info(cpi, cpu_devi); 4432 break; 4433 default: 4434 break; 4435 } 4436 } 4437 4438 struct l2info { 4439 int *l2i_csz; 4440 int *l2i_lsz; 4441 int *l2i_assoc; 4442 int l2i_ret; 4443 }; 4444 4445 /* 4446 * A cacheinfo walker that fetches the size, line-size and associativity 4447 * of the L2 cache 4448 */ 4449 static int 4450 intel_l2cinfo(void *arg, const struct cachetab *ct) 4451 { 4452 struct l2info *l2i = arg; 4453 int *ip; 4454 4455 if (ct->ct_label != l2_cache_str && 4456 ct->ct_label != sl2_cache_str) 4457 return (0); /* not an L2 -- keep walking */ 4458 4459 if ((ip = l2i->l2i_csz) != NULL) 4460 *ip = ct->ct_size; 4461 if ((ip = l2i->l2i_lsz) != NULL) 4462 *ip = ct->ct_line_size; 4463 if ((ip = l2i->l2i_assoc) != NULL) 4464 *ip = ct->ct_assoc; 4465 l2i->l2i_ret = ct->ct_size; 4466 return (1); /* was an L2 -- terminate walk */ 4467 } 4468 4469 /* 4470 * AMD L2/L3 Cache and TLB Associativity Field Definition: 4471 * 4472 * Unlike the associativity for the L1 cache and tlb where the 8 bit 4473 * value is the associativity, the associativity for the L2 cache and 4474 * tlb is encoded in the following table. The 4 bit L2 value serves as 4475 * an index into the amd_afd[] array to determine the associativity. 4476 * -1 is undefined. 0 is fully associative. 4477 */ 4478 4479 static int amd_afd[] = 4480 {-1, 1, 2, -1, 4, -1, 8, -1, 16, -1, 32, 48, 64, 96, 128, 0}; 4481 4482 static void 4483 amd_l2cacheinfo(struct cpuid_info *cpi, struct l2info *l2i) 4484 { 4485 struct cpuid_regs *cp; 4486 uint_t size, assoc; 4487 int i; 4488 int *ip; 4489 4490 if (cpi->cpi_xmaxeax < 0x80000006) 4491 return; 4492 cp = &cpi->cpi_extd[6]; 4493 4494 if ((i = BITX(cp->cp_ecx, 15, 12)) != 0 && 4495 (size = BITX(cp->cp_ecx, 31, 16)) != 0) { 4496 uint_t cachesz = size * 1024; 4497 assoc = amd_afd[i]; 4498 4499 ASSERT(assoc != -1); 4500 4501 if ((ip = l2i->l2i_csz) != NULL) 4502 *ip = cachesz; 4503 if ((ip = l2i->l2i_lsz) != NULL) 4504 *ip = BITX(cp->cp_ecx, 7, 0); 4505 if ((ip = l2i->l2i_assoc) != NULL) 4506 *ip = assoc; 4507 l2i->l2i_ret = cachesz; 4508 } 4509 } 4510 4511 int 4512 getl2cacheinfo(cpu_t *cpu, int *csz, int *lsz, int *assoc) 4513 { 4514 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 4515 struct l2info __l2info, *l2i = &__l2info; 4516 4517 l2i->l2i_csz = csz; 4518 l2i->l2i_lsz = lsz; 4519 l2i->l2i_assoc = assoc; 4520 l2i->l2i_ret = -1; 4521 4522 switch (x86_which_cacheinfo(cpi)) { 4523 case X86_VENDOR_Intel: 4524 intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 4525 break; 4526 case X86_VENDOR_Cyrix: 4527 cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 4528 break; 4529 case X86_VENDOR_AMD: 4530 amd_l2cacheinfo(cpi, l2i); 4531 break; 4532 default: 4533 break; 4534 } 4535 return (l2i->l2i_ret); 4536 } 4537 4538 #if !defined(__xpv) 4539 4540 uint32_t * 4541 cpuid_mwait_alloc(cpu_t *cpu) 4542 { 4543 uint32_t *ret; 4544 size_t mwait_size; 4545 4546 ASSERT(cpuid_checkpass(CPU, 2)); 4547 4548 mwait_size = CPU->cpu_m.mcpu_cpi->cpi_mwait.mon_max; 4549 if (mwait_size == 0) 4550 return (NULL); 4551 4552 /* 4553 * kmem_alloc() returns cache line size aligned data for mwait_size 4554 * allocations. mwait_size is currently cache line sized. Neither 4555 * of these implementation details are guarantied to be true in the 4556 * future. 4557 * 4558 * First try allocating mwait_size as kmem_alloc() currently returns 4559 * correctly aligned memory. If kmem_alloc() does not return 4560 * mwait_size aligned memory, then use mwait_size ROUNDUP. 4561 * 4562 * Set cpi_mwait.buf_actual and cpi_mwait.size_actual in case we 4563 * decide to free this memory. 4564 */ 4565 ret = kmem_zalloc(mwait_size, KM_SLEEP); 4566 if (ret == (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size)) { 4567 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret; 4568 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size; 4569 *ret = MWAIT_RUNNING; 4570 return (ret); 4571 } else { 4572 kmem_free(ret, mwait_size); 4573 ret = kmem_zalloc(mwait_size * 2, KM_SLEEP); 4574 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret; 4575 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size * 2; 4576 ret = (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size); 4577 *ret = MWAIT_RUNNING; 4578 return (ret); 4579 } 4580 } 4581 4582 void 4583 cpuid_mwait_free(cpu_t *cpu) 4584 { 4585 if (cpu->cpu_m.mcpu_cpi == NULL) { 4586 return; 4587 } 4588 4589 if (cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual != NULL && 4590 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual > 0) { 4591 kmem_free(cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual, 4592 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual); 4593 } 4594 4595 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = NULL; 4596 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = 0; 4597 } 4598 4599 void 4600 patch_tsc_read(int flag) 4601 { 4602 size_t cnt; 4603 4604 switch (flag) { 4605 case TSC_NONE: 4606 cnt = &_no_rdtsc_end - &_no_rdtsc_start; 4607 (void) memcpy((void *)tsc_read, (void *)&_no_rdtsc_start, cnt); 4608 break; 4609 case TSC_RDTSC_MFENCE: 4610 cnt = &_tsc_mfence_end - &_tsc_mfence_start; 4611 (void) memcpy((void *)tsc_read, 4612 (void *)&_tsc_mfence_start, cnt); 4613 break; 4614 case TSC_RDTSC_LFENCE: 4615 cnt = &_tsc_lfence_end - &_tsc_lfence_start; 4616 (void) memcpy((void *)tsc_read, 4617 (void *)&_tsc_lfence_start, cnt); 4618 break; 4619 case TSC_TSCP: 4620 cnt = &_tscp_end - &_tscp_start; 4621 (void) memcpy((void *)tsc_read, (void *)&_tscp_start, cnt); 4622 break; 4623 default: 4624 /* Bail for unexpected TSC types. (TSC_NONE covers 0) */ 4625 cmn_err(CE_PANIC, "Unrecogized TSC type: %d", flag); 4626 break; 4627 } 4628 tsc_type = flag; 4629 } 4630 4631 int 4632 cpuid_deep_cstates_supported(void) 4633 { 4634 struct cpuid_info *cpi; 4635 struct cpuid_regs regs; 4636 4637 ASSERT(cpuid_checkpass(CPU, 1)); 4638 4639 cpi = CPU->cpu_m.mcpu_cpi; 4640 4641 if (!is_x86_feature(x86_featureset, X86FSET_CPUID)) 4642 return (0); 4643 4644 switch (cpi->cpi_vendor) { 4645 case X86_VENDOR_Intel: 4646 if (cpi->cpi_xmaxeax < 0x80000007) 4647 return (0); 4648 4649 /* 4650 * TSC run at a constant rate in all ACPI C-states? 4651 */ 4652 regs.cp_eax = 0x80000007; 4653 (void) __cpuid_insn(®s); 4654 return (regs.cp_edx & CPUID_TSC_CSTATE_INVARIANCE); 4655 4656 default: 4657 return (0); 4658 } 4659 } 4660 4661 #endif /* !__xpv */ 4662 4663 void 4664 post_startup_cpu_fixups(void) 4665 { 4666 #ifndef __xpv 4667 /* 4668 * Some AMD processors support C1E state. Entering this state will 4669 * cause the local APIC timer to stop, which we can't deal with at 4670 * this time. 4671 */ 4672 if (cpuid_getvendor(CPU) == X86_VENDOR_AMD) { 4673 on_trap_data_t otd; 4674 uint64_t reg; 4675 4676 if (!on_trap(&otd, OT_DATA_ACCESS)) { 4677 reg = rdmsr(MSR_AMD_INT_PENDING_CMP_HALT); 4678 /* Disable C1E state if it is enabled by BIOS */ 4679 if ((reg >> AMD_ACTONCMPHALT_SHIFT) & 4680 AMD_ACTONCMPHALT_MASK) { 4681 reg &= ~(AMD_ACTONCMPHALT_MASK << 4682 AMD_ACTONCMPHALT_SHIFT); 4683 wrmsr(MSR_AMD_INT_PENDING_CMP_HALT, reg); 4684 } 4685 } 4686 no_trap(); 4687 } 4688 #endif /* !__xpv */ 4689 } 4690 4691 /* 4692 * Setup necessary registers to enable XSAVE feature on this processor. 4693 * This function needs to be called early enough, so that no xsave/xrstor 4694 * ops will execute on the processor before the MSRs are properly set up. 4695 * 4696 * Current implementation has the following assumption: 4697 * - cpuid_pass1() is done, so that X86 features are known. 4698 * - fpu_probe() is done, so that fp_save_mech is chosen. 4699 */ 4700 void 4701 xsave_setup_msr(cpu_t *cpu) 4702 { 4703 ASSERT(fp_save_mech == FP_XSAVE); 4704 ASSERT(is_x86_feature(x86_featureset, X86FSET_XSAVE)); 4705 4706 /* Enable OSXSAVE in CR4. */ 4707 setcr4(getcr4() | CR4_OSXSAVE); 4708 /* 4709 * Update SW copy of ECX, so that /dev/cpu/self/cpuid will report 4710 * correct value. 4711 */ 4712 cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_ecx |= CPUID_INTC_ECX_OSXSAVE; 4713 setup_xfem(); 4714 } 4715 4716 /* 4717 * Starting with the Westmere processor the local 4718 * APIC timer will continue running in all C-states, 4719 * including the deepest C-states. 4720 */ 4721 int 4722 cpuid_arat_supported(void) 4723 { 4724 struct cpuid_info *cpi; 4725 struct cpuid_regs regs; 4726 4727 ASSERT(cpuid_checkpass(CPU, 1)); 4728 ASSERT(is_x86_feature(x86_featureset, X86FSET_CPUID)); 4729 4730 cpi = CPU->cpu_m.mcpu_cpi; 4731 4732 switch (cpi->cpi_vendor) { 4733 case X86_VENDOR_Intel: 4734 /* 4735 * Always-running Local APIC Timer is 4736 * indicated by CPUID.6.EAX[2]. 4737 */ 4738 if (cpi->cpi_maxeax >= 6) { 4739 regs.cp_eax = 6; 4740 (void) cpuid_insn(NULL, ®s); 4741 return (regs.cp_eax & CPUID_CSTATE_ARAT); 4742 } else { 4743 return (0); 4744 } 4745 default: 4746 return (0); 4747 } 4748 } 4749 4750 /* 4751 * Check support for Intel ENERGY_PERF_BIAS feature 4752 */ 4753 int 4754 cpuid_iepb_supported(struct cpu *cp) 4755 { 4756 struct cpuid_info *cpi = cp->cpu_m.mcpu_cpi; 4757 struct cpuid_regs regs; 4758 4759 ASSERT(cpuid_checkpass(cp, 1)); 4760 4761 if (!(is_x86_feature(x86_featureset, X86FSET_CPUID)) || 4762 !(is_x86_feature(x86_featureset, X86FSET_MSR))) { 4763 return (0); 4764 } 4765 4766 /* 4767 * Intel ENERGY_PERF_BIAS MSR is indicated by 4768 * capability bit CPUID.6.ECX.3 4769 */ 4770 if ((cpi->cpi_vendor != X86_VENDOR_Intel) || (cpi->cpi_maxeax < 6)) 4771 return (0); 4772 4773 regs.cp_eax = 0x6; 4774 (void) cpuid_insn(NULL, ®s); 4775 return (regs.cp_ecx & CPUID_EPB_SUPPORT); 4776 } 4777 4778 /* 4779 * Check support for TSC deadline timer 4780 * 4781 * TSC deadline timer provides a superior software programming 4782 * model over local APIC timer that eliminates "time drifts". 4783 * Instead of specifying a relative time, software specifies an 4784 * absolute time as the target at which the processor should 4785 * generate a timer event. 4786 */ 4787 int 4788 cpuid_deadline_tsc_supported(void) 4789 { 4790 struct cpuid_info *cpi = CPU->cpu_m.mcpu_cpi; 4791 struct cpuid_regs regs; 4792 4793 ASSERT(cpuid_checkpass(CPU, 1)); 4794 ASSERT(is_x86_feature(x86_featureset, X86FSET_CPUID)); 4795 4796 switch (cpi->cpi_vendor) { 4797 case X86_VENDOR_Intel: 4798 if (cpi->cpi_maxeax >= 1) { 4799 regs.cp_eax = 1; 4800 (void) cpuid_insn(NULL, ®s); 4801 return (regs.cp_ecx & CPUID_DEADLINE_TSC); 4802 } else { 4803 return (0); 4804 } 4805 default: 4806 return (0); 4807 } 4808 } 4809 4810 #if defined(__amd64) && !defined(__xpv) 4811 /* 4812 * Patch in versions of bcopy for high performance Intel Nhm processors 4813 * and later... 4814 */ 4815 void 4816 patch_memops(uint_t vendor) 4817 { 4818 size_t cnt, i; 4819 caddr_t to, from; 4820 4821 if ((vendor == X86_VENDOR_Intel) && 4822 is_x86_feature(x86_featureset, X86FSET_SSE4_2)) { 4823 cnt = &bcopy_patch_end - &bcopy_patch_start; 4824 to = &bcopy_ck_size; 4825 from = &bcopy_patch_start; 4826 for (i = 0; i < cnt; i++) { 4827 *to++ = *from++; 4828 } 4829 } 4830 } 4831 #endif /* __amd64 && !__xpv */ 4832 4833 /* 4834 * This function finds the number of bits to represent the number of cores per 4835 * chip and the number of strands per core for the Intel platforms. 4836 * It re-uses the x2APIC cpuid code of the cpuid_pass2(). 4837 */ 4838 void 4839 cpuid_get_ext_topo(uint_t vendor, uint_t *core_nbits, uint_t *strand_nbits) 4840 { 4841 struct cpuid_regs regs; 4842 struct cpuid_regs *cp = ®s; 4843 4844 if (vendor != X86_VENDOR_Intel) { 4845 return; 4846 } 4847 4848 /* if the cpuid level is 0xB, extended topo is available. */ 4849 cp->cp_eax = 0; 4850 if (__cpuid_insn(cp) >= 0xB) { 4851 4852 cp->cp_eax = 0xB; 4853 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0; 4854 (void) __cpuid_insn(cp); 4855 4856 /* 4857 * Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero, which 4858 * indicates that the extended topology enumeration leaf is 4859 * available. 4860 */ 4861 if (cp->cp_ebx) { 4862 uint_t coreid_shift = 0; 4863 uint_t chipid_shift = 0; 4864 uint_t i; 4865 uint_t level; 4866 4867 for (i = 0; i < CPI_FNB_ECX_MAX; i++) { 4868 cp->cp_eax = 0xB; 4869 cp->cp_ecx = i; 4870 4871 (void) __cpuid_insn(cp); 4872 level = CPI_CPU_LEVEL_TYPE(cp); 4873 4874 if (level == 1) { 4875 /* 4876 * Thread level processor topology 4877 * Number of bits shift right APIC ID 4878 * to get the coreid. 4879 */ 4880 coreid_shift = BITX(cp->cp_eax, 4, 0); 4881 } else if (level == 2) { 4882 /* 4883 * Core level processor topology 4884 * Number of bits shift right APIC ID 4885 * to get the chipid. 4886 */ 4887 chipid_shift = BITX(cp->cp_eax, 4, 0); 4888 } 4889 } 4890 4891 if (coreid_shift > 0 && chipid_shift > coreid_shift) { 4892 *strand_nbits = coreid_shift; 4893 *core_nbits = chipid_shift - coreid_shift; 4894 } 4895 } 4896 } 4897 } 4898