1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * Various routines to handle identification 28 * and classification of x86 processors. 29 */ 30 31 #include <sys/types.h> 32 #include <sys/archsystm.h> 33 #include <sys/x86_archext.h> 34 #include <sys/kmem.h> 35 #include <sys/systm.h> 36 #include <sys/cmn_err.h> 37 #include <sys/sunddi.h> 38 #include <sys/sunndi.h> 39 #include <sys/cpuvar.h> 40 #include <sys/processor.h> 41 #include <sys/sysmacros.h> 42 #include <sys/pg.h> 43 #include <sys/fp.h> 44 #include <sys/controlregs.h> 45 #include <sys/auxv_386.h> 46 #include <sys/bitmap.h> 47 #include <sys/memnode.h> 48 49 #ifdef __xpv 50 #include <sys/hypervisor.h> 51 #endif 52 53 /* 54 * Pass 0 of cpuid feature analysis happens in locore. It contains special code 55 * to recognize Cyrix processors that are not cpuid-compliant, and to deal with 56 * them accordingly. For most modern processors, feature detection occurs here 57 * in pass 1. 58 * 59 * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup() 60 * for the boot CPU and does the basic analysis that the early kernel needs. 61 * x86_feature is set based on the return value of cpuid_pass1() of the boot 62 * CPU. 63 * 64 * Pass 1 includes: 65 * 66 * o Determining vendor/model/family/stepping and setting x86_type and 67 * x86_vendor accordingly. 68 * o Processing the feature flags returned by the cpuid instruction while 69 * applying any workarounds or tricks for the specific processor. 70 * o Mapping the feature flags into Solaris feature bits (X86_*). 71 * o Processing extended feature flags if supported by the processor, 72 * again while applying specific processor knowledge. 73 * o Determining the CMT characteristics of the system. 74 * 75 * Pass 1 is done on non-boot CPUs during their initialization and the results 76 * are used only as a meager attempt at ensuring that all processors within the 77 * system support the same features. 78 * 79 * Pass 2 of cpuid feature analysis happens just at the beginning 80 * of startup(). It just copies in and corrects the remainder 81 * of the cpuid data we depend on: standard cpuid functions that we didn't 82 * need for pass1 feature analysis, and extended cpuid functions beyond the 83 * simple feature processing done in pass1. 84 * 85 * Pass 3 of cpuid analysis is invoked after basic kernel services; in 86 * particular kernel memory allocation has been made available. It creates a 87 * readable brand string based on the data collected in the first two passes. 88 * 89 * Pass 4 of cpuid analysis is invoked after post_startup() when all 90 * the support infrastructure for various hardware features has been 91 * initialized. It determines which processor features will be reported 92 * to userland via the aux vector. 93 * 94 * All passes are executed on all CPUs, but only the boot CPU determines what 95 * features the kernel will use. 96 * 97 * Much of the worst junk in this file is for the support of processors 98 * that didn't really implement the cpuid instruction properly. 99 * 100 * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon, 101 * the pass numbers. Accordingly, changes to the pass code may require changes 102 * to the accessor code. 103 */ 104 105 uint_t x86_feature = 0; 106 uint_t x86_vendor = X86_VENDOR_IntelClone; 107 uint_t x86_type = X86_TYPE_OTHER; 108 uint_t x86_clflush_size = 0; 109 110 uint_t pentiumpro_bug4046376; 111 uint_t pentiumpro_bug4064495; 112 113 uint_t enable486; 114 115 /* 116 * monitor/mwait info. 117 * 118 * size_actual and buf_actual are the real address and size allocated to get 119 * proper mwait_buf alignement. buf_actual and size_actual should be passed 120 * to kmem_free(). Currently kmem_alloc() and mwait happen to both use 121 * processor cache-line alignment, but this is not guarantied in the furture. 122 */ 123 struct mwait_info { 124 size_t mon_min; /* min size to avoid missed wakeups */ 125 size_t mon_max; /* size to avoid false wakeups */ 126 size_t size_actual; /* size actually allocated */ 127 void *buf_actual; /* memory actually allocated */ 128 uint32_t support; /* processor support of monitor/mwait */ 129 }; 130 131 /* 132 * These constants determine how many of the elements of the 133 * cpuid we cache in the cpuid_info data structure; the 134 * remaining elements are accessible via the cpuid instruction. 135 */ 136 137 #define NMAX_CPI_STD 6 /* eax = 0 .. 5 */ 138 #define NMAX_CPI_EXTD 9 /* eax = 0x80000000 .. 0x80000008 */ 139 140 struct cpuid_info { 141 uint_t cpi_pass; /* last pass completed */ 142 /* 143 * standard function information 144 */ 145 uint_t cpi_maxeax; /* fn 0: %eax */ 146 char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */ 147 uint_t cpi_vendor; /* enum of cpi_vendorstr */ 148 149 uint_t cpi_family; /* fn 1: extended family */ 150 uint_t cpi_model; /* fn 1: extended model */ 151 uint_t cpi_step; /* fn 1: stepping */ 152 chipid_t cpi_chipid; /* fn 1: %ebx: chip # on ht cpus */ 153 uint_t cpi_brandid; /* fn 1: %ebx: brand ID */ 154 int cpi_clogid; /* fn 1: %ebx: thread # */ 155 uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */ 156 uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */ 157 uint_t cpi_ncache; /* fn 2: number of elements */ 158 uint_t cpi_ncpu_shr_last_cache; /* fn 4: %eax: ncpus sharing cache */ 159 id_t cpi_last_lvl_cacheid; /* fn 4: %eax: derived cache id */ 160 uint_t cpi_std_4_size; /* fn 4: number of fn 4 elements */ 161 struct cpuid_regs **cpi_std_4; /* fn 4: %ecx == 0 .. fn4_size */ 162 struct cpuid_regs cpi_std[NMAX_CPI_STD]; /* 0 .. 5 */ 163 /* 164 * extended function information 165 */ 166 uint_t cpi_xmaxeax; /* fn 0x80000000: %eax */ 167 char cpi_brandstr[49]; /* fn 0x8000000[234] */ 168 uint8_t cpi_pabits; /* fn 0x80000006: %eax */ 169 uint8_t cpi_vabits; /* fn 0x80000006: %eax */ 170 struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x8000000[0-8] */ 171 id_t cpi_coreid; /* same coreid => strands share core */ 172 int cpi_pkgcoreid; /* core number within single package */ 173 uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */ 174 /* Intel: fn 4: %eax[31-26] */ 175 /* 176 * supported feature information 177 */ 178 uint32_t cpi_support[5]; 179 #define STD_EDX_FEATURES 0 180 #define AMD_EDX_FEATURES 1 181 #define TM_EDX_FEATURES 2 182 #define STD_ECX_FEATURES 3 183 #define AMD_ECX_FEATURES 4 184 /* 185 * Synthesized information, where known. 186 */ 187 uint32_t cpi_chiprev; /* See X86_CHIPREV_* in x86_archext.h */ 188 const char *cpi_chiprevstr; /* May be NULL if chiprev unknown */ 189 uint32_t cpi_socket; /* Chip package/socket type */ 190 191 struct mwait_info cpi_mwait; /* fn 5: monitor/mwait info */ 192 uint32_t cpi_apicid; 193 }; 194 195 196 static struct cpuid_info cpuid_info0; 197 198 /* 199 * These bit fields are defined by the Intel Application Note AP-485 200 * "Intel Processor Identification and the CPUID Instruction" 201 */ 202 #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20) 203 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16) 204 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12) 205 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8) 206 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0) 207 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4) 208 209 #define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx) 210 #define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx) 211 #define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx) 212 #define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx) 213 214 #define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0) 215 #define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7) 216 #define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16) 217 #define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24) 218 219 #define CPI_MAXEAX_MAX 0x100 /* sanity control */ 220 #define CPI_XMAXEAX_MAX 0x80000100 221 #define CPI_FN4_ECX_MAX 0x20 /* sanity: max fn 4 levels */ 222 #define CPI_FNB_ECX_MAX 0x20 /* sanity: max fn B levels */ 223 224 /* 225 * Function 4 (Deterministic Cache Parameters) macros 226 * Defined by Intel Application Note AP-485 227 */ 228 #define CPI_NUM_CORES(regs) BITX((regs)->cp_eax, 31, 26) 229 #define CPI_NTHR_SHR_CACHE(regs) BITX((regs)->cp_eax, 25, 14) 230 #define CPI_FULL_ASSOC_CACHE(regs) BITX((regs)->cp_eax, 9, 9) 231 #define CPI_SELF_INIT_CACHE(regs) BITX((regs)->cp_eax, 8, 8) 232 #define CPI_CACHE_LVL(regs) BITX((regs)->cp_eax, 7, 5) 233 #define CPI_CACHE_TYPE(regs) BITX((regs)->cp_eax, 4, 0) 234 #define CPI_CPU_LEVEL_TYPE(regs) BITX((regs)->cp_ecx, 15, 8) 235 236 #define CPI_CACHE_WAYS(regs) BITX((regs)->cp_ebx, 31, 22) 237 #define CPI_CACHE_PARTS(regs) BITX((regs)->cp_ebx, 21, 12) 238 #define CPI_CACHE_COH_LN_SZ(regs) BITX((regs)->cp_ebx, 11, 0) 239 240 #define CPI_CACHE_SETS(regs) BITX((regs)->cp_ecx, 31, 0) 241 242 #define CPI_PREFCH_STRIDE(regs) BITX((regs)->cp_edx, 9, 0) 243 244 245 /* 246 * A couple of shorthand macros to identify "later" P6-family chips 247 * like the Pentium M and Core. First, the "older" P6-based stuff 248 * (loosely defined as "pre-Pentium-4"): 249 * P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon 250 */ 251 252 #define IS_LEGACY_P6(cpi) ( \ 253 cpi->cpi_family == 6 && \ 254 (cpi->cpi_model == 1 || \ 255 cpi->cpi_model == 3 || \ 256 cpi->cpi_model == 5 || \ 257 cpi->cpi_model == 6 || \ 258 cpi->cpi_model == 7 || \ 259 cpi->cpi_model == 8 || \ 260 cpi->cpi_model == 0xA || \ 261 cpi->cpi_model == 0xB) \ 262 ) 263 264 /* A "new F6" is everything with family 6 that's not the above */ 265 #define IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi)) 266 267 /* Extended family/model support */ 268 #define IS_EXTENDED_MODEL_INTEL(cpi) (cpi->cpi_family == 0x6 || \ 269 cpi->cpi_family >= 0xf) 270 271 /* 272 * Info for monitor/mwait idle loop. 273 * 274 * See cpuid section of "Intel 64 and IA-32 Architectures Software Developer's 275 * Manual Volume 2A: Instruction Set Reference, A-M" #25366-022US, November 276 * 2006. 277 * See MONITOR/MWAIT section of "AMD64 Architecture Programmer's Manual 278 * Documentation Updates" #33633, Rev 2.05, December 2006. 279 */ 280 #define MWAIT_SUPPORT (0x00000001) /* mwait supported */ 281 #define MWAIT_EXTENSIONS (0x00000002) /* extenstion supported */ 282 #define MWAIT_ECX_INT_ENABLE (0x00000004) /* ecx 1 extension supported */ 283 #define MWAIT_SUPPORTED(cpi) ((cpi)->cpi_std[1].cp_ecx & CPUID_INTC_ECX_MON) 284 #define MWAIT_INT_ENABLE(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x2) 285 #define MWAIT_EXTENSION(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x1) 286 #define MWAIT_SIZE_MIN(cpi) BITX((cpi)->cpi_std[5].cp_eax, 15, 0) 287 #define MWAIT_SIZE_MAX(cpi) BITX((cpi)->cpi_std[5].cp_ebx, 15, 0) 288 /* 289 * Number of sub-cstates for a given c-state. 290 */ 291 #define MWAIT_NUM_SUBC_STATES(cpi, c_state) \ 292 BITX((cpi)->cpi_std[5].cp_edx, c_state + 3, c_state) 293 294 /* 295 * Functions we consune from cpuid_subr.c; don't publish these in a header 296 * file to try and keep people using the expected cpuid_* interfaces. 297 */ 298 extern uint32_t _cpuid_skt(uint_t, uint_t, uint_t, uint_t); 299 extern uint32_t _cpuid_chiprev(uint_t, uint_t, uint_t, uint_t); 300 extern const char *_cpuid_chiprevstr(uint_t, uint_t, uint_t, uint_t); 301 extern uint_t _cpuid_vendorstr_to_vendorcode(char *); 302 303 /* 304 * Apply up various platform-dependent restrictions where the 305 * underlying platform restrictions mean the CPU can be marked 306 * as less capable than its cpuid instruction would imply. 307 */ 308 #if defined(__xpv) 309 static void 310 platform_cpuid_mangle(uint_t vendor, uint32_t eax, struct cpuid_regs *cp) 311 { 312 switch (eax) { 313 case 1: { 314 uint32_t mcamask = DOMAIN_IS_INITDOMAIN(xen_info) ? 315 0 : CPUID_INTC_EDX_MCA; 316 cp->cp_edx &= 317 ~(mcamask | 318 CPUID_INTC_EDX_PSE | 319 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE | 320 CPUID_INTC_EDX_SEP | CPUID_INTC_EDX_MTRR | 321 CPUID_INTC_EDX_PGE | CPUID_INTC_EDX_PAT | 322 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP | 323 CPUID_INTC_EDX_PSE36 | CPUID_INTC_EDX_HTT); 324 break; 325 } 326 327 case 0x80000001: 328 cp->cp_edx &= 329 ~(CPUID_AMD_EDX_PSE | 330 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE | 331 CPUID_AMD_EDX_MTRR | CPUID_AMD_EDX_PGE | 332 CPUID_AMD_EDX_PAT | CPUID_AMD_EDX_PSE36 | 333 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP | 334 CPUID_AMD_EDX_TSCP); 335 cp->cp_ecx &= ~CPUID_AMD_ECX_CMP_LGCY; 336 break; 337 default: 338 break; 339 } 340 341 switch (vendor) { 342 case X86_VENDOR_Intel: 343 switch (eax) { 344 case 4: 345 /* 346 * Zero out the (ncores-per-chip - 1) field 347 */ 348 cp->cp_eax &= 0x03fffffff; 349 break; 350 default: 351 break; 352 } 353 break; 354 case X86_VENDOR_AMD: 355 switch (eax) { 356 case 0x80000008: 357 /* 358 * Zero out the (ncores-per-chip - 1) field 359 */ 360 cp->cp_ecx &= 0xffffff00; 361 break; 362 default: 363 break; 364 } 365 break; 366 default: 367 break; 368 } 369 } 370 #else 371 #define platform_cpuid_mangle(vendor, eax, cp) /* nothing */ 372 #endif 373 374 /* 375 * Some undocumented ways of patching the results of the cpuid 376 * instruction to permit running Solaris 10 on future cpus that 377 * we don't currently support. Could be set to non-zero values 378 * via settings in eeprom. 379 */ 380 381 uint32_t cpuid_feature_ecx_include; 382 uint32_t cpuid_feature_ecx_exclude; 383 uint32_t cpuid_feature_edx_include; 384 uint32_t cpuid_feature_edx_exclude; 385 386 void 387 cpuid_alloc_space(cpu_t *cpu) 388 { 389 /* 390 * By convention, cpu0 is the boot cpu, which is set up 391 * before memory allocation is available. All other cpus get 392 * their cpuid_info struct allocated here. 393 */ 394 ASSERT(cpu->cpu_id != 0); 395 cpu->cpu_m.mcpu_cpi = 396 kmem_zalloc(sizeof (*cpu->cpu_m.mcpu_cpi), KM_SLEEP); 397 } 398 399 void 400 cpuid_free_space(cpu_t *cpu) 401 { 402 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 403 int i; 404 405 ASSERT(cpu->cpu_id != 0); 406 407 /* 408 * Free up any function 4 related dynamic storage 409 */ 410 for (i = 1; i < cpi->cpi_std_4_size; i++) 411 kmem_free(cpi->cpi_std_4[i], sizeof (struct cpuid_regs)); 412 if (cpi->cpi_std_4_size > 0) 413 kmem_free(cpi->cpi_std_4, 414 cpi->cpi_std_4_size * sizeof (struct cpuid_regs *)); 415 416 kmem_free(cpu->cpu_m.mcpu_cpi, sizeof (*cpu->cpu_m.mcpu_cpi)); 417 } 418 419 #if !defined(__xpv) 420 421 static void 422 check_for_hvm() 423 { 424 struct cpuid_regs cp; 425 char *xen_str; 426 uint32_t xen_signature[4]; 427 extern int xpv_is_hvm; 428 429 /* 430 * In a fully virtualized domain, Xen's pseudo-cpuid function 431 * 0x40000000 returns a string representing the Xen signature in 432 * %ebx, %ecx, and %edx. %eax contains the maximum supported cpuid 433 * function. 434 */ 435 cp.cp_eax = 0x40000000; 436 (void) __cpuid_insn(&cp); 437 xen_signature[0] = cp.cp_ebx; 438 xen_signature[1] = cp.cp_ecx; 439 xen_signature[2] = cp.cp_edx; 440 xen_signature[3] = 0; 441 xen_str = (char *)xen_signature; 442 if (strcmp("XenVMMXenVMM", xen_str) == 0 && cp.cp_eax <= 0x40000002) 443 xpv_is_hvm = 1; 444 } 445 #endif /* __xpv */ 446 447 uint_t 448 cpuid_pass1(cpu_t *cpu) 449 { 450 uint32_t mask_ecx, mask_edx; 451 uint_t feature = X86_CPUID; 452 struct cpuid_info *cpi; 453 struct cpuid_regs *cp; 454 int xcpuid; 455 #if !defined(__xpv) 456 extern int idle_cpu_prefer_mwait; 457 #endif 458 459 /* 460 * Space statically allocated for cpu0, ensure pointer is set 461 */ 462 if (cpu->cpu_id == 0) 463 cpu->cpu_m.mcpu_cpi = &cpuid_info0; 464 cpi = cpu->cpu_m.mcpu_cpi; 465 ASSERT(cpi != NULL); 466 cp = &cpi->cpi_std[0]; 467 cp->cp_eax = 0; 468 cpi->cpi_maxeax = __cpuid_insn(cp); 469 { 470 uint32_t *iptr = (uint32_t *)cpi->cpi_vendorstr; 471 *iptr++ = cp->cp_ebx; 472 *iptr++ = cp->cp_edx; 473 *iptr++ = cp->cp_ecx; 474 *(char *)&cpi->cpi_vendorstr[12] = '\0'; 475 } 476 477 cpi->cpi_vendor = _cpuid_vendorstr_to_vendorcode(cpi->cpi_vendorstr); 478 x86_vendor = cpi->cpi_vendor; /* for compatibility */ 479 480 /* 481 * Limit the range in case of weird hardware 482 */ 483 if (cpi->cpi_maxeax > CPI_MAXEAX_MAX) 484 cpi->cpi_maxeax = CPI_MAXEAX_MAX; 485 if (cpi->cpi_maxeax < 1) 486 goto pass1_done; 487 488 cp = &cpi->cpi_std[1]; 489 cp->cp_eax = 1; 490 (void) __cpuid_insn(cp); 491 492 /* 493 * Extract identifying constants for easy access. 494 */ 495 cpi->cpi_model = CPI_MODEL(cpi); 496 cpi->cpi_family = CPI_FAMILY(cpi); 497 498 if (cpi->cpi_family == 0xf) 499 cpi->cpi_family += CPI_FAMILY_XTD(cpi); 500 501 /* 502 * Beware: AMD uses "extended model" iff base *FAMILY* == 0xf. 503 * Intel, and presumably everyone else, uses model == 0xf, as 504 * one would expect (max value means possible overflow). Sigh. 505 */ 506 507 switch (cpi->cpi_vendor) { 508 case X86_VENDOR_Intel: 509 if (IS_EXTENDED_MODEL_INTEL(cpi)) 510 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 511 break; 512 case X86_VENDOR_AMD: 513 if (CPI_FAMILY(cpi) == 0xf) 514 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 515 break; 516 default: 517 if (cpi->cpi_model == 0xf) 518 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 519 break; 520 } 521 522 cpi->cpi_step = CPI_STEP(cpi); 523 cpi->cpi_brandid = CPI_BRANDID(cpi); 524 525 /* 526 * *default* assumptions: 527 * - believe %edx feature word 528 * - ignore %ecx feature word 529 * - 32-bit virtual and physical addressing 530 */ 531 mask_edx = 0xffffffff; 532 mask_ecx = 0; 533 534 cpi->cpi_pabits = cpi->cpi_vabits = 32; 535 536 switch (cpi->cpi_vendor) { 537 case X86_VENDOR_Intel: 538 if (cpi->cpi_family == 5) 539 x86_type = X86_TYPE_P5; 540 else if (IS_LEGACY_P6(cpi)) { 541 x86_type = X86_TYPE_P6; 542 pentiumpro_bug4046376 = 1; 543 pentiumpro_bug4064495 = 1; 544 /* 545 * Clear the SEP bit when it was set erroneously 546 */ 547 if (cpi->cpi_model < 3 && cpi->cpi_step < 3) 548 cp->cp_edx &= ~CPUID_INTC_EDX_SEP; 549 } else if (IS_NEW_F6(cpi) || cpi->cpi_family == 0xf) { 550 x86_type = X86_TYPE_P4; 551 /* 552 * We don't currently depend on any of the %ecx 553 * features until Prescott, so we'll only check 554 * this from P4 onwards. We might want to revisit 555 * that idea later. 556 */ 557 mask_ecx = 0xffffffff; 558 } else if (cpi->cpi_family > 0xf) 559 mask_ecx = 0xffffffff; 560 /* 561 * We don't support MONITOR/MWAIT if leaf 5 is not available 562 * to obtain the monitor linesize. 563 */ 564 if (cpi->cpi_maxeax < 5) 565 mask_ecx &= ~CPUID_INTC_ECX_MON; 566 break; 567 case X86_VENDOR_IntelClone: 568 default: 569 break; 570 case X86_VENDOR_AMD: 571 #if defined(OPTERON_ERRATUM_108) 572 if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) { 573 cp->cp_eax = (0xf0f & cp->cp_eax) | 0xc0; 574 cpi->cpi_model = 0xc; 575 } else 576 #endif 577 if (cpi->cpi_family == 5) { 578 /* 579 * AMD K5 and K6 580 * 581 * These CPUs have an incomplete implementation 582 * of MCA/MCE which we mask away. 583 */ 584 mask_edx &= ~(CPUID_INTC_EDX_MCE | CPUID_INTC_EDX_MCA); 585 586 /* 587 * Model 0 uses the wrong (APIC) bit 588 * to indicate PGE. Fix it here. 589 */ 590 if (cpi->cpi_model == 0) { 591 if (cp->cp_edx & 0x200) { 592 cp->cp_edx &= ~0x200; 593 cp->cp_edx |= CPUID_INTC_EDX_PGE; 594 } 595 } 596 597 /* 598 * Early models had problems w/ MMX; disable. 599 */ 600 if (cpi->cpi_model < 6) 601 mask_edx &= ~CPUID_INTC_EDX_MMX; 602 } 603 604 /* 605 * For newer families, SSE3 and CX16, at least, are valid; 606 * enable all 607 */ 608 if (cpi->cpi_family >= 0xf) 609 mask_ecx = 0xffffffff; 610 /* 611 * We don't support MONITOR/MWAIT if leaf 5 is not available 612 * to obtain the monitor linesize. 613 */ 614 if (cpi->cpi_maxeax < 5) 615 mask_ecx &= ~CPUID_INTC_ECX_MON; 616 617 #if !defined(__xpv) 618 /* 619 * Do not use MONITOR/MWAIT to halt in the idle loop on any AMD 620 * processors. AMD does not intend MWAIT to be used in the cpu 621 * idle loop on current and future processors. 10h and future 622 * AMD processors use more power in MWAIT than HLT. 623 * Pre-family-10h Opterons do not have the MWAIT instruction. 624 */ 625 idle_cpu_prefer_mwait = 0; 626 #endif 627 628 break; 629 case X86_VENDOR_TM: 630 /* 631 * workaround the NT workaround in CMS 4.1 632 */ 633 if (cpi->cpi_family == 5 && cpi->cpi_model == 4 && 634 (cpi->cpi_step == 2 || cpi->cpi_step == 3)) 635 cp->cp_edx |= CPUID_INTC_EDX_CX8; 636 break; 637 case X86_VENDOR_Centaur: 638 /* 639 * workaround the NT workarounds again 640 */ 641 if (cpi->cpi_family == 6) 642 cp->cp_edx |= CPUID_INTC_EDX_CX8; 643 break; 644 case X86_VENDOR_Cyrix: 645 /* 646 * We rely heavily on the probing in locore 647 * to actually figure out what parts, if any, 648 * of the Cyrix cpuid instruction to believe. 649 */ 650 switch (x86_type) { 651 case X86_TYPE_CYRIX_486: 652 mask_edx = 0; 653 break; 654 case X86_TYPE_CYRIX_6x86: 655 mask_edx = 0; 656 break; 657 case X86_TYPE_CYRIX_6x86L: 658 mask_edx = 659 CPUID_INTC_EDX_DE | 660 CPUID_INTC_EDX_CX8; 661 break; 662 case X86_TYPE_CYRIX_6x86MX: 663 mask_edx = 664 CPUID_INTC_EDX_DE | 665 CPUID_INTC_EDX_MSR | 666 CPUID_INTC_EDX_CX8 | 667 CPUID_INTC_EDX_PGE | 668 CPUID_INTC_EDX_CMOV | 669 CPUID_INTC_EDX_MMX; 670 break; 671 case X86_TYPE_CYRIX_GXm: 672 mask_edx = 673 CPUID_INTC_EDX_MSR | 674 CPUID_INTC_EDX_CX8 | 675 CPUID_INTC_EDX_CMOV | 676 CPUID_INTC_EDX_MMX; 677 break; 678 case X86_TYPE_CYRIX_MediaGX: 679 break; 680 case X86_TYPE_CYRIX_MII: 681 case X86_TYPE_VIA_CYRIX_III: 682 mask_edx = 683 CPUID_INTC_EDX_DE | 684 CPUID_INTC_EDX_TSC | 685 CPUID_INTC_EDX_MSR | 686 CPUID_INTC_EDX_CX8 | 687 CPUID_INTC_EDX_PGE | 688 CPUID_INTC_EDX_CMOV | 689 CPUID_INTC_EDX_MMX; 690 break; 691 default: 692 break; 693 } 694 break; 695 } 696 697 #if defined(__xpv) 698 /* 699 * Do not support MONITOR/MWAIT under a hypervisor 700 */ 701 mask_ecx &= ~CPUID_INTC_ECX_MON; 702 #endif /* __xpv */ 703 704 /* 705 * Now we've figured out the masks that determine 706 * which bits we choose to believe, apply the masks 707 * to the feature words, then map the kernel's view 708 * of these feature words into its feature word. 709 */ 710 cp->cp_edx &= mask_edx; 711 cp->cp_ecx &= mask_ecx; 712 713 /* 714 * apply any platform restrictions (we don't call this 715 * immediately after __cpuid_insn here, because we need the 716 * workarounds applied above first) 717 */ 718 platform_cpuid_mangle(cpi->cpi_vendor, 1, cp); 719 720 /* 721 * fold in overrides from the "eeprom" mechanism 722 */ 723 cp->cp_edx |= cpuid_feature_edx_include; 724 cp->cp_edx &= ~cpuid_feature_edx_exclude; 725 726 cp->cp_ecx |= cpuid_feature_ecx_include; 727 cp->cp_ecx &= ~cpuid_feature_ecx_exclude; 728 729 if (cp->cp_edx & CPUID_INTC_EDX_PSE) 730 feature |= X86_LARGEPAGE; 731 if (cp->cp_edx & CPUID_INTC_EDX_TSC) 732 feature |= X86_TSC; 733 if (cp->cp_edx & CPUID_INTC_EDX_MSR) 734 feature |= X86_MSR; 735 if (cp->cp_edx & CPUID_INTC_EDX_MTRR) 736 feature |= X86_MTRR; 737 if (cp->cp_edx & CPUID_INTC_EDX_PGE) 738 feature |= X86_PGE; 739 if (cp->cp_edx & CPUID_INTC_EDX_CMOV) 740 feature |= X86_CMOV; 741 if (cp->cp_edx & CPUID_INTC_EDX_MMX) 742 feature |= X86_MMX; 743 if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 && 744 (cp->cp_edx & CPUID_INTC_EDX_MCA) != 0) 745 feature |= X86_MCA; 746 if (cp->cp_edx & CPUID_INTC_EDX_PAE) 747 feature |= X86_PAE; 748 if (cp->cp_edx & CPUID_INTC_EDX_CX8) 749 feature |= X86_CX8; 750 if (cp->cp_ecx & CPUID_INTC_ECX_CX16) 751 feature |= X86_CX16; 752 if (cp->cp_edx & CPUID_INTC_EDX_PAT) 753 feature |= X86_PAT; 754 if (cp->cp_edx & CPUID_INTC_EDX_SEP) 755 feature |= X86_SEP; 756 if (cp->cp_edx & CPUID_INTC_EDX_FXSR) { 757 /* 758 * In our implementation, fxsave/fxrstor 759 * are prerequisites before we'll even 760 * try and do SSE things. 761 */ 762 if (cp->cp_edx & CPUID_INTC_EDX_SSE) 763 feature |= X86_SSE; 764 if (cp->cp_edx & CPUID_INTC_EDX_SSE2) 765 feature |= X86_SSE2; 766 if (cp->cp_ecx & CPUID_INTC_ECX_SSE3) 767 feature |= X86_SSE3; 768 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 769 if (cp->cp_ecx & CPUID_INTC_ECX_SSSE3) 770 feature |= X86_SSSE3; 771 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_1) 772 feature |= X86_SSE4_1; 773 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_2) 774 feature |= X86_SSE4_2; 775 } 776 } 777 if (cp->cp_edx & CPUID_INTC_EDX_DE) 778 feature |= X86_DE; 779 if (cp->cp_ecx & CPUID_INTC_ECX_MON) { 780 cpi->cpi_mwait.support |= MWAIT_SUPPORT; 781 feature |= X86_MWAIT; 782 } 783 784 /* 785 * Only need it first time, rest of the cpus would follow suite. 786 * we only capture this for the bootcpu. 787 */ 788 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) { 789 feature |= X86_CLFSH; 790 x86_clflush_size = (BITX(cp->cp_ebx, 15, 8) * 8); 791 } 792 793 if (feature & X86_PAE) 794 cpi->cpi_pabits = 36; 795 796 /* 797 * Hyperthreading configuration is slightly tricky on Intel 798 * and pure clones, and even trickier on AMD. 799 * 800 * (AMD chose to set the HTT bit on their CMP processors, 801 * even though they're not actually hyperthreaded. Thus it 802 * takes a bit more work to figure out what's really going 803 * on ... see the handling of the CMP_LGCY bit below) 804 */ 805 if (cp->cp_edx & CPUID_INTC_EDX_HTT) { 806 cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi); 807 if (cpi->cpi_ncpu_per_chip > 1) 808 feature |= X86_HTT; 809 } else { 810 cpi->cpi_ncpu_per_chip = 1; 811 } 812 813 /* 814 * Work on the "extended" feature information, doing 815 * some basic initialization for cpuid_pass2() 816 */ 817 xcpuid = 0; 818 switch (cpi->cpi_vendor) { 819 case X86_VENDOR_Intel: 820 if (IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf) 821 xcpuid++; 822 break; 823 case X86_VENDOR_AMD: 824 if (cpi->cpi_family > 5 || 825 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 826 xcpuid++; 827 break; 828 case X86_VENDOR_Cyrix: 829 /* 830 * Only these Cyrix CPUs are -known- to support 831 * extended cpuid operations. 832 */ 833 if (x86_type == X86_TYPE_VIA_CYRIX_III || 834 x86_type == X86_TYPE_CYRIX_GXm) 835 xcpuid++; 836 break; 837 case X86_VENDOR_Centaur: 838 case X86_VENDOR_TM: 839 default: 840 xcpuid++; 841 break; 842 } 843 844 if (xcpuid) { 845 cp = &cpi->cpi_extd[0]; 846 cp->cp_eax = 0x80000000; 847 cpi->cpi_xmaxeax = __cpuid_insn(cp); 848 } 849 850 if (cpi->cpi_xmaxeax & 0x80000000) { 851 852 if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX) 853 cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX; 854 855 switch (cpi->cpi_vendor) { 856 case X86_VENDOR_Intel: 857 case X86_VENDOR_AMD: 858 if (cpi->cpi_xmaxeax < 0x80000001) 859 break; 860 cp = &cpi->cpi_extd[1]; 861 cp->cp_eax = 0x80000001; 862 (void) __cpuid_insn(cp); 863 864 if (cpi->cpi_vendor == X86_VENDOR_AMD && 865 cpi->cpi_family == 5 && 866 cpi->cpi_model == 6 && 867 cpi->cpi_step == 6) { 868 /* 869 * K6 model 6 uses bit 10 to indicate SYSC 870 * Later models use bit 11. Fix it here. 871 */ 872 if (cp->cp_edx & 0x400) { 873 cp->cp_edx &= ~0x400; 874 cp->cp_edx |= CPUID_AMD_EDX_SYSC; 875 } 876 } 877 878 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000001, cp); 879 880 /* 881 * Compute the additions to the kernel's feature word. 882 */ 883 if (cp->cp_edx & CPUID_AMD_EDX_NX) 884 feature |= X86_NX; 885 886 #if defined(__amd64) 887 /* 1 GB large page - enable only for 64 bit kernel */ 888 if (cp->cp_edx & CPUID_AMD_EDX_1GPG) 889 feature |= X86_1GPG; 890 #endif 891 892 if ((cpi->cpi_vendor == X86_VENDOR_AMD) && 893 (cpi->cpi_std[1].cp_edx & CPUID_INTC_EDX_FXSR) && 894 (cp->cp_ecx & CPUID_AMD_ECX_SSE4A)) 895 feature |= X86_SSE4A; 896 897 /* 898 * If both the HTT and CMP_LGCY bits are set, 899 * then we're not actually HyperThreaded. Read 900 * "AMD CPUID Specification" for more details. 901 */ 902 if (cpi->cpi_vendor == X86_VENDOR_AMD && 903 (feature & X86_HTT) && 904 (cp->cp_ecx & CPUID_AMD_ECX_CMP_LGCY)) { 905 feature &= ~X86_HTT; 906 feature |= X86_CMP; 907 } 908 #if defined(__amd64) 909 /* 910 * It's really tricky to support syscall/sysret in 911 * the i386 kernel; we rely on sysenter/sysexit 912 * instead. In the amd64 kernel, things are -way- 913 * better. 914 */ 915 if (cp->cp_edx & CPUID_AMD_EDX_SYSC) 916 feature |= X86_ASYSC; 917 918 /* 919 * While we're thinking about system calls, note 920 * that AMD processors don't support sysenter 921 * in long mode at all, so don't try to program them. 922 */ 923 if (x86_vendor == X86_VENDOR_AMD) 924 feature &= ~X86_SEP; 925 #endif 926 if (cp->cp_edx & CPUID_AMD_EDX_TSCP) 927 feature |= X86_TSCP; 928 break; 929 default: 930 break; 931 } 932 933 /* 934 * Get CPUID data about processor cores and hyperthreads. 935 */ 936 switch (cpi->cpi_vendor) { 937 case X86_VENDOR_Intel: 938 if (cpi->cpi_maxeax >= 4) { 939 cp = &cpi->cpi_std[4]; 940 cp->cp_eax = 4; 941 cp->cp_ecx = 0; 942 (void) __cpuid_insn(cp); 943 platform_cpuid_mangle(cpi->cpi_vendor, 4, cp); 944 } 945 /*FALLTHROUGH*/ 946 case X86_VENDOR_AMD: 947 if (cpi->cpi_xmaxeax < 0x80000008) 948 break; 949 cp = &cpi->cpi_extd[8]; 950 cp->cp_eax = 0x80000008; 951 (void) __cpuid_insn(cp); 952 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000008, cp); 953 954 /* 955 * Virtual and physical address limits from 956 * cpuid override previously guessed values. 957 */ 958 cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0); 959 cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8); 960 break; 961 default: 962 break; 963 } 964 965 /* 966 * Derive the number of cores per chip 967 */ 968 switch (cpi->cpi_vendor) { 969 case X86_VENDOR_Intel: 970 if (cpi->cpi_maxeax < 4) { 971 cpi->cpi_ncore_per_chip = 1; 972 break; 973 } else { 974 cpi->cpi_ncore_per_chip = 975 BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1; 976 } 977 break; 978 case X86_VENDOR_AMD: 979 if (cpi->cpi_xmaxeax < 0x80000008) { 980 cpi->cpi_ncore_per_chip = 1; 981 break; 982 } else { 983 /* 984 * On family 0xf cpuid fn 2 ECX[7:0] "NC" is 985 * 1 less than the number of physical cores on 986 * the chip. In family 0x10 this value can 987 * be affected by "downcoring" - it reflects 988 * 1 less than the number of cores actually 989 * enabled on this node. 990 */ 991 cpi->cpi_ncore_per_chip = 992 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1; 993 } 994 break; 995 default: 996 cpi->cpi_ncore_per_chip = 1; 997 break; 998 } 999 } else { 1000 cpi->cpi_ncore_per_chip = 1; 1001 } 1002 1003 /* 1004 * If more than one core, then this processor is CMP. 1005 */ 1006 if (cpi->cpi_ncore_per_chip > 1) 1007 feature |= X86_CMP; 1008 1009 /* 1010 * If the number of cores is the same as the number 1011 * of CPUs, then we cannot have HyperThreading. 1012 */ 1013 if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip) 1014 feature &= ~X86_HTT; 1015 1016 if ((feature & (X86_HTT | X86_CMP)) == 0) { 1017 /* 1018 * Single-core single-threaded processors. 1019 */ 1020 cpi->cpi_chipid = -1; 1021 cpi->cpi_clogid = 0; 1022 cpi->cpi_coreid = cpu->cpu_id; 1023 cpi->cpi_pkgcoreid = 0; 1024 } else if (cpi->cpi_ncpu_per_chip > 1) { 1025 uint_t i; 1026 uint_t chipid_shift = 0; 1027 uint_t coreid_shift = 0; 1028 uint_t apic_id = CPI_APIC_ID(cpi); 1029 1030 for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1) 1031 chipid_shift++; 1032 cpi->cpi_chipid = apic_id >> chipid_shift; 1033 cpi->cpi_clogid = apic_id & ((1 << chipid_shift) - 1); 1034 1035 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 1036 if (feature & X86_CMP) { 1037 /* 1038 * Multi-core (and possibly multi-threaded) 1039 * processors. 1040 */ 1041 uint_t ncpu_per_core; 1042 if (cpi->cpi_ncore_per_chip == 1) 1043 ncpu_per_core = cpi->cpi_ncpu_per_chip; 1044 else if (cpi->cpi_ncore_per_chip > 1) 1045 ncpu_per_core = cpi->cpi_ncpu_per_chip / 1046 cpi->cpi_ncore_per_chip; 1047 /* 1048 * 8bit APIC IDs on dual core Pentiums 1049 * look like this: 1050 * 1051 * +-----------------------+------+------+ 1052 * | Physical Package ID | MC | HT | 1053 * +-----------------------+------+------+ 1054 * <------- chipid --------> 1055 * <------- coreid ---------------> 1056 * <--- clogid --> 1057 * <------> 1058 * pkgcoreid 1059 * 1060 * Where the number of bits necessary to 1061 * represent MC and HT fields together equals 1062 * to the minimum number of bits necessary to 1063 * store the value of cpi->cpi_ncpu_per_chip. 1064 * Of those bits, the MC part uses the number 1065 * of bits necessary to store the value of 1066 * cpi->cpi_ncore_per_chip. 1067 */ 1068 for (i = 1; i < ncpu_per_core; i <<= 1) 1069 coreid_shift++; 1070 cpi->cpi_coreid = apic_id >> coreid_shift; 1071 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> 1072 coreid_shift; 1073 } else if (feature & X86_HTT) { 1074 /* 1075 * Single-core multi-threaded processors. 1076 */ 1077 cpi->cpi_coreid = cpi->cpi_chipid; 1078 cpi->cpi_pkgcoreid = 0; 1079 } 1080 } else if (cpi->cpi_vendor == X86_VENDOR_AMD) { 1081 /* 1082 * AMD CMP chips currently have a single thread per 1083 * core, with 2 cores on family 0xf and 2, 3 or 4 1084 * cores on family 0x10. 1085 * 1086 * Since no two cpus share a core we must assign a 1087 * distinct coreid per cpu, and we do this by using 1088 * the cpu_id. This scheme does not, however, 1089 * guarantee that sibling cores of a chip will have 1090 * sequential coreids starting at a multiple of the 1091 * number of cores per chip - that is usually the 1092 * case, but if the ACPI MADT table is presented 1093 * in a different order then we need to perform a 1094 * few more gymnastics for the pkgcoreid. 1095 * 1096 * In family 0xf CMPs there are 2 cores on all nodes 1097 * present - no mixing of single and dual core parts. 1098 * 1099 * In family 0x10 CMPs cpuid fn 2 ECX[15:12] 1100 * "ApicIdCoreIdSize[3:0]" tells us how 1101 * many least-significant bits in the ApicId 1102 * are used to represent the core number 1103 * within the node. Cores are always 1104 * numbered sequentially from 0 regardless 1105 * of how many or which are disabled, and 1106 * there seems to be no way to discover the 1107 * real core id when some are disabled. 1108 */ 1109 cpi->cpi_coreid = cpu->cpu_id; 1110 1111 if (cpi->cpi_family == 0x10 && 1112 cpi->cpi_xmaxeax >= 0x80000008) { 1113 int coreidsz = 1114 BITX((cpi)->cpi_extd[8].cp_ecx, 15, 12); 1115 1116 cpi->cpi_pkgcoreid = 1117 apic_id & ((1 << coreidsz) - 1); 1118 } else { 1119 cpi->cpi_pkgcoreid = cpi->cpi_clogid; 1120 } 1121 } else { 1122 /* 1123 * All other processors are currently 1124 * assumed to have single cores. 1125 */ 1126 cpi->cpi_coreid = cpi->cpi_chipid; 1127 cpi->cpi_pkgcoreid = 0; 1128 } 1129 } 1130 1131 cpi->cpi_apicid = CPI_APIC_ID(cpi); 1132 1133 /* 1134 * Synthesize chip "revision" and socket type 1135 */ 1136 cpi->cpi_chiprev = _cpuid_chiprev(cpi->cpi_vendor, cpi->cpi_family, 1137 cpi->cpi_model, cpi->cpi_step); 1138 cpi->cpi_chiprevstr = _cpuid_chiprevstr(cpi->cpi_vendor, 1139 cpi->cpi_family, cpi->cpi_model, cpi->cpi_step); 1140 cpi->cpi_socket = _cpuid_skt(cpi->cpi_vendor, cpi->cpi_family, 1141 cpi->cpi_model, cpi->cpi_step); 1142 1143 pass1_done: 1144 #if !defined(__xpv) 1145 check_for_hvm(); 1146 #endif 1147 cpi->cpi_pass = 1; 1148 return (feature); 1149 } 1150 1151 /* 1152 * Make copies of the cpuid table entries we depend on, in 1153 * part for ease of parsing now, in part so that we have only 1154 * one place to correct any of it, in part for ease of 1155 * later export to userland, and in part so we can look at 1156 * this stuff in a crash dump. 1157 */ 1158 1159 /*ARGSUSED*/ 1160 void 1161 cpuid_pass2(cpu_t *cpu) 1162 { 1163 uint_t n, nmax; 1164 int i; 1165 struct cpuid_regs *cp; 1166 uint8_t *dp; 1167 uint32_t *iptr; 1168 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1169 1170 ASSERT(cpi->cpi_pass == 1); 1171 1172 if (cpi->cpi_maxeax < 1) 1173 goto pass2_done; 1174 1175 if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD) 1176 nmax = NMAX_CPI_STD; 1177 /* 1178 * (We already handled n == 0 and n == 1 in pass 1) 1179 */ 1180 for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) { 1181 cp->cp_eax = n; 1182 1183 /* 1184 * CPUID function 4 expects %ecx to be initialized 1185 * with an index which indicates which cache to return 1186 * information about. The OS is expected to call function 4 1187 * with %ecx set to 0, 1, 2, ... until it returns with 1188 * EAX[4:0] set to 0, which indicates there are no more 1189 * caches. 1190 * 1191 * Here, populate cpi_std[4] with the information returned by 1192 * function 4 when %ecx == 0, and do the rest in cpuid_pass3() 1193 * when dynamic memory allocation becomes available. 1194 * 1195 * Note: we need to explicitly initialize %ecx here, since 1196 * function 4 may have been previously invoked. 1197 */ 1198 if (n == 4) 1199 cp->cp_ecx = 0; 1200 1201 (void) __cpuid_insn(cp); 1202 platform_cpuid_mangle(cpi->cpi_vendor, n, cp); 1203 switch (n) { 1204 case 2: 1205 /* 1206 * "the lower 8 bits of the %eax register 1207 * contain a value that identifies the number 1208 * of times the cpuid [instruction] has to be 1209 * executed to obtain a complete image of the 1210 * processor's caching systems." 1211 * 1212 * How *do* they make this stuff up? 1213 */ 1214 cpi->cpi_ncache = sizeof (*cp) * 1215 BITX(cp->cp_eax, 7, 0); 1216 if (cpi->cpi_ncache == 0) 1217 break; 1218 cpi->cpi_ncache--; /* skip count byte */ 1219 1220 /* 1221 * Well, for now, rather than attempt to implement 1222 * this slightly dubious algorithm, we just look 1223 * at the first 15 .. 1224 */ 1225 if (cpi->cpi_ncache > (sizeof (*cp) - 1)) 1226 cpi->cpi_ncache = sizeof (*cp) - 1; 1227 1228 dp = cpi->cpi_cacheinfo; 1229 if (BITX(cp->cp_eax, 31, 31) == 0) { 1230 uint8_t *p = (void *)&cp->cp_eax; 1231 for (i = 1; i < 4; i++) 1232 if (p[i] != 0) 1233 *dp++ = p[i]; 1234 } 1235 if (BITX(cp->cp_ebx, 31, 31) == 0) { 1236 uint8_t *p = (void *)&cp->cp_ebx; 1237 for (i = 0; i < 4; i++) 1238 if (p[i] != 0) 1239 *dp++ = p[i]; 1240 } 1241 if (BITX(cp->cp_ecx, 31, 31) == 0) { 1242 uint8_t *p = (void *)&cp->cp_ecx; 1243 for (i = 0; i < 4; i++) 1244 if (p[i] != 0) 1245 *dp++ = p[i]; 1246 } 1247 if (BITX(cp->cp_edx, 31, 31) == 0) { 1248 uint8_t *p = (void *)&cp->cp_edx; 1249 for (i = 0; i < 4; i++) 1250 if (p[i] != 0) 1251 *dp++ = p[i]; 1252 } 1253 break; 1254 1255 case 3: /* Processor serial number, if PSN supported */ 1256 break; 1257 1258 case 4: /* Deterministic cache parameters */ 1259 break; 1260 1261 case 5: /* Monitor/Mwait parameters */ 1262 { 1263 size_t mwait_size; 1264 1265 /* 1266 * check cpi_mwait.support which was set in cpuid_pass1 1267 */ 1268 if (!(cpi->cpi_mwait.support & MWAIT_SUPPORT)) 1269 break; 1270 1271 /* 1272 * Protect ourself from insane mwait line size. 1273 * Workaround for incomplete hardware emulator(s). 1274 */ 1275 mwait_size = (size_t)MWAIT_SIZE_MAX(cpi); 1276 if (mwait_size < sizeof (uint32_t) || 1277 !ISP2(mwait_size)) { 1278 #if DEBUG 1279 cmn_err(CE_NOTE, "Cannot handle cpu %d mwait " 1280 "size %ld", 1281 cpu->cpu_id, (long)mwait_size); 1282 #endif 1283 break; 1284 } 1285 1286 cpi->cpi_mwait.mon_min = (size_t)MWAIT_SIZE_MIN(cpi); 1287 cpi->cpi_mwait.mon_max = mwait_size; 1288 if (MWAIT_EXTENSION(cpi)) { 1289 cpi->cpi_mwait.support |= MWAIT_EXTENSIONS; 1290 if (MWAIT_INT_ENABLE(cpi)) 1291 cpi->cpi_mwait.support |= 1292 MWAIT_ECX_INT_ENABLE; 1293 } 1294 break; 1295 } 1296 default: 1297 break; 1298 } 1299 } 1300 1301 if (cpi->cpi_maxeax >= 0xB && cpi->cpi_vendor == X86_VENDOR_Intel) { 1302 cp->cp_eax = 0xB; 1303 cp->cp_ecx = 0; 1304 1305 (void) __cpuid_insn(cp); 1306 1307 /* 1308 * Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero, which 1309 * indicates that the extended topology enumeration leaf is 1310 * available. 1311 */ 1312 if (cp->cp_ebx) { 1313 uint32_t x2apic_id; 1314 uint_t coreid_shift = 0; 1315 uint_t ncpu_per_core = 1; 1316 uint_t chipid_shift = 0; 1317 uint_t ncpu_per_chip = 1; 1318 uint_t i; 1319 uint_t level; 1320 1321 for (i = 0; i < CPI_FNB_ECX_MAX; i++) { 1322 cp->cp_eax = 0xB; 1323 cp->cp_ecx = i; 1324 1325 (void) __cpuid_insn(cp); 1326 level = CPI_CPU_LEVEL_TYPE(cp); 1327 1328 if (level == 1) { 1329 x2apic_id = cp->cp_edx; 1330 coreid_shift = BITX(cp->cp_eax, 4, 0); 1331 ncpu_per_core = BITX(cp->cp_ebx, 15, 0); 1332 } else if (level == 2) { 1333 x2apic_id = cp->cp_edx; 1334 chipid_shift = BITX(cp->cp_eax, 4, 0); 1335 ncpu_per_chip = BITX(cp->cp_ebx, 15, 0); 1336 } 1337 } 1338 1339 cpi->cpi_apicid = x2apic_id; 1340 cpi->cpi_ncpu_per_chip = ncpu_per_chip; 1341 cpi->cpi_ncore_per_chip = ncpu_per_chip / 1342 ncpu_per_core; 1343 cpi->cpi_chipid = x2apic_id >> chipid_shift; 1344 cpi->cpi_clogid = x2apic_id & ((1 << chipid_shift) - 1); 1345 cpi->cpi_coreid = x2apic_id >> coreid_shift; 1346 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift; 1347 } 1348 } 1349 1350 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) 1351 goto pass2_done; 1352 1353 if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD) 1354 nmax = NMAX_CPI_EXTD; 1355 /* 1356 * Copy the extended properties, fixing them as we go. 1357 * (We already handled n == 0 and n == 1 in pass 1) 1358 */ 1359 iptr = (void *)cpi->cpi_brandstr; 1360 for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) { 1361 cp->cp_eax = 0x80000000 + n; 1362 (void) __cpuid_insn(cp); 1363 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000000 + n, cp); 1364 switch (n) { 1365 case 2: 1366 case 3: 1367 case 4: 1368 /* 1369 * Extract the brand string 1370 */ 1371 *iptr++ = cp->cp_eax; 1372 *iptr++ = cp->cp_ebx; 1373 *iptr++ = cp->cp_ecx; 1374 *iptr++ = cp->cp_edx; 1375 break; 1376 case 5: 1377 switch (cpi->cpi_vendor) { 1378 case X86_VENDOR_AMD: 1379 /* 1380 * The Athlon and Duron were the first 1381 * parts to report the sizes of the 1382 * TLB for large pages. Before then, 1383 * we don't trust the data. 1384 */ 1385 if (cpi->cpi_family < 6 || 1386 (cpi->cpi_family == 6 && 1387 cpi->cpi_model < 1)) 1388 cp->cp_eax = 0; 1389 break; 1390 default: 1391 break; 1392 } 1393 break; 1394 case 6: 1395 switch (cpi->cpi_vendor) { 1396 case X86_VENDOR_AMD: 1397 /* 1398 * The Athlon and Duron were the first 1399 * AMD parts with L2 TLB's. 1400 * Before then, don't trust the data. 1401 */ 1402 if (cpi->cpi_family < 6 || 1403 cpi->cpi_family == 6 && 1404 cpi->cpi_model < 1) 1405 cp->cp_eax = cp->cp_ebx = 0; 1406 /* 1407 * AMD Duron rev A0 reports L2 1408 * cache size incorrectly as 1K 1409 * when it is really 64K 1410 */ 1411 if (cpi->cpi_family == 6 && 1412 cpi->cpi_model == 3 && 1413 cpi->cpi_step == 0) { 1414 cp->cp_ecx &= 0xffff; 1415 cp->cp_ecx |= 0x400000; 1416 } 1417 break; 1418 case X86_VENDOR_Cyrix: /* VIA C3 */ 1419 /* 1420 * VIA C3 processors are a bit messed 1421 * up w.r.t. encoding cache sizes in %ecx 1422 */ 1423 if (cpi->cpi_family != 6) 1424 break; 1425 /* 1426 * model 7 and 8 were incorrectly encoded 1427 * 1428 * xxx is model 8 really broken? 1429 */ 1430 if (cpi->cpi_model == 7 || 1431 cpi->cpi_model == 8) 1432 cp->cp_ecx = 1433 BITX(cp->cp_ecx, 31, 24) << 16 | 1434 BITX(cp->cp_ecx, 23, 16) << 12 | 1435 BITX(cp->cp_ecx, 15, 8) << 8 | 1436 BITX(cp->cp_ecx, 7, 0); 1437 /* 1438 * model 9 stepping 1 has wrong associativity 1439 */ 1440 if (cpi->cpi_model == 9 && cpi->cpi_step == 1) 1441 cp->cp_ecx |= 8 << 12; 1442 break; 1443 case X86_VENDOR_Intel: 1444 /* 1445 * Extended L2 Cache features function. 1446 * First appeared on Prescott. 1447 */ 1448 default: 1449 break; 1450 } 1451 break; 1452 default: 1453 break; 1454 } 1455 } 1456 1457 pass2_done: 1458 cpi->cpi_pass = 2; 1459 } 1460 1461 static const char * 1462 intel_cpubrand(const struct cpuid_info *cpi) 1463 { 1464 int i; 1465 1466 if ((x86_feature & X86_CPUID) == 0 || 1467 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 1468 return ("i486"); 1469 1470 switch (cpi->cpi_family) { 1471 case 5: 1472 return ("Intel Pentium(r)"); 1473 case 6: 1474 switch (cpi->cpi_model) { 1475 uint_t celeron, xeon; 1476 const struct cpuid_regs *cp; 1477 case 0: 1478 case 1: 1479 case 2: 1480 return ("Intel Pentium(r) Pro"); 1481 case 3: 1482 case 4: 1483 return ("Intel Pentium(r) II"); 1484 case 6: 1485 return ("Intel Celeron(r)"); 1486 case 5: 1487 case 7: 1488 celeron = xeon = 0; 1489 cp = &cpi->cpi_std[2]; /* cache info */ 1490 1491 for (i = 1; i < 4; i++) { 1492 uint_t tmp; 1493 1494 tmp = (cp->cp_eax >> (8 * i)) & 0xff; 1495 if (tmp == 0x40) 1496 celeron++; 1497 if (tmp >= 0x44 && tmp <= 0x45) 1498 xeon++; 1499 } 1500 1501 for (i = 0; i < 2; i++) { 1502 uint_t tmp; 1503 1504 tmp = (cp->cp_ebx >> (8 * i)) & 0xff; 1505 if (tmp == 0x40) 1506 celeron++; 1507 else if (tmp >= 0x44 && tmp <= 0x45) 1508 xeon++; 1509 } 1510 1511 for (i = 0; i < 4; i++) { 1512 uint_t tmp; 1513 1514 tmp = (cp->cp_ecx >> (8 * i)) & 0xff; 1515 if (tmp == 0x40) 1516 celeron++; 1517 else if (tmp >= 0x44 && tmp <= 0x45) 1518 xeon++; 1519 } 1520 1521 for (i = 0; i < 4; i++) { 1522 uint_t tmp; 1523 1524 tmp = (cp->cp_edx >> (8 * i)) & 0xff; 1525 if (tmp == 0x40) 1526 celeron++; 1527 else if (tmp >= 0x44 && tmp <= 0x45) 1528 xeon++; 1529 } 1530 1531 if (celeron) 1532 return ("Intel Celeron(r)"); 1533 if (xeon) 1534 return (cpi->cpi_model == 5 ? 1535 "Intel Pentium(r) II Xeon(tm)" : 1536 "Intel Pentium(r) III Xeon(tm)"); 1537 return (cpi->cpi_model == 5 ? 1538 "Intel Pentium(r) II or Pentium(r) II Xeon(tm)" : 1539 "Intel Pentium(r) III or Pentium(r) III Xeon(tm)"); 1540 default: 1541 break; 1542 } 1543 default: 1544 break; 1545 } 1546 1547 /* BrandID is present if the field is nonzero */ 1548 if (cpi->cpi_brandid != 0) { 1549 static const struct { 1550 uint_t bt_bid; 1551 const char *bt_str; 1552 } brand_tbl[] = { 1553 { 0x1, "Intel(r) Celeron(r)" }, 1554 { 0x2, "Intel(r) Pentium(r) III" }, 1555 { 0x3, "Intel(r) Pentium(r) III Xeon(tm)" }, 1556 { 0x4, "Intel(r) Pentium(r) III" }, 1557 { 0x6, "Mobile Intel(r) Pentium(r) III" }, 1558 { 0x7, "Mobile Intel(r) Celeron(r)" }, 1559 { 0x8, "Intel(r) Pentium(r) 4" }, 1560 { 0x9, "Intel(r) Pentium(r) 4" }, 1561 { 0xa, "Intel(r) Celeron(r)" }, 1562 { 0xb, "Intel(r) Xeon(tm)" }, 1563 { 0xc, "Intel(r) Xeon(tm) MP" }, 1564 { 0xe, "Mobile Intel(r) Pentium(r) 4" }, 1565 { 0xf, "Mobile Intel(r) Celeron(r)" }, 1566 { 0x11, "Mobile Genuine Intel(r)" }, 1567 { 0x12, "Intel(r) Celeron(r) M" }, 1568 { 0x13, "Mobile Intel(r) Celeron(r)" }, 1569 { 0x14, "Intel(r) Celeron(r)" }, 1570 { 0x15, "Mobile Genuine Intel(r)" }, 1571 { 0x16, "Intel(r) Pentium(r) M" }, 1572 { 0x17, "Mobile Intel(r) Celeron(r)" } 1573 }; 1574 uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]); 1575 uint_t sgn; 1576 1577 sgn = (cpi->cpi_family << 8) | 1578 (cpi->cpi_model << 4) | cpi->cpi_step; 1579 1580 for (i = 0; i < btblmax; i++) 1581 if (brand_tbl[i].bt_bid == cpi->cpi_brandid) 1582 break; 1583 if (i < btblmax) { 1584 if (sgn == 0x6b1 && cpi->cpi_brandid == 3) 1585 return ("Intel(r) Celeron(r)"); 1586 if (sgn < 0xf13 && cpi->cpi_brandid == 0xb) 1587 return ("Intel(r) Xeon(tm) MP"); 1588 if (sgn < 0xf13 && cpi->cpi_brandid == 0xe) 1589 return ("Intel(r) Xeon(tm)"); 1590 return (brand_tbl[i].bt_str); 1591 } 1592 } 1593 1594 return (NULL); 1595 } 1596 1597 static const char * 1598 amd_cpubrand(const struct cpuid_info *cpi) 1599 { 1600 if ((x86_feature & X86_CPUID) == 0 || 1601 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 1602 return ("i486 compatible"); 1603 1604 switch (cpi->cpi_family) { 1605 case 5: 1606 switch (cpi->cpi_model) { 1607 case 0: 1608 case 1: 1609 case 2: 1610 case 3: 1611 case 4: 1612 case 5: 1613 return ("AMD-K5(r)"); 1614 case 6: 1615 case 7: 1616 return ("AMD-K6(r)"); 1617 case 8: 1618 return ("AMD-K6(r)-2"); 1619 case 9: 1620 return ("AMD-K6(r)-III"); 1621 default: 1622 return ("AMD (family 5)"); 1623 } 1624 case 6: 1625 switch (cpi->cpi_model) { 1626 case 1: 1627 return ("AMD-K7(tm)"); 1628 case 0: 1629 case 2: 1630 case 4: 1631 return ("AMD Athlon(tm)"); 1632 case 3: 1633 case 7: 1634 return ("AMD Duron(tm)"); 1635 case 6: 1636 case 8: 1637 case 10: 1638 /* 1639 * Use the L2 cache size to distinguish 1640 */ 1641 return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ? 1642 "AMD Athlon(tm)" : "AMD Duron(tm)"); 1643 default: 1644 return ("AMD (family 6)"); 1645 } 1646 default: 1647 break; 1648 } 1649 1650 if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 && 1651 cpi->cpi_brandid != 0) { 1652 switch (BITX(cpi->cpi_brandid, 7, 5)) { 1653 case 3: 1654 return ("AMD Opteron(tm) UP 1xx"); 1655 case 4: 1656 return ("AMD Opteron(tm) DP 2xx"); 1657 case 5: 1658 return ("AMD Opteron(tm) MP 8xx"); 1659 default: 1660 return ("AMD Opteron(tm)"); 1661 } 1662 } 1663 1664 return (NULL); 1665 } 1666 1667 static const char * 1668 cyrix_cpubrand(struct cpuid_info *cpi, uint_t type) 1669 { 1670 if ((x86_feature & X86_CPUID) == 0 || 1671 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5 || 1672 type == X86_TYPE_CYRIX_486) 1673 return ("i486 compatible"); 1674 1675 switch (type) { 1676 case X86_TYPE_CYRIX_6x86: 1677 return ("Cyrix 6x86"); 1678 case X86_TYPE_CYRIX_6x86L: 1679 return ("Cyrix 6x86L"); 1680 case X86_TYPE_CYRIX_6x86MX: 1681 return ("Cyrix 6x86MX"); 1682 case X86_TYPE_CYRIX_GXm: 1683 return ("Cyrix GXm"); 1684 case X86_TYPE_CYRIX_MediaGX: 1685 return ("Cyrix MediaGX"); 1686 case X86_TYPE_CYRIX_MII: 1687 return ("Cyrix M2"); 1688 case X86_TYPE_VIA_CYRIX_III: 1689 return ("VIA Cyrix M3"); 1690 default: 1691 /* 1692 * Have another wild guess .. 1693 */ 1694 if (cpi->cpi_family == 4 && cpi->cpi_model == 9) 1695 return ("Cyrix 5x86"); 1696 else if (cpi->cpi_family == 5) { 1697 switch (cpi->cpi_model) { 1698 case 2: 1699 return ("Cyrix 6x86"); /* Cyrix M1 */ 1700 case 4: 1701 return ("Cyrix MediaGX"); 1702 default: 1703 break; 1704 } 1705 } else if (cpi->cpi_family == 6) { 1706 switch (cpi->cpi_model) { 1707 case 0: 1708 return ("Cyrix 6x86MX"); /* Cyrix M2? */ 1709 case 5: 1710 case 6: 1711 case 7: 1712 case 8: 1713 case 9: 1714 return ("VIA C3"); 1715 default: 1716 break; 1717 } 1718 } 1719 break; 1720 } 1721 return (NULL); 1722 } 1723 1724 /* 1725 * This only gets called in the case that the CPU extended 1726 * feature brand string (0x80000002, 0x80000003, 0x80000004) 1727 * aren't available, or contain null bytes for some reason. 1728 */ 1729 static void 1730 fabricate_brandstr(struct cpuid_info *cpi) 1731 { 1732 const char *brand = NULL; 1733 1734 switch (cpi->cpi_vendor) { 1735 case X86_VENDOR_Intel: 1736 brand = intel_cpubrand(cpi); 1737 break; 1738 case X86_VENDOR_AMD: 1739 brand = amd_cpubrand(cpi); 1740 break; 1741 case X86_VENDOR_Cyrix: 1742 brand = cyrix_cpubrand(cpi, x86_type); 1743 break; 1744 case X86_VENDOR_NexGen: 1745 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 1746 brand = "NexGen Nx586"; 1747 break; 1748 case X86_VENDOR_Centaur: 1749 if (cpi->cpi_family == 5) 1750 switch (cpi->cpi_model) { 1751 case 4: 1752 brand = "Centaur C6"; 1753 break; 1754 case 8: 1755 brand = "Centaur C2"; 1756 break; 1757 case 9: 1758 brand = "Centaur C3"; 1759 break; 1760 default: 1761 break; 1762 } 1763 break; 1764 case X86_VENDOR_Rise: 1765 if (cpi->cpi_family == 5 && 1766 (cpi->cpi_model == 0 || cpi->cpi_model == 2)) 1767 brand = "Rise mP6"; 1768 break; 1769 case X86_VENDOR_SiS: 1770 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 1771 brand = "SiS 55x"; 1772 break; 1773 case X86_VENDOR_TM: 1774 if (cpi->cpi_family == 5 && cpi->cpi_model == 4) 1775 brand = "Transmeta Crusoe TM3x00 or TM5x00"; 1776 break; 1777 case X86_VENDOR_NSC: 1778 case X86_VENDOR_UMC: 1779 default: 1780 break; 1781 } 1782 if (brand) { 1783 (void) strcpy((char *)cpi->cpi_brandstr, brand); 1784 return; 1785 } 1786 1787 /* 1788 * If all else fails ... 1789 */ 1790 (void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr), 1791 "%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family, 1792 cpi->cpi_model, cpi->cpi_step); 1793 } 1794 1795 /* 1796 * This routine is called just after kernel memory allocation 1797 * becomes available on cpu0, and as part of mp_startup() on 1798 * the other cpus. 1799 * 1800 * Fixup the brand string, and collect any information from cpuid 1801 * that requires dynamicically allocated storage to represent. 1802 */ 1803 /*ARGSUSED*/ 1804 void 1805 cpuid_pass3(cpu_t *cpu) 1806 { 1807 int i, max, shft, level, size; 1808 struct cpuid_regs regs; 1809 struct cpuid_regs *cp; 1810 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1811 1812 ASSERT(cpi->cpi_pass == 2); 1813 1814 /* 1815 * Function 4: Deterministic cache parameters 1816 * 1817 * Take this opportunity to detect the number of threads 1818 * sharing the last level cache, and construct a corresponding 1819 * cache id. The respective cpuid_info members are initialized 1820 * to the default case of "no last level cache sharing". 1821 */ 1822 cpi->cpi_ncpu_shr_last_cache = 1; 1823 cpi->cpi_last_lvl_cacheid = cpu->cpu_id; 1824 1825 if (cpi->cpi_maxeax >= 4 && cpi->cpi_vendor == X86_VENDOR_Intel) { 1826 1827 /* 1828 * Find the # of elements (size) returned by fn 4, and along 1829 * the way detect last level cache sharing details. 1830 */ 1831 bzero(®s, sizeof (regs)); 1832 cp = ®s; 1833 for (i = 0, max = 0; i < CPI_FN4_ECX_MAX; i++) { 1834 cp->cp_eax = 4; 1835 cp->cp_ecx = i; 1836 1837 (void) __cpuid_insn(cp); 1838 1839 if (CPI_CACHE_TYPE(cp) == 0) 1840 break; 1841 level = CPI_CACHE_LVL(cp); 1842 if (level > max) { 1843 max = level; 1844 cpi->cpi_ncpu_shr_last_cache = 1845 CPI_NTHR_SHR_CACHE(cp) + 1; 1846 } 1847 } 1848 cpi->cpi_std_4_size = size = i; 1849 1850 /* 1851 * Allocate the cpi_std_4 array. The first element 1852 * references the regs for fn 4, %ecx == 0, which 1853 * cpuid_pass2() stashed in cpi->cpi_std[4]. 1854 */ 1855 if (size > 0) { 1856 cpi->cpi_std_4 = 1857 kmem_alloc(size * sizeof (cp), KM_SLEEP); 1858 cpi->cpi_std_4[0] = &cpi->cpi_std[4]; 1859 1860 /* 1861 * Allocate storage to hold the additional regs 1862 * for function 4, %ecx == 1 .. cpi_std_4_size. 1863 * 1864 * The regs for fn 4, %ecx == 0 has already 1865 * been allocated as indicated above. 1866 */ 1867 for (i = 1; i < size; i++) { 1868 cp = cpi->cpi_std_4[i] = 1869 kmem_zalloc(sizeof (regs), KM_SLEEP); 1870 cp->cp_eax = 4; 1871 cp->cp_ecx = i; 1872 1873 (void) __cpuid_insn(cp); 1874 } 1875 } 1876 /* 1877 * Determine the number of bits needed to represent 1878 * the number of CPUs sharing the last level cache. 1879 * 1880 * Shift off that number of bits from the APIC id to 1881 * derive the cache id. 1882 */ 1883 shft = 0; 1884 for (i = 1; i < cpi->cpi_ncpu_shr_last_cache; i <<= 1) 1885 shft++; 1886 cpi->cpi_last_lvl_cacheid = cpi->cpi_apicid >> shft; 1887 } 1888 1889 /* 1890 * Now fixup the brand string 1891 */ 1892 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) { 1893 fabricate_brandstr(cpi); 1894 } else { 1895 1896 /* 1897 * If we successfully extracted a brand string from the cpuid 1898 * instruction, clean it up by removing leading spaces and 1899 * similar junk. 1900 */ 1901 if (cpi->cpi_brandstr[0]) { 1902 size_t maxlen = sizeof (cpi->cpi_brandstr); 1903 char *src, *dst; 1904 1905 dst = src = (char *)cpi->cpi_brandstr; 1906 src[maxlen - 1] = '\0'; 1907 /* 1908 * strip leading spaces 1909 */ 1910 while (*src == ' ') 1911 src++; 1912 /* 1913 * Remove any 'Genuine' or "Authentic" prefixes 1914 */ 1915 if (strncmp(src, "Genuine ", 8) == 0) 1916 src += 8; 1917 if (strncmp(src, "Authentic ", 10) == 0) 1918 src += 10; 1919 1920 /* 1921 * Now do an in-place copy. 1922 * Map (R) to (r) and (TM) to (tm). 1923 * The era of teletypes is long gone, and there's 1924 * -really- no need to shout. 1925 */ 1926 while (*src != '\0') { 1927 if (src[0] == '(') { 1928 if (strncmp(src + 1, "R)", 2) == 0) { 1929 (void) strncpy(dst, "(r)", 3); 1930 src += 3; 1931 dst += 3; 1932 continue; 1933 } 1934 if (strncmp(src + 1, "TM)", 3) == 0) { 1935 (void) strncpy(dst, "(tm)", 4); 1936 src += 4; 1937 dst += 4; 1938 continue; 1939 } 1940 } 1941 *dst++ = *src++; 1942 } 1943 *dst = '\0'; 1944 1945 /* 1946 * Finally, remove any trailing spaces 1947 */ 1948 while (--dst > cpi->cpi_brandstr) 1949 if (*dst == ' ') 1950 *dst = '\0'; 1951 else 1952 break; 1953 } else 1954 fabricate_brandstr(cpi); 1955 } 1956 cpi->cpi_pass = 3; 1957 } 1958 1959 /* 1960 * This routine is called out of bind_hwcap() much later in the life 1961 * of the kernel (post_startup()). The job of this routine is to resolve 1962 * the hardware feature support and kernel support for those features into 1963 * what we're actually going to tell applications via the aux vector. 1964 */ 1965 uint_t 1966 cpuid_pass4(cpu_t *cpu) 1967 { 1968 struct cpuid_info *cpi; 1969 uint_t hwcap_flags = 0; 1970 1971 if (cpu == NULL) 1972 cpu = CPU; 1973 cpi = cpu->cpu_m.mcpu_cpi; 1974 1975 ASSERT(cpi->cpi_pass == 3); 1976 1977 if (cpi->cpi_maxeax >= 1) { 1978 uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES]; 1979 uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES]; 1980 1981 *edx = CPI_FEATURES_EDX(cpi); 1982 *ecx = CPI_FEATURES_ECX(cpi); 1983 1984 /* 1985 * [these require explicit kernel support] 1986 */ 1987 if ((x86_feature & X86_SEP) == 0) 1988 *edx &= ~CPUID_INTC_EDX_SEP; 1989 1990 if ((x86_feature & X86_SSE) == 0) 1991 *edx &= ~(CPUID_INTC_EDX_FXSR|CPUID_INTC_EDX_SSE); 1992 if ((x86_feature & X86_SSE2) == 0) 1993 *edx &= ~CPUID_INTC_EDX_SSE2; 1994 1995 if ((x86_feature & X86_HTT) == 0) 1996 *edx &= ~CPUID_INTC_EDX_HTT; 1997 1998 if ((x86_feature & X86_SSE3) == 0) 1999 *ecx &= ~CPUID_INTC_ECX_SSE3; 2000 2001 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 2002 if ((x86_feature & X86_SSSE3) == 0) 2003 *ecx &= ~CPUID_INTC_ECX_SSSE3; 2004 if ((x86_feature & X86_SSE4_1) == 0) 2005 *ecx &= ~CPUID_INTC_ECX_SSE4_1; 2006 if ((x86_feature & X86_SSE4_2) == 0) 2007 *ecx &= ~CPUID_INTC_ECX_SSE4_2; 2008 } 2009 2010 /* 2011 * [no explicit support required beyond x87 fp context] 2012 */ 2013 if (!fpu_exists) 2014 *edx &= ~(CPUID_INTC_EDX_FPU | CPUID_INTC_EDX_MMX); 2015 2016 /* 2017 * Now map the supported feature vector to things that we 2018 * think userland will care about. 2019 */ 2020 if (*edx & CPUID_INTC_EDX_SEP) 2021 hwcap_flags |= AV_386_SEP; 2022 if (*edx & CPUID_INTC_EDX_SSE) 2023 hwcap_flags |= AV_386_FXSR | AV_386_SSE; 2024 if (*edx & CPUID_INTC_EDX_SSE2) 2025 hwcap_flags |= AV_386_SSE2; 2026 if (*ecx & CPUID_INTC_ECX_SSE3) 2027 hwcap_flags |= AV_386_SSE3; 2028 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 2029 if (*ecx & CPUID_INTC_ECX_SSSE3) 2030 hwcap_flags |= AV_386_SSSE3; 2031 if (*ecx & CPUID_INTC_ECX_SSE4_1) 2032 hwcap_flags |= AV_386_SSE4_1; 2033 if (*ecx & CPUID_INTC_ECX_SSE4_2) 2034 hwcap_flags |= AV_386_SSE4_2; 2035 } 2036 if (*ecx & CPUID_INTC_ECX_POPCNT) 2037 hwcap_flags |= AV_386_POPCNT; 2038 if (*edx & CPUID_INTC_EDX_FPU) 2039 hwcap_flags |= AV_386_FPU; 2040 if (*edx & CPUID_INTC_EDX_MMX) 2041 hwcap_flags |= AV_386_MMX; 2042 2043 if (*edx & CPUID_INTC_EDX_TSC) 2044 hwcap_flags |= AV_386_TSC; 2045 if (*edx & CPUID_INTC_EDX_CX8) 2046 hwcap_flags |= AV_386_CX8; 2047 if (*edx & CPUID_INTC_EDX_CMOV) 2048 hwcap_flags |= AV_386_CMOV; 2049 if (*ecx & CPUID_INTC_ECX_MON) 2050 hwcap_flags |= AV_386_MON; 2051 if (*ecx & CPUID_INTC_ECX_CX16) 2052 hwcap_flags |= AV_386_CX16; 2053 } 2054 2055 if (x86_feature & X86_HTT) 2056 hwcap_flags |= AV_386_PAUSE; 2057 2058 if (cpi->cpi_xmaxeax < 0x80000001) 2059 goto pass4_done; 2060 2061 switch (cpi->cpi_vendor) { 2062 struct cpuid_regs cp; 2063 uint32_t *edx, *ecx; 2064 2065 case X86_VENDOR_Intel: 2066 /* 2067 * Seems like Intel duplicated what we necessary 2068 * here to make the initial crop of 64-bit OS's work. 2069 * Hopefully, those are the only "extended" bits 2070 * they'll add. 2071 */ 2072 /*FALLTHROUGH*/ 2073 2074 case X86_VENDOR_AMD: 2075 edx = &cpi->cpi_support[AMD_EDX_FEATURES]; 2076 ecx = &cpi->cpi_support[AMD_ECX_FEATURES]; 2077 2078 *edx = CPI_FEATURES_XTD_EDX(cpi); 2079 *ecx = CPI_FEATURES_XTD_ECX(cpi); 2080 2081 /* 2082 * [these features require explicit kernel support] 2083 */ 2084 switch (cpi->cpi_vendor) { 2085 case X86_VENDOR_Intel: 2086 if ((x86_feature & X86_TSCP) == 0) 2087 *edx &= ~CPUID_AMD_EDX_TSCP; 2088 break; 2089 2090 case X86_VENDOR_AMD: 2091 if ((x86_feature & X86_TSCP) == 0) 2092 *edx &= ~CPUID_AMD_EDX_TSCP; 2093 if ((x86_feature & X86_SSE4A) == 0) 2094 *ecx &= ~CPUID_AMD_ECX_SSE4A; 2095 break; 2096 2097 default: 2098 break; 2099 } 2100 2101 /* 2102 * [no explicit support required beyond 2103 * x87 fp context and exception handlers] 2104 */ 2105 if (!fpu_exists) 2106 *edx &= ~(CPUID_AMD_EDX_MMXamd | 2107 CPUID_AMD_EDX_3DNow | CPUID_AMD_EDX_3DNowx); 2108 2109 if ((x86_feature & X86_NX) == 0) 2110 *edx &= ~CPUID_AMD_EDX_NX; 2111 #if !defined(__amd64) 2112 *edx &= ~CPUID_AMD_EDX_LM; 2113 #endif 2114 /* 2115 * Now map the supported feature vector to 2116 * things that we think userland will care about. 2117 */ 2118 #if defined(__amd64) 2119 if (*edx & CPUID_AMD_EDX_SYSC) 2120 hwcap_flags |= AV_386_AMD_SYSC; 2121 #endif 2122 if (*edx & CPUID_AMD_EDX_MMXamd) 2123 hwcap_flags |= AV_386_AMD_MMX; 2124 if (*edx & CPUID_AMD_EDX_3DNow) 2125 hwcap_flags |= AV_386_AMD_3DNow; 2126 if (*edx & CPUID_AMD_EDX_3DNowx) 2127 hwcap_flags |= AV_386_AMD_3DNowx; 2128 2129 switch (cpi->cpi_vendor) { 2130 case X86_VENDOR_AMD: 2131 if (*edx & CPUID_AMD_EDX_TSCP) 2132 hwcap_flags |= AV_386_TSCP; 2133 if (*ecx & CPUID_AMD_ECX_AHF64) 2134 hwcap_flags |= AV_386_AHF; 2135 if (*ecx & CPUID_AMD_ECX_SSE4A) 2136 hwcap_flags |= AV_386_AMD_SSE4A; 2137 if (*ecx & CPUID_AMD_ECX_LZCNT) 2138 hwcap_flags |= AV_386_AMD_LZCNT; 2139 break; 2140 2141 case X86_VENDOR_Intel: 2142 if (*edx & CPUID_AMD_EDX_TSCP) 2143 hwcap_flags |= AV_386_TSCP; 2144 /* 2145 * Aarrgh. 2146 * Intel uses a different bit in the same word. 2147 */ 2148 if (*ecx & CPUID_INTC_ECX_AHF64) 2149 hwcap_flags |= AV_386_AHF; 2150 break; 2151 2152 default: 2153 break; 2154 } 2155 break; 2156 2157 case X86_VENDOR_TM: 2158 cp.cp_eax = 0x80860001; 2159 (void) __cpuid_insn(&cp); 2160 cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx; 2161 break; 2162 2163 default: 2164 break; 2165 } 2166 2167 pass4_done: 2168 cpi->cpi_pass = 4; 2169 return (hwcap_flags); 2170 } 2171 2172 2173 /* 2174 * Simulate the cpuid instruction using the data we previously 2175 * captured about this CPU. We try our best to return the truth 2176 * about the hardware, independently of kernel support. 2177 */ 2178 uint32_t 2179 cpuid_insn(cpu_t *cpu, struct cpuid_regs *cp) 2180 { 2181 struct cpuid_info *cpi; 2182 struct cpuid_regs *xcp; 2183 2184 if (cpu == NULL) 2185 cpu = CPU; 2186 cpi = cpu->cpu_m.mcpu_cpi; 2187 2188 ASSERT(cpuid_checkpass(cpu, 3)); 2189 2190 /* 2191 * CPUID data is cached in two separate places: cpi_std for standard 2192 * CPUID functions, and cpi_extd for extended CPUID functions. 2193 */ 2194 if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD) 2195 xcp = &cpi->cpi_std[cp->cp_eax]; 2196 else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax && 2197 cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD) 2198 xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000]; 2199 else 2200 /* 2201 * The caller is asking for data from an input parameter which 2202 * the kernel has not cached. In this case we go fetch from 2203 * the hardware and return the data directly to the user. 2204 */ 2205 return (__cpuid_insn(cp)); 2206 2207 cp->cp_eax = xcp->cp_eax; 2208 cp->cp_ebx = xcp->cp_ebx; 2209 cp->cp_ecx = xcp->cp_ecx; 2210 cp->cp_edx = xcp->cp_edx; 2211 return (cp->cp_eax); 2212 } 2213 2214 int 2215 cpuid_checkpass(cpu_t *cpu, int pass) 2216 { 2217 return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL && 2218 cpu->cpu_m.mcpu_cpi->cpi_pass >= pass); 2219 } 2220 2221 int 2222 cpuid_getbrandstr(cpu_t *cpu, char *s, size_t n) 2223 { 2224 ASSERT(cpuid_checkpass(cpu, 3)); 2225 2226 return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr)); 2227 } 2228 2229 int 2230 cpuid_is_cmt(cpu_t *cpu) 2231 { 2232 if (cpu == NULL) 2233 cpu = CPU; 2234 2235 ASSERT(cpuid_checkpass(cpu, 1)); 2236 2237 return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0); 2238 } 2239 2240 /* 2241 * AMD and Intel both implement the 64-bit variant of the syscall 2242 * instruction (syscallq), so if there's -any- support for syscall, 2243 * cpuid currently says "yes, we support this". 2244 * 2245 * However, Intel decided to -not- implement the 32-bit variant of the 2246 * syscall instruction, so we provide a predicate to allow our caller 2247 * to test that subtlety here. 2248 * 2249 * XXPV Currently, 32-bit syscall instructions don't work via the hypervisor, 2250 * even in the case where the hardware would in fact support it. 2251 */ 2252 /*ARGSUSED*/ 2253 int 2254 cpuid_syscall32_insn(cpu_t *cpu) 2255 { 2256 ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1)); 2257 2258 #if !defined(__xpv) 2259 if (cpu == NULL) 2260 cpu = CPU; 2261 2262 /*CSTYLED*/ 2263 { 2264 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2265 2266 if (cpi->cpi_vendor == X86_VENDOR_AMD && 2267 cpi->cpi_xmaxeax >= 0x80000001 && 2268 (CPI_FEATURES_XTD_EDX(cpi) & CPUID_AMD_EDX_SYSC)) 2269 return (1); 2270 } 2271 #endif 2272 return (0); 2273 } 2274 2275 int 2276 cpuid_getidstr(cpu_t *cpu, char *s, size_t n) 2277 { 2278 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2279 2280 static const char fmt[] = 2281 "x86 (%s %X family %d model %d step %d clock %d MHz)"; 2282 static const char fmt_ht[] = 2283 "x86 (chipid 0x%x %s %X family %d model %d step %d clock %d MHz)"; 2284 2285 ASSERT(cpuid_checkpass(cpu, 1)); 2286 2287 if (cpuid_is_cmt(cpu)) 2288 return (snprintf(s, n, fmt_ht, cpi->cpi_chipid, 2289 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, 2290 cpi->cpi_family, cpi->cpi_model, 2291 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 2292 return (snprintf(s, n, fmt, 2293 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, 2294 cpi->cpi_family, cpi->cpi_model, 2295 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 2296 } 2297 2298 const char * 2299 cpuid_getvendorstr(cpu_t *cpu) 2300 { 2301 ASSERT(cpuid_checkpass(cpu, 1)); 2302 return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr); 2303 } 2304 2305 uint_t 2306 cpuid_getvendor(cpu_t *cpu) 2307 { 2308 ASSERT(cpuid_checkpass(cpu, 1)); 2309 return (cpu->cpu_m.mcpu_cpi->cpi_vendor); 2310 } 2311 2312 uint_t 2313 cpuid_getfamily(cpu_t *cpu) 2314 { 2315 ASSERT(cpuid_checkpass(cpu, 1)); 2316 return (cpu->cpu_m.mcpu_cpi->cpi_family); 2317 } 2318 2319 uint_t 2320 cpuid_getmodel(cpu_t *cpu) 2321 { 2322 ASSERT(cpuid_checkpass(cpu, 1)); 2323 return (cpu->cpu_m.mcpu_cpi->cpi_model); 2324 } 2325 2326 uint_t 2327 cpuid_get_ncpu_per_chip(cpu_t *cpu) 2328 { 2329 ASSERT(cpuid_checkpass(cpu, 1)); 2330 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip); 2331 } 2332 2333 uint_t 2334 cpuid_get_ncore_per_chip(cpu_t *cpu) 2335 { 2336 ASSERT(cpuid_checkpass(cpu, 1)); 2337 return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip); 2338 } 2339 2340 uint_t 2341 cpuid_get_ncpu_sharing_last_cache(cpu_t *cpu) 2342 { 2343 ASSERT(cpuid_checkpass(cpu, 2)); 2344 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_shr_last_cache); 2345 } 2346 2347 id_t 2348 cpuid_get_last_lvl_cacheid(cpu_t *cpu) 2349 { 2350 ASSERT(cpuid_checkpass(cpu, 2)); 2351 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid); 2352 } 2353 2354 uint_t 2355 cpuid_getstep(cpu_t *cpu) 2356 { 2357 ASSERT(cpuid_checkpass(cpu, 1)); 2358 return (cpu->cpu_m.mcpu_cpi->cpi_step); 2359 } 2360 2361 uint_t 2362 cpuid_getsig(struct cpu *cpu) 2363 { 2364 ASSERT(cpuid_checkpass(cpu, 1)); 2365 return (cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_eax); 2366 } 2367 2368 uint32_t 2369 cpuid_getchiprev(struct cpu *cpu) 2370 { 2371 ASSERT(cpuid_checkpass(cpu, 1)); 2372 return (cpu->cpu_m.mcpu_cpi->cpi_chiprev); 2373 } 2374 2375 const char * 2376 cpuid_getchiprevstr(struct cpu *cpu) 2377 { 2378 ASSERT(cpuid_checkpass(cpu, 1)); 2379 return (cpu->cpu_m.mcpu_cpi->cpi_chiprevstr); 2380 } 2381 2382 uint32_t 2383 cpuid_getsockettype(struct cpu *cpu) 2384 { 2385 ASSERT(cpuid_checkpass(cpu, 1)); 2386 return (cpu->cpu_m.mcpu_cpi->cpi_socket); 2387 } 2388 2389 int 2390 cpuid_get_chipid(cpu_t *cpu) 2391 { 2392 ASSERT(cpuid_checkpass(cpu, 1)); 2393 2394 if (cpuid_is_cmt(cpu)) 2395 return (cpu->cpu_m.mcpu_cpi->cpi_chipid); 2396 return (cpu->cpu_id); 2397 } 2398 2399 id_t 2400 cpuid_get_coreid(cpu_t *cpu) 2401 { 2402 ASSERT(cpuid_checkpass(cpu, 1)); 2403 return (cpu->cpu_m.mcpu_cpi->cpi_coreid); 2404 } 2405 2406 int 2407 cpuid_get_pkgcoreid(cpu_t *cpu) 2408 { 2409 ASSERT(cpuid_checkpass(cpu, 1)); 2410 return (cpu->cpu_m.mcpu_cpi->cpi_pkgcoreid); 2411 } 2412 2413 int 2414 cpuid_get_clogid(cpu_t *cpu) 2415 { 2416 ASSERT(cpuid_checkpass(cpu, 1)); 2417 return (cpu->cpu_m.mcpu_cpi->cpi_clogid); 2418 } 2419 2420 void 2421 cpuid_get_addrsize(cpu_t *cpu, uint_t *pabits, uint_t *vabits) 2422 { 2423 struct cpuid_info *cpi; 2424 2425 if (cpu == NULL) 2426 cpu = CPU; 2427 cpi = cpu->cpu_m.mcpu_cpi; 2428 2429 ASSERT(cpuid_checkpass(cpu, 1)); 2430 2431 if (pabits) 2432 *pabits = cpi->cpi_pabits; 2433 if (vabits) 2434 *vabits = cpi->cpi_vabits; 2435 } 2436 2437 /* 2438 * Returns the number of data TLB entries for a corresponding 2439 * pagesize. If it can't be computed, or isn't known, the 2440 * routine returns zero. If you ask about an architecturally 2441 * impossible pagesize, the routine will panic (so that the 2442 * hat implementor knows that things are inconsistent.) 2443 */ 2444 uint_t 2445 cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize) 2446 { 2447 struct cpuid_info *cpi; 2448 uint_t dtlb_nent = 0; 2449 2450 if (cpu == NULL) 2451 cpu = CPU; 2452 cpi = cpu->cpu_m.mcpu_cpi; 2453 2454 ASSERT(cpuid_checkpass(cpu, 1)); 2455 2456 /* 2457 * Check the L2 TLB info 2458 */ 2459 if (cpi->cpi_xmaxeax >= 0x80000006) { 2460 struct cpuid_regs *cp = &cpi->cpi_extd[6]; 2461 2462 switch (pagesize) { 2463 2464 case 4 * 1024: 2465 /* 2466 * All zero in the top 16 bits of the register 2467 * indicates a unified TLB. Size is in low 16 bits. 2468 */ 2469 if ((cp->cp_ebx & 0xffff0000) == 0) 2470 dtlb_nent = cp->cp_ebx & 0x0000ffff; 2471 else 2472 dtlb_nent = BITX(cp->cp_ebx, 27, 16); 2473 break; 2474 2475 case 2 * 1024 * 1024: 2476 if ((cp->cp_eax & 0xffff0000) == 0) 2477 dtlb_nent = cp->cp_eax & 0x0000ffff; 2478 else 2479 dtlb_nent = BITX(cp->cp_eax, 27, 16); 2480 break; 2481 2482 default: 2483 panic("unknown L2 pagesize"); 2484 /*NOTREACHED*/ 2485 } 2486 } 2487 2488 if (dtlb_nent != 0) 2489 return (dtlb_nent); 2490 2491 /* 2492 * No L2 TLB support for this size, try L1. 2493 */ 2494 if (cpi->cpi_xmaxeax >= 0x80000005) { 2495 struct cpuid_regs *cp = &cpi->cpi_extd[5]; 2496 2497 switch (pagesize) { 2498 case 4 * 1024: 2499 dtlb_nent = BITX(cp->cp_ebx, 23, 16); 2500 break; 2501 case 2 * 1024 * 1024: 2502 dtlb_nent = BITX(cp->cp_eax, 23, 16); 2503 break; 2504 default: 2505 panic("unknown L1 d-TLB pagesize"); 2506 /*NOTREACHED*/ 2507 } 2508 } 2509 2510 return (dtlb_nent); 2511 } 2512 2513 /* 2514 * Return 0 if the erratum is not present or not applicable, positive 2515 * if it is, and negative if the status of the erratum is unknown. 2516 * 2517 * See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm) 2518 * Processors" #25759, Rev 3.57, August 2005 2519 */ 2520 int 2521 cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum) 2522 { 2523 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2524 uint_t eax; 2525 2526 /* 2527 * Bail out if this CPU isn't an AMD CPU, or if it's 2528 * a legacy (32-bit) AMD CPU. 2529 */ 2530 if (cpi->cpi_vendor != X86_VENDOR_AMD || 2531 cpi->cpi_family == 4 || cpi->cpi_family == 5 || 2532 cpi->cpi_family == 6) 2533 2534 return (0); 2535 2536 eax = cpi->cpi_std[1].cp_eax; 2537 2538 #define SH_B0(eax) (eax == 0xf40 || eax == 0xf50) 2539 #define SH_B3(eax) (eax == 0xf51) 2540 #define B(eax) (SH_B0(eax) || SH_B3(eax)) 2541 2542 #define SH_C0(eax) (eax == 0xf48 || eax == 0xf58) 2543 2544 #define SH_CG(eax) (eax == 0xf4a || eax == 0xf5a || eax == 0xf7a) 2545 #define DH_CG(eax) (eax == 0xfc0 || eax == 0xfe0 || eax == 0xff0) 2546 #define CH_CG(eax) (eax == 0xf82 || eax == 0xfb2) 2547 #define CG(eax) (SH_CG(eax) || DH_CG(eax) || CH_CG(eax)) 2548 2549 #define SH_D0(eax) (eax == 0x10f40 || eax == 0x10f50 || eax == 0x10f70) 2550 #define DH_D0(eax) (eax == 0x10fc0 || eax == 0x10ff0) 2551 #define CH_D0(eax) (eax == 0x10f80 || eax == 0x10fb0) 2552 #define D0(eax) (SH_D0(eax) || DH_D0(eax) || CH_D0(eax)) 2553 2554 #define SH_E0(eax) (eax == 0x20f50 || eax == 0x20f40 || eax == 0x20f70) 2555 #define JH_E1(eax) (eax == 0x20f10) /* JH8_E0 had 0x20f30 */ 2556 #define DH_E3(eax) (eax == 0x20fc0 || eax == 0x20ff0) 2557 #define SH_E4(eax) (eax == 0x20f51 || eax == 0x20f71) 2558 #define BH_E4(eax) (eax == 0x20fb1) 2559 #define SH_E5(eax) (eax == 0x20f42) 2560 #define DH_E6(eax) (eax == 0x20ff2 || eax == 0x20fc2) 2561 #define JH_E6(eax) (eax == 0x20f12 || eax == 0x20f32) 2562 #define EX(eax) (SH_E0(eax) || JH_E1(eax) || DH_E3(eax) || \ 2563 SH_E4(eax) || BH_E4(eax) || SH_E5(eax) || \ 2564 DH_E6(eax) || JH_E6(eax)) 2565 2566 #define DR_AX(eax) (eax == 0x100f00 || eax == 0x100f01 || eax == 0x100f02) 2567 #define DR_B0(eax) (eax == 0x100f20) 2568 #define DR_B1(eax) (eax == 0x100f21) 2569 #define DR_BA(eax) (eax == 0x100f2a) 2570 #define DR_B2(eax) (eax == 0x100f22) 2571 #define DR_B3(eax) (eax == 0x100f23) 2572 #define RB_C0(eax) (eax == 0x100f40) 2573 2574 switch (erratum) { 2575 case 1: 2576 return (cpi->cpi_family < 0x10); 2577 case 51: /* what does the asterisk mean? */ 2578 return (B(eax) || SH_C0(eax) || CG(eax)); 2579 case 52: 2580 return (B(eax)); 2581 case 57: 2582 return (cpi->cpi_family <= 0x11); 2583 case 58: 2584 return (B(eax)); 2585 case 60: 2586 return (cpi->cpi_family <= 0x11); 2587 case 61: 2588 case 62: 2589 case 63: 2590 case 64: 2591 case 65: 2592 case 66: 2593 case 68: 2594 case 69: 2595 case 70: 2596 case 71: 2597 return (B(eax)); 2598 case 72: 2599 return (SH_B0(eax)); 2600 case 74: 2601 return (B(eax)); 2602 case 75: 2603 return (cpi->cpi_family < 0x10); 2604 case 76: 2605 return (B(eax)); 2606 case 77: 2607 return (cpi->cpi_family <= 0x11); 2608 case 78: 2609 return (B(eax) || SH_C0(eax)); 2610 case 79: 2611 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2612 case 80: 2613 case 81: 2614 case 82: 2615 return (B(eax)); 2616 case 83: 2617 return (B(eax) || SH_C0(eax) || CG(eax)); 2618 case 85: 2619 return (cpi->cpi_family < 0x10); 2620 case 86: 2621 return (SH_C0(eax) || CG(eax)); 2622 case 88: 2623 #if !defined(__amd64) 2624 return (0); 2625 #else 2626 return (B(eax) || SH_C0(eax)); 2627 #endif 2628 case 89: 2629 return (cpi->cpi_family < 0x10); 2630 case 90: 2631 return (B(eax) || SH_C0(eax) || CG(eax)); 2632 case 91: 2633 case 92: 2634 return (B(eax) || SH_C0(eax)); 2635 case 93: 2636 return (SH_C0(eax)); 2637 case 94: 2638 return (B(eax) || SH_C0(eax) || CG(eax)); 2639 case 95: 2640 #if !defined(__amd64) 2641 return (0); 2642 #else 2643 return (B(eax) || SH_C0(eax)); 2644 #endif 2645 case 96: 2646 return (B(eax) || SH_C0(eax) || CG(eax)); 2647 case 97: 2648 case 98: 2649 return (SH_C0(eax) || CG(eax)); 2650 case 99: 2651 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2652 case 100: 2653 return (B(eax) || SH_C0(eax)); 2654 case 101: 2655 case 103: 2656 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2657 case 104: 2658 return (SH_C0(eax) || CG(eax) || D0(eax)); 2659 case 105: 2660 case 106: 2661 case 107: 2662 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2663 case 108: 2664 return (DH_CG(eax)); 2665 case 109: 2666 return (SH_C0(eax) || CG(eax) || D0(eax)); 2667 case 110: 2668 return (D0(eax) || EX(eax)); 2669 case 111: 2670 return (CG(eax)); 2671 case 112: 2672 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2673 case 113: 2674 return (eax == 0x20fc0); 2675 case 114: 2676 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 2677 case 115: 2678 return (SH_E0(eax) || JH_E1(eax)); 2679 case 116: 2680 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 2681 case 117: 2682 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2683 case 118: 2684 return (SH_E0(eax) || JH_E1(eax) || SH_E4(eax) || BH_E4(eax) || 2685 JH_E6(eax)); 2686 case 121: 2687 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2688 case 122: 2689 return (cpi->cpi_family < 0x10 || cpi->cpi_family == 0x11); 2690 case 123: 2691 return (JH_E1(eax) || BH_E4(eax) || JH_E6(eax)); 2692 case 131: 2693 return (cpi->cpi_family < 0x10); 2694 case 6336786: 2695 /* 2696 * Test for AdvPowerMgmtInfo.TscPStateInvariant 2697 * if this is a K8 family or newer processor 2698 */ 2699 if (CPI_FAMILY(cpi) == 0xf) { 2700 struct cpuid_regs regs; 2701 regs.cp_eax = 0x80000007; 2702 (void) __cpuid_insn(®s); 2703 return (!(regs.cp_edx & 0x100)); 2704 } 2705 return (0); 2706 case 6323525: 2707 return (((((eax >> 12) & 0xff00) + (eax & 0xf00)) | 2708 (((eax >> 4) & 0xf) | ((eax >> 12) & 0xf0))) < 0xf40); 2709 2710 case 6671130: 2711 /* 2712 * check for processors (pre-Shanghai) that do not provide 2713 * optimal management of 1gb ptes in its tlb. 2714 */ 2715 return (cpi->cpi_family == 0x10 && cpi->cpi_model < 4); 2716 2717 case 298: 2718 return (DR_AX(eax) || DR_B0(eax) || DR_B1(eax) || DR_BA(eax) || 2719 DR_B2(eax) || RB_C0(eax)); 2720 2721 default: 2722 return (-1); 2723 2724 } 2725 } 2726 2727 /* 2728 * Determine if specified erratum is present via OSVW (OS Visible Workaround). 2729 * Return 1 if erratum is present, 0 if not present and -1 if indeterminate. 2730 */ 2731 int 2732 osvw_opteron_erratum(cpu_t *cpu, uint_t erratum) 2733 { 2734 struct cpuid_info *cpi; 2735 uint_t osvwid; 2736 static int osvwfeature = -1; 2737 uint64_t osvwlength; 2738 2739 2740 cpi = cpu->cpu_m.mcpu_cpi; 2741 2742 /* confirm OSVW supported */ 2743 if (osvwfeature == -1) { 2744 osvwfeature = cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW; 2745 } else { 2746 /* assert that osvw feature setting is consistent on all cpus */ 2747 ASSERT(osvwfeature == 2748 (cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW)); 2749 } 2750 if (!osvwfeature) 2751 return (-1); 2752 2753 osvwlength = rdmsr(MSR_AMD_OSVW_ID_LEN) & OSVW_ID_LEN_MASK; 2754 2755 switch (erratum) { 2756 case 298: /* osvwid is 0 */ 2757 osvwid = 0; 2758 if (osvwlength <= (uint64_t)osvwid) { 2759 /* osvwid 0 is unknown */ 2760 return (-1); 2761 } 2762 2763 /* 2764 * Check the OSVW STATUS MSR to determine the state 2765 * of the erratum where: 2766 * 0 - fixed by HW 2767 * 1 - BIOS has applied the workaround when BIOS 2768 * workaround is available. (Or for other errata, 2769 * OS workaround is required.) 2770 * For a value of 1, caller will confirm that the 2771 * erratum 298 workaround has indeed been applied by BIOS. 2772 * 2773 * A 1 may be set in cpus that have a HW fix 2774 * in a mixed cpu system. Regarding erratum 298: 2775 * In a multiprocessor platform, the workaround above 2776 * should be applied to all processors regardless of 2777 * silicon revision when an affected processor is 2778 * present. 2779 */ 2780 2781 return (rdmsr(MSR_AMD_OSVW_STATUS + 2782 (osvwid / OSVW_ID_CNT_PER_MSR)) & 2783 (1ULL << (osvwid % OSVW_ID_CNT_PER_MSR))); 2784 2785 default: 2786 return (-1); 2787 } 2788 } 2789 2790 static const char assoc_str[] = "associativity"; 2791 static const char line_str[] = "line-size"; 2792 static const char size_str[] = "size"; 2793 2794 static void 2795 add_cache_prop(dev_info_t *devi, const char *label, const char *type, 2796 uint32_t val) 2797 { 2798 char buf[128]; 2799 2800 /* 2801 * ndi_prop_update_int() is used because it is desirable for 2802 * DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set. 2803 */ 2804 if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf)) 2805 (void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val); 2806 } 2807 2808 /* 2809 * Intel-style cache/tlb description 2810 * 2811 * Standard cpuid level 2 gives a randomly ordered 2812 * selection of tags that index into a table that describes 2813 * cache and tlb properties. 2814 */ 2815 2816 static const char l1_icache_str[] = "l1-icache"; 2817 static const char l1_dcache_str[] = "l1-dcache"; 2818 static const char l2_cache_str[] = "l2-cache"; 2819 static const char l3_cache_str[] = "l3-cache"; 2820 static const char itlb4k_str[] = "itlb-4K"; 2821 static const char dtlb4k_str[] = "dtlb-4K"; 2822 static const char itlb2M_str[] = "itlb-2M"; 2823 static const char itlb4M_str[] = "itlb-4M"; 2824 static const char dtlb4M_str[] = "dtlb-4M"; 2825 static const char dtlb24_str[] = "dtlb0-2M-4M"; 2826 static const char itlb424_str[] = "itlb-4K-2M-4M"; 2827 static const char itlb24_str[] = "itlb-2M-4M"; 2828 static const char dtlb44_str[] = "dtlb-4K-4M"; 2829 static const char sl1_dcache_str[] = "sectored-l1-dcache"; 2830 static const char sl2_cache_str[] = "sectored-l2-cache"; 2831 static const char itrace_str[] = "itrace-cache"; 2832 static const char sl3_cache_str[] = "sectored-l3-cache"; 2833 static const char sh_l2_tlb4k_str[] = "shared-l2-tlb-4k"; 2834 2835 static const struct cachetab { 2836 uint8_t ct_code; 2837 uint8_t ct_assoc; 2838 uint16_t ct_line_size; 2839 size_t ct_size; 2840 const char *ct_label; 2841 } intel_ctab[] = { 2842 /* 2843 * maintain descending order! 2844 * 2845 * Codes ignored - Reason 2846 * ---------------------- 2847 * 40H - intel_cpuid_4_cache_info() disambiguates l2/l3 cache 2848 * f0H/f1H - Currently we do not interpret prefetch size by design 2849 */ 2850 { 0xe4, 16, 64, 8*1024*1024, l3_cache_str}, 2851 { 0xe3, 16, 64, 4*1024*1024, l3_cache_str}, 2852 { 0xe2, 16, 64, 2*1024*1024, l3_cache_str}, 2853 { 0xde, 12, 64, 6*1024*1024, l3_cache_str}, 2854 { 0xdd, 12, 64, 3*1024*1024, l3_cache_str}, 2855 { 0xdc, 12, 64, ((1*1024*1024)+(512*1024)), l3_cache_str}, 2856 { 0xd8, 8, 64, 4*1024*1024, l3_cache_str}, 2857 { 0xd7, 8, 64, 2*1024*1024, l3_cache_str}, 2858 { 0xd6, 8, 64, 1*1024*1024, l3_cache_str}, 2859 { 0xd2, 4, 64, 2*1024*1024, l3_cache_str}, 2860 { 0xd1, 4, 64, 1*1024*1024, l3_cache_str}, 2861 { 0xd0, 4, 64, 512*1024, l3_cache_str}, 2862 { 0xca, 4, 0, 512, sh_l2_tlb4k_str}, 2863 { 0xc0, 4, 0, 8, dtlb44_str }, 2864 { 0xba, 4, 0, 64, dtlb4k_str }, 2865 { 0xb4, 4, 0, 256, dtlb4k_str }, 2866 { 0xb3, 4, 0, 128, dtlb4k_str }, 2867 { 0xb2, 4, 0, 64, itlb4k_str }, 2868 { 0xb0, 4, 0, 128, itlb4k_str }, 2869 { 0x87, 8, 64, 1024*1024, l2_cache_str}, 2870 { 0x86, 4, 64, 512*1024, l2_cache_str}, 2871 { 0x85, 8, 32, 2*1024*1024, l2_cache_str}, 2872 { 0x84, 8, 32, 1024*1024, l2_cache_str}, 2873 { 0x83, 8, 32, 512*1024, l2_cache_str}, 2874 { 0x82, 8, 32, 256*1024, l2_cache_str}, 2875 { 0x80, 8, 64, 512*1024, l2_cache_str}, 2876 { 0x7f, 2, 64, 512*1024, l2_cache_str}, 2877 { 0x7d, 8, 64, 2*1024*1024, sl2_cache_str}, 2878 { 0x7c, 8, 64, 1024*1024, sl2_cache_str}, 2879 { 0x7b, 8, 64, 512*1024, sl2_cache_str}, 2880 { 0x7a, 8, 64, 256*1024, sl2_cache_str}, 2881 { 0x79, 8, 64, 128*1024, sl2_cache_str}, 2882 { 0x78, 8, 64, 1024*1024, l2_cache_str}, 2883 { 0x73, 8, 0, 64*1024, itrace_str}, 2884 { 0x72, 8, 0, 32*1024, itrace_str}, 2885 { 0x71, 8, 0, 16*1024, itrace_str}, 2886 { 0x70, 8, 0, 12*1024, itrace_str}, 2887 { 0x68, 4, 64, 32*1024, sl1_dcache_str}, 2888 { 0x67, 4, 64, 16*1024, sl1_dcache_str}, 2889 { 0x66, 4, 64, 8*1024, sl1_dcache_str}, 2890 { 0x60, 8, 64, 16*1024, sl1_dcache_str}, 2891 { 0x5d, 0, 0, 256, dtlb44_str}, 2892 { 0x5c, 0, 0, 128, dtlb44_str}, 2893 { 0x5b, 0, 0, 64, dtlb44_str}, 2894 { 0x5a, 4, 0, 32, dtlb24_str}, 2895 { 0x59, 0, 0, 16, dtlb4k_str}, 2896 { 0x57, 4, 0, 16, dtlb4k_str}, 2897 { 0x56, 4, 0, 16, dtlb4M_str}, 2898 { 0x55, 0, 0, 7, itlb24_str}, 2899 { 0x52, 0, 0, 256, itlb424_str}, 2900 { 0x51, 0, 0, 128, itlb424_str}, 2901 { 0x50, 0, 0, 64, itlb424_str}, 2902 { 0x4f, 0, 0, 32, itlb4k_str}, 2903 { 0x4e, 24, 64, 6*1024*1024, l2_cache_str}, 2904 { 0x4d, 16, 64, 16*1024*1024, l3_cache_str}, 2905 { 0x4c, 12, 64, 12*1024*1024, l3_cache_str}, 2906 { 0x4b, 16, 64, 8*1024*1024, l3_cache_str}, 2907 { 0x4a, 12, 64, 6*1024*1024, l3_cache_str}, 2908 { 0x49, 16, 64, 4*1024*1024, l3_cache_str}, 2909 { 0x48, 12, 64, 3*1024*1024, l2_cache_str}, 2910 { 0x47, 8, 64, 8*1024*1024, l3_cache_str}, 2911 { 0x46, 4, 64, 4*1024*1024, l3_cache_str}, 2912 { 0x45, 4, 32, 2*1024*1024, l2_cache_str}, 2913 { 0x44, 4, 32, 1024*1024, l2_cache_str}, 2914 { 0x43, 4, 32, 512*1024, l2_cache_str}, 2915 { 0x42, 4, 32, 256*1024, l2_cache_str}, 2916 { 0x41, 4, 32, 128*1024, l2_cache_str}, 2917 { 0x3e, 4, 64, 512*1024, sl2_cache_str}, 2918 { 0x3d, 6, 64, 384*1024, sl2_cache_str}, 2919 { 0x3c, 4, 64, 256*1024, sl2_cache_str}, 2920 { 0x3b, 2, 64, 128*1024, sl2_cache_str}, 2921 { 0x3a, 6, 64, 192*1024, sl2_cache_str}, 2922 { 0x39, 4, 64, 128*1024, sl2_cache_str}, 2923 { 0x30, 8, 64, 32*1024, l1_icache_str}, 2924 { 0x2c, 8, 64, 32*1024, l1_dcache_str}, 2925 { 0x29, 8, 64, 4096*1024, sl3_cache_str}, 2926 { 0x25, 8, 64, 2048*1024, sl3_cache_str}, 2927 { 0x23, 8, 64, 1024*1024, sl3_cache_str}, 2928 { 0x22, 4, 64, 512*1024, sl3_cache_str}, 2929 { 0x0e, 6, 64, 24*1024, l1_dcache_str}, 2930 { 0x0d, 4, 32, 16*1024, l1_dcache_str}, 2931 { 0x0c, 4, 32, 16*1024, l1_dcache_str}, 2932 { 0x0b, 4, 0, 4, itlb4M_str}, 2933 { 0x0a, 2, 32, 8*1024, l1_dcache_str}, 2934 { 0x08, 4, 32, 16*1024, l1_icache_str}, 2935 { 0x06, 4, 32, 8*1024, l1_icache_str}, 2936 { 0x05, 4, 0, 32, dtlb4M_str}, 2937 { 0x04, 4, 0, 8, dtlb4M_str}, 2938 { 0x03, 4, 0, 64, dtlb4k_str}, 2939 { 0x02, 4, 0, 2, itlb4M_str}, 2940 { 0x01, 4, 0, 32, itlb4k_str}, 2941 { 0 } 2942 }; 2943 2944 static const struct cachetab cyrix_ctab[] = { 2945 { 0x70, 4, 0, 32, "tlb-4K" }, 2946 { 0x80, 4, 16, 16*1024, "l1-cache" }, 2947 { 0 } 2948 }; 2949 2950 /* 2951 * Search a cache table for a matching entry 2952 */ 2953 static const struct cachetab * 2954 find_cacheent(const struct cachetab *ct, uint_t code) 2955 { 2956 if (code != 0) { 2957 for (; ct->ct_code != 0; ct++) 2958 if (ct->ct_code <= code) 2959 break; 2960 if (ct->ct_code == code) 2961 return (ct); 2962 } 2963 return (NULL); 2964 } 2965 2966 /* 2967 * Populate cachetab entry with L2 or L3 cache-information using 2968 * cpuid function 4. This function is called from intel_walk_cacheinfo() 2969 * when descriptor 0x49 is encountered. It returns 0 if no such cache 2970 * information is found. 2971 */ 2972 static int 2973 intel_cpuid_4_cache_info(struct cachetab *ct, struct cpuid_info *cpi) 2974 { 2975 uint32_t level, i; 2976 int ret = 0; 2977 2978 for (i = 0; i < cpi->cpi_std_4_size; i++) { 2979 level = CPI_CACHE_LVL(cpi->cpi_std_4[i]); 2980 2981 if (level == 2 || level == 3) { 2982 ct->ct_assoc = CPI_CACHE_WAYS(cpi->cpi_std_4[i]) + 1; 2983 ct->ct_line_size = 2984 CPI_CACHE_COH_LN_SZ(cpi->cpi_std_4[i]) + 1; 2985 ct->ct_size = ct->ct_assoc * 2986 (CPI_CACHE_PARTS(cpi->cpi_std_4[i]) + 1) * 2987 ct->ct_line_size * 2988 (cpi->cpi_std_4[i]->cp_ecx + 1); 2989 2990 if (level == 2) { 2991 ct->ct_label = l2_cache_str; 2992 } else if (level == 3) { 2993 ct->ct_label = l3_cache_str; 2994 } 2995 ret = 1; 2996 } 2997 } 2998 2999 return (ret); 3000 } 3001 3002 /* 3003 * Walk the cacheinfo descriptor, applying 'func' to every valid element 3004 * The walk is terminated if the walker returns non-zero. 3005 */ 3006 static void 3007 intel_walk_cacheinfo(struct cpuid_info *cpi, 3008 void *arg, int (*func)(void *, const struct cachetab *)) 3009 { 3010 const struct cachetab *ct; 3011 struct cachetab des_49_ct, des_b1_ct; 3012 uint8_t *dp; 3013 int i; 3014 3015 if ((dp = cpi->cpi_cacheinfo) == NULL) 3016 return; 3017 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { 3018 /* 3019 * For overloaded descriptor 0x49 we use cpuid function 4 3020 * if supported by the current processor, to create 3021 * cache information. 3022 * For overloaded descriptor 0xb1 we use X86_PAE flag 3023 * to disambiguate the cache information. 3024 */ 3025 if (*dp == 0x49 && cpi->cpi_maxeax >= 0x4 && 3026 intel_cpuid_4_cache_info(&des_49_ct, cpi) == 1) { 3027 ct = &des_49_ct; 3028 } else if (*dp == 0xb1) { 3029 des_b1_ct.ct_code = 0xb1; 3030 des_b1_ct.ct_assoc = 4; 3031 des_b1_ct.ct_line_size = 0; 3032 if (x86_feature & X86_PAE) { 3033 des_b1_ct.ct_size = 8; 3034 des_b1_ct.ct_label = itlb2M_str; 3035 } else { 3036 des_b1_ct.ct_size = 4; 3037 des_b1_ct.ct_label = itlb4M_str; 3038 } 3039 ct = &des_b1_ct; 3040 } else { 3041 if ((ct = find_cacheent(intel_ctab, *dp)) == NULL) { 3042 continue; 3043 } 3044 } 3045 3046 if (func(arg, ct) != 0) { 3047 break; 3048 } 3049 } 3050 } 3051 3052 /* 3053 * (Like the Intel one, except for Cyrix CPUs) 3054 */ 3055 static void 3056 cyrix_walk_cacheinfo(struct cpuid_info *cpi, 3057 void *arg, int (*func)(void *, const struct cachetab *)) 3058 { 3059 const struct cachetab *ct; 3060 uint8_t *dp; 3061 int i; 3062 3063 if ((dp = cpi->cpi_cacheinfo) == NULL) 3064 return; 3065 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { 3066 /* 3067 * Search Cyrix-specific descriptor table first .. 3068 */ 3069 if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) { 3070 if (func(arg, ct) != 0) 3071 break; 3072 continue; 3073 } 3074 /* 3075 * .. else fall back to the Intel one 3076 */ 3077 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { 3078 if (func(arg, ct) != 0) 3079 break; 3080 continue; 3081 } 3082 } 3083 } 3084 3085 /* 3086 * A cacheinfo walker that adds associativity, line-size, and size properties 3087 * to the devinfo node it is passed as an argument. 3088 */ 3089 static int 3090 add_cacheent_props(void *arg, const struct cachetab *ct) 3091 { 3092 dev_info_t *devi = arg; 3093 3094 add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc); 3095 if (ct->ct_line_size != 0) 3096 add_cache_prop(devi, ct->ct_label, line_str, 3097 ct->ct_line_size); 3098 add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size); 3099 return (0); 3100 } 3101 3102 3103 static const char fully_assoc[] = "fully-associative?"; 3104 3105 /* 3106 * AMD style cache/tlb description 3107 * 3108 * Extended functions 5 and 6 directly describe properties of 3109 * tlbs and various cache levels. 3110 */ 3111 static void 3112 add_amd_assoc(dev_info_t *devi, const char *label, uint_t assoc) 3113 { 3114 switch (assoc) { 3115 case 0: /* reserved; ignore */ 3116 break; 3117 default: 3118 add_cache_prop(devi, label, assoc_str, assoc); 3119 break; 3120 case 0xff: 3121 add_cache_prop(devi, label, fully_assoc, 1); 3122 break; 3123 } 3124 } 3125 3126 static void 3127 add_amd_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 3128 { 3129 if (size == 0) 3130 return; 3131 add_cache_prop(devi, label, size_str, size); 3132 add_amd_assoc(devi, label, assoc); 3133 } 3134 3135 static void 3136 add_amd_cache(dev_info_t *devi, const char *label, 3137 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 3138 { 3139 if (size == 0 || line_size == 0) 3140 return; 3141 add_amd_assoc(devi, label, assoc); 3142 /* 3143 * Most AMD parts have a sectored cache. Multiple cache lines are 3144 * associated with each tag. A sector consists of all cache lines 3145 * associated with a tag. For example, the AMD K6-III has a sector 3146 * size of 2 cache lines per tag. 3147 */ 3148 if (lines_per_tag != 0) 3149 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 3150 add_cache_prop(devi, label, line_str, line_size); 3151 add_cache_prop(devi, label, size_str, size * 1024); 3152 } 3153 3154 static void 3155 add_amd_l2_assoc(dev_info_t *devi, const char *label, uint_t assoc) 3156 { 3157 switch (assoc) { 3158 case 0: /* off */ 3159 break; 3160 case 1: 3161 case 2: 3162 case 4: 3163 add_cache_prop(devi, label, assoc_str, assoc); 3164 break; 3165 case 6: 3166 add_cache_prop(devi, label, assoc_str, 8); 3167 break; 3168 case 8: 3169 add_cache_prop(devi, label, assoc_str, 16); 3170 break; 3171 case 0xf: 3172 add_cache_prop(devi, label, fully_assoc, 1); 3173 break; 3174 default: /* reserved; ignore */ 3175 break; 3176 } 3177 } 3178 3179 static void 3180 add_amd_l2_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 3181 { 3182 if (size == 0 || assoc == 0) 3183 return; 3184 add_amd_l2_assoc(devi, label, assoc); 3185 add_cache_prop(devi, label, size_str, size); 3186 } 3187 3188 static void 3189 add_amd_l2_cache(dev_info_t *devi, const char *label, 3190 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 3191 { 3192 if (size == 0 || assoc == 0 || line_size == 0) 3193 return; 3194 add_amd_l2_assoc(devi, label, assoc); 3195 if (lines_per_tag != 0) 3196 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 3197 add_cache_prop(devi, label, line_str, line_size); 3198 add_cache_prop(devi, label, size_str, size * 1024); 3199 } 3200 3201 static void 3202 amd_cache_info(struct cpuid_info *cpi, dev_info_t *devi) 3203 { 3204 struct cpuid_regs *cp; 3205 3206 if (cpi->cpi_xmaxeax < 0x80000005) 3207 return; 3208 cp = &cpi->cpi_extd[5]; 3209 3210 /* 3211 * 4M/2M L1 TLB configuration 3212 * 3213 * We report the size for 2M pages because AMD uses two 3214 * TLB entries for one 4M page. 3215 */ 3216 add_amd_tlb(devi, "dtlb-2M", 3217 BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16)); 3218 add_amd_tlb(devi, "itlb-2M", 3219 BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0)); 3220 3221 /* 3222 * 4K L1 TLB configuration 3223 */ 3224 3225 switch (cpi->cpi_vendor) { 3226 uint_t nentries; 3227 case X86_VENDOR_TM: 3228 if (cpi->cpi_family >= 5) { 3229 /* 3230 * Crusoe processors have 256 TLB entries, but 3231 * cpuid data format constrains them to only 3232 * reporting 255 of them. 3233 */ 3234 if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255) 3235 nentries = 256; 3236 /* 3237 * Crusoe processors also have a unified TLB 3238 */ 3239 add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24), 3240 nentries); 3241 break; 3242 } 3243 /*FALLTHROUGH*/ 3244 default: 3245 add_amd_tlb(devi, itlb4k_str, 3246 BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16)); 3247 add_amd_tlb(devi, dtlb4k_str, 3248 BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0)); 3249 break; 3250 } 3251 3252 /* 3253 * data L1 cache configuration 3254 */ 3255 3256 add_amd_cache(devi, l1_dcache_str, 3257 BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16), 3258 BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0)); 3259 3260 /* 3261 * code L1 cache configuration 3262 */ 3263 3264 add_amd_cache(devi, l1_icache_str, 3265 BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16), 3266 BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0)); 3267 3268 if (cpi->cpi_xmaxeax < 0x80000006) 3269 return; 3270 cp = &cpi->cpi_extd[6]; 3271 3272 /* Check for a unified L2 TLB for large pages */ 3273 3274 if (BITX(cp->cp_eax, 31, 16) == 0) 3275 add_amd_l2_tlb(devi, "l2-tlb-2M", 3276 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3277 else { 3278 add_amd_l2_tlb(devi, "l2-dtlb-2M", 3279 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 3280 add_amd_l2_tlb(devi, "l2-itlb-2M", 3281 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3282 } 3283 3284 /* Check for a unified L2 TLB for 4K pages */ 3285 3286 if (BITX(cp->cp_ebx, 31, 16) == 0) { 3287 add_amd_l2_tlb(devi, "l2-tlb-4K", 3288 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3289 } else { 3290 add_amd_l2_tlb(devi, "l2-dtlb-4K", 3291 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 3292 add_amd_l2_tlb(devi, "l2-itlb-4K", 3293 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3294 } 3295 3296 add_amd_l2_cache(devi, l2_cache_str, 3297 BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12), 3298 BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0)); 3299 } 3300 3301 /* 3302 * There are two basic ways that the x86 world describes it cache 3303 * and tlb architecture - Intel's way and AMD's way. 3304 * 3305 * Return which flavor of cache architecture we should use 3306 */ 3307 static int 3308 x86_which_cacheinfo(struct cpuid_info *cpi) 3309 { 3310 switch (cpi->cpi_vendor) { 3311 case X86_VENDOR_Intel: 3312 if (cpi->cpi_maxeax >= 2) 3313 return (X86_VENDOR_Intel); 3314 break; 3315 case X86_VENDOR_AMD: 3316 /* 3317 * The K5 model 1 was the first part from AMD that reported 3318 * cache sizes via extended cpuid functions. 3319 */ 3320 if (cpi->cpi_family > 5 || 3321 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 3322 return (X86_VENDOR_AMD); 3323 break; 3324 case X86_VENDOR_TM: 3325 if (cpi->cpi_family >= 5) 3326 return (X86_VENDOR_AMD); 3327 /*FALLTHROUGH*/ 3328 default: 3329 /* 3330 * If they have extended CPU data for 0x80000005 3331 * then we assume they have AMD-format cache 3332 * information. 3333 * 3334 * If not, and the vendor happens to be Cyrix, 3335 * then try our-Cyrix specific handler. 3336 * 3337 * If we're not Cyrix, then assume we're using Intel's 3338 * table-driven format instead. 3339 */ 3340 if (cpi->cpi_xmaxeax >= 0x80000005) 3341 return (X86_VENDOR_AMD); 3342 else if (cpi->cpi_vendor == X86_VENDOR_Cyrix) 3343 return (X86_VENDOR_Cyrix); 3344 else if (cpi->cpi_maxeax >= 2) 3345 return (X86_VENDOR_Intel); 3346 break; 3347 } 3348 return (-1); 3349 } 3350 3351 /* 3352 * create a node for the given cpu under the prom root node. 3353 * Also, create a cpu node in the device tree. 3354 */ 3355 static dev_info_t *cpu_nex_devi = NULL; 3356 static kmutex_t cpu_node_lock; 3357 3358 /* 3359 * Called from post_startup() and mp_startup() 3360 */ 3361 void 3362 add_cpunode2devtree(processorid_t cpu_id, struct cpuid_info *cpi) 3363 { 3364 dev_info_t *cpu_devi; 3365 int create; 3366 3367 mutex_enter(&cpu_node_lock); 3368 3369 /* 3370 * create a nexus node for all cpus identified as 'cpu_id' under 3371 * the root node. 3372 */ 3373 if (cpu_nex_devi == NULL) { 3374 if (ndi_devi_alloc(ddi_root_node(), "cpus", 3375 (pnode_t)DEVI_SID_NODEID, &cpu_nex_devi) != NDI_SUCCESS) { 3376 mutex_exit(&cpu_node_lock); 3377 return; 3378 } 3379 (void) ndi_devi_online(cpu_nex_devi, 0); 3380 } 3381 3382 /* 3383 * create a child node for cpu identified as 'cpu_id' 3384 */ 3385 cpu_devi = ddi_add_child(cpu_nex_devi, "cpu", DEVI_SID_NODEID, 3386 cpu_id); 3387 if (cpu_devi == NULL) { 3388 mutex_exit(&cpu_node_lock); 3389 return; 3390 } 3391 3392 /* device_type */ 3393 3394 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3395 "device_type", "cpu"); 3396 3397 /* reg */ 3398 3399 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3400 "reg", cpu_id); 3401 3402 /* cpu-mhz, and clock-frequency */ 3403 3404 if (cpu_freq > 0) { 3405 long long mul; 3406 3407 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3408 "cpu-mhz", cpu_freq); 3409 3410 if ((mul = cpu_freq * 1000000LL) <= INT_MAX) 3411 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3412 "clock-frequency", (int)mul); 3413 } 3414 3415 (void) ndi_devi_online(cpu_devi, 0); 3416 3417 if ((x86_feature & X86_CPUID) == 0) { 3418 mutex_exit(&cpu_node_lock); 3419 return; 3420 } 3421 3422 /* vendor-id */ 3423 3424 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3425 "vendor-id", cpi->cpi_vendorstr); 3426 3427 if (cpi->cpi_maxeax == 0) { 3428 mutex_exit(&cpu_node_lock); 3429 return; 3430 } 3431 3432 /* 3433 * family, model, and step 3434 */ 3435 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3436 "family", CPI_FAMILY(cpi)); 3437 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3438 "cpu-model", CPI_MODEL(cpi)); 3439 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3440 "stepping-id", CPI_STEP(cpi)); 3441 3442 /* type */ 3443 3444 switch (cpi->cpi_vendor) { 3445 case X86_VENDOR_Intel: 3446 create = 1; 3447 break; 3448 default: 3449 create = 0; 3450 break; 3451 } 3452 if (create) 3453 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3454 "type", CPI_TYPE(cpi)); 3455 3456 /* ext-family */ 3457 3458 switch (cpi->cpi_vendor) { 3459 case X86_VENDOR_Intel: 3460 case X86_VENDOR_AMD: 3461 create = cpi->cpi_family >= 0xf; 3462 break; 3463 default: 3464 create = 0; 3465 break; 3466 } 3467 if (create) 3468 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3469 "ext-family", CPI_FAMILY_XTD(cpi)); 3470 3471 /* ext-model */ 3472 3473 switch (cpi->cpi_vendor) { 3474 case X86_VENDOR_Intel: 3475 create = IS_EXTENDED_MODEL_INTEL(cpi); 3476 break; 3477 case X86_VENDOR_AMD: 3478 create = CPI_FAMILY(cpi) == 0xf; 3479 break; 3480 default: 3481 create = 0; 3482 break; 3483 } 3484 if (create) 3485 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3486 "ext-model", CPI_MODEL_XTD(cpi)); 3487 3488 /* generation */ 3489 3490 switch (cpi->cpi_vendor) { 3491 case X86_VENDOR_AMD: 3492 /* 3493 * AMD K5 model 1 was the first part to support this 3494 */ 3495 create = cpi->cpi_xmaxeax >= 0x80000001; 3496 break; 3497 default: 3498 create = 0; 3499 break; 3500 } 3501 if (create) 3502 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3503 "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8)); 3504 3505 /* brand-id */ 3506 3507 switch (cpi->cpi_vendor) { 3508 case X86_VENDOR_Intel: 3509 /* 3510 * brand id first appeared on Pentium III Xeon model 8, 3511 * and Celeron model 8 processors and Opteron 3512 */ 3513 create = cpi->cpi_family > 6 || 3514 (cpi->cpi_family == 6 && cpi->cpi_model >= 8); 3515 break; 3516 case X86_VENDOR_AMD: 3517 create = cpi->cpi_family >= 0xf; 3518 break; 3519 default: 3520 create = 0; 3521 break; 3522 } 3523 if (create && cpi->cpi_brandid != 0) { 3524 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3525 "brand-id", cpi->cpi_brandid); 3526 } 3527 3528 /* chunks, and apic-id */ 3529 3530 switch (cpi->cpi_vendor) { 3531 /* 3532 * first available on Pentium IV and Opteron (K8) 3533 */ 3534 case X86_VENDOR_Intel: 3535 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 3536 break; 3537 case X86_VENDOR_AMD: 3538 create = cpi->cpi_family >= 0xf; 3539 break; 3540 default: 3541 create = 0; 3542 break; 3543 } 3544 if (create) { 3545 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3546 "chunks", CPI_CHUNKS(cpi)); 3547 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3548 "apic-id", cpi->cpi_apicid); 3549 if (cpi->cpi_chipid >= 0) { 3550 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3551 "chip#", cpi->cpi_chipid); 3552 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3553 "clog#", cpi->cpi_clogid); 3554 } 3555 } 3556 3557 /* cpuid-features */ 3558 3559 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3560 "cpuid-features", CPI_FEATURES_EDX(cpi)); 3561 3562 3563 /* cpuid-features-ecx */ 3564 3565 switch (cpi->cpi_vendor) { 3566 case X86_VENDOR_Intel: 3567 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 3568 break; 3569 default: 3570 create = 0; 3571 break; 3572 } 3573 if (create) 3574 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3575 "cpuid-features-ecx", CPI_FEATURES_ECX(cpi)); 3576 3577 /* ext-cpuid-features */ 3578 3579 switch (cpi->cpi_vendor) { 3580 case X86_VENDOR_Intel: 3581 case X86_VENDOR_AMD: 3582 case X86_VENDOR_Cyrix: 3583 case X86_VENDOR_TM: 3584 case X86_VENDOR_Centaur: 3585 create = cpi->cpi_xmaxeax >= 0x80000001; 3586 break; 3587 default: 3588 create = 0; 3589 break; 3590 } 3591 if (create) { 3592 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3593 "ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi)); 3594 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3595 "ext-cpuid-features-ecx", CPI_FEATURES_XTD_ECX(cpi)); 3596 } 3597 3598 /* 3599 * Brand String first appeared in Intel Pentium IV, AMD K5 3600 * model 1, and Cyrix GXm. On earlier models we try and 3601 * simulate something similar .. so this string should always 3602 * same -something- about the processor, however lame. 3603 */ 3604 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3605 "brand-string", cpi->cpi_brandstr); 3606 3607 /* 3608 * Finally, cache and tlb information 3609 */ 3610 switch (x86_which_cacheinfo(cpi)) { 3611 case X86_VENDOR_Intel: 3612 intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 3613 break; 3614 case X86_VENDOR_Cyrix: 3615 cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 3616 break; 3617 case X86_VENDOR_AMD: 3618 amd_cache_info(cpi, cpu_devi); 3619 break; 3620 default: 3621 break; 3622 } 3623 3624 mutex_exit(&cpu_node_lock); 3625 } 3626 3627 struct l2info { 3628 int *l2i_csz; 3629 int *l2i_lsz; 3630 int *l2i_assoc; 3631 int l2i_ret; 3632 }; 3633 3634 /* 3635 * A cacheinfo walker that fetches the size, line-size and associativity 3636 * of the L2 cache 3637 */ 3638 static int 3639 intel_l2cinfo(void *arg, const struct cachetab *ct) 3640 { 3641 struct l2info *l2i = arg; 3642 int *ip; 3643 3644 if (ct->ct_label != l2_cache_str && 3645 ct->ct_label != sl2_cache_str) 3646 return (0); /* not an L2 -- keep walking */ 3647 3648 if ((ip = l2i->l2i_csz) != NULL) 3649 *ip = ct->ct_size; 3650 if ((ip = l2i->l2i_lsz) != NULL) 3651 *ip = ct->ct_line_size; 3652 if ((ip = l2i->l2i_assoc) != NULL) 3653 *ip = ct->ct_assoc; 3654 l2i->l2i_ret = ct->ct_size; 3655 return (1); /* was an L2 -- terminate walk */ 3656 } 3657 3658 /* 3659 * AMD L2/L3 Cache and TLB Associativity Field Definition: 3660 * 3661 * Unlike the associativity for the L1 cache and tlb where the 8 bit 3662 * value is the associativity, the associativity for the L2 cache and 3663 * tlb is encoded in the following table. The 4 bit L2 value serves as 3664 * an index into the amd_afd[] array to determine the associativity. 3665 * -1 is undefined. 0 is fully associative. 3666 */ 3667 3668 static int amd_afd[] = 3669 {-1, 1, 2, -1, 4, -1, 8, -1, 16, -1, 32, 48, 64, 96, 128, 0}; 3670 3671 static void 3672 amd_l2cacheinfo(struct cpuid_info *cpi, struct l2info *l2i) 3673 { 3674 struct cpuid_regs *cp; 3675 uint_t size, assoc; 3676 int i; 3677 int *ip; 3678 3679 if (cpi->cpi_xmaxeax < 0x80000006) 3680 return; 3681 cp = &cpi->cpi_extd[6]; 3682 3683 if ((i = BITX(cp->cp_ecx, 15, 12)) != 0 && 3684 (size = BITX(cp->cp_ecx, 31, 16)) != 0) { 3685 uint_t cachesz = size * 1024; 3686 assoc = amd_afd[i]; 3687 3688 ASSERT(assoc != -1); 3689 3690 if ((ip = l2i->l2i_csz) != NULL) 3691 *ip = cachesz; 3692 if ((ip = l2i->l2i_lsz) != NULL) 3693 *ip = BITX(cp->cp_ecx, 7, 0); 3694 if ((ip = l2i->l2i_assoc) != NULL) 3695 *ip = assoc; 3696 l2i->l2i_ret = cachesz; 3697 } 3698 } 3699 3700 int 3701 getl2cacheinfo(cpu_t *cpu, int *csz, int *lsz, int *assoc) 3702 { 3703 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 3704 struct l2info __l2info, *l2i = &__l2info; 3705 3706 l2i->l2i_csz = csz; 3707 l2i->l2i_lsz = lsz; 3708 l2i->l2i_assoc = assoc; 3709 l2i->l2i_ret = -1; 3710 3711 switch (x86_which_cacheinfo(cpi)) { 3712 case X86_VENDOR_Intel: 3713 intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 3714 break; 3715 case X86_VENDOR_Cyrix: 3716 cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 3717 break; 3718 case X86_VENDOR_AMD: 3719 amd_l2cacheinfo(cpi, l2i); 3720 break; 3721 default: 3722 break; 3723 } 3724 return (l2i->l2i_ret); 3725 } 3726 3727 #if !defined(__xpv) 3728 3729 uint32_t * 3730 cpuid_mwait_alloc(cpu_t *cpu) 3731 { 3732 uint32_t *ret; 3733 size_t mwait_size; 3734 3735 ASSERT(cpuid_checkpass(cpu, 2)); 3736 3737 mwait_size = cpu->cpu_m.mcpu_cpi->cpi_mwait.mon_max; 3738 if (mwait_size == 0) 3739 return (NULL); 3740 3741 /* 3742 * kmem_alloc() returns cache line size aligned data for mwait_size 3743 * allocations. mwait_size is currently cache line sized. Neither 3744 * of these implementation details are guarantied to be true in the 3745 * future. 3746 * 3747 * First try allocating mwait_size as kmem_alloc() currently returns 3748 * correctly aligned memory. If kmem_alloc() does not return 3749 * mwait_size aligned memory, then use mwait_size ROUNDUP. 3750 * 3751 * Set cpi_mwait.buf_actual and cpi_mwait.size_actual in case we 3752 * decide to free this memory. 3753 */ 3754 ret = kmem_zalloc(mwait_size, KM_SLEEP); 3755 if (ret == (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size)) { 3756 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret; 3757 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size; 3758 *ret = MWAIT_RUNNING; 3759 return (ret); 3760 } else { 3761 kmem_free(ret, mwait_size); 3762 ret = kmem_zalloc(mwait_size * 2, KM_SLEEP); 3763 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret; 3764 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size * 2; 3765 ret = (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size); 3766 *ret = MWAIT_RUNNING; 3767 return (ret); 3768 } 3769 } 3770 3771 void 3772 cpuid_mwait_free(cpu_t *cpu) 3773 { 3774 ASSERT(cpuid_checkpass(cpu, 2)); 3775 3776 if (cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual != NULL && 3777 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual > 0) { 3778 kmem_free(cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual, 3779 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual); 3780 } 3781 3782 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = NULL; 3783 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = 0; 3784 } 3785 3786 void 3787 patch_tsc_read(int flag) 3788 { 3789 size_t cnt; 3790 3791 switch (flag) { 3792 case X86_NO_TSC: 3793 cnt = &_no_rdtsc_end - &_no_rdtsc_start; 3794 (void) memcpy((void *)tsc_read, (void *)&_no_rdtsc_start, cnt); 3795 break; 3796 case X86_HAVE_TSCP: 3797 cnt = &_tscp_end - &_tscp_start; 3798 (void) memcpy((void *)tsc_read, (void *)&_tscp_start, cnt); 3799 break; 3800 case X86_TSC_MFENCE: 3801 cnt = &_tsc_mfence_end - &_tsc_mfence_start; 3802 (void) memcpy((void *)tsc_read, 3803 (void *)&_tsc_mfence_start, cnt); 3804 break; 3805 case X86_TSC_LFENCE: 3806 cnt = &_tsc_lfence_end - &_tsc_lfence_start; 3807 (void) memcpy((void *)tsc_read, 3808 (void *)&_tsc_lfence_start, cnt); 3809 break; 3810 default: 3811 break; 3812 } 3813 } 3814 3815 #endif /* !__xpv */ 3816