1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * Various routines to handle identification 30 * and classification of x86 processors. 31 */ 32 33 #include <sys/types.h> 34 #include <sys/archsystm.h> 35 #include <sys/x86_archext.h> 36 #include <sys/kmem.h> 37 #include <sys/systm.h> 38 #include <sys/cmn_err.h> 39 #include <sys/sunddi.h> 40 #include <sys/sunndi.h> 41 #include <sys/cpuvar.h> 42 #include <sys/processor.h> 43 #include <sys/pg.h> 44 #include <sys/fp.h> 45 #include <sys/controlregs.h> 46 #include <sys/auxv_386.h> 47 #include <sys/bitmap.h> 48 #include <sys/memnode.h> 49 50 /* 51 * Pass 0 of cpuid feature analysis happens in locore. It contains special code 52 * to recognize Cyrix processors that are not cpuid-compliant, and to deal with 53 * them accordingly. For most modern processors, feature detection occurs here 54 * in pass 1. 55 * 56 * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup() 57 * for the boot CPU and does the basic analysis that the early kernel needs. 58 * x86_feature is set based on the return value of cpuid_pass1() of the boot 59 * CPU. 60 * 61 * Pass 1 includes: 62 * 63 * o Determining vendor/model/family/stepping and setting x86_type and 64 * x86_vendor accordingly. 65 * o Processing the feature flags returned by the cpuid instruction while 66 * applying any workarounds or tricks for the specific processor. 67 * o Mapping the feature flags into Solaris feature bits (X86_*). 68 * o Processing extended feature flags if supported by the processor, 69 * again while applying specific processor knowledge. 70 * o Determining the CMT characteristics of the system. 71 * 72 * Pass 1 is done on non-boot CPUs during their initialization and the results 73 * are used only as a meager attempt at ensuring that all processors within the 74 * system support the same features. 75 * 76 * Pass 2 of cpuid feature analysis happens just at the beginning 77 * of startup(). It just copies in and corrects the remainder 78 * of the cpuid data we depend on: standard cpuid functions that we didn't 79 * need for pass1 feature analysis, and extended cpuid functions beyond the 80 * simple feature processing done in pass1. 81 * 82 * Pass 3 of cpuid analysis is invoked after basic kernel services; in 83 * particular kernel memory allocation has been made available. It creates a 84 * readable brand string based on the data collected in the first two passes. 85 * 86 * Pass 4 of cpuid analysis is invoked after post_startup() when all 87 * the support infrastructure for various hardware features has been 88 * initialized. It determines which processor features will be reported 89 * to userland via the aux vector. 90 * 91 * All passes are executed on all CPUs, but only the boot CPU determines what 92 * features the kernel will use. 93 * 94 * Much of the worst junk in this file is for the support of processors 95 * that didn't really implement the cpuid instruction properly. 96 * 97 * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon, 98 * the pass numbers. Accordingly, changes to the pass code may require changes 99 * to the accessor code. 100 */ 101 102 uint_t x86_feature = 0; 103 uint_t x86_vendor = X86_VENDOR_IntelClone; 104 uint_t x86_type = X86_TYPE_OTHER; 105 106 uint_t pentiumpro_bug4046376; 107 uint_t pentiumpro_bug4064495; 108 109 uint_t enable486; 110 111 /* 112 * This set of strings are for processors rumored to support the cpuid 113 * instruction, and is used by locore.s to figure out how to set x86_vendor 114 */ 115 const char CyrixInstead[] = "CyrixInstead"; 116 117 /* 118 * monitor/mwait info. 119 */ 120 struct mwait_info { 121 size_t mon_min; /* min size to avoid missed wakeups */ 122 size_t mon_max; /* size to avoid false wakeups */ 123 uint32_t support; /* processor support of monitor/mwait */ 124 }; 125 126 /* 127 * These constants determine how many of the elements of the 128 * cpuid we cache in the cpuid_info data structure; the 129 * remaining elements are accessible via the cpuid instruction. 130 */ 131 132 #define NMAX_CPI_STD 6 /* eax = 0 .. 5 */ 133 #define NMAX_CPI_EXTD 9 /* eax = 0x80000000 .. 0x80000008 */ 134 135 struct cpuid_info { 136 uint_t cpi_pass; /* last pass completed */ 137 /* 138 * standard function information 139 */ 140 uint_t cpi_maxeax; /* fn 0: %eax */ 141 char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */ 142 uint_t cpi_vendor; /* enum of cpi_vendorstr */ 143 144 uint_t cpi_family; /* fn 1: extended family */ 145 uint_t cpi_model; /* fn 1: extended model */ 146 uint_t cpi_step; /* fn 1: stepping */ 147 chipid_t cpi_chipid; /* fn 1: %ebx: chip # on ht cpus */ 148 uint_t cpi_brandid; /* fn 1: %ebx: brand ID */ 149 int cpi_clogid; /* fn 1: %ebx: thread # */ 150 uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */ 151 uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */ 152 uint_t cpi_ncache; /* fn 2: number of elements */ 153 struct cpuid_regs cpi_std[NMAX_CPI_STD]; /* 0 .. 5 */ 154 /* 155 * extended function information 156 */ 157 uint_t cpi_xmaxeax; /* fn 0x80000000: %eax */ 158 char cpi_brandstr[49]; /* fn 0x8000000[234] */ 159 uint8_t cpi_pabits; /* fn 0x80000006: %eax */ 160 uint8_t cpi_vabits; /* fn 0x80000006: %eax */ 161 struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x8000000[0-8] */ 162 id_t cpi_coreid; 163 uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */ 164 /* Intel: fn 4: %eax[31-26] */ 165 /* 166 * supported feature information 167 */ 168 uint32_t cpi_support[5]; 169 #define STD_EDX_FEATURES 0 170 #define AMD_EDX_FEATURES 1 171 #define TM_EDX_FEATURES 2 172 #define STD_ECX_FEATURES 3 173 #define AMD_ECX_FEATURES 4 174 /* 175 * Synthesized information, where known. 176 */ 177 uint32_t cpi_chiprev; /* See X86_CHIPREV_* in x86_archext.h */ 178 const char *cpi_chiprevstr; /* May be NULL if chiprev unknown */ 179 uint32_t cpi_socket; /* Chip package/socket type */ 180 181 struct mwait_info cpi_mwait; /* fn 5: monitor/mwait info */ 182 }; 183 184 185 static struct cpuid_info cpuid_info0; 186 187 /* 188 * These bit fields are defined by the Intel Application Note AP-485 189 * "Intel Processor Identification and the CPUID Instruction" 190 */ 191 #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20) 192 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16) 193 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12) 194 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8) 195 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0) 196 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4) 197 198 #define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx) 199 #define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx) 200 #define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx) 201 #define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx) 202 203 #define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0) 204 #define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7) 205 #define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16) 206 #define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24) 207 208 #define CPI_MAXEAX_MAX 0x100 /* sanity control */ 209 #define CPI_XMAXEAX_MAX 0x80000100 210 211 /* 212 * A couple of shorthand macros to identify "later" P6-family chips 213 * like the Pentium M and Core. First, the "older" P6-based stuff 214 * (loosely defined as "pre-Pentium-4"): 215 * P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon 216 */ 217 218 #define IS_LEGACY_P6(cpi) ( \ 219 cpi->cpi_family == 6 && \ 220 (cpi->cpi_model == 1 || \ 221 cpi->cpi_model == 3 || \ 222 cpi->cpi_model == 5 || \ 223 cpi->cpi_model == 6 || \ 224 cpi->cpi_model == 7 || \ 225 cpi->cpi_model == 8 || \ 226 cpi->cpi_model == 0xA || \ 227 cpi->cpi_model == 0xB) \ 228 ) 229 230 /* A "new F6" is everything with family 6 that's not the above */ 231 #define IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi)) 232 233 /* 234 * AMD family 0xf socket types. 235 * First index is 0 for revs B thru E, 1 for F and G. 236 * Second index by (model & 0x3) 237 */ 238 static uint32_t amd_skts[2][4] = { 239 { 240 X86_SOCKET_754, /* 0b00 */ 241 X86_SOCKET_940, /* 0b01 */ 242 X86_SOCKET_754, /* 0b10 */ 243 X86_SOCKET_939 /* 0b11 */ 244 }, 245 { 246 X86_SOCKET_S1g1, /* 0b00 */ 247 X86_SOCKET_F1207, /* 0b01 */ 248 X86_SOCKET_UNKNOWN, /* 0b10 */ 249 X86_SOCKET_AM2 /* 0b11 */ 250 } 251 }; 252 253 /* 254 * Table for mapping AMD Family 0xf model/stepping combination to 255 * chip "revision" and socket type. Only rm_family 0xf is used at the 256 * moment, but AMD family 0x10 will extend the exsiting revision names 257 * so will likely also use this table. 258 * 259 * The first member of this array that matches a given family, extended model 260 * plus model range, and stepping range will be considered a match. 261 */ 262 static const struct amd_rev_mapent { 263 uint_t rm_family; 264 uint_t rm_modello; 265 uint_t rm_modelhi; 266 uint_t rm_steplo; 267 uint_t rm_stephi; 268 uint32_t rm_chiprev; 269 const char *rm_chiprevstr; 270 int rm_sktidx; 271 } amd_revmap[] = { 272 /* 273 * Rev B includes model 0x4 stepping 0 and model 0x5 stepping 0 and 1. 274 */ 275 { 0xf, 0x04, 0x04, 0x0, 0x0, X86_CHIPREV_AMD_F_REV_B, "B", 0 }, 276 { 0xf, 0x05, 0x05, 0x0, 0x1, X86_CHIPREV_AMD_F_REV_B, "B", 0 }, 277 /* 278 * Rev C0 includes model 0x4 stepping 8 and model 0x5 stepping 8 279 */ 280 { 0xf, 0x04, 0x05, 0x8, 0x8, X86_CHIPREV_AMD_F_REV_C0, "C0", 0 }, 281 /* 282 * Rev CG is the rest of extended model 0x0 - i.e., everything 283 * but the rev B and C0 combinations covered above. 284 */ 285 { 0xf, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_CG, "CG", 0 }, 286 /* 287 * Rev D has extended model 0x1. 288 */ 289 { 0xf, 0x10, 0x1f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_D, "D", 0 }, 290 /* 291 * Rev E has extended model 0x2. 292 * Extended model 0x3 is unused but available to grow into. 293 */ 294 { 0xf, 0x20, 0x3f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_E, "E", 0 }, 295 /* 296 * Rev F has extended models 0x4 and 0x5. 297 */ 298 { 0xf, 0x40, 0x5f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_F, "F", 1 }, 299 /* 300 * Rev G has extended model 0x6. 301 */ 302 { 0xf, 0x60, 0x6f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_G, "G", 1 }, 303 }; 304 305 /* 306 * Info for monitor/mwait idle loop. 307 * 308 * See cpuid section of "Intel 64 and IA-32 Architectures Software Developer's 309 * Manual Volume 2A: Instruction Set Reference, A-M" #25366-022US, November 310 * 2006. 311 * See MONITOR/MWAIT section of "AMD64 Architecture Programmer's Manual 312 * Documentation Updates" #33633, Rev 2.05, December 2006. 313 */ 314 #define MWAIT_SUPPORT (0x00000001) /* mwait supported */ 315 #define MWAIT_EXTENSIONS (0x00000002) /* extenstion supported */ 316 #define MWAIT_ECX_INT_ENABLE (0x00000004) /* ecx 1 extension supported */ 317 #define MWAIT_SUPPORTED(cpi) ((cpi)->cpi_std[1].cp_ecx & CPUID_INTC_ECX_MON) 318 #define MWAIT_INT_ENABLE(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x2) 319 #define MWAIT_EXTENSION(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x1) 320 #define MWAIT_SIZE_MIN(cpi) BITX((cpi)->cpi_std[5].cp_eax, 15, 0) 321 #define MWAIT_SIZE_MAX(cpi) BITX((cpi)->cpi_std[5].cp_ebx, 15, 0) 322 /* 323 * Number of sub-cstates for a given c-state. 324 */ 325 #define MWAIT_NUM_SUBC_STATES(cpi, c_state) \ 326 BITX((cpi)->cpi_std[5].cp_edx, c_state + 3, c_state) 327 328 static void 329 synth_amd_info(struct cpuid_info *cpi) 330 { 331 const struct amd_rev_mapent *rmp; 332 uint_t family, model, step; 333 int i; 334 335 /* 336 * Currently only AMD family 0xf uses these fields. 337 */ 338 if (cpi->cpi_family != 0xf) 339 return; 340 341 family = cpi->cpi_family; 342 model = cpi->cpi_model; 343 step = cpi->cpi_step; 344 345 for (i = 0, rmp = amd_revmap; i < sizeof (amd_revmap) / sizeof (*rmp); 346 i++, rmp++) { 347 if (family == rmp->rm_family && 348 model >= rmp->rm_modello && model <= rmp->rm_modelhi && 349 step >= rmp->rm_steplo && step <= rmp->rm_stephi) { 350 cpi->cpi_chiprev = rmp->rm_chiprev; 351 cpi->cpi_chiprevstr = rmp->rm_chiprevstr; 352 cpi->cpi_socket = amd_skts[rmp->rm_sktidx][model & 0x3]; 353 return; 354 } 355 } 356 } 357 358 static void 359 synth_info(struct cpuid_info *cpi) 360 { 361 cpi->cpi_chiprev = X86_CHIPREV_UNKNOWN; 362 cpi->cpi_chiprevstr = "Unknown"; 363 cpi->cpi_socket = X86_SOCKET_UNKNOWN; 364 365 switch (cpi->cpi_vendor) { 366 case X86_VENDOR_AMD: 367 synth_amd_info(cpi); 368 break; 369 370 default: 371 break; 372 373 } 374 } 375 376 /* 377 * Apply up various platform-dependent restrictions where the 378 * underlying platform restrictions mean the CPU can be marked 379 * as less capable than its cpuid instruction would imply. 380 */ 381 382 #define platform_cpuid_mangle(vendor, eax, cp) /* nothing */ 383 384 /* 385 * Some undocumented ways of patching the results of the cpuid 386 * instruction to permit running Solaris 10 on future cpus that 387 * we don't currently support. Could be set to non-zero values 388 * via settings in eeprom. 389 */ 390 391 uint32_t cpuid_feature_ecx_include; 392 uint32_t cpuid_feature_ecx_exclude; 393 uint32_t cpuid_feature_edx_include; 394 uint32_t cpuid_feature_edx_exclude; 395 396 void 397 cpuid_alloc_space(cpu_t *cpu) 398 { 399 /* 400 * By convention, cpu0 is the boot cpu, which is set up 401 * before memory allocation is available. All other cpus get 402 * their cpuid_info struct allocated here. 403 */ 404 ASSERT(cpu->cpu_id != 0); 405 cpu->cpu_m.mcpu_cpi = 406 kmem_zalloc(sizeof (*cpu->cpu_m.mcpu_cpi), KM_SLEEP); 407 } 408 409 void 410 cpuid_free_space(cpu_t *cpu) 411 { 412 ASSERT(cpu->cpu_id != 0); 413 kmem_free(cpu->cpu_m.mcpu_cpi, sizeof (*cpu->cpu_m.mcpu_cpi)); 414 } 415 416 uint_t 417 cpuid_pass1(cpu_t *cpu) 418 { 419 uint32_t mask_ecx, mask_edx; 420 uint_t feature = X86_CPUID; 421 struct cpuid_info *cpi; 422 struct cpuid_regs *cp; 423 int xcpuid; 424 425 426 /* 427 * Space statically allocated for cpu0, ensure pointer is set 428 */ 429 if (cpu->cpu_id == 0) 430 cpu->cpu_m.mcpu_cpi = &cpuid_info0; 431 cpi = cpu->cpu_m.mcpu_cpi; 432 ASSERT(cpi != NULL); 433 cp = &cpi->cpi_std[0]; 434 cp->cp_eax = 0; 435 cpi->cpi_maxeax = __cpuid_insn(cp); 436 { 437 uint32_t *iptr = (uint32_t *)cpi->cpi_vendorstr; 438 *iptr++ = cp->cp_ebx; 439 *iptr++ = cp->cp_edx; 440 *iptr++ = cp->cp_ecx; 441 *(char *)&cpi->cpi_vendorstr[12] = '\0'; 442 } 443 444 /* 445 * Map the vendor string to a type code 446 */ 447 if (strcmp(cpi->cpi_vendorstr, "GenuineIntel") == 0) 448 cpi->cpi_vendor = X86_VENDOR_Intel; 449 else if (strcmp(cpi->cpi_vendorstr, "AuthenticAMD") == 0) 450 cpi->cpi_vendor = X86_VENDOR_AMD; 451 else if (strcmp(cpi->cpi_vendorstr, "GenuineTMx86") == 0) 452 cpi->cpi_vendor = X86_VENDOR_TM; 453 else if (strcmp(cpi->cpi_vendorstr, CyrixInstead) == 0) 454 /* 455 * CyrixInstead is a variable used by the Cyrix detection code 456 * in locore. 457 */ 458 cpi->cpi_vendor = X86_VENDOR_Cyrix; 459 else if (strcmp(cpi->cpi_vendorstr, "UMC UMC UMC ") == 0) 460 cpi->cpi_vendor = X86_VENDOR_UMC; 461 else if (strcmp(cpi->cpi_vendorstr, "NexGenDriven") == 0) 462 cpi->cpi_vendor = X86_VENDOR_NexGen; 463 else if (strcmp(cpi->cpi_vendorstr, "CentaurHauls") == 0) 464 cpi->cpi_vendor = X86_VENDOR_Centaur; 465 else if (strcmp(cpi->cpi_vendorstr, "RiseRiseRise") == 0) 466 cpi->cpi_vendor = X86_VENDOR_Rise; 467 else if (strcmp(cpi->cpi_vendorstr, "SiS SiS SiS ") == 0) 468 cpi->cpi_vendor = X86_VENDOR_SiS; 469 else if (strcmp(cpi->cpi_vendorstr, "Geode by NSC") == 0) 470 cpi->cpi_vendor = X86_VENDOR_NSC; 471 else 472 cpi->cpi_vendor = X86_VENDOR_IntelClone; 473 474 x86_vendor = cpi->cpi_vendor; /* for compatibility */ 475 476 /* 477 * Limit the range in case of weird hardware 478 */ 479 if (cpi->cpi_maxeax > CPI_MAXEAX_MAX) 480 cpi->cpi_maxeax = CPI_MAXEAX_MAX; 481 if (cpi->cpi_maxeax < 1) 482 goto pass1_done; 483 484 cp = &cpi->cpi_std[1]; 485 cp->cp_eax = 1; 486 (void) __cpuid_insn(cp); 487 488 /* 489 * Extract identifying constants for easy access. 490 */ 491 cpi->cpi_model = CPI_MODEL(cpi); 492 cpi->cpi_family = CPI_FAMILY(cpi); 493 494 if (cpi->cpi_family == 0xf) 495 cpi->cpi_family += CPI_FAMILY_XTD(cpi); 496 497 /* 498 * Beware: AMD uses "extended model" iff base *FAMILY* == 0xf. 499 * Intel, and presumably everyone else, uses model == 0xf, as 500 * one would expect (max value means possible overflow). Sigh. 501 */ 502 503 switch (cpi->cpi_vendor) { 504 case X86_VENDOR_AMD: 505 if (CPI_FAMILY(cpi) == 0xf) 506 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 507 break; 508 default: 509 if (cpi->cpi_model == 0xf) 510 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 511 break; 512 } 513 514 cpi->cpi_step = CPI_STEP(cpi); 515 cpi->cpi_brandid = CPI_BRANDID(cpi); 516 517 /* 518 * *default* assumptions: 519 * - believe %edx feature word 520 * - ignore %ecx feature word 521 * - 32-bit virtual and physical addressing 522 */ 523 mask_edx = 0xffffffff; 524 mask_ecx = 0; 525 526 cpi->cpi_pabits = cpi->cpi_vabits = 32; 527 528 switch (cpi->cpi_vendor) { 529 case X86_VENDOR_Intel: 530 if (cpi->cpi_family == 5) 531 x86_type = X86_TYPE_P5; 532 else if (IS_LEGACY_P6(cpi)) { 533 x86_type = X86_TYPE_P6; 534 pentiumpro_bug4046376 = 1; 535 pentiumpro_bug4064495 = 1; 536 /* 537 * Clear the SEP bit when it was set erroneously 538 */ 539 if (cpi->cpi_model < 3 && cpi->cpi_step < 3) 540 cp->cp_edx &= ~CPUID_INTC_EDX_SEP; 541 } else if (IS_NEW_F6(cpi) || cpi->cpi_family == 0xf) { 542 x86_type = X86_TYPE_P4; 543 /* 544 * We don't currently depend on any of the %ecx 545 * features until Prescott, so we'll only check 546 * this from P4 onwards. We might want to revisit 547 * that idea later. 548 */ 549 mask_ecx = 0xffffffff; 550 } else if (cpi->cpi_family > 0xf) 551 mask_ecx = 0xffffffff; 552 break; 553 case X86_VENDOR_IntelClone: 554 default: 555 break; 556 case X86_VENDOR_AMD: 557 #if defined(OPTERON_ERRATUM_108) 558 if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) { 559 cp->cp_eax = (0xf0f & cp->cp_eax) | 0xc0; 560 cpi->cpi_model = 0xc; 561 } else 562 #endif 563 if (cpi->cpi_family == 5) { 564 /* 565 * AMD K5 and K6 566 * 567 * These CPUs have an incomplete implementation 568 * of MCA/MCE which we mask away. 569 */ 570 mask_edx &= ~(CPUID_INTC_EDX_MCE | CPUID_INTC_EDX_MCA); 571 572 /* 573 * Model 0 uses the wrong (APIC) bit 574 * to indicate PGE. Fix it here. 575 */ 576 if (cpi->cpi_model == 0) { 577 if (cp->cp_edx & 0x200) { 578 cp->cp_edx &= ~0x200; 579 cp->cp_edx |= CPUID_INTC_EDX_PGE; 580 } 581 } 582 583 /* 584 * Early models had problems w/ MMX; disable. 585 */ 586 if (cpi->cpi_model < 6) 587 mask_edx &= ~CPUID_INTC_EDX_MMX; 588 } 589 590 /* 591 * For newer families, SSE3 and CX16, at least, are valid; 592 * enable all 593 */ 594 if (cpi->cpi_family >= 0xf) 595 mask_ecx = 0xffffffff; 596 break; 597 case X86_VENDOR_TM: 598 /* 599 * workaround the NT workaround in CMS 4.1 600 */ 601 if (cpi->cpi_family == 5 && cpi->cpi_model == 4 && 602 (cpi->cpi_step == 2 || cpi->cpi_step == 3)) 603 cp->cp_edx |= CPUID_INTC_EDX_CX8; 604 break; 605 case X86_VENDOR_Centaur: 606 /* 607 * workaround the NT workarounds again 608 */ 609 if (cpi->cpi_family == 6) 610 cp->cp_edx |= CPUID_INTC_EDX_CX8; 611 break; 612 case X86_VENDOR_Cyrix: 613 /* 614 * We rely heavily on the probing in locore 615 * to actually figure out what parts, if any, 616 * of the Cyrix cpuid instruction to believe. 617 */ 618 switch (x86_type) { 619 case X86_TYPE_CYRIX_486: 620 mask_edx = 0; 621 break; 622 case X86_TYPE_CYRIX_6x86: 623 mask_edx = 0; 624 break; 625 case X86_TYPE_CYRIX_6x86L: 626 mask_edx = 627 CPUID_INTC_EDX_DE | 628 CPUID_INTC_EDX_CX8; 629 break; 630 case X86_TYPE_CYRIX_6x86MX: 631 mask_edx = 632 CPUID_INTC_EDX_DE | 633 CPUID_INTC_EDX_MSR | 634 CPUID_INTC_EDX_CX8 | 635 CPUID_INTC_EDX_PGE | 636 CPUID_INTC_EDX_CMOV | 637 CPUID_INTC_EDX_MMX; 638 break; 639 case X86_TYPE_CYRIX_GXm: 640 mask_edx = 641 CPUID_INTC_EDX_MSR | 642 CPUID_INTC_EDX_CX8 | 643 CPUID_INTC_EDX_CMOV | 644 CPUID_INTC_EDX_MMX; 645 break; 646 case X86_TYPE_CYRIX_MediaGX: 647 break; 648 case X86_TYPE_CYRIX_MII: 649 case X86_TYPE_VIA_CYRIX_III: 650 mask_edx = 651 CPUID_INTC_EDX_DE | 652 CPUID_INTC_EDX_TSC | 653 CPUID_INTC_EDX_MSR | 654 CPUID_INTC_EDX_CX8 | 655 CPUID_INTC_EDX_PGE | 656 CPUID_INTC_EDX_CMOV | 657 CPUID_INTC_EDX_MMX; 658 break; 659 default: 660 break; 661 } 662 break; 663 } 664 665 /* 666 * Now we've figured out the masks that determine 667 * which bits we choose to believe, apply the masks 668 * to the feature words, then map the kernel's view 669 * of these feature words into its feature word. 670 */ 671 cp->cp_edx &= mask_edx; 672 cp->cp_ecx &= mask_ecx; 673 674 /* 675 * apply any platform restrictions (we don't call this 676 * immediately after __cpuid_insn here, because we need the 677 * workarounds applied above first) 678 */ 679 platform_cpuid_mangle(cpi->cpi_vendor, 1, cp); 680 681 /* 682 * fold in overrides from the "eeprom" mechanism 683 */ 684 cp->cp_edx |= cpuid_feature_edx_include; 685 cp->cp_edx &= ~cpuid_feature_edx_exclude; 686 687 cp->cp_ecx |= cpuid_feature_ecx_include; 688 cp->cp_ecx &= ~cpuid_feature_ecx_exclude; 689 690 if (cp->cp_edx & CPUID_INTC_EDX_PSE) 691 feature |= X86_LARGEPAGE; 692 if (cp->cp_edx & CPUID_INTC_EDX_TSC) 693 feature |= X86_TSC; 694 if (cp->cp_edx & CPUID_INTC_EDX_MSR) 695 feature |= X86_MSR; 696 if (cp->cp_edx & CPUID_INTC_EDX_MTRR) 697 feature |= X86_MTRR; 698 if (cp->cp_edx & CPUID_INTC_EDX_PGE) 699 feature |= X86_PGE; 700 if (cp->cp_edx & CPUID_INTC_EDX_CMOV) 701 feature |= X86_CMOV; 702 if (cp->cp_edx & CPUID_INTC_EDX_MMX) 703 feature |= X86_MMX; 704 if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 && 705 (cp->cp_edx & CPUID_INTC_EDX_MCA) != 0) 706 feature |= X86_MCA; 707 if (cp->cp_edx & CPUID_INTC_EDX_PAE) 708 feature |= X86_PAE; 709 if (cp->cp_edx & CPUID_INTC_EDX_CX8) 710 feature |= X86_CX8; 711 if (cp->cp_ecx & CPUID_INTC_ECX_CX16) 712 feature |= X86_CX16; 713 if (cp->cp_edx & CPUID_INTC_EDX_PAT) 714 feature |= X86_PAT; 715 if (cp->cp_edx & CPUID_INTC_EDX_SEP) 716 feature |= X86_SEP; 717 if (cp->cp_edx & CPUID_INTC_EDX_FXSR) { 718 /* 719 * In our implementation, fxsave/fxrstor 720 * are prerequisites before we'll even 721 * try and do SSE things. 722 */ 723 if (cp->cp_edx & CPUID_INTC_EDX_SSE) 724 feature |= X86_SSE; 725 if (cp->cp_edx & CPUID_INTC_EDX_SSE2) 726 feature |= X86_SSE2; 727 if (cp->cp_ecx & CPUID_INTC_ECX_SSE3) 728 feature |= X86_SSE3; 729 } 730 if (cp->cp_edx & CPUID_INTC_EDX_DE) 731 feature |= X86_DE; 732 if (cp->cp_ecx & CPUID_INTC_ECX_MON) { 733 cpi->cpi_mwait.support |= MWAIT_SUPPORT; 734 feature |= X86_MWAIT; 735 } 736 737 if (feature & X86_PAE) 738 cpi->cpi_pabits = 36; 739 740 /* 741 * Hyperthreading configuration is slightly tricky on Intel 742 * and pure clones, and even trickier on AMD. 743 * 744 * (AMD chose to set the HTT bit on their CMP processors, 745 * even though they're not actually hyperthreaded. Thus it 746 * takes a bit more work to figure out what's really going 747 * on ... see the handling of the CMP_LGCY bit below) 748 */ 749 if (cp->cp_edx & CPUID_INTC_EDX_HTT) { 750 cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi); 751 if (cpi->cpi_ncpu_per_chip > 1) 752 feature |= X86_HTT; 753 } else { 754 cpi->cpi_ncpu_per_chip = 1; 755 } 756 757 /* 758 * Work on the "extended" feature information, doing 759 * some basic initialization for cpuid_pass2() 760 */ 761 xcpuid = 0; 762 switch (cpi->cpi_vendor) { 763 case X86_VENDOR_Intel: 764 if (IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf) 765 xcpuid++; 766 break; 767 case X86_VENDOR_AMD: 768 if (cpi->cpi_family > 5 || 769 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 770 xcpuid++; 771 break; 772 case X86_VENDOR_Cyrix: 773 /* 774 * Only these Cyrix CPUs are -known- to support 775 * extended cpuid operations. 776 */ 777 if (x86_type == X86_TYPE_VIA_CYRIX_III || 778 x86_type == X86_TYPE_CYRIX_GXm) 779 xcpuid++; 780 break; 781 case X86_VENDOR_Centaur: 782 case X86_VENDOR_TM: 783 default: 784 xcpuid++; 785 break; 786 } 787 788 if (xcpuid) { 789 cp = &cpi->cpi_extd[0]; 790 cp->cp_eax = 0x80000000; 791 cpi->cpi_xmaxeax = __cpuid_insn(cp); 792 } 793 794 if (cpi->cpi_xmaxeax & 0x80000000) { 795 796 if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX) 797 cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX; 798 799 switch (cpi->cpi_vendor) { 800 case X86_VENDOR_Intel: 801 case X86_VENDOR_AMD: 802 if (cpi->cpi_xmaxeax < 0x80000001) 803 break; 804 cp = &cpi->cpi_extd[1]; 805 cp->cp_eax = 0x80000001; 806 (void) __cpuid_insn(cp); 807 808 if (cpi->cpi_vendor == X86_VENDOR_AMD && 809 cpi->cpi_family == 5 && 810 cpi->cpi_model == 6 && 811 cpi->cpi_step == 6) { 812 /* 813 * K6 model 6 uses bit 10 to indicate SYSC 814 * Later models use bit 11. Fix it here. 815 */ 816 if (cp->cp_edx & 0x400) { 817 cp->cp_edx &= ~0x400; 818 cp->cp_edx |= CPUID_AMD_EDX_SYSC; 819 } 820 } 821 822 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000001, cp); 823 824 /* 825 * Compute the additions to the kernel's feature word. 826 */ 827 if (cp->cp_edx & CPUID_AMD_EDX_NX) 828 feature |= X86_NX; 829 830 /* 831 * If both the HTT and CMP_LGCY bits are set, 832 * then we're not actually HyperThreaded. Read 833 * "AMD CPUID Specification" for more details. 834 */ 835 if (cpi->cpi_vendor == X86_VENDOR_AMD && 836 (feature & X86_HTT) && 837 (cp->cp_ecx & CPUID_AMD_ECX_CMP_LGCY)) { 838 feature &= ~X86_HTT; 839 feature |= X86_CMP; 840 } 841 #if defined(__amd64) 842 /* 843 * It's really tricky to support syscall/sysret in 844 * the i386 kernel; we rely on sysenter/sysexit 845 * instead. In the amd64 kernel, things are -way- 846 * better. 847 */ 848 if (cp->cp_edx & CPUID_AMD_EDX_SYSC) 849 feature |= X86_ASYSC; 850 851 /* 852 * While we're thinking about system calls, note 853 * that AMD processors don't support sysenter 854 * in long mode at all, so don't try to program them. 855 */ 856 if (x86_vendor == X86_VENDOR_AMD) 857 feature &= ~X86_SEP; 858 #endif 859 if (cp->cp_edx & CPUID_AMD_EDX_TSCP) 860 feature |= X86_TSCP; 861 break; 862 default: 863 break; 864 } 865 866 /* 867 * Get CPUID data about processor cores and hyperthreads. 868 */ 869 switch (cpi->cpi_vendor) { 870 case X86_VENDOR_Intel: 871 if (cpi->cpi_maxeax >= 4) { 872 cp = &cpi->cpi_std[4]; 873 cp->cp_eax = 4; 874 cp->cp_ecx = 0; 875 (void) __cpuid_insn(cp); 876 platform_cpuid_mangle(cpi->cpi_vendor, 4, cp); 877 } 878 /*FALLTHROUGH*/ 879 case X86_VENDOR_AMD: 880 if (cpi->cpi_xmaxeax < 0x80000008) 881 break; 882 cp = &cpi->cpi_extd[8]; 883 cp->cp_eax = 0x80000008; 884 (void) __cpuid_insn(cp); 885 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000008, cp); 886 887 /* 888 * Virtual and physical address limits from 889 * cpuid override previously guessed values. 890 */ 891 cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0); 892 cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8); 893 break; 894 default: 895 break; 896 } 897 898 switch (cpi->cpi_vendor) { 899 case X86_VENDOR_Intel: 900 if (cpi->cpi_maxeax < 4) { 901 cpi->cpi_ncore_per_chip = 1; 902 break; 903 } else { 904 cpi->cpi_ncore_per_chip = 905 BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1; 906 } 907 break; 908 case X86_VENDOR_AMD: 909 if (cpi->cpi_xmaxeax < 0x80000008) { 910 cpi->cpi_ncore_per_chip = 1; 911 break; 912 } else { 913 cpi->cpi_ncore_per_chip = 914 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1; 915 } 916 break; 917 default: 918 cpi->cpi_ncore_per_chip = 1; 919 break; 920 } 921 } 922 923 /* 924 * If more than one core, then this processor is CMP. 925 */ 926 if (cpi->cpi_ncore_per_chip > 1) 927 feature |= X86_CMP; 928 929 /* 930 * If the number of cores is the same as the number 931 * of CPUs, then we cannot have HyperThreading. 932 */ 933 if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip) 934 feature &= ~X86_HTT; 935 936 if ((feature & (X86_HTT | X86_CMP)) == 0) { 937 /* 938 * Single-core single-threaded processors. 939 */ 940 cpi->cpi_chipid = -1; 941 cpi->cpi_clogid = 0; 942 cpi->cpi_coreid = cpu->cpu_id; 943 } else if (cpi->cpi_ncpu_per_chip > 1) { 944 uint_t i; 945 uint_t chipid_shift = 0; 946 uint_t coreid_shift = 0; 947 uint_t apic_id = CPI_APIC_ID(cpi); 948 949 for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1) 950 chipid_shift++; 951 cpi->cpi_chipid = apic_id >> chipid_shift; 952 cpi->cpi_clogid = apic_id & ((1 << chipid_shift) - 1); 953 954 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 955 if (feature & X86_CMP) { 956 /* 957 * Multi-core (and possibly multi-threaded) 958 * processors. 959 */ 960 uint_t ncpu_per_core; 961 if (cpi->cpi_ncore_per_chip == 1) 962 ncpu_per_core = cpi->cpi_ncpu_per_chip; 963 else if (cpi->cpi_ncore_per_chip > 1) 964 ncpu_per_core = cpi->cpi_ncpu_per_chip / 965 cpi->cpi_ncore_per_chip; 966 /* 967 * 8bit APIC IDs on dual core Pentiums 968 * look like this: 969 * 970 * +-----------------------+------+------+ 971 * | Physical Package ID | MC | HT | 972 * +-----------------------+------+------+ 973 * <------- chipid --------> 974 * <------- coreid ---------------> 975 * <--- clogid --> 976 * 977 * Where the number of bits necessary to 978 * represent MC and HT fields together equals 979 * to the minimum number of bits necessary to 980 * store the value of cpi->cpi_ncpu_per_chip. 981 * Of those bits, the MC part uses the number 982 * of bits necessary to store the value of 983 * cpi->cpi_ncore_per_chip. 984 */ 985 for (i = 1; i < ncpu_per_core; i <<= 1) 986 coreid_shift++; 987 cpi->cpi_coreid = apic_id >> coreid_shift; 988 } else if (feature & X86_HTT) { 989 /* 990 * Single-core multi-threaded processors. 991 */ 992 cpi->cpi_coreid = cpi->cpi_chipid; 993 } 994 } else if (cpi->cpi_vendor == X86_VENDOR_AMD) { 995 /* 996 * AMD currently only has dual-core processors with 997 * single-threaded cores. If they ever release 998 * multi-threaded processors, then this code 999 * will have to be updated. 1000 */ 1001 cpi->cpi_coreid = cpu->cpu_id; 1002 } else { 1003 /* 1004 * All other processors are currently 1005 * assumed to have single cores. 1006 */ 1007 cpi->cpi_coreid = cpi->cpi_chipid; 1008 } 1009 } 1010 1011 /* 1012 * Synthesize chip "revision" and socket type 1013 */ 1014 synth_info(cpi); 1015 1016 pass1_done: 1017 cpi->cpi_pass = 1; 1018 return (feature); 1019 } 1020 1021 /* 1022 * Make copies of the cpuid table entries we depend on, in 1023 * part for ease of parsing now, in part so that we have only 1024 * one place to correct any of it, in part for ease of 1025 * later export to userland, and in part so we can look at 1026 * this stuff in a crash dump. 1027 */ 1028 1029 /*ARGSUSED*/ 1030 void 1031 cpuid_pass2(cpu_t *cpu) 1032 { 1033 uint_t n, nmax; 1034 int i; 1035 struct cpuid_regs *cp; 1036 uint8_t *dp; 1037 uint32_t *iptr; 1038 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1039 1040 ASSERT(cpi->cpi_pass == 1); 1041 1042 if (cpi->cpi_maxeax < 1) 1043 goto pass2_done; 1044 1045 if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD) 1046 nmax = NMAX_CPI_STD; 1047 /* 1048 * (We already handled n == 0 and n == 1 in pass 1) 1049 */ 1050 for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) { 1051 cp->cp_eax = n; 1052 (void) __cpuid_insn(cp); 1053 platform_cpuid_mangle(cpi->cpi_vendor, n, cp); 1054 switch (n) { 1055 case 2: 1056 /* 1057 * "the lower 8 bits of the %eax register 1058 * contain a value that identifies the number 1059 * of times the cpuid [instruction] has to be 1060 * executed to obtain a complete image of the 1061 * processor's caching systems." 1062 * 1063 * How *do* they make this stuff up? 1064 */ 1065 cpi->cpi_ncache = sizeof (*cp) * 1066 BITX(cp->cp_eax, 7, 0); 1067 if (cpi->cpi_ncache == 0) 1068 break; 1069 cpi->cpi_ncache--; /* skip count byte */ 1070 1071 /* 1072 * Well, for now, rather than attempt to implement 1073 * this slightly dubious algorithm, we just look 1074 * at the first 15 .. 1075 */ 1076 if (cpi->cpi_ncache > (sizeof (*cp) - 1)) 1077 cpi->cpi_ncache = sizeof (*cp) - 1; 1078 1079 dp = cpi->cpi_cacheinfo; 1080 if (BITX(cp->cp_eax, 31, 31) == 0) { 1081 uint8_t *p = (void *)&cp->cp_eax; 1082 for (i = 1; i < 3; i++) 1083 if (p[i] != 0) 1084 *dp++ = p[i]; 1085 } 1086 if (BITX(cp->cp_ebx, 31, 31) == 0) { 1087 uint8_t *p = (void *)&cp->cp_ebx; 1088 for (i = 0; i < 4; i++) 1089 if (p[i] != 0) 1090 *dp++ = p[i]; 1091 } 1092 if (BITX(cp->cp_ecx, 31, 31) == 0) { 1093 uint8_t *p = (void *)&cp->cp_ecx; 1094 for (i = 0; i < 4; i++) 1095 if (p[i] != 0) 1096 *dp++ = p[i]; 1097 } 1098 if (BITX(cp->cp_edx, 31, 31) == 0) { 1099 uint8_t *p = (void *)&cp->cp_edx; 1100 for (i = 0; i < 4; i++) 1101 if (p[i] != 0) 1102 *dp++ = p[i]; 1103 } 1104 break; 1105 1106 case 3: /* Processor serial number, if PSN supported */ 1107 break; 1108 1109 case 4: /* Deterministic cache parameters */ 1110 break; 1111 1112 case 5: /* Monitor/Mwait parameters */ 1113 1114 /* 1115 * check cpi_mwait.support which was set in cpuid_pass1 1116 */ 1117 if (!(cpi->cpi_mwait.support & MWAIT_SUPPORT)) 1118 break; 1119 1120 cpi->cpi_mwait.mon_min = (size_t)MWAIT_SIZE_MIN(cpi); 1121 cpi->cpi_mwait.mon_max = (size_t)MWAIT_SIZE_MAX(cpi); 1122 if (MWAIT_EXTENSION(cpi)) { 1123 cpi->cpi_mwait.support |= MWAIT_EXTENSIONS; 1124 if (MWAIT_INT_ENABLE(cpi)) 1125 cpi->cpi_mwait.support |= 1126 MWAIT_ECX_INT_ENABLE; 1127 } 1128 break; 1129 1130 default: 1131 break; 1132 } 1133 } 1134 1135 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) 1136 goto pass2_done; 1137 1138 if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD) 1139 nmax = NMAX_CPI_EXTD; 1140 /* 1141 * Copy the extended properties, fixing them as we go. 1142 * (We already handled n == 0 and n == 1 in pass 1) 1143 */ 1144 iptr = (void *)cpi->cpi_brandstr; 1145 for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) { 1146 cp->cp_eax = 0x80000000 + n; 1147 (void) __cpuid_insn(cp); 1148 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000000 + n, cp); 1149 switch (n) { 1150 case 2: 1151 case 3: 1152 case 4: 1153 /* 1154 * Extract the brand string 1155 */ 1156 *iptr++ = cp->cp_eax; 1157 *iptr++ = cp->cp_ebx; 1158 *iptr++ = cp->cp_ecx; 1159 *iptr++ = cp->cp_edx; 1160 break; 1161 case 5: 1162 switch (cpi->cpi_vendor) { 1163 case X86_VENDOR_AMD: 1164 /* 1165 * The Athlon and Duron were the first 1166 * parts to report the sizes of the 1167 * TLB for large pages. Before then, 1168 * we don't trust the data. 1169 */ 1170 if (cpi->cpi_family < 6 || 1171 (cpi->cpi_family == 6 && 1172 cpi->cpi_model < 1)) 1173 cp->cp_eax = 0; 1174 break; 1175 default: 1176 break; 1177 } 1178 break; 1179 case 6: 1180 switch (cpi->cpi_vendor) { 1181 case X86_VENDOR_AMD: 1182 /* 1183 * The Athlon and Duron were the first 1184 * AMD parts with L2 TLB's. 1185 * Before then, don't trust the data. 1186 */ 1187 if (cpi->cpi_family < 6 || 1188 cpi->cpi_family == 6 && 1189 cpi->cpi_model < 1) 1190 cp->cp_eax = cp->cp_ebx = 0; 1191 /* 1192 * AMD Duron rev A0 reports L2 1193 * cache size incorrectly as 1K 1194 * when it is really 64K 1195 */ 1196 if (cpi->cpi_family == 6 && 1197 cpi->cpi_model == 3 && 1198 cpi->cpi_step == 0) { 1199 cp->cp_ecx &= 0xffff; 1200 cp->cp_ecx |= 0x400000; 1201 } 1202 break; 1203 case X86_VENDOR_Cyrix: /* VIA C3 */ 1204 /* 1205 * VIA C3 processors are a bit messed 1206 * up w.r.t. encoding cache sizes in %ecx 1207 */ 1208 if (cpi->cpi_family != 6) 1209 break; 1210 /* 1211 * model 7 and 8 were incorrectly encoded 1212 * 1213 * xxx is model 8 really broken? 1214 */ 1215 if (cpi->cpi_model == 7 || 1216 cpi->cpi_model == 8) 1217 cp->cp_ecx = 1218 BITX(cp->cp_ecx, 31, 24) << 16 | 1219 BITX(cp->cp_ecx, 23, 16) << 12 | 1220 BITX(cp->cp_ecx, 15, 8) << 8 | 1221 BITX(cp->cp_ecx, 7, 0); 1222 /* 1223 * model 9 stepping 1 has wrong associativity 1224 */ 1225 if (cpi->cpi_model == 9 && cpi->cpi_step == 1) 1226 cp->cp_ecx |= 8 << 12; 1227 break; 1228 case X86_VENDOR_Intel: 1229 /* 1230 * Extended L2 Cache features function. 1231 * First appeared on Prescott. 1232 */ 1233 default: 1234 break; 1235 } 1236 break; 1237 default: 1238 break; 1239 } 1240 } 1241 1242 pass2_done: 1243 cpi->cpi_pass = 2; 1244 } 1245 1246 static const char * 1247 intel_cpubrand(const struct cpuid_info *cpi) 1248 { 1249 int i; 1250 1251 if ((x86_feature & X86_CPUID) == 0 || 1252 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 1253 return ("i486"); 1254 1255 switch (cpi->cpi_family) { 1256 case 5: 1257 return ("Intel Pentium(r)"); 1258 case 6: 1259 switch (cpi->cpi_model) { 1260 uint_t celeron, xeon; 1261 const struct cpuid_regs *cp; 1262 case 0: 1263 case 1: 1264 case 2: 1265 return ("Intel Pentium(r) Pro"); 1266 case 3: 1267 case 4: 1268 return ("Intel Pentium(r) II"); 1269 case 6: 1270 return ("Intel Celeron(r)"); 1271 case 5: 1272 case 7: 1273 celeron = xeon = 0; 1274 cp = &cpi->cpi_std[2]; /* cache info */ 1275 1276 for (i = 1; i < 3; i++) { 1277 uint_t tmp; 1278 1279 tmp = (cp->cp_eax >> (8 * i)) & 0xff; 1280 if (tmp == 0x40) 1281 celeron++; 1282 if (tmp >= 0x44 && tmp <= 0x45) 1283 xeon++; 1284 } 1285 1286 for (i = 0; i < 2; i++) { 1287 uint_t tmp; 1288 1289 tmp = (cp->cp_ebx >> (8 * i)) & 0xff; 1290 if (tmp == 0x40) 1291 celeron++; 1292 else if (tmp >= 0x44 && tmp <= 0x45) 1293 xeon++; 1294 } 1295 1296 for (i = 0; i < 4; i++) { 1297 uint_t tmp; 1298 1299 tmp = (cp->cp_ecx >> (8 * i)) & 0xff; 1300 if (tmp == 0x40) 1301 celeron++; 1302 else if (tmp >= 0x44 && tmp <= 0x45) 1303 xeon++; 1304 } 1305 1306 for (i = 0; i < 4; i++) { 1307 uint_t tmp; 1308 1309 tmp = (cp->cp_edx >> (8 * i)) & 0xff; 1310 if (tmp == 0x40) 1311 celeron++; 1312 else if (tmp >= 0x44 && tmp <= 0x45) 1313 xeon++; 1314 } 1315 1316 if (celeron) 1317 return ("Intel Celeron(r)"); 1318 if (xeon) 1319 return (cpi->cpi_model == 5 ? 1320 "Intel Pentium(r) II Xeon(tm)" : 1321 "Intel Pentium(r) III Xeon(tm)"); 1322 return (cpi->cpi_model == 5 ? 1323 "Intel Pentium(r) II or Pentium(r) II Xeon(tm)" : 1324 "Intel Pentium(r) III or Pentium(r) III Xeon(tm)"); 1325 default: 1326 break; 1327 } 1328 default: 1329 break; 1330 } 1331 1332 /* BrandID is present if the field is nonzero */ 1333 if (cpi->cpi_brandid != 0) { 1334 static const struct { 1335 uint_t bt_bid; 1336 const char *bt_str; 1337 } brand_tbl[] = { 1338 { 0x1, "Intel(r) Celeron(r)" }, 1339 { 0x2, "Intel(r) Pentium(r) III" }, 1340 { 0x3, "Intel(r) Pentium(r) III Xeon(tm)" }, 1341 { 0x4, "Intel(r) Pentium(r) III" }, 1342 { 0x6, "Mobile Intel(r) Pentium(r) III" }, 1343 { 0x7, "Mobile Intel(r) Celeron(r)" }, 1344 { 0x8, "Intel(r) Pentium(r) 4" }, 1345 { 0x9, "Intel(r) Pentium(r) 4" }, 1346 { 0xa, "Intel(r) Celeron(r)" }, 1347 { 0xb, "Intel(r) Xeon(tm)" }, 1348 { 0xc, "Intel(r) Xeon(tm) MP" }, 1349 { 0xe, "Mobile Intel(r) Pentium(r) 4" }, 1350 { 0xf, "Mobile Intel(r) Celeron(r)" }, 1351 { 0x11, "Mobile Genuine Intel(r)" }, 1352 { 0x12, "Intel(r) Celeron(r) M" }, 1353 { 0x13, "Mobile Intel(r) Celeron(r)" }, 1354 { 0x14, "Intel(r) Celeron(r)" }, 1355 { 0x15, "Mobile Genuine Intel(r)" }, 1356 { 0x16, "Intel(r) Pentium(r) M" }, 1357 { 0x17, "Mobile Intel(r) Celeron(r)" } 1358 }; 1359 uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]); 1360 uint_t sgn; 1361 1362 sgn = (cpi->cpi_family << 8) | 1363 (cpi->cpi_model << 4) | cpi->cpi_step; 1364 1365 for (i = 0; i < btblmax; i++) 1366 if (brand_tbl[i].bt_bid == cpi->cpi_brandid) 1367 break; 1368 if (i < btblmax) { 1369 if (sgn == 0x6b1 && cpi->cpi_brandid == 3) 1370 return ("Intel(r) Celeron(r)"); 1371 if (sgn < 0xf13 && cpi->cpi_brandid == 0xb) 1372 return ("Intel(r) Xeon(tm) MP"); 1373 if (sgn < 0xf13 && cpi->cpi_brandid == 0xe) 1374 return ("Intel(r) Xeon(tm)"); 1375 return (brand_tbl[i].bt_str); 1376 } 1377 } 1378 1379 return (NULL); 1380 } 1381 1382 static const char * 1383 amd_cpubrand(const struct cpuid_info *cpi) 1384 { 1385 if ((x86_feature & X86_CPUID) == 0 || 1386 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 1387 return ("i486 compatible"); 1388 1389 switch (cpi->cpi_family) { 1390 case 5: 1391 switch (cpi->cpi_model) { 1392 case 0: 1393 case 1: 1394 case 2: 1395 case 3: 1396 case 4: 1397 case 5: 1398 return ("AMD-K5(r)"); 1399 case 6: 1400 case 7: 1401 return ("AMD-K6(r)"); 1402 case 8: 1403 return ("AMD-K6(r)-2"); 1404 case 9: 1405 return ("AMD-K6(r)-III"); 1406 default: 1407 return ("AMD (family 5)"); 1408 } 1409 case 6: 1410 switch (cpi->cpi_model) { 1411 case 1: 1412 return ("AMD-K7(tm)"); 1413 case 0: 1414 case 2: 1415 case 4: 1416 return ("AMD Athlon(tm)"); 1417 case 3: 1418 case 7: 1419 return ("AMD Duron(tm)"); 1420 case 6: 1421 case 8: 1422 case 10: 1423 /* 1424 * Use the L2 cache size to distinguish 1425 */ 1426 return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ? 1427 "AMD Athlon(tm)" : "AMD Duron(tm)"); 1428 default: 1429 return ("AMD (family 6)"); 1430 } 1431 default: 1432 break; 1433 } 1434 1435 if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 && 1436 cpi->cpi_brandid != 0) { 1437 switch (BITX(cpi->cpi_brandid, 7, 5)) { 1438 case 3: 1439 return ("AMD Opteron(tm) UP 1xx"); 1440 case 4: 1441 return ("AMD Opteron(tm) DP 2xx"); 1442 case 5: 1443 return ("AMD Opteron(tm) MP 8xx"); 1444 default: 1445 return ("AMD Opteron(tm)"); 1446 } 1447 } 1448 1449 return (NULL); 1450 } 1451 1452 static const char * 1453 cyrix_cpubrand(struct cpuid_info *cpi, uint_t type) 1454 { 1455 if ((x86_feature & X86_CPUID) == 0 || 1456 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5 || 1457 type == X86_TYPE_CYRIX_486) 1458 return ("i486 compatible"); 1459 1460 switch (type) { 1461 case X86_TYPE_CYRIX_6x86: 1462 return ("Cyrix 6x86"); 1463 case X86_TYPE_CYRIX_6x86L: 1464 return ("Cyrix 6x86L"); 1465 case X86_TYPE_CYRIX_6x86MX: 1466 return ("Cyrix 6x86MX"); 1467 case X86_TYPE_CYRIX_GXm: 1468 return ("Cyrix GXm"); 1469 case X86_TYPE_CYRIX_MediaGX: 1470 return ("Cyrix MediaGX"); 1471 case X86_TYPE_CYRIX_MII: 1472 return ("Cyrix M2"); 1473 case X86_TYPE_VIA_CYRIX_III: 1474 return ("VIA Cyrix M3"); 1475 default: 1476 /* 1477 * Have another wild guess .. 1478 */ 1479 if (cpi->cpi_family == 4 && cpi->cpi_model == 9) 1480 return ("Cyrix 5x86"); 1481 else if (cpi->cpi_family == 5) { 1482 switch (cpi->cpi_model) { 1483 case 2: 1484 return ("Cyrix 6x86"); /* Cyrix M1 */ 1485 case 4: 1486 return ("Cyrix MediaGX"); 1487 default: 1488 break; 1489 } 1490 } else if (cpi->cpi_family == 6) { 1491 switch (cpi->cpi_model) { 1492 case 0: 1493 return ("Cyrix 6x86MX"); /* Cyrix M2? */ 1494 case 5: 1495 case 6: 1496 case 7: 1497 case 8: 1498 case 9: 1499 return ("VIA C3"); 1500 default: 1501 break; 1502 } 1503 } 1504 break; 1505 } 1506 return (NULL); 1507 } 1508 1509 /* 1510 * This only gets called in the case that the CPU extended 1511 * feature brand string (0x80000002, 0x80000003, 0x80000004) 1512 * aren't available, or contain null bytes for some reason. 1513 */ 1514 static void 1515 fabricate_brandstr(struct cpuid_info *cpi) 1516 { 1517 const char *brand = NULL; 1518 1519 switch (cpi->cpi_vendor) { 1520 case X86_VENDOR_Intel: 1521 brand = intel_cpubrand(cpi); 1522 break; 1523 case X86_VENDOR_AMD: 1524 brand = amd_cpubrand(cpi); 1525 break; 1526 case X86_VENDOR_Cyrix: 1527 brand = cyrix_cpubrand(cpi, x86_type); 1528 break; 1529 case X86_VENDOR_NexGen: 1530 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 1531 brand = "NexGen Nx586"; 1532 break; 1533 case X86_VENDOR_Centaur: 1534 if (cpi->cpi_family == 5) 1535 switch (cpi->cpi_model) { 1536 case 4: 1537 brand = "Centaur C6"; 1538 break; 1539 case 8: 1540 brand = "Centaur C2"; 1541 break; 1542 case 9: 1543 brand = "Centaur C3"; 1544 break; 1545 default: 1546 break; 1547 } 1548 break; 1549 case X86_VENDOR_Rise: 1550 if (cpi->cpi_family == 5 && 1551 (cpi->cpi_model == 0 || cpi->cpi_model == 2)) 1552 brand = "Rise mP6"; 1553 break; 1554 case X86_VENDOR_SiS: 1555 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 1556 brand = "SiS 55x"; 1557 break; 1558 case X86_VENDOR_TM: 1559 if (cpi->cpi_family == 5 && cpi->cpi_model == 4) 1560 brand = "Transmeta Crusoe TM3x00 or TM5x00"; 1561 break; 1562 case X86_VENDOR_NSC: 1563 case X86_VENDOR_UMC: 1564 default: 1565 break; 1566 } 1567 if (brand) { 1568 (void) strcpy((char *)cpi->cpi_brandstr, brand); 1569 return; 1570 } 1571 1572 /* 1573 * If all else fails ... 1574 */ 1575 (void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr), 1576 "%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family, 1577 cpi->cpi_model, cpi->cpi_step); 1578 } 1579 1580 /* 1581 * This routine is called just after kernel memory allocation 1582 * becomes available on cpu0, and as part of mp_startup() on 1583 * the other cpus. 1584 * 1585 * Fixup the brand string. 1586 */ 1587 /*ARGSUSED*/ 1588 void 1589 cpuid_pass3(cpu_t *cpu) 1590 { 1591 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1592 1593 ASSERT(cpi->cpi_pass == 2); 1594 1595 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) { 1596 fabricate_brandstr(cpi); 1597 goto pass3_done; 1598 } 1599 1600 /* 1601 * If we successfully extracted a brand string from the cpuid 1602 * instruction, clean it up by removing leading spaces and 1603 * similar junk. 1604 */ 1605 if (cpi->cpi_brandstr[0]) { 1606 size_t maxlen = sizeof (cpi->cpi_brandstr); 1607 char *src, *dst; 1608 1609 dst = src = (char *)cpi->cpi_brandstr; 1610 src[maxlen - 1] = '\0'; 1611 /* 1612 * strip leading spaces 1613 */ 1614 while (*src == ' ') 1615 src++; 1616 /* 1617 * Remove any 'Genuine' or "Authentic" prefixes 1618 */ 1619 if (strncmp(src, "Genuine ", 8) == 0) 1620 src += 8; 1621 if (strncmp(src, "Authentic ", 10) == 0) 1622 src += 10; 1623 1624 /* 1625 * Now do an in-place copy. 1626 * Map (R) to (r) and (TM) to (tm). 1627 * The era of teletypes is long gone, and there's 1628 * -really- no need to shout. 1629 */ 1630 while (*src != '\0') { 1631 if (src[0] == '(') { 1632 if (strncmp(src + 1, "R)", 2) == 0) { 1633 (void) strncpy(dst, "(r)", 3); 1634 src += 3; 1635 dst += 3; 1636 continue; 1637 } 1638 if (strncmp(src + 1, "TM)", 3) == 0) { 1639 (void) strncpy(dst, "(tm)", 4); 1640 src += 4; 1641 dst += 4; 1642 continue; 1643 } 1644 } 1645 *dst++ = *src++; 1646 } 1647 *dst = '\0'; 1648 1649 /* 1650 * Finally, remove any trailing spaces 1651 */ 1652 while (--dst > cpi->cpi_brandstr) 1653 if (*dst == ' ') 1654 *dst = '\0'; 1655 else 1656 break; 1657 } else 1658 fabricate_brandstr(cpi); 1659 1660 pass3_done: 1661 cpi->cpi_pass = 3; 1662 } 1663 1664 /* 1665 * This routine is called out of bind_hwcap() much later in the life 1666 * of the kernel (post_startup()). The job of this routine is to resolve 1667 * the hardware feature support and kernel support for those features into 1668 * what we're actually going to tell applications via the aux vector. 1669 */ 1670 uint_t 1671 cpuid_pass4(cpu_t *cpu) 1672 { 1673 struct cpuid_info *cpi; 1674 uint_t hwcap_flags = 0; 1675 1676 if (cpu == NULL) 1677 cpu = CPU; 1678 cpi = cpu->cpu_m.mcpu_cpi; 1679 1680 ASSERT(cpi->cpi_pass == 3); 1681 1682 if (cpi->cpi_maxeax >= 1) { 1683 uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES]; 1684 uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES]; 1685 1686 *edx = CPI_FEATURES_EDX(cpi); 1687 *ecx = CPI_FEATURES_ECX(cpi); 1688 1689 /* 1690 * [these require explicit kernel support] 1691 */ 1692 if ((x86_feature & X86_SEP) == 0) 1693 *edx &= ~CPUID_INTC_EDX_SEP; 1694 1695 if ((x86_feature & X86_SSE) == 0) 1696 *edx &= ~(CPUID_INTC_EDX_FXSR|CPUID_INTC_EDX_SSE); 1697 if ((x86_feature & X86_SSE2) == 0) 1698 *edx &= ~CPUID_INTC_EDX_SSE2; 1699 1700 if ((x86_feature & X86_HTT) == 0) 1701 *edx &= ~CPUID_INTC_EDX_HTT; 1702 1703 if ((x86_feature & X86_SSE3) == 0) 1704 *ecx &= ~CPUID_INTC_ECX_SSE3; 1705 1706 /* 1707 * [no explicit support required beyond x87 fp context] 1708 */ 1709 if (!fpu_exists) 1710 *edx &= ~(CPUID_INTC_EDX_FPU | CPUID_INTC_EDX_MMX); 1711 1712 /* 1713 * Now map the supported feature vector to things that we 1714 * think userland will care about. 1715 */ 1716 if (*edx & CPUID_INTC_EDX_SEP) 1717 hwcap_flags |= AV_386_SEP; 1718 if (*edx & CPUID_INTC_EDX_SSE) 1719 hwcap_flags |= AV_386_FXSR | AV_386_SSE; 1720 if (*edx & CPUID_INTC_EDX_SSE2) 1721 hwcap_flags |= AV_386_SSE2; 1722 if (*ecx & CPUID_INTC_ECX_SSE3) 1723 hwcap_flags |= AV_386_SSE3; 1724 1725 if (*edx & CPUID_INTC_EDX_FPU) 1726 hwcap_flags |= AV_386_FPU; 1727 if (*edx & CPUID_INTC_EDX_MMX) 1728 hwcap_flags |= AV_386_MMX; 1729 1730 if (*edx & CPUID_INTC_EDX_TSC) 1731 hwcap_flags |= AV_386_TSC; 1732 if (*edx & CPUID_INTC_EDX_CX8) 1733 hwcap_flags |= AV_386_CX8; 1734 if (*edx & CPUID_INTC_EDX_CMOV) 1735 hwcap_flags |= AV_386_CMOV; 1736 if (*ecx & CPUID_INTC_ECX_MON) 1737 hwcap_flags |= AV_386_MON; 1738 if (*ecx & CPUID_INTC_ECX_CX16) 1739 hwcap_flags |= AV_386_CX16; 1740 } 1741 1742 if (x86_feature & X86_HTT) 1743 hwcap_flags |= AV_386_PAUSE; 1744 1745 if (cpi->cpi_xmaxeax < 0x80000001) 1746 goto pass4_done; 1747 1748 switch (cpi->cpi_vendor) { 1749 struct cpuid_regs cp; 1750 uint32_t *edx, *ecx; 1751 1752 case X86_VENDOR_Intel: 1753 /* 1754 * Seems like Intel duplicated what we necessary 1755 * here to make the initial crop of 64-bit OS's work. 1756 * Hopefully, those are the only "extended" bits 1757 * they'll add. 1758 */ 1759 /*FALLTHROUGH*/ 1760 1761 case X86_VENDOR_AMD: 1762 edx = &cpi->cpi_support[AMD_EDX_FEATURES]; 1763 ecx = &cpi->cpi_support[AMD_ECX_FEATURES]; 1764 1765 *edx = CPI_FEATURES_XTD_EDX(cpi); 1766 *ecx = CPI_FEATURES_XTD_ECX(cpi); 1767 1768 /* 1769 * [these features require explicit kernel support] 1770 */ 1771 switch (cpi->cpi_vendor) { 1772 case X86_VENDOR_Intel: 1773 break; 1774 1775 case X86_VENDOR_AMD: 1776 if ((x86_feature & X86_TSCP) == 0) 1777 *edx &= ~CPUID_AMD_EDX_TSCP; 1778 break; 1779 1780 default: 1781 break; 1782 } 1783 1784 /* 1785 * [no explicit support required beyond 1786 * x87 fp context and exception handlers] 1787 */ 1788 if (!fpu_exists) 1789 *edx &= ~(CPUID_AMD_EDX_MMXamd | 1790 CPUID_AMD_EDX_3DNow | CPUID_AMD_EDX_3DNowx); 1791 1792 if ((x86_feature & X86_NX) == 0) 1793 *edx &= ~CPUID_AMD_EDX_NX; 1794 #if !defined(__amd64) 1795 *edx &= ~CPUID_AMD_EDX_LM; 1796 #endif 1797 /* 1798 * Now map the supported feature vector to 1799 * things that we think userland will care about. 1800 */ 1801 #if defined(__amd64) 1802 if (*edx & CPUID_AMD_EDX_SYSC) 1803 hwcap_flags |= AV_386_AMD_SYSC; 1804 #endif 1805 if (*edx & CPUID_AMD_EDX_MMXamd) 1806 hwcap_flags |= AV_386_AMD_MMX; 1807 if (*edx & CPUID_AMD_EDX_3DNow) 1808 hwcap_flags |= AV_386_AMD_3DNow; 1809 if (*edx & CPUID_AMD_EDX_3DNowx) 1810 hwcap_flags |= AV_386_AMD_3DNowx; 1811 1812 switch (cpi->cpi_vendor) { 1813 case X86_VENDOR_AMD: 1814 if (*edx & CPUID_AMD_EDX_TSCP) 1815 hwcap_flags |= AV_386_TSCP; 1816 if (*ecx & CPUID_AMD_ECX_AHF64) 1817 hwcap_flags |= AV_386_AHF; 1818 break; 1819 1820 case X86_VENDOR_Intel: 1821 /* 1822 * Aarrgh. 1823 * Intel uses a different bit in the same word. 1824 */ 1825 if (*ecx & CPUID_INTC_ECX_AHF64) 1826 hwcap_flags |= AV_386_AHF; 1827 break; 1828 1829 default: 1830 break; 1831 } 1832 break; 1833 1834 case X86_VENDOR_TM: 1835 cp.cp_eax = 0x80860001; 1836 (void) __cpuid_insn(&cp); 1837 cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx; 1838 break; 1839 1840 default: 1841 break; 1842 } 1843 1844 pass4_done: 1845 cpi->cpi_pass = 4; 1846 return (hwcap_flags); 1847 } 1848 1849 1850 /* 1851 * Simulate the cpuid instruction using the data we previously 1852 * captured about this CPU. We try our best to return the truth 1853 * about the hardware, independently of kernel support. 1854 */ 1855 uint32_t 1856 cpuid_insn(cpu_t *cpu, struct cpuid_regs *cp) 1857 { 1858 struct cpuid_info *cpi; 1859 struct cpuid_regs *xcp; 1860 1861 if (cpu == NULL) 1862 cpu = CPU; 1863 cpi = cpu->cpu_m.mcpu_cpi; 1864 1865 ASSERT(cpuid_checkpass(cpu, 3)); 1866 1867 /* 1868 * CPUID data is cached in two separate places: cpi_std for standard 1869 * CPUID functions, and cpi_extd for extended CPUID functions. 1870 */ 1871 if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD) 1872 xcp = &cpi->cpi_std[cp->cp_eax]; 1873 else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax && 1874 cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD) 1875 xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000]; 1876 else 1877 /* 1878 * The caller is asking for data from an input parameter which 1879 * the kernel has not cached. In this case we go fetch from 1880 * the hardware and return the data directly to the user. 1881 */ 1882 return (__cpuid_insn(cp)); 1883 1884 cp->cp_eax = xcp->cp_eax; 1885 cp->cp_ebx = xcp->cp_ebx; 1886 cp->cp_ecx = xcp->cp_ecx; 1887 cp->cp_edx = xcp->cp_edx; 1888 return (cp->cp_eax); 1889 } 1890 1891 int 1892 cpuid_checkpass(cpu_t *cpu, int pass) 1893 { 1894 return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL && 1895 cpu->cpu_m.mcpu_cpi->cpi_pass >= pass); 1896 } 1897 1898 int 1899 cpuid_getbrandstr(cpu_t *cpu, char *s, size_t n) 1900 { 1901 ASSERT(cpuid_checkpass(cpu, 3)); 1902 1903 return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr)); 1904 } 1905 1906 int 1907 cpuid_is_cmt(cpu_t *cpu) 1908 { 1909 if (cpu == NULL) 1910 cpu = CPU; 1911 1912 ASSERT(cpuid_checkpass(cpu, 1)); 1913 1914 return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0); 1915 } 1916 1917 /* 1918 * AMD and Intel both implement the 64-bit variant of the syscall 1919 * instruction (syscallq), so if there's -any- support for syscall, 1920 * cpuid currently says "yes, we support this". 1921 * 1922 * However, Intel decided to -not- implement the 32-bit variant of the 1923 * syscall instruction, so we provide a predicate to allow our caller 1924 * to test that subtlety here. 1925 */ 1926 /*ARGSUSED*/ 1927 int 1928 cpuid_syscall32_insn(cpu_t *cpu) 1929 { 1930 ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1)); 1931 1932 if (cpu == NULL) 1933 cpu = CPU; 1934 1935 /*CSTYLED*/ 1936 { 1937 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1938 1939 if (cpi->cpi_vendor == X86_VENDOR_AMD && 1940 cpi->cpi_xmaxeax >= 0x80000001 && 1941 (CPI_FEATURES_XTD_EDX(cpi) & CPUID_AMD_EDX_SYSC)) 1942 return (1); 1943 } 1944 return (0); 1945 } 1946 1947 int 1948 cpuid_getidstr(cpu_t *cpu, char *s, size_t n) 1949 { 1950 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1951 1952 static const char fmt[] = 1953 "x86 (%s %X family %d model %d step %d clock %d MHz)"; 1954 static const char fmt_ht[] = 1955 "x86 (chipid 0x%x %s %X family %d model %d step %d clock %d MHz)"; 1956 1957 ASSERT(cpuid_checkpass(cpu, 1)); 1958 1959 if (cpuid_is_cmt(cpu)) 1960 return (snprintf(s, n, fmt_ht, cpi->cpi_chipid, 1961 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, 1962 cpi->cpi_family, cpi->cpi_model, 1963 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 1964 return (snprintf(s, n, fmt, 1965 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, 1966 cpi->cpi_family, cpi->cpi_model, 1967 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 1968 } 1969 1970 const char * 1971 cpuid_getvendorstr(cpu_t *cpu) 1972 { 1973 ASSERT(cpuid_checkpass(cpu, 1)); 1974 return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr); 1975 } 1976 1977 uint_t 1978 cpuid_getvendor(cpu_t *cpu) 1979 { 1980 ASSERT(cpuid_checkpass(cpu, 1)); 1981 return (cpu->cpu_m.mcpu_cpi->cpi_vendor); 1982 } 1983 1984 uint_t 1985 cpuid_getfamily(cpu_t *cpu) 1986 { 1987 ASSERT(cpuid_checkpass(cpu, 1)); 1988 return (cpu->cpu_m.mcpu_cpi->cpi_family); 1989 } 1990 1991 uint_t 1992 cpuid_getmodel(cpu_t *cpu) 1993 { 1994 ASSERT(cpuid_checkpass(cpu, 1)); 1995 return (cpu->cpu_m.mcpu_cpi->cpi_model); 1996 } 1997 1998 uint_t 1999 cpuid_get_ncpu_per_chip(cpu_t *cpu) 2000 { 2001 ASSERT(cpuid_checkpass(cpu, 1)); 2002 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip); 2003 } 2004 2005 uint_t 2006 cpuid_get_ncore_per_chip(cpu_t *cpu) 2007 { 2008 ASSERT(cpuid_checkpass(cpu, 1)); 2009 return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip); 2010 } 2011 2012 uint_t 2013 cpuid_getstep(cpu_t *cpu) 2014 { 2015 ASSERT(cpuid_checkpass(cpu, 1)); 2016 return (cpu->cpu_m.mcpu_cpi->cpi_step); 2017 } 2018 2019 uint32_t 2020 cpuid_getchiprev(struct cpu *cpu) 2021 { 2022 ASSERT(cpuid_checkpass(cpu, 1)); 2023 return (cpu->cpu_m.mcpu_cpi->cpi_chiprev); 2024 } 2025 2026 const char * 2027 cpuid_getchiprevstr(struct cpu *cpu) 2028 { 2029 ASSERT(cpuid_checkpass(cpu, 1)); 2030 return (cpu->cpu_m.mcpu_cpi->cpi_chiprevstr); 2031 } 2032 2033 uint32_t 2034 cpuid_getsockettype(struct cpu *cpu) 2035 { 2036 ASSERT(cpuid_checkpass(cpu, 1)); 2037 return (cpu->cpu_m.mcpu_cpi->cpi_socket); 2038 } 2039 2040 int 2041 cpuid_get_chipid(cpu_t *cpu) 2042 { 2043 ASSERT(cpuid_checkpass(cpu, 1)); 2044 2045 if (cpuid_is_cmt(cpu)) 2046 return (cpu->cpu_m.mcpu_cpi->cpi_chipid); 2047 return (cpu->cpu_id); 2048 } 2049 2050 id_t 2051 cpuid_get_coreid(cpu_t *cpu) 2052 { 2053 ASSERT(cpuid_checkpass(cpu, 1)); 2054 return (cpu->cpu_m.mcpu_cpi->cpi_coreid); 2055 } 2056 2057 int 2058 cpuid_get_clogid(cpu_t *cpu) 2059 { 2060 ASSERT(cpuid_checkpass(cpu, 1)); 2061 return (cpu->cpu_m.mcpu_cpi->cpi_clogid); 2062 } 2063 2064 void 2065 cpuid_get_addrsize(cpu_t *cpu, uint_t *pabits, uint_t *vabits) 2066 { 2067 struct cpuid_info *cpi; 2068 2069 if (cpu == NULL) 2070 cpu = CPU; 2071 cpi = cpu->cpu_m.mcpu_cpi; 2072 2073 ASSERT(cpuid_checkpass(cpu, 1)); 2074 2075 if (pabits) 2076 *pabits = cpi->cpi_pabits; 2077 if (vabits) 2078 *vabits = cpi->cpi_vabits; 2079 } 2080 2081 /* 2082 * Returns the number of data TLB entries for a corresponding 2083 * pagesize. If it can't be computed, or isn't known, the 2084 * routine returns zero. If you ask about an architecturally 2085 * impossible pagesize, the routine will panic (so that the 2086 * hat implementor knows that things are inconsistent.) 2087 */ 2088 uint_t 2089 cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize) 2090 { 2091 struct cpuid_info *cpi; 2092 uint_t dtlb_nent = 0; 2093 2094 if (cpu == NULL) 2095 cpu = CPU; 2096 cpi = cpu->cpu_m.mcpu_cpi; 2097 2098 ASSERT(cpuid_checkpass(cpu, 1)); 2099 2100 /* 2101 * Check the L2 TLB info 2102 */ 2103 if (cpi->cpi_xmaxeax >= 0x80000006) { 2104 struct cpuid_regs *cp = &cpi->cpi_extd[6]; 2105 2106 switch (pagesize) { 2107 2108 case 4 * 1024: 2109 /* 2110 * All zero in the top 16 bits of the register 2111 * indicates a unified TLB. Size is in low 16 bits. 2112 */ 2113 if ((cp->cp_ebx & 0xffff0000) == 0) 2114 dtlb_nent = cp->cp_ebx & 0x0000ffff; 2115 else 2116 dtlb_nent = BITX(cp->cp_ebx, 27, 16); 2117 break; 2118 2119 case 2 * 1024 * 1024: 2120 if ((cp->cp_eax & 0xffff0000) == 0) 2121 dtlb_nent = cp->cp_eax & 0x0000ffff; 2122 else 2123 dtlb_nent = BITX(cp->cp_eax, 27, 16); 2124 break; 2125 2126 default: 2127 panic("unknown L2 pagesize"); 2128 /*NOTREACHED*/ 2129 } 2130 } 2131 2132 if (dtlb_nent != 0) 2133 return (dtlb_nent); 2134 2135 /* 2136 * No L2 TLB support for this size, try L1. 2137 */ 2138 if (cpi->cpi_xmaxeax >= 0x80000005) { 2139 struct cpuid_regs *cp = &cpi->cpi_extd[5]; 2140 2141 switch (pagesize) { 2142 case 4 * 1024: 2143 dtlb_nent = BITX(cp->cp_ebx, 23, 16); 2144 break; 2145 case 2 * 1024 * 1024: 2146 dtlb_nent = BITX(cp->cp_eax, 23, 16); 2147 break; 2148 default: 2149 panic("unknown L1 d-TLB pagesize"); 2150 /*NOTREACHED*/ 2151 } 2152 } 2153 2154 return (dtlb_nent); 2155 } 2156 2157 /* 2158 * Return 0 if the erratum is not present or not applicable, positive 2159 * if it is, and negative if the status of the erratum is unknown. 2160 * 2161 * See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm) 2162 * Processors" #25759, Rev 3.57, August 2005 2163 */ 2164 int 2165 cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum) 2166 { 2167 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2168 uint_t eax; 2169 2170 /* 2171 * Bail out if this CPU isn't an AMD CPU, or if it's 2172 * a legacy (32-bit) AMD CPU. 2173 */ 2174 if (cpi->cpi_vendor != X86_VENDOR_AMD || 2175 cpi->cpi_family == 4 || cpi->cpi_family == 5 || 2176 cpi->cpi_family == 6) 2177 2178 return (0); 2179 2180 eax = cpi->cpi_std[1].cp_eax; 2181 2182 #define SH_B0(eax) (eax == 0xf40 || eax == 0xf50) 2183 #define SH_B3(eax) (eax == 0xf51) 2184 #define B(eax) (SH_B0(eax) || SH_B3(eax)) 2185 2186 #define SH_C0(eax) (eax == 0xf48 || eax == 0xf58) 2187 2188 #define SH_CG(eax) (eax == 0xf4a || eax == 0xf5a || eax == 0xf7a) 2189 #define DH_CG(eax) (eax == 0xfc0 || eax == 0xfe0 || eax == 0xff0) 2190 #define CH_CG(eax) (eax == 0xf82 || eax == 0xfb2) 2191 #define CG(eax) (SH_CG(eax) || DH_CG(eax) || CH_CG(eax)) 2192 2193 #define SH_D0(eax) (eax == 0x10f40 || eax == 0x10f50 || eax == 0x10f70) 2194 #define DH_D0(eax) (eax == 0x10fc0 || eax == 0x10ff0) 2195 #define CH_D0(eax) (eax == 0x10f80 || eax == 0x10fb0) 2196 #define D0(eax) (SH_D0(eax) || DH_D0(eax) || CH_D0(eax)) 2197 2198 #define SH_E0(eax) (eax == 0x20f50 || eax == 0x20f40 || eax == 0x20f70) 2199 #define JH_E1(eax) (eax == 0x20f10) /* JH8_E0 had 0x20f30 */ 2200 #define DH_E3(eax) (eax == 0x20fc0 || eax == 0x20ff0) 2201 #define SH_E4(eax) (eax == 0x20f51 || eax == 0x20f71) 2202 #define BH_E4(eax) (eax == 0x20fb1) 2203 #define SH_E5(eax) (eax == 0x20f42) 2204 #define DH_E6(eax) (eax == 0x20ff2 || eax == 0x20fc2) 2205 #define JH_E6(eax) (eax == 0x20f12 || eax == 0x20f32) 2206 #define EX(eax) (SH_E0(eax) || JH_E1(eax) || DH_E3(eax) || \ 2207 SH_E4(eax) || BH_E4(eax) || SH_E5(eax) || \ 2208 DH_E6(eax) || JH_E6(eax)) 2209 2210 switch (erratum) { 2211 case 1: 2212 return (cpi->cpi_family < 0x10); 2213 case 51: /* what does the asterisk mean? */ 2214 return (B(eax) || SH_C0(eax) || CG(eax)); 2215 case 52: 2216 return (B(eax)); 2217 case 57: 2218 return (cpi->cpi_family <= 0x10); 2219 case 58: 2220 return (B(eax)); 2221 case 60: 2222 return (cpi->cpi_family <= 0x10); 2223 case 61: 2224 case 62: 2225 case 63: 2226 case 64: 2227 case 65: 2228 case 66: 2229 case 68: 2230 case 69: 2231 case 70: 2232 case 71: 2233 return (B(eax)); 2234 case 72: 2235 return (SH_B0(eax)); 2236 case 74: 2237 return (B(eax)); 2238 case 75: 2239 return (cpi->cpi_family < 0x10); 2240 case 76: 2241 return (B(eax)); 2242 case 77: 2243 return (cpi->cpi_family <= 0x10); 2244 case 78: 2245 return (B(eax) || SH_C0(eax)); 2246 case 79: 2247 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2248 case 80: 2249 case 81: 2250 case 82: 2251 return (B(eax)); 2252 case 83: 2253 return (B(eax) || SH_C0(eax) || CG(eax)); 2254 case 85: 2255 return (cpi->cpi_family < 0x10); 2256 case 86: 2257 return (SH_C0(eax) || CG(eax)); 2258 case 88: 2259 #if !defined(__amd64) 2260 return (0); 2261 #else 2262 return (B(eax) || SH_C0(eax)); 2263 #endif 2264 case 89: 2265 return (cpi->cpi_family < 0x10); 2266 case 90: 2267 return (B(eax) || SH_C0(eax) || CG(eax)); 2268 case 91: 2269 case 92: 2270 return (B(eax) || SH_C0(eax)); 2271 case 93: 2272 return (SH_C0(eax)); 2273 case 94: 2274 return (B(eax) || SH_C0(eax) || CG(eax)); 2275 case 95: 2276 #if !defined(__amd64) 2277 return (0); 2278 #else 2279 return (B(eax) || SH_C0(eax)); 2280 #endif 2281 case 96: 2282 return (B(eax) || SH_C0(eax) || CG(eax)); 2283 case 97: 2284 case 98: 2285 return (SH_C0(eax) || CG(eax)); 2286 case 99: 2287 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2288 case 100: 2289 return (B(eax) || SH_C0(eax)); 2290 case 101: 2291 case 103: 2292 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2293 case 104: 2294 return (SH_C0(eax) || CG(eax) || D0(eax)); 2295 case 105: 2296 case 106: 2297 case 107: 2298 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2299 case 108: 2300 return (DH_CG(eax)); 2301 case 109: 2302 return (SH_C0(eax) || CG(eax) || D0(eax)); 2303 case 110: 2304 return (D0(eax) || EX(eax)); 2305 case 111: 2306 return (CG(eax)); 2307 case 112: 2308 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2309 case 113: 2310 return (eax == 0x20fc0); 2311 case 114: 2312 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 2313 case 115: 2314 return (SH_E0(eax) || JH_E1(eax)); 2315 case 116: 2316 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 2317 case 117: 2318 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2319 case 118: 2320 return (SH_E0(eax) || JH_E1(eax) || SH_E4(eax) || BH_E4(eax) || 2321 JH_E6(eax)); 2322 case 121: 2323 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2324 case 122: 2325 return (cpi->cpi_family < 0x10); 2326 case 123: 2327 return (JH_E1(eax) || BH_E4(eax) || JH_E6(eax)); 2328 case 131: 2329 return (cpi->cpi_family < 0x10); 2330 case 6336786: 2331 /* 2332 * Test for AdvPowerMgmtInfo.TscPStateInvariant 2333 * if this is a K8 family or newer processor 2334 */ 2335 if (CPI_FAMILY(cpi) == 0xf) { 2336 struct cpuid_regs regs; 2337 regs.cp_eax = 0x80000007; 2338 (void) __cpuid_insn(®s); 2339 return (!(regs.cp_edx & 0x100)); 2340 } 2341 return (0); 2342 case 6323525: 2343 return (((((eax >> 12) & 0xff00) + (eax & 0xf00)) | 2344 (((eax >> 4) & 0xf) | ((eax >> 12) & 0xf0))) < 0xf40); 2345 2346 default: 2347 return (-1); 2348 } 2349 } 2350 2351 static const char assoc_str[] = "associativity"; 2352 static const char line_str[] = "line-size"; 2353 static const char size_str[] = "size"; 2354 2355 static void 2356 add_cache_prop(dev_info_t *devi, const char *label, const char *type, 2357 uint32_t val) 2358 { 2359 char buf[128]; 2360 2361 /* 2362 * ndi_prop_update_int() is used because it is desirable for 2363 * DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set. 2364 */ 2365 if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf)) 2366 (void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val); 2367 } 2368 2369 /* 2370 * Intel-style cache/tlb description 2371 * 2372 * Standard cpuid level 2 gives a randomly ordered 2373 * selection of tags that index into a table that describes 2374 * cache and tlb properties. 2375 */ 2376 2377 static const char l1_icache_str[] = "l1-icache"; 2378 static const char l1_dcache_str[] = "l1-dcache"; 2379 static const char l2_cache_str[] = "l2-cache"; 2380 static const char l3_cache_str[] = "l3-cache"; 2381 static const char itlb4k_str[] = "itlb-4K"; 2382 static const char dtlb4k_str[] = "dtlb-4K"; 2383 static const char itlb4M_str[] = "itlb-4M"; 2384 static const char dtlb4M_str[] = "dtlb-4M"; 2385 static const char itlb424_str[] = "itlb-4K-2M-4M"; 2386 static const char dtlb44_str[] = "dtlb-4K-4M"; 2387 static const char sl1_dcache_str[] = "sectored-l1-dcache"; 2388 static const char sl2_cache_str[] = "sectored-l2-cache"; 2389 static const char itrace_str[] = "itrace-cache"; 2390 static const char sl3_cache_str[] = "sectored-l3-cache"; 2391 2392 static const struct cachetab { 2393 uint8_t ct_code; 2394 uint8_t ct_assoc; 2395 uint16_t ct_line_size; 2396 size_t ct_size; 2397 const char *ct_label; 2398 } intel_ctab[] = { 2399 /* maintain descending order! */ 2400 { 0xb4, 4, 0, 256, dtlb4k_str }, 2401 { 0xb3, 4, 0, 128, dtlb4k_str }, 2402 { 0xb0, 4, 0, 128, itlb4k_str }, 2403 { 0x87, 8, 64, 1024*1024, l2_cache_str}, 2404 { 0x86, 4, 64, 512*1024, l2_cache_str}, 2405 { 0x85, 8, 32, 2*1024*1024, l2_cache_str}, 2406 { 0x84, 8, 32, 1024*1024, l2_cache_str}, 2407 { 0x83, 8, 32, 512*1024, l2_cache_str}, 2408 { 0x82, 8, 32, 256*1024, l2_cache_str}, 2409 { 0x7f, 2, 64, 512*1024, l2_cache_str}, 2410 { 0x7d, 8, 64, 2*1024*1024, sl2_cache_str}, 2411 { 0x7c, 8, 64, 1024*1024, sl2_cache_str}, 2412 { 0x7b, 8, 64, 512*1024, sl2_cache_str}, 2413 { 0x7a, 8, 64, 256*1024, sl2_cache_str}, 2414 { 0x79, 8, 64, 128*1024, sl2_cache_str}, 2415 { 0x78, 8, 64, 1024*1024, l2_cache_str}, 2416 { 0x73, 8, 0, 64*1024, itrace_str}, 2417 { 0x72, 8, 0, 32*1024, itrace_str}, 2418 { 0x71, 8, 0, 16*1024, itrace_str}, 2419 { 0x70, 8, 0, 12*1024, itrace_str}, 2420 { 0x68, 4, 64, 32*1024, sl1_dcache_str}, 2421 { 0x67, 4, 64, 16*1024, sl1_dcache_str}, 2422 { 0x66, 4, 64, 8*1024, sl1_dcache_str}, 2423 { 0x60, 8, 64, 16*1024, sl1_dcache_str}, 2424 { 0x5d, 0, 0, 256, dtlb44_str}, 2425 { 0x5c, 0, 0, 128, dtlb44_str}, 2426 { 0x5b, 0, 0, 64, dtlb44_str}, 2427 { 0x52, 0, 0, 256, itlb424_str}, 2428 { 0x51, 0, 0, 128, itlb424_str}, 2429 { 0x50, 0, 0, 64, itlb424_str}, 2430 { 0x4d, 16, 64, 16*1024*1024, l3_cache_str}, 2431 { 0x4c, 12, 64, 12*1024*1024, l3_cache_str}, 2432 { 0x4b, 16, 64, 8*1024*1024, l3_cache_str}, 2433 { 0x4a, 12, 64, 6*1024*1024, l3_cache_str}, 2434 { 0x49, 16, 64, 4*1024*1024, l3_cache_str}, 2435 { 0x47, 8, 64, 8*1024*1024, l3_cache_str}, 2436 { 0x46, 4, 64, 4*1024*1024, l3_cache_str}, 2437 { 0x45, 4, 32, 2*1024*1024, l2_cache_str}, 2438 { 0x44, 4, 32, 1024*1024, l2_cache_str}, 2439 { 0x43, 4, 32, 512*1024, l2_cache_str}, 2440 { 0x42, 4, 32, 256*1024, l2_cache_str}, 2441 { 0x41, 4, 32, 128*1024, l2_cache_str}, 2442 { 0x3e, 4, 64, 512*1024, sl2_cache_str}, 2443 { 0x3d, 6, 64, 384*1024, sl2_cache_str}, 2444 { 0x3c, 4, 64, 256*1024, sl2_cache_str}, 2445 { 0x3b, 2, 64, 128*1024, sl2_cache_str}, 2446 { 0x3a, 6, 64, 192*1024, sl2_cache_str}, 2447 { 0x39, 4, 64, 128*1024, sl2_cache_str}, 2448 { 0x30, 8, 64, 32*1024, l1_icache_str}, 2449 { 0x2c, 8, 64, 32*1024, l1_dcache_str}, 2450 { 0x29, 8, 64, 4096*1024, sl3_cache_str}, 2451 { 0x25, 8, 64, 2048*1024, sl3_cache_str}, 2452 { 0x23, 8, 64, 1024*1024, sl3_cache_str}, 2453 { 0x22, 4, 64, 512*1024, sl3_cache_str}, 2454 { 0x0c, 4, 32, 16*1024, l1_dcache_str}, 2455 { 0x0b, 4, 0, 4, itlb4M_str}, 2456 { 0x0a, 2, 32, 8*1024, l1_dcache_str}, 2457 { 0x08, 4, 32, 16*1024, l1_icache_str}, 2458 { 0x06, 4, 32, 8*1024, l1_icache_str}, 2459 { 0x04, 4, 0, 8, dtlb4M_str}, 2460 { 0x03, 4, 0, 64, dtlb4k_str}, 2461 { 0x02, 4, 0, 2, itlb4M_str}, 2462 { 0x01, 4, 0, 32, itlb4k_str}, 2463 { 0 } 2464 }; 2465 2466 static const struct cachetab cyrix_ctab[] = { 2467 { 0x70, 4, 0, 32, "tlb-4K" }, 2468 { 0x80, 4, 16, 16*1024, "l1-cache" }, 2469 { 0 } 2470 }; 2471 2472 /* 2473 * Search a cache table for a matching entry 2474 */ 2475 static const struct cachetab * 2476 find_cacheent(const struct cachetab *ct, uint_t code) 2477 { 2478 if (code != 0) { 2479 for (; ct->ct_code != 0; ct++) 2480 if (ct->ct_code <= code) 2481 break; 2482 if (ct->ct_code == code) 2483 return (ct); 2484 } 2485 return (NULL); 2486 } 2487 2488 /* 2489 * Walk the cacheinfo descriptor, applying 'func' to every valid element 2490 * The walk is terminated if the walker returns non-zero. 2491 */ 2492 static void 2493 intel_walk_cacheinfo(struct cpuid_info *cpi, 2494 void *arg, int (*func)(void *, const struct cachetab *)) 2495 { 2496 const struct cachetab *ct; 2497 uint8_t *dp; 2498 int i; 2499 2500 if ((dp = cpi->cpi_cacheinfo) == NULL) 2501 return; 2502 for (i = 0; i < cpi->cpi_ncache; i++, dp++) 2503 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { 2504 if (func(arg, ct) != 0) 2505 break; 2506 } 2507 } 2508 2509 /* 2510 * (Like the Intel one, except for Cyrix CPUs) 2511 */ 2512 static void 2513 cyrix_walk_cacheinfo(struct cpuid_info *cpi, 2514 void *arg, int (*func)(void *, const struct cachetab *)) 2515 { 2516 const struct cachetab *ct; 2517 uint8_t *dp; 2518 int i; 2519 2520 if ((dp = cpi->cpi_cacheinfo) == NULL) 2521 return; 2522 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { 2523 /* 2524 * Search Cyrix-specific descriptor table first .. 2525 */ 2526 if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) { 2527 if (func(arg, ct) != 0) 2528 break; 2529 continue; 2530 } 2531 /* 2532 * .. else fall back to the Intel one 2533 */ 2534 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { 2535 if (func(arg, ct) != 0) 2536 break; 2537 continue; 2538 } 2539 } 2540 } 2541 2542 /* 2543 * A cacheinfo walker that adds associativity, line-size, and size properties 2544 * to the devinfo node it is passed as an argument. 2545 */ 2546 static int 2547 add_cacheent_props(void *arg, const struct cachetab *ct) 2548 { 2549 dev_info_t *devi = arg; 2550 2551 add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc); 2552 if (ct->ct_line_size != 0) 2553 add_cache_prop(devi, ct->ct_label, line_str, 2554 ct->ct_line_size); 2555 add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size); 2556 return (0); 2557 } 2558 2559 static const char fully_assoc[] = "fully-associative?"; 2560 2561 /* 2562 * AMD style cache/tlb description 2563 * 2564 * Extended functions 5 and 6 directly describe properties of 2565 * tlbs and various cache levels. 2566 */ 2567 static void 2568 add_amd_assoc(dev_info_t *devi, const char *label, uint_t assoc) 2569 { 2570 switch (assoc) { 2571 case 0: /* reserved; ignore */ 2572 break; 2573 default: 2574 add_cache_prop(devi, label, assoc_str, assoc); 2575 break; 2576 case 0xff: 2577 add_cache_prop(devi, label, fully_assoc, 1); 2578 break; 2579 } 2580 } 2581 2582 static void 2583 add_amd_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 2584 { 2585 if (size == 0) 2586 return; 2587 add_cache_prop(devi, label, size_str, size); 2588 add_amd_assoc(devi, label, assoc); 2589 } 2590 2591 static void 2592 add_amd_cache(dev_info_t *devi, const char *label, 2593 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 2594 { 2595 if (size == 0 || line_size == 0) 2596 return; 2597 add_amd_assoc(devi, label, assoc); 2598 /* 2599 * Most AMD parts have a sectored cache. Multiple cache lines are 2600 * associated with each tag. A sector consists of all cache lines 2601 * associated with a tag. For example, the AMD K6-III has a sector 2602 * size of 2 cache lines per tag. 2603 */ 2604 if (lines_per_tag != 0) 2605 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 2606 add_cache_prop(devi, label, line_str, line_size); 2607 add_cache_prop(devi, label, size_str, size * 1024); 2608 } 2609 2610 static void 2611 add_amd_l2_assoc(dev_info_t *devi, const char *label, uint_t assoc) 2612 { 2613 switch (assoc) { 2614 case 0: /* off */ 2615 break; 2616 case 1: 2617 case 2: 2618 case 4: 2619 add_cache_prop(devi, label, assoc_str, assoc); 2620 break; 2621 case 6: 2622 add_cache_prop(devi, label, assoc_str, 8); 2623 break; 2624 case 8: 2625 add_cache_prop(devi, label, assoc_str, 16); 2626 break; 2627 case 0xf: 2628 add_cache_prop(devi, label, fully_assoc, 1); 2629 break; 2630 default: /* reserved; ignore */ 2631 break; 2632 } 2633 } 2634 2635 static void 2636 add_amd_l2_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 2637 { 2638 if (size == 0 || assoc == 0) 2639 return; 2640 add_amd_l2_assoc(devi, label, assoc); 2641 add_cache_prop(devi, label, size_str, size); 2642 } 2643 2644 static void 2645 add_amd_l2_cache(dev_info_t *devi, const char *label, 2646 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 2647 { 2648 if (size == 0 || assoc == 0 || line_size == 0) 2649 return; 2650 add_amd_l2_assoc(devi, label, assoc); 2651 if (lines_per_tag != 0) 2652 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 2653 add_cache_prop(devi, label, line_str, line_size); 2654 add_cache_prop(devi, label, size_str, size * 1024); 2655 } 2656 2657 static void 2658 amd_cache_info(struct cpuid_info *cpi, dev_info_t *devi) 2659 { 2660 struct cpuid_regs *cp; 2661 2662 if (cpi->cpi_xmaxeax < 0x80000005) 2663 return; 2664 cp = &cpi->cpi_extd[5]; 2665 2666 /* 2667 * 4M/2M L1 TLB configuration 2668 * 2669 * We report the size for 2M pages because AMD uses two 2670 * TLB entries for one 4M page. 2671 */ 2672 add_amd_tlb(devi, "dtlb-2M", 2673 BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16)); 2674 add_amd_tlb(devi, "itlb-2M", 2675 BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0)); 2676 2677 /* 2678 * 4K L1 TLB configuration 2679 */ 2680 2681 switch (cpi->cpi_vendor) { 2682 uint_t nentries; 2683 case X86_VENDOR_TM: 2684 if (cpi->cpi_family >= 5) { 2685 /* 2686 * Crusoe processors have 256 TLB entries, but 2687 * cpuid data format constrains them to only 2688 * reporting 255 of them. 2689 */ 2690 if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255) 2691 nentries = 256; 2692 /* 2693 * Crusoe processors also have a unified TLB 2694 */ 2695 add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24), 2696 nentries); 2697 break; 2698 } 2699 /*FALLTHROUGH*/ 2700 default: 2701 add_amd_tlb(devi, itlb4k_str, 2702 BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16)); 2703 add_amd_tlb(devi, dtlb4k_str, 2704 BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0)); 2705 break; 2706 } 2707 2708 /* 2709 * data L1 cache configuration 2710 */ 2711 2712 add_amd_cache(devi, l1_dcache_str, 2713 BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16), 2714 BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0)); 2715 2716 /* 2717 * code L1 cache configuration 2718 */ 2719 2720 add_amd_cache(devi, l1_icache_str, 2721 BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16), 2722 BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0)); 2723 2724 if (cpi->cpi_xmaxeax < 0x80000006) 2725 return; 2726 cp = &cpi->cpi_extd[6]; 2727 2728 /* Check for a unified L2 TLB for large pages */ 2729 2730 if (BITX(cp->cp_eax, 31, 16) == 0) 2731 add_amd_l2_tlb(devi, "l2-tlb-2M", 2732 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 2733 else { 2734 add_amd_l2_tlb(devi, "l2-dtlb-2M", 2735 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 2736 add_amd_l2_tlb(devi, "l2-itlb-2M", 2737 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 2738 } 2739 2740 /* Check for a unified L2 TLB for 4K pages */ 2741 2742 if (BITX(cp->cp_ebx, 31, 16) == 0) { 2743 add_amd_l2_tlb(devi, "l2-tlb-4K", 2744 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 2745 } else { 2746 add_amd_l2_tlb(devi, "l2-dtlb-4K", 2747 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 2748 add_amd_l2_tlb(devi, "l2-itlb-4K", 2749 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 2750 } 2751 2752 add_amd_l2_cache(devi, l2_cache_str, 2753 BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12), 2754 BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0)); 2755 } 2756 2757 /* 2758 * There are two basic ways that the x86 world describes it cache 2759 * and tlb architecture - Intel's way and AMD's way. 2760 * 2761 * Return which flavor of cache architecture we should use 2762 */ 2763 static int 2764 x86_which_cacheinfo(struct cpuid_info *cpi) 2765 { 2766 switch (cpi->cpi_vendor) { 2767 case X86_VENDOR_Intel: 2768 if (cpi->cpi_maxeax >= 2) 2769 return (X86_VENDOR_Intel); 2770 break; 2771 case X86_VENDOR_AMD: 2772 /* 2773 * The K5 model 1 was the first part from AMD that reported 2774 * cache sizes via extended cpuid functions. 2775 */ 2776 if (cpi->cpi_family > 5 || 2777 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 2778 return (X86_VENDOR_AMD); 2779 break; 2780 case X86_VENDOR_TM: 2781 if (cpi->cpi_family >= 5) 2782 return (X86_VENDOR_AMD); 2783 /*FALLTHROUGH*/ 2784 default: 2785 /* 2786 * If they have extended CPU data for 0x80000005 2787 * then we assume they have AMD-format cache 2788 * information. 2789 * 2790 * If not, and the vendor happens to be Cyrix, 2791 * then try our-Cyrix specific handler. 2792 * 2793 * If we're not Cyrix, then assume we're using Intel's 2794 * table-driven format instead. 2795 */ 2796 if (cpi->cpi_xmaxeax >= 0x80000005) 2797 return (X86_VENDOR_AMD); 2798 else if (cpi->cpi_vendor == X86_VENDOR_Cyrix) 2799 return (X86_VENDOR_Cyrix); 2800 else if (cpi->cpi_maxeax >= 2) 2801 return (X86_VENDOR_Intel); 2802 break; 2803 } 2804 return (-1); 2805 } 2806 2807 /* 2808 * create a node for the given cpu under the prom root node. 2809 * Also, create a cpu node in the device tree. 2810 */ 2811 static dev_info_t *cpu_nex_devi = NULL; 2812 static kmutex_t cpu_node_lock; 2813 2814 /* 2815 * Called from post_startup() and mp_startup() 2816 */ 2817 void 2818 add_cpunode2devtree(processorid_t cpu_id, struct cpuid_info *cpi) 2819 { 2820 dev_info_t *cpu_devi; 2821 int create; 2822 2823 mutex_enter(&cpu_node_lock); 2824 2825 /* 2826 * create a nexus node for all cpus identified as 'cpu_id' under 2827 * the root node. 2828 */ 2829 if (cpu_nex_devi == NULL) { 2830 if (ndi_devi_alloc(ddi_root_node(), "cpus", 2831 (pnode_t)DEVI_SID_NODEID, &cpu_nex_devi) != NDI_SUCCESS) { 2832 mutex_exit(&cpu_node_lock); 2833 return; 2834 } 2835 (void) ndi_devi_online(cpu_nex_devi, 0); 2836 } 2837 2838 /* 2839 * create a child node for cpu identified as 'cpu_id' 2840 */ 2841 cpu_devi = ddi_add_child(cpu_nex_devi, "cpu", DEVI_SID_NODEID, 2842 cpu_id); 2843 if (cpu_devi == NULL) { 2844 mutex_exit(&cpu_node_lock); 2845 return; 2846 } 2847 2848 /* device_type */ 2849 2850 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 2851 "device_type", "cpu"); 2852 2853 /* reg */ 2854 2855 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2856 "reg", cpu_id); 2857 2858 /* cpu-mhz, and clock-frequency */ 2859 2860 if (cpu_freq > 0) { 2861 long long mul; 2862 2863 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2864 "cpu-mhz", cpu_freq); 2865 2866 if ((mul = cpu_freq * 1000000LL) <= INT_MAX) 2867 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2868 "clock-frequency", (int)mul); 2869 } 2870 2871 (void) ndi_devi_online(cpu_devi, 0); 2872 2873 if ((x86_feature & X86_CPUID) == 0) { 2874 mutex_exit(&cpu_node_lock); 2875 return; 2876 } 2877 2878 /* vendor-id */ 2879 2880 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 2881 "vendor-id", cpi->cpi_vendorstr); 2882 2883 if (cpi->cpi_maxeax == 0) { 2884 mutex_exit(&cpu_node_lock); 2885 return; 2886 } 2887 2888 /* 2889 * family, model, and step 2890 */ 2891 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2892 "family", CPI_FAMILY(cpi)); 2893 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2894 "cpu-model", CPI_MODEL(cpi)); 2895 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2896 "stepping-id", CPI_STEP(cpi)); 2897 2898 /* type */ 2899 2900 switch (cpi->cpi_vendor) { 2901 case X86_VENDOR_Intel: 2902 create = 1; 2903 break; 2904 default: 2905 create = 0; 2906 break; 2907 } 2908 if (create) 2909 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2910 "type", CPI_TYPE(cpi)); 2911 2912 /* ext-family */ 2913 2914 switch (cpi->cpi_vendor) { 2915 case X86_VENDOR_Intel: 2916 case X86_VENDOR_AMD: 2917 create = cpi->cpi_family >= 0xf; 2918 break; 2919 default: 2920 create = 0; 2921 break; 2922 } 2923 if (create) 2924 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2925 "ext-family", CPI_FAMILY_XTD(cpi)); 2926 2927 /* ext-model */ 2928 2929 switch (cpi->cpi_vendor) { 2930 case X86_VENDOR_Intel: 2931 create = CPI_MODEL(cpi) == 0xf; 2932 break; 2933 case X86_VENDOR_AMD: 2934 create = CPI_FAMILY(cpi) == 0xf; 2935 break; 2936 default: 2937 create = 0; 2938 break; 2939 } 2940 if (create) 2941 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2942 "ext-model", CPI_MODEL_XTD(cpi)); 2943 2944 /* generation */ 2945 2946 switch (cpi->cpi_vendor) { 2947 case X86_VENDOR_AMD: 2948 /* 2949 * AMD K5 model 1 was the first part to support this 2950 */ 2951 create = cpi->cpi_xmaxeax >= 0x80000001; 2952 break; 2953 default: 2954 create = 0; 2955 break; 2956 } 2957 if (create) 2958 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2959 "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8)); 2960 2961 /* brand-id */ 2962 2963 switch (cpi->cpi_vendor) { 2964 case X86_VENDOR_Intel: 2965 /* 2966 * brand id first appeared on Pentium III Xeon model 8, 2967 * and Celeron model 8 processors and Opteron 2968 */ 2969 create = cpi->cpi_family > 6 || 2970 (cpi->cpi_family == 6 && cpi->cpi_model >= 8); 2971 break; 2972 case X86_VENDOR_AMD: 2973 create = cpi->cpi_family >= 0xf; 2974 break; 2975 default: 2976 create = 0; 2977 break; 2978 } 2979 if (create && cpi->cpi_brandid != 0) { 2980 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2981 "brand-id", cpi->cpi_brandid); 2982 } 2983 2984 /* chunks, and apic-id */ 2985 2986 switch (cpi->cpi_vendor) { 2987 /* 2988 * first available on Pentium IV and Opteron (K8) 2989 */ 2990 case X86_VENDOR_Intel: 2991 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 2992 break; 2993 case X86_VENDOR_AMD: 2994 create = cpi->cpi_family >= 0xf; 2995 break; 2996 default: 2997 create = 0; 2998 break; 2999 } 3000 if (create) { 3001 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3002 "chunks", CPI_CHUNKS(cpi)); 3003 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3004 "apic-id", CPI_APIC_ID(cpi)); 3005 if (cpi->cpi_chipid >= 0) { 3006 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3007 "chip#", cpi->cpi_chipid); 3008 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3009 "clog#", cpi->cpi_clogid); 3010 } 3011 } 3012 3013 /* cpuid-features */ 3014 3015 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3016 "cpuid-features", CPI_FEATURES_EDX(cpi)); 3017 3018 3019 /* cpuid-features-ecx */ 3020 3021 switch (cpi->cpi_vendor) { 3022 case X86_VENDOR_Intel: 3023 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 3024 break; 3025 default: 3026 create = 0; 3027 break; 3028 } 3029 if (create) 3030 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3031 "cpuid-features-ecx", CPI_FEATURES_ECX(cpi)); 3032 3033 /* ext-cpuid-features */ 3034 3035 switch (cpi->cpi_vendor) { 3036 case X86_VENDOR_Intel: 3037 case X86_VENDOR_AMD: 3038 case X86_VENDOR_Cyrix: 3039 case X86_VENDOR_TM: 3040 case X86_VENDOR_Centaur: 3041 create = cpi->cpi_xmaxeax >= 0x80000001; 3042 break; 3043 default: 3044 create = 0; 3045 break; 3046 } 3047 if (create) { 3048 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3049 "ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi)); 3050 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3051 "ext-cpuid-features-ecx", CPI_FEATURES_XTD_ECX(cpi)); 3052 } 3053 3054 /* 3055 * Brand String first appeared in Intel Pentium IV, AMD K5 3056 * model 1, and Cyrix GXm. On earlier models we try and 3057 * simulate something similar .. so this string should always 3058 * same -something- about the processor, however lame. 3059 */ 3060 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3061 "brand-string", cpi->cpi_brandstr); 3062 3063 /* 3064 * Finally, cache and tlb information 3065 */ 3066 switch (x86_which_cacheinfo(cpi)) { 3067 case X86_VENDOR_Intel: 3068 intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 3069 break; 3070 case X86_VENDOR_Cyrix: 3071 cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 3072 break; 3073 case X86_VENDOR_AMD: 3074 amd_cache_info(cpi, cpu_devi); 3075 break; 3076 default: 3077 break; 3078 } 3079 3080 mutex_exit(&cpu_node_lock); 3081 } 3082 3083 struct l2info { 3084 int *l2i_csz; 3085 int *l2i_lsz; 3086 int *l2i_assoc; 3087 int l2i_ret; 3088 }; 3089 3090 /* 3091 * A cacheinfo walker that fetches the size, line-size and associativity 3092 * of the L2 cache 3093 */ 3094 static int 3095 intel_l2cinfo(void *arg, const struct cachetab *ct) 3096 { 3097 struct l2info *l2i = arg; 3098 int *ip; 3099 3100 if (ct->ct_label != l2_cache_str && 3101 ct->ct_label != sl2_cache_str) 3102 return (0); /* not an L2 -- keep walking */ 3103 3104 if ((ip = l2i->l2i_csz) != NULL) 3105 *ip = ct->ct_size; 3106 if ((ip = l2i->l2i_lsz) != NULL) 3107 *ip = ct->ct_line_size; 3108 if ((ip = l2i->l2i_assoc) != NULL) 3109 *ip = ct->ct_assoc; 3110 l2i->l2i_ret = ct->ct_size; 3111 return (1); /* was an L2 -- terminate walk */ 3112 } 3113 3114 static void 3115 amd_l2cacheinfo(struct cpuid_info *cpi, struct l2info *l2i) 3116 { 3117 struct cpuid_regs *cp; 3118 uint_t size, assoc; 3119 int *ip; 3120 3121 if (cpi->cpi_xmaxeax < 0x80000006) 3122 return; 3123 cp = &cpi->cpi_extd[6]; 3124 3125 if ((assoc = BITX(cp->cp_ecx, 15, 12)) != 0 && 3126 (size = BITX(cp->cp_ecx, 31, 16)) != 0) { 3127 uint_t cachesz = size * 1024; 3128 3129 3130 if ((ip = l2i->l2i_csz) != NULL) 3131 *ip = cachesz; 3132 if ((ip = l2i->l2i_lsz) != NULL) 3133 *ip = BITX(cp->cp_ecx, 7, 0); 3134 if ((ip = l2i->l2i_assoc) != NULL) 3135 *ip = assoc; 3136 l2i->l2i_ret = cachesz; 3137 } 3138 } 3139 3140 int 3141 getl2cacheinfo(cpu_t *cpu, int *csz, int *lsz, int *assoc) 3142 { 3143 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 3144 struct l2info __l2info, *l2i = &__l2info; 3145 3146 l2i->l2i_csz = csz; 3147 l2i->l2i_lsz = lsz; 3148 l2i->l2i_assoc = assoc; 3149 l2i->l2i_ret = -1; 3150 3151 switch (x86_which_cacheinfo(cpi)) { 3152 case X86_VENDOR_Intel: 3153 intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 3154 break; 3155 case X86_VENDOR_Cyrix: 3156 cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 3157 break; 3158 case X86_VENDOR_AMD: 3159 amd_l2cacheinfo(cpi, l2i); 3160 break; 3161 default: 3162 break; 3163 } 3164 return (l2i->l2i_ret); 3165 } 3166 3167 size_t 3168 cpuid_get_mwait_size(cpu_t *cpu) 3169 { 3170 ASSERT(cpuid_checkpass(cpu, 2)); 3171 return (cpu->cpu_m.mcpu_cpi->cpi_mwait.mon_max); 3172 } 3173