1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * Various routines to handle identification 30 * and classification of x86 processors. 31 */ 32 33 #include <sys/types.h> 34 #include <sys/archsystm.h> 35 #include <sys/x86_archext.h> 36 #include <sys/kmem.h> 37 #include <sys/systm.h> 38 #include <sys/cmn_err.h> 39 #include <sys/sunddi.h> 40 #include <sys/sunndi.h> 41 #include <sys/cpuvar.h> 42 #include <sys/processor.h> 43 #include <sys/sysmacros.h> 44 #include <sys/pg.h> 45 #include <sys/fp.h> 46 #include <sys/controlregs.h> 47 #include <sys/auxv_386.h> 48 #include <sys/bitmap.h> 49 #include <sys/memnode.h> 50 51 /* 52 * Pass 0 of cpuid feature analysis happens in locore. It contains special code 53 * to recognize Cyrix processors that are not cpuid-compliant, and to deal with 54 * them accordingly. For most modern processors, feature detection occurs here 55 * in pass 1. 56 * 57 * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup() 58 * for the boot CPU and does the basic analysis that the early kernel needs. 59 * x86_feature is set based on the return value of cpuid_pass1() of the boot 60 * CPU. 61 * 62 * Pass 1 includes: 63 * 64 * o Determining vendor/model/family/stepping and setting x86_type and 65 * x86_vendor accordingly. 66 * o Processing the feature flags returned by the cpuid instruction while 67 * applying any workarounds or tricks for the specific processor. 68 * o Mapping the feature flags into Solaris feature bits (X86_*). 69 * o Processing extended feature flags if supported by the processor, 70 * again while applying specific processor knowledge. 71 * o Determining the CMT characteristics of the system. 72 * 73 * Pass 1 is done on non-boot CPUs during their initialization and the results 74 * are used only as a meager attempt at ensuring that all processors within the 75 * system support the same features. 76 * 77 * Pass 2 of cpuid feature analysis happens just at the beginning 78 * of startup(). It just copies in and corrects the remainder 79 * of the cpuid data we depend on: standard cpuid functions that we didn't 80 * need for pass1 feature analysis, and extended cpuid functions beyond the 81 * simple feature processing done in pass1. 82 * 83 * Pass 3 of cpuid analysis is invoked after basic kernel services; in 84 * particular kernel memory allocation has been made available. It creates a 85 * readable brand string based on the data collected in the first two passes. 86 * 87 * Pass 4 of cpuid analysis is invoked after post_startup() when all 88 * the support infrastructure for various hardware features has been 89 * initialized. It determines which processor features will be reported 90 * to userland via the aux vector. 91 * 92 * All passes are executed on all CPUs, but only the boot CPU determines what 93 * features the kernel will use. 94 * 95 * Much of the worst junk in this file is for the support of processors 96 * that didn't really implement the cpuid instruction properly. 97 * 98 * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon, 99 * the pass numbers. Accordingly, changes to the pass code may require changes 100 * to the accessor code. 101 */ 102 103 uint_t x86_feature = 0; 104 uint_t x86_vendor = X86_VENDOR_IntelClone; 105 uint_t x86_type = X86_TYPE_OTHER; 106 107 uint_t pentiumpro_bug4046376; 108 uint_t pentiumpro_bug4064495; 109 110 uint_t enable486; 111 112 /* 113 * This set of strings are for processors rumored to support the cpuid 114 * instruction, and is used by locore.s to figure out how to set x86_vendor 115 */ 116 const char CyrixInstead[] = "CyrixInstead"; 117 118 /* 119 * monitor/mwait info. 120 * 121 * size_actual and buf_actual are the real address and size allocated to get 122 * proper mwait_buf alignement. buf_actual and size_actual should be passed 123 * to kmem_free(). Currently kmem_alloc() and mwait happen to both use 124 * processor cache-line alignment, but this is not guarantied in the furture. 125 */ 126 struct mwait_info { 127 size_t mon_min; /* min size to avoid missed wakeups */ 128 size_t mon_max; /* size to avoid false wakeups */ 129 size_t size_actual; /* size actually allocated */ 130 void *buf_actual; /* memory actually allocated */ 131 uint32_t support; /* processor support of monitor/mwait */ 132 }; 133 134 /* 135 * These constants determine how many of the elements of the 136 * cpuid we cache in the cpuid_info data structure; the 137 * remaining elements are accessible via the cpuid instruction. 138 */ 139 140 #define NMAX_CPI_STD 6 /* eax = 0 .. 5 */ 141 #define NMAX_CPI_EXTD 9 /* eax = 0x80000000 .. 0x80000008 */ 142 143 struct cpuid_info { 144 uint_t cpi_pass; /* last pass completed */ 145 /* 146 * standard function information 147 */ 148 uint_t cpi_maxeax; /* fn 0: %eax */ 149 char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */ 150 uint_t cpi_vendor; /* enum of cpi_vendorstr */ 151 152 uint_t cpi_family; /* fn 1: extended family */ 153 uint_t cpi_model; /* fn 1: extended model */ 154 uint_t cpi_step; /* fn 1: stepping */ 155 chipid_t cpi_chipid; /* fn 1: %ebx: chip # on ht cpus */ 156 uint_t cpi_brandid; /* fn 1: %ebx: brand ID */ 157 int cpi_clogid; /* fn 1: %ebx: thread # */ 158 uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */ 159 uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */ 160 uint_t cpi_ncache; /* fn 2: number of elements */ 161 uint_t cpi_ncpu_shr_last_cache; /* fn 4: %eax: ncpus sharing cache */ 162 id_t cpi_last_lvl_cacheid; /* fn 4: %eax: derived cache id */ 163 uint_t cpi_std_4_size; /* fn 4: number of fn 4 elements */ 164 struct cpuid_regs **cpi_std_4; /* fn 4: %ecx == 0 .. fn4_size */ 165 struct cpuid_regs cpi_std[NMAX_CPI_STD]; /* 0 .. 5 */ 166 /* 167 * extended function information 168 */ 169 uint_t cpi_xmaxeax; /* fn 0x80000000: %eax */ 170 char cpi_brandstr[49]; /* fn 0x8000000[234] */ 171 uint8_t cpi_pabits; /* fn 0x80000006: %eax */ 172 uint8_t cpi_vabits; /* fn 0x80000006: %eax */ 173 struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x8000000[0-8] */ 174 id_t cpi_coreid; 175 uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */ 176 /* Intel: fn 4: %eax[31-26] */ 177 /* 178 * supported feature information 179 */ 180 uint32_t cpi_support[5]; 181 #define STD_EDX_FEATURES 0 182 #define AMD_EDX_FEATURES 1 183 #define TM_EDX_FEATURES 2 184 #define STD_ECX_FEATURES 3 185 #define AMD_ECX_FEATURES 4 186 /* 187 * Synthesized information, where known. 188 */ 189 uint32_t cpi_chiprev; /* See X86_CHIPREV_* in x86_archext.h */ 190 const char *cpi_chiprevstr; /* May be NULL if chiprev unknown */ 191 uint32_t cpi_socket; /* Chip package/socket type */ 192 193 struct mwait_info cpi_mwait; /* fn 5: monitor/mwait info */ 194 }; 195 196 197 static struct cpuid_info cpuid_info0; 198 199 /* 200 * These bit fields are defined by the Intel Application Note AP-485 201 * "Intel Processor Identification and the CPUID Instruction" 202 */ 203 #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20) 204 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16) 205 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12) 206 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8) 207 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0) 208 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4) 209 210 #define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx) 211 #define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx) 212 #define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx) 213 #define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx) 214 215 #define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0) 216 #define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7) 217 #define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16) 218 #define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24) 219 220 #define CPI_MAXEAX_MAX 0x100 /* sanity control */ 221 #define CPI_XMAXEAX_MAX 0x80000100 222 #define CPI_FN4_ECX_MAX 0x20 /* sanity: max fn 4 levels */ 223 224 /* 225 * Function 4 (Deterministic Cache Parameters) macros 226 * Defined by Intel Application Note AP-485 227 */ 228 #define CPI_NUM_CORES(regs) BITX((regs)->cp_eax, 31, 26) 229 #define CPI_NTHR_SHR_CACHE(regs) BITX((regs)->cp_eax, 25, 14) 230 #define CPI_FULL_ASSOC_CACHE(regs) BITX((regs)->cp_eax, 9, 9) 231 #define CPI_SELF_INIT_CACHE(regs) BITX((regs)->cp_eax, 8, 8) 232 #define CPI_CACHE_LVL(regs) BITX((regs)->cp_eax, 7, 5) 233 #define CPI_CACHE_TYPE(regs) BITX((regs)->cp_eax, 4, 0) 234 235 #define CPI_CACHE_WAYS(regs) BITX((regs)->cp_ebx, 31, 22) 236 #define CPI_CACHE_PARTS(regs) BITX((regs)->cp_ebx, 21, 12) 237 #define CPI_CACHE_COH_LN_SZ(regs) BITX((regs)->cp_ebx, 11, 0) 238 239 #define CPI_CACHE_SETS(regs) BITX((regs)->cp_ecx, 31, 0) 240 241 #define CPI_PREFCH_STRIDE(regs) BITX((regs)->cp_edx, 9, 0) 242 243 244 /* 245 * A couple of shorthand macros to identify "later" P6-family chips 246 * like the Pentium M and Core. First, the "older" P6-based stuff 247 * (loosely defined as "pre-Pentium-4"): 248 * P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon 249 */ 250 251 #define IS_LEGACY_P6(cpi) ( \ 252 cpi->cpi_family == 6 && \ 253 (cpi->cpi_model == 1 || \ 254 cpi->cpi_model == 3 || \ 255 cpi->cpi_model == 5 || \ 256 cpi->cpi_model == 6 || \ 257 cpi->cpi_model == 7 || \ 258 cpi->cpi_model == 8 || \ 259 cpi->cpi_model == 0xA || \ 260 cpi->cpi_model == 0xB) \ 261 ) 262 263 /* A "new F6" is everything with family 6 that's not the above */ 264 #define IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi)) 265 266 /* Extended family/model support */ 267 #define IS_EXTENDED_MODEL_INTEL(cpi) (cpi->cpi_family == 0x6 || \ 268 cpi->cpi_family >= 0xf) 269 270 /* 271 * AMD family 0xf and family 0x10 socket types. 272 * First index : 273 * 0 for family 0xf, revs B thru E 274 * 1 for family 0xf, revs F and G 275 * 2 for family 0x10, rev B 276 * Second index by (model & 0x3) 277 */ 278 static uint32_t amd_skts[3][4] = { 279 /* 280 * Family 0xf revisions B through E 281 */ 282 #define A_SKTS_0 0 283 { 284 X86_SOCKET_754, /* 0b00 */ 285 X86_SOCKET_940, /* 0b01 */ 286 X86_SOCKET_754, /* 0b10 */ 287 X86_SOCKET_939 /* 0b11 */ 288 }, 289 /* 290 * Family 0xf revisions F and G 291 */ 292 #define A_SKTS_1 1 293 { 294 X86_SOCKET_S1g1, /* 0b00 */ 295 X86_SOCKET_F1207, /* 0b01 */ 296 X86_SOCKET_UNKNOWN, /* 0b10 */ 297 X86_SOCKET_AM2 /* 0b11 */ 298 }, 299 /* 300 * Family 0x10 revisions A and B 301 * It is not clear whether, as new sockets release, that 302 * model & 0x3 will id socket for this family 303 */ 304 #define A_SKTS_2 2 305 { 306 X86_SOCKET_F1207, /* 0b00 */ 307 X86_SOCKET_F1207, /* 0b01 */ 308 X86_SOCKET_F1207, /* 0b10 */ 309 X86_SOCKET_F1207, /* 0b11 */ 310 } 311 }; 312 313 /* 314 * Table for mapping AMD Family 0xf and AMD Family 0x10 model/stepping 315 * combination to chip "revision" and socket type. 316 * 317 * The first member of this array that matches a given family, extended model 318 * plus model range, and stepping range will be considered a match. 319 */ 320 static const struct amd_rev_mapent { 321 uint_t rm_family; 322 uint_t rm_modello; 323 uint_t rm_modelhi; 324 uint_t rm_steplo; 325 uint_t rm_stephi; 326 uint32_t rm_chiprev; 327 const char *rm_chiprevstr; 328 int rm_sktidx; 329 } amd_revmap[] = { 330 /* 331 * =============== AuthenticAMD Family 0xf =============== 332 */ 333 334 /* 335 * Rev B includes model 0x4 stepping 0 and model 0x5 stepping 0 and 1. 336 */ 337 { 0xf, 0x04, 0x04, 0x0, 0x0, X86_CHIPREV_AMD_F_REV_B, "B", A_SKTS_0 }, 338 { 0xf, 0x05, 0x05, 0x0, 0x1, X86_CHIPREV_AMD_F_REV_B, "B", A_SKTS_0 }, 339 /* 340 * Rev C0 includes model 0x4 stepping 8 and model 0x5 stepping 8 341 */ 342 { 0xf, 0x04, 0x05, 0x8, 0x8, X86_CHIPREV_AMD_F_REV_C0, "C0", A_SKTS_0 }, 343 /* 344 * Rev CG is the rest of extended model 0x0 - i.e., everything 345 * but the rev B and C0 combinations covered above. 346 */ 347 { 0xf, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_CG, "CG", A_SKTS_0 }, 348 /* 349 * Rev D has extended model 0x1. 350 */ 351 { 0xf, 0x10, 0x1f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_D, "D", A_SKTS_0 }, 352 /* 353 * Rev E has extended model 0x2. 354 * Extended model 0x3 is unused but available to grow into. 355 */ 356 { 0xf, 0x20, 0x3f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_E, "E", A_SKTS_0 }, 357 /* 358 * Rev F has extended models 0x4 and 0x5. 359 */ 360 { 0xf, 0x40, 0x5f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_F, "F", A_SKTS_1 }, 361 /* 362 * Rev G has extended model 0x6. 363 */ 364 { 0xf, 0x60, 0x6f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_G, "G", A_SKTS_1 }, 365 366 /* 367 * =============== AuthenticAMD Family 0x10 =============== 368 */ 369 370 /* 371 * Rev A has model 0 and stepping 0/1/2 for DR-{A0,A1,A2}. 372 * Give all of model 0 stepping range to rev A. 373 */ 374 { 0x10, 0x00, 0x00, 0x0, 0x2, X86_CHIPREV_AMD_10_REV_A, "A", A_SKTS_2 }, 375 376 /* 377 * Rev B has model 2 and steppings 0/1/0xa/2 for DR-{B0,B1,BA,B2}. 378 * Give all of model 2 stepping range to rev B. 379 */ 380 { 0x10, 0x02, 0x02, 0x0, 0xf, X86_CHIPREV_AMD_10_REV_B, "B", A_SKTS_2 }, 381 }; 382 383 /* 384 * Info for monitor/mwait idle loop. 385 * 386 * See cpuid section of "Intel 64 and IA-32 Architectures Software Developer's 387 * Manual Volume 2A: Instruction Set Reference, A-M" #25366-022US, November 388 * 2006. 389 * See MONITOR/MWAIT section of "AMD64 Architecture Programmer's Manual 390 * Documentation Updates" #33633, Rev 2.05, December 2006. 391 */ 392 #define MWAIT_SUPPORT (0x00000001) /* mwait supported */ 393 #define MWAIT_EXTENSIONS (0x00000002) /* extenstion supported */ 394 #define MWAIT_ECX_INT_ENABLE (0x00000004) /* ecx 1 extension supported */ 395 #define MWAIT_SUPPORTED(cpi) ((cpi)->cpi_std[1].cp_ecx & CPUID_INTC_ECX_MON) 396 #define MWAIT_INT_ENABLE(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x2) 397 #define MWAIT_EXTENSION(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x1) 398 #define MWAIT_SIZE_MIN(cpi) BITX((cpi)->cpi_std[5].cp_eax, 15, 0) 399 #define MWAIT_SIZE_MAX(cpi) BITX((cpi)->cpi_std[5].cp_ebx, 15, 0) 400 /* 401 * Number of sub-cstates for a given c-state. 402 */ 403 #define MWAIT_NUM_SUBC_STATES(cpi, c_state) \ 404 BITX((cpi)->cpi_std[5].cp_edx, c_state + 3, c_state) 405 406 static void intel_cpuid_4_cache_info(void *, struct cpuid_info *); 407 408 static void 409 synth_amd_info(struct cpuid_info *cpi) 410 { 411 const struct amd_rev_mapent *rmp; 412 uint_t family, model, step; 413 int i; 414 415 /* 416 * Currently only AMD family 0xf and family 0x10 use these fields. 417 */ 418 if (cpi->cpi_family != 0xf && cpi->cpi_family != 0x10) 419 return; 420 421 family = cpi->cpi_family; 422 model = cpi->cpi_model; 423 step = cpi->cpi_step; 424 425 for (i = 0, rmp = amd_revmap; i < sizeof (amd_revmap) / sizeof (*rmp); 426 i++, rmp++) { 427 if (family == rmp->rm_family && 428 model >= rmp->rm_modello && model <= rmp->rm_modelhi && 429 step >= rmp->rm_steplo && step <= rmp->rm_stephi) { 430 cpi->cpi_chiprev = rmp->rm_chiprev; 431 cpi->cpi_chiprevstr = rmp->rm_chiprevstr; 432 cpi->cpi_socket = amd_skts[rmp->rm_sktidx][model & 0x3]; 433 return; 434 } 435 } 436 } 437 438 static void 439 synth_info(struct cpuid_info *cpi) 440 { 441 cpi->cpi_chiprev = X86_CHIPREV_UNKNOWN; 442 cpi->cpi_chiprevstr = "Unknown"; 443 cpi->cpi_socket = X86_SOCKET_UNKNOWN; 444 445 switch (cpi->cpi_vendor) { 446 case X86_VENDOR_AMD: 447 synth_amd_info(cpi); 448 break; 449 450 default: 451 break; 452 453 } 454 } 455 456 /* 457 * Apply up various platform-dependent restrictions where the 458 * underlying platform restrictions mean the CPU can be marked 459 * as less capable than its cpuid instruction would imply. 460 */ 461 #if defined(__xpv) 462 static void 463 platform_cpuid_mangle(uint_t vendor, uint32_t eax, struct cpuid_regs *cp) 464 { 465 switch (eax) { 466 case 1: 467 cp->cp_edx &= 468 ~(CPUID_INTC_EDX_PSE | 469 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE | 470 CPUID_INTC_EDX_MCA | /* XXPV true on dom0? */ 471 CPUID_INTC_EDX_SEP | CPUID_INTC_EDX_MTRR | 472 CPUID_INTC_EDX_PGE | CPUID_INTC_EDX_PAT | 473 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP | 474 CPUID_INTC_EDX_PSE36 | CPUID_INTC_EDX_HTT); 475 break; 476 477 case 0x80000001: 478 cp->cp_edx &= 479 ~(CPUID_AMD_EDX_PSE | 480 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE | 481 CPUID_AMD_EDX_MTRR | CPUID_AMD_EDX_PGE | 482 CPUID_AMD_EDX_PAT | CPUID_AMD_EDX_PSE36 | 483 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP | 484 CPUID_AMD_EDX_TSCP); 485 cp->cp_ecx &= ~CPUID_AMD_ECX_CMP_LGCY; 486 break; 487 default: 488 break; 489 } 490 491 switch (vendor) { 492 case X86_VENDOR_Intel: 493 switch (eax) { 494 case 4: 495 /* 496 * Zero out the (ncores-per-chip - 1) field 497 */ 498 cp->cp_eax &= 0x03fffffff; 499 break; 500 default: 501 break; 502 } 503 break; 504 case X86_VENDOR_AMD: 505 switch (eax) { 506 case 0x80000008: 507 /* 508 * Zero out the (ncores-per-chip - 1) field 509 */ 510 cp->cp_ecx &= 0xffffff00; 511 break; 512 default: 513 break; 514 } 515 break; 516 default: 517 break; 518 } 519 } 520 #else 521 #define platform_cpuid_mangle(vendor, eax, cp) /* nothing */ 522 #endif 523 524 /* 525 * Some undocumented ways of patching the results of the cpuid 526 * instruction to permit running Solaris 10 on future cpus that 527 * we don't currently support. Could be set to non-zero values 528 * via settings in eeprom. 529 */ 530 531 uint32_t cpuid_feature_ecx_include; 532 uint32_t cpuid_feature_ecx_exclude; 533 uint32_t cpuid_feature_edx_include; 534 uint32_t cpuid_feature_edx_exclude; 535 536 void 537 cpuid_alloc_space(cpu_t *cpu) 538 { 539 /* 540 * By convention, cpu0 is the boot cpu, which is set up 541 * before memory allocation is available. All other cpus get 542 * their cpuid_info struct allocated here. 543 */ 544 ASSERT(cpu->cpu_id != 0); 545 cpu->cpu_m.mcpu_cpi = 546 kmem_zalloc(sizeof (*cpu->cpu_m.mcpu_cpi), KM_SLEEP); 547 } 548 549 void 550 cpuid_free_space(cpu_t *cpu) 551 { 552 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 553 int i; 554 555 ASSERT(cpu->cpu_id != 0); 556 557 /* 558 * Free up any function 4 related dynamic storage 559 */ 560 for (i = 1; i < cpi->cpi_std_4_size; i++) 561 kmem_free(cpi->cpi_std_4[i], sizeof (struct cpuid_regs)); 562 if (cpi->cpi_std_4_size > 0) 563 kmem_free(cpi->cpi_std_4, 564 cpi->cpi_std_4_size * sizeof (struct cpuid_regs *)); 565 566 kmem_free(cpu->cpu_m.mcpu_cpi, sizeof (*cpu->cpu_m.mcpu_cpi)); 567 } 568 569 uint_t 570 cpuid_pass1(cpu_t *cpu) 571 { 572 uint32_t mask_ecx, mask_edx; 573 uint_t feature = X86_CPUID; 574 struct cpuid_info *cpi; 575 struct cpuid_regs *cp; 576 int xcpuid; 577 #if !defined(__xpv) 578 extern int idle_cpu_prefer_mwait; 579 #endif 580 581 /* 582 * Space statically allocated for cpu0, ensure pointer is set 583 */ 584 if (cpu->cpu_id == 0) 585 cpu->cpu_m.mcpu_cpi = &cpuid_info0; 586 cpi = cpu->cpu_m.mcpu_cpi; 587 ASSERT(cpi != NULL); 588 cp = &cpi->cpi_std[0]; 589 cp->cp_eax = 0; 590 cpi->cpi_maxeax = __cpuid_insn(cp); 591 { 592 uint32_t *iptr = (uint32_t *)cpi->cpi_vendorstr; 593 *iptr++ = cp->cp_ebx; 594 *iptr++ = cp->cp_edx; 595 *iptr++ = cp->cp_ecx; 596 *(char *)&cpi->cpi_vendorstr[12] = '\0'; 597 } 598 599 /* 600 * Map the vendor string to a type code 601 */ 602 if (strcmp(cpi->cpi_vendorstr, "GenuineIntel") == 0) 603 cpi->cpi_vendor = X86_VENDOR_Intel; 604 else if (strcmp(cpi->cpi_vendorstr, "AuthenticAMD") == 0) 605 cpi->cpi_vendor = X86_VENDOR_AMD; 606 else if (strcmp(cpi->cpi_vendorstr, "GenuineTMx86") == 0) 607 cpi->cpi_vendor = X86_VENDOR_TM; 608 else if (strcmp(cpi->cpi_vendorstr, CyrixInstead) == 0) 609 /* 610 * CyrixInstead is a variable used by the Cyrix detection code 611 * in locore. 612 */ 613 cpi->cpi_vendor = X86_VENDOR_Cyrix; 614 else if (strcmp(cpi->cpi_vendorstr, "UMC UMC UMC ") == 0) 615 cpi->cpi_vendor = X86_VENDOR_UMC; 616 else if (strcmp(cpi->cpi_vendorstr, "NexGenDriven") == 0) 617 cpi->cpi_vendor = X86_VENDOR_NexGen; 618 else if (strcmp(cpi->cpi_vendorstr, "CentaurHauls") == 0) 619 cpi->cpi_vendor = X86_VENDOR_Centaur; 620 else if (strcmp(cpi->cpi_vendorstr, "RiseRiseRise") == 0) 621 cpi->cpi_vendor = X86_VENDOR_Rise; 622 else if (strcmp(cpi->cpi_vendorstr, "SiS SiS SiS ") == 0) 623 cpi->cpi_vendor = X86_VENDOR_SiS; 624 else if (strcmp(cpi->cpi_vendorstr, "Geode by NSC") == 0) 625 cpi->cpi_vendor = X86_VENDOR_NSC; 626 else 627 cpi->cpi_vendor = X86_VENDOR_IntelClone; 628 629 x86_vendor = cpi->cpi_vendor; /* for compatibility */ 630 631 /* 632 * Limit the range in case of weird hardware 633 */ 634 if (cpi->cpi_maxeax > CPI_MAXEAX_MAX) 635 cpi->cpi_maxeax = CPI_MAXEAX_MAX; 636 if (cpi->cpi_maxeax < 1) 637 goto pass1_done; 638 639 cp = &cpi->cpi_std[1]; 640 cp->cp_eax = 1; 641 (void) __cpuid_insn(cp); 642 643 /* 644 * Extract identifying constants for easy access. 645 */ 646 cpi->cpi_model = CPI_MODEL(cpi); 647 cpi->cpi_family = CPI_FAMILY(cpi); 648 649 if (cpi->cpi_family == 0xf) 650 cpi->cpi_family += CPI_FAMILY_XTD(cpi); 651 652 /* 653 * Beware: AMD uses "extended model" iff base *FAMILY* == 0xf. 654 * Intel, and presumably everyone else, uses model == 0xf, as 655 * one would expect (max value means possible overflow). Sigh. 656 */ 657 658 switch (cpi->cpi_vendor) { 659 case X86_VENDOR_Intel: 660 if (IS_EXTENDED_MODEL_INTEL(cpi)) 661 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 662 break; 663 case X86_VENDOR_AMD: 664 if (CPI_FAMILY(cpi) == 0xf) 665 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 666 break; 667 default: 668 if (cpi->cpi_model == 0xf) 669 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 670 break; 671 } 672 673 cpi->cpi_step = CPI_STEP(cpi); 674 cpi->cpi_brandid = CPI_BRANDID(cpi); 675 676 /* 677 * *default* assumptions: 678 * - believe %edx feature word 679 * - ignore %ecx feature word 680 * - 32-bit virtual and physical addressing 681 */ 682 mask_edx = 0xffffffff; 683 mask_ecx = 0; 684 685 cpi->cpi_pabits = cpi->cpi_vabits = 32; 686 687 switch (cpi->cpi_vendor) { 688 case X86_VENDOR_Intel: 689 if (cpi->cpi_family == 5) 690 x86_type = X86_TYPE_P5; 691 else if (IS_LEGACY_P6(cpi)) { 692 x86_type = X86_TYPE_P6; 693 pentiumpro_bug4046376 = 1; 694 pentiumpro_bug4064495 = 1; 695 /* 696 * Clear the SEP bit when it was set erroneously 697 */ 698 if (cpi->cpi_model < 3 && cpi->cpi_step < 3) 699 cp->cp_edx &= ~CPUID_INTC_EDX_SEP; 700 } else if (IS_NEW_F6(cpi) || cpi->cpi_family == 0xf) { 701 x86_type = X86_TYPE_P4; 702 /* 703 * We don't currently depend on any of the %ecx 704 * features until Prescott, so we'll only check 705 * this from P4 onwards. We might want to revisit 706 * that idea later. 707 */ 708 mask_ecx = 0xffffffff; 709 } else if (cpi->cpi_family > 0xf) 710 mask_ecx = 0xffffffff; 711 /* 712 * We don't support MONITOR/MWAIT if leaf 5 is not available 713 * to obtain the monitor linesize. 714 */ 715 if (cpi->cpi_maxeax < 5) 716 mask_ecx &= ~CPUID_INTC_ECX_MON; 717 break; 718 case X86_VENDOR_IntelClone: 719 default: 720 break; 721 case X86_VENDOR_AMD: 722 #if defined(OPTERON_ERRATUM_108) 723 if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) { 724 cp->cp_eax = (0xf0f & cp->cp_eax) | 0xc0; 725 cpi->cpi_model = 0xc; 726 } else 727 #endif 728 if (cpi->cpi_family == 5) { 729 /* 730 * AMD K5 and K6 731 * 732 * These CPUs have an incomplete implementation 733 * of MCA/MCE which we mask away. 734 */ 735 mask_edx &= ~(CPUID_INTC_EDX_MCE | CPUID_INTC_EDX_MCA); 736 737 /* 738 * Model 0 uses the wrong (APIC) bit 739 * to indicate PGE. Fix it here. 740 */ 741 if (cpi->cpi_model == 0) { 742 if (cp->cp_edx & 0x200) { 743 cp->cp_edx &= ~0x200; 744 cp->cp_edx |= CPUID_INTC_EDX_PGE; 745 } 746 } 747 748 /* 749 * Early models had problems w/ MMX; disable. 750 */ 751 if (cpi->cpi_model < 6) 752 mask_edx &= ~CPUID_INTC_EDX_MMX; 753 } 754 755 /* 756 * For newer families, SSE3 and CX16, at least, are valid; 757 * enable all 758 */ 759 if (cpi->cpi_family >= 0xf) 760 mask_ecx = 0xffffffff; 761 /* 762 * We don't support MONITOR/MWAIT if leaf 5 is not available 763 * to obtain the monitor linesize. 764 */ 765 if (cpi->cpi_maxeax < 5) 766 mask_ecx &= ~CPUID_INTC_ECX_MON; 767 768 #if !defined(__xpv) 769 /* 770 * Do not use MONITOR/MWAIT to halt in the idle loop on any AMD 771 * processors. AMD does not intend MWAIT to be used in the cpu 772 * idle loop on current and future processors. 10h and future 773 * AMD processors use more power in MWAIT than HLT. 774 * Pre-family-10h Opterons do not have the MWAIT instruction. 775 */ 776 idle_cpu_prefer_mwait = 0; 777 #endif 778 779 break; 780 case X86_VENDOR_TM: 781 /* 782 * workaround the NT workaround in CMS 4.1 783 */ 784 if (cpi->cpi_family == 5 && cpi->cpi_model == 4 && 785 (cpi->cpi_step == 2 || cpi->cpi_step == 3)) 786 cp->cp_edx |= CPUID_INTC_EDX_CX8; 787 break; 788 case X86_VENDOR_Centaur: 789 /* 790 * workaround the NT workarounds again 791 */ 792 if (cpi->cpi_family == 6) 793 cp->cp_edx |= CPUID_INTC_EDX_CX8; 794 break; 795 case X86_VENDOR_Cyrix: 796 /* 797 * We rely heavily on the probing in locore 798 * to actually figure out what parts, if any, 799 * of the Cyrix cpuid instruction to believe. 800 */ 801 switch (x86_type) { 802 case X86_TYPE_CYRIX_486: 803 mask_edx = 0; 804 break; 805 case X86_TYPE_CYRIX_6x86: 806 mask_edx = 0; 807 break; 808 case X86_TYPE_CYRIX_6x86L: 809 mask_edx = 810 CPUID_INTC_EDX_DE | 811 CPUID_INTC_EDX_CX8; 812 break; 813 case X86_TYPE_CYRIX_6x86MX: 814 mask_edx = 815 CPUID_INTC_EDX_DE | 816 CPUID_INTC_EDX_MSR | 817 CPUID_INTC_EDX_CX8 | 818 CPUID_INTC_EDX_PGE | 819 CPUID_INTC_EDX_CMOV | 820 CPUID_INTC_EDX_MMX; 821 break; 822 case X86_TYPE_CYRIX_GXm: 823 mask_edx = 824 CPUID_INTC_EDX_MSR | 825 CPUID_INTC_EDX_CX8 | 826 CPUID_INTC_EDX_CMOV | 827 CPUID_INTC_EDX_MMX; 828 break; 829 case X86_TYPE_CYRIX_MediaGX: 830 break; 831 case X86_TYPE_CYRIX_MII: 832 case X86_TYPE_VIA_CYRIX_III: 833 mask_edx = 834 CPUID_INTC_EDX_DE | 835 CPUID_INTC_EDX_TSC | 836 CPUID_INTC_EDX_MSR | 837 CPUID_INTC_EDX_CX8 | 838 CPUID_INTC_EDX_PGE | 839 CPUID_INTC_EDX_CMOV | 840 CPUID_INTC_EDX_MMX; 841 break; 842 default: 843 break; 844 } 845 break; 846 } 847 848 #if defined(__xpv) 849 /* 850 * Do not support MONITOR/MWAIT under a hypervisor 851 */ 852 mask_ecx &= ~CPUID_INTC_ECX_MON; 853 #endif /* __xpv */ 854 855 /* 856 * Now we've figured out the masks that determine 857 * which bits we choose to believe, apply the masks 858 * to the feature words, then map the kernel's view 859 * of these feature words into its feature word. 860 */ 861 cp->cp_edx &= mask_edx; 862 cp->cp_ecx &= mask_ecx; 863 864 /* 865 * apply any platform restrictions (we don't call this 866 * immediately after __cpuid_insn here, because we need the 867 * workarounds applied above first) 868 */ 869 platform_cpuid_mangle(cpi->cpi_vendor, 1, cp); 870 871 /* 872 * fold in overrides from the "eeprom" mechanism 873 */ 874 cp->cp_edx |= cpuid_feature_edx_include; 875 cp->cp_edx &= ~cpuid_feature_edx_exclude; 876 877 cp->cp_ecx |= cpuid_feature_ecx_include; 878 cp->cp_ecx &= ~cpuid_feature_ecx_exclude; 879 880 if (cp->cp_edx & CPUID_INTC_EDX_PSE) 881 feature |= X86_LARGEPAGE; 882 if (cp->cp_edx & CPUID_INTC_EDX_TSC) 883 feature |= X86_TSC; 884 if (cp->cp_edx & CPUID_INTC_EDX_MSR) 885 feature |= X86_MSR; 886 if (cp->cp_edx & CPUID_INTC_EDX_MTRR) 887 feature |= X86_MTRR; 888 if (cp->cp_edx & CPUID_INTC_EDX_PGE) 889 feature |= X86_PGE; 890 if (cp->cp_edx & CPUID_INTC_EDX_CMOV) 891 feature |= X86_CMOV; 892 if (cp->cp_edx & CPUID_INTC_EDX_MMX) 893 feature |= X86_MMX; 894 if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 && 895 (cp->cp_edx & CPUID_INTC_EDX_MCA) != 0) 896 feature |= X86_MCA; 897 if (cp->cp_edx & CPUID_INTC_EDX_PAE) 898 feature |= X86_PAE; 899 if (cp->cp_edx & CPUID_INTC_EDX_CX8) 900 feature |= X86_CX8; 901 if (cp->cp_ecx & CPUID_INTC_ECX_CX16) 902 feature |= X86_CX16; 903 if (cp->cp_edx & CPUID_INTC_EDX_PAT) 904 feature |= X86_PAT; 905 if (cp->cp_edx & CPUID_INTC_EDX_SEP) 906 feature |= X86_SEP; 907 if (cp->cp_edx & CPUID_INTC_EDX_FXSR) { 908 /* 909 * In our implementation, fxsave/fxrstor 910 * are prerequisites before we'll even 911 * try and do SSE things. 912 */ 913 if (cp->cp_edx & CPUID_INTC_EDX_SSE) 914 feature |= X86_SSE; 915 if (cp->cp_edx & CPUID_INTC_EDX_SSE2) 916 feature |= X86_SSE2; 917 if (cp->cp_ecx & CPUID_INTC_ECX_SSE3) 918 feature |= X86_SSE3; 919 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 920 if (cp->cp_ecx & CPUID_INTC_ECX_SSSE3) 921 feature |= X86_SSSE3; 922 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_1) 923 feature |= X86_SSE4_1; 924 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_2) 925 feature |= X86_SSE4_2; 926 } 927 } 928 if (cp->cp_edx & CPUID_INTC_EDX_DE) 929 feature |= X86_DE; 930 if (cp->cp_ecx & CPUID_INTC_ECX_MON) { 931 cpi->cpi_mwait.support |= MWAIT_SUPPORT; 932 feature |= X86_MWAIT; 933 } 934 935 if (feature & X86_PAE) 936 cpi->cpi_pabits = 36; 937 938 /* 939 * Hyperthreading configuration is slightly tricky on Intel 940 * and pure clones, and even trickier on AMD. 941 * 942 * (AMD chose to set the HTT bit on their CMP processors, 943 * even though they're not actually hyperthreaded. Thus it 944 * takes a bit more work to figure out what's really going 945 * on ... see the handling of the CMP_LGCY bit below) 946 */ 947 if (cp->cp_edx & CPUID_INTC_EDX_HTT) { 948 cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi); 949 if (cpi->cpi_ncpu_per_chip > 1) 950 feature |= X86_HTT; 951 } else { 952 cpi->cpi_ncpu_per_chip = 1; 953 } 954 955 /* 956 * Work on the "extended" feature information, doing 957 * some basic initialization for cpuid_pass2() 958 */ 959 xcpuid = 0; 960 switch (cpi->cpi_vendor) { 961 case X86_VENDOR_Intel: 962 if (IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf) 963 xcpuid++; 964 break; 965 case X86_VENDOR_AMD: 966 if (cpi->cpi_family > 5 || 967 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 968 xcpuid++; 969 break; 970 case X86_VENDOR_Cyrix: 971 /* 972 * Only these Cyrix CPUs are -known- to support 973 * extended cpuid operations. 974 */ 975 if (x86_type == X86_TYPE_VIA_CYRIX_III || 976 x86_type == X86_TYPE_CYRIX_GXm) 977 xcpuid++; 978 break; 979 case X86_VENDOR_Centaur: 980 case X86_VENDOR_TM: 981 default: 982 xcpuid++; 983 break; 984 } 985 986 if (xcpuid) { 987 cp = &cpi->cpi_extd[0]; 988 cp->cp_eax = 0x80000000; 989 cpi->cpi_xmaxeax = __cpuid_insn(cp); 990 } 991 992 if (cpi->cpi_xmaxeax & 0x80000000) { 993 994 if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX) 995 cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX; 996 997 switch (cpi->cpi_vendor) { 998 case X86_VENDOR_Intel: 999 case X86_VENDOR_AMD: 1000 if (cpi->cpi_xmaxeax < 0x80000001) 1001 break; 1002 cp = &cpi->cpi_extd[1]; 1003 cp->cp_eax = 0x80000001; 1004 (void) __cpuid_insn(cp); 1005 1006 if (cpi->cpi_vendor == X86_VENDOR_AMD && 1007 cpi->cpi_family == 5 && 1008 cpi->cpi_model == 6 && 1009 cpi->cpi_step == 6) { 1010 /* 1011 * K6 model 6 uses bit 10 to indicate SYSC 1012 * Later models use bit 11. Fix it here. 1013 */ 1014 if (cp->cp_edx & 0x400) { 1015 cp->cp_edx &= ~0x400; 1016 cp->cp_edx |= CPUID_AMD_EDX_SYSC; 1017 } 1018 } 1019 1020 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000001, cp); 1021 1022 /* 1023 * Compute the additions to the kernel's feature word. 1024 */ 1025 if (cp->cp_edx & CPUID_AMD_EDX_NX) 1026 feature |= X86_NX; 1027 1028 #if defined(__amd64) 1029 /* 1 GB large page - enable only for 64 bit kernel */ 1030 if (cp->cp_edx & CPUID_AMD_EDX_1GPG) 1031 feature |= X86_1GPG; 1032 #endif 1033 1034 if ((cpi->cpi_vendor == X86_VENDOR_AMD) && 1035 (cpi->cpi_std[1].cp_edx & CPUID_INTC_EDX_FXSR) && 1036 (cp->cp_ecx & CPUID_AMD_ECX_SSE4A)) 1037 feature |= X86_SSE4A; 1038 1039 /* 1040 * If both the HTT and CMP_LGCY bits are set, 1041 * then we're not actually HyperThreaded. Read 1042 * "AMD CPUID Specification" for more details. 1043 */ 1044 if (cpi->cpi_vendor == X86_VENDOR_AMD && 1045 (feature & X86_HTT) && 1046 (cp->cp_ecx & CPUID_AMD_ECX_CMP_LGCY)) { 1047 feature &= ~X86_HTT; 1048 feature |= X86_CMP; 1049 } 1050 #if defined(__amd64) 1051 /* 1052 * It's really tricky to support syscall/sysret in 1053 * the i386 kernel; we rely on sysenter/sysexit 1054 * instead. In the amd64 kernel, things are -way- 1055 * better. 1056 */ 1057 if (cp->cp_edx & CPUID_AMD_EDX_SYSC) 1058 feature |= X86_ASYSC; 1059 1060 /* 1061 * While we're thinking about system calls, note 1062 * that AMD processors don't support sysenter 1063 * in long mode at all, so don't try to program them. 1064 */ 1065 if (x86_vendor == X86_VENDOR_AMD) 1066 feature &= ~X86_SEP; 1067 #endif 1068 if (x86_vendor == X86_VENDOR_AMD && 1069 cp->cp_edx & CPUID_AMD_EDX_TSCP) 1070 feature |= X86_TSCP; 1071 break; 1072 default: 1073 break; 1074 } 1075 1076 /* 1077 * Get CPUID data about processor cores and hyperthreads. 1078 */ 1079 switch (cpi->cpi_vendor) { 1080 case X86_VENDOR_Intel: 1081 if (cpi->cpi_maxeax >= 4) { 1082 cp = &cpi->cpi_std[4]; 1083 cp->cp_eax = 4; 1084 cp->cp_ecx = 0; 1085 (void) __cpuid_insn(cp); 1086 platform_cpuid_mangle(cpi->cpi_vendor, 4, cp); 1087 } 1088 /*FALLTHROUGH*/ 1089 case X86_VENDOR_AMD: 1090 if (cpi->cpi_xmaxeax < 0x80000008) 1091 break; 1092 cp = &cpi->cpi_extd[8]; 1093 cp->cp_eax = 0x80000008; 1094 (void) __cpuid_insn(cp); 1095 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000008, cp); 1096 1097 /* 1098 * Virtual and physical address limits from 1099 * cpuid override previously guessed values. 1100 */ 1101 cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0); 1102 cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8); 1103 break; 1104 default: 1105 break; 1106 } 1107 1108 /* 1109 * Derive the number of cores per chip 1110 */ 1111 switch (cpi->cpi_vendor) { 1112 case X86_VENDOR_Intel: 1113 if (cpi->cpi_maxeax < 4) { 1114 cpi->cpi_ncore_per_chip = 1; 1115 break; 1116 } else { 1117 cpi->cpi_ncore_per_chip = 1118 BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1; 1119 } 1120 break; 1121 case X86_VENDOR_AMD: 1122 if (cpi->cpi_xmaxeax < 0x80000008) { 1123 cpi->cpi_ncore_per_chip = 1; 1124 break; 1125 } else { 1126 cpi->cpi_ncore_per_chip = 1127 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1; 1128 } 1129 break; 1130 default: 1131 cpi->cpi_ncore_per_chip = 1; 1132 break; 1133 } 1134 } else { 1135 cpi->cpi_ncore_per_chip = 1; 1136 } 1137 1138 /* 1139 * If more than one core, then this processor is CMP. 1140 */ 1141 if (cpi->cpi_ncore_per_chip > 1) 1142 feature |= X86_CMP; 1143 1144 /* 1145 * If the number of cores is the same as the number 1146 * of CPUs, then we cannot have HyperThreading. 1147 */ 1148 if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip) 1149 feature &= ~X86_HTT; 1150 1151 if ((feature & (X86_HTT | X86_CMP)) == 0) { 1152 /* 1153 * Single-core single-threaded processors. 1154 */ 1155 cpi->cpi_chipid = -1; 1156 cpi->cpi_clogid = 0; 1157 cpi->cpi_coreid = cpu->cpu_id; 1158 } else if (cpi->cpi_ncpu_per_chip > 1) { 1159 uint_t i; 1160 uint_t chipid_shift = 0; 1161 uint_t coreid_shift = 0; 1162 uint_t apic_id = CPI_APIC_ID(cpi); 1163 1164 for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1) 1165 chipid_shift++; 1166 cpi->cpi_chipid = apic_id >> chipid_shift; 1167 cpi->cpi_clogid = apic_id & ((1 << chipid_shift) - 1); 1168 1169 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 1170 if (feature & X86_CMP) { 1171 /* 1172 * Multi-core (and possibly multi-threaded) 1173 * processors. 1174 */ 1175 uint_t ncpu_per_core; 1176 if (cpi->cpi_ncore_per_chip == 1) 1177 ncpu_per_core = cpi->cpi_ncpu_per_chip; 1178 else if (cpi->cpi_ncore_per_chip > 1) 1179 ncpu_per_core = cpi->cpi_ncpu_per_chip / 1180 cpi->cpi_ncore_per_chip; 1181 /* 1182 * 8bit APIC IDs on dual core Pentiums 1183 * look like this: 1184 * 1185 * +-----------------------+------+------+ 1186 * | Physical Package ID | MC | HT | 1187 * +-----------------------+------+------+ 1188 * <------- chipid --------> 1189 * <------- coreid ---------------> 1190 * <--- clogid --> 1191 * 1192 * Where the number of bits necessary to 1193 * represent MC and HT fields together equals 1194 * to the minimum number of bits necessary to 1195 * store the value of cpi->cpi_ncpu_per_chip. 1196 * Of those bits, the MC part uses the number 1197 * of bits necessary to store the value of 1198 * cpi->cpi_ncore_per_chip. 1199 */ 1200 for (i = 1; i < ncpu_per_core; i <<= 1) 1201 coreid_shift++; 1202 cpi->cpi_coreid = apic_id >> coreid_shift; 1203 } else if (feature & X86_HTT) { 1204 /* 1205 * Single-core multi-threaded processors. 1206 */ 1207 cpi->cpi_coreid = cpi->cpi_chipid; 1208 } 1209 } else if (cpi->cpi_vendor == X86_VENDOR_AMD) { 1210 /* 1211 * AMD currently only has dual-core processors with 1212 * single-threaded cores. If they ever release 1213 * multi-threaded processors, then this code 1214 * will have to be updated. 1215 */ 1216 cpi->cpi_coreid = cpu->cpu_id; 1217 } else { 1218 /* 1219 * All other processors are currently 1220 * assumed to have single cores. 1221 */ 1222 cpi->cpi_coreid = cpi->cpi_chipid; 1223 } 1224 } 1225 1226 /* 1227 * Synthesize chip "revision" and socket type 1228 */ 1229 synth_info(cpi); 1230 1231 pass1_done: 1232 cpi->cpi_pass = 1; 1233 return (feature); 1234 } 1235 1236 /* 1237 * Make copies of the cpuid table entries we depend on, in 1238 * part for ease of parsing now, in part so that we have only 1239 * one place to correct any of it, in part for ease of 1240 * later export to userland, and in part so we can look at 1241 * this stuff in a crash dump. 1242 */ 1243 1244 /*ARGSUSED*/ 1245 void 1246 cpuid_pass2(cpu_t *cpu) 1247 { 1248 uint_t n, nmax; 1249 int i; 1250 struct cpuid_regs *cp; 1251 uint8_t *dp; 1252 uint32_t *iptr; 1253 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1254 1255 ASSERT(cpi->cpi_pass == 1); 1256 1257 if (cpi->cpi_maxeax < 1) 1258 goto pass2_done; 1259 1260 if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD) 1261 nmax = NMAX_CPI_STD; 1262 /* 1263 * (We already handled n == 0 and n == 1 in pass 1) 1264 */ 1265 for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) { 1266 cp->cp_eax = n; 1267 1268 /* 1269 * CPUID function 4 expects %ecx to be initialized 1270 * with an index which indicates which cache to return 1271 * information about. The OS is expected to call function 4 1272 * with %ecx set to 0, 1, 2, ... until it returns with 1273 * EAX[4:0] set to 0, which indicates there are no more 1274 * caches. 1275 * 1276 * Here, populate cpi_std[4] with the information returned by 1277 * function 4 when %ecx == 0, and do the rest in cpuid_pass3() 1278 * when dynamic memory allocation becomes available. 1279 * 1280 * Note: we need to explicitly initialize %ecx here, since 1281 * function 4 may have been previously invoked. 1282 */ 1283 if (n == 4) 1284 cp->cp_ecx = 0; 1285 1286 (void) __cpuid_insn(cp); 1287 platform_cpuid_mangle(cpi->cpi_vendor, n, cp); 1288 switch (n) { 1289 case 2: 1290 /* 1291 * "the lower 8 bits of the %eax register 1292 * contain a value that identifies the number 1293 * of times the cpuid [instruction] has to be 1294 * executed to obtain a complete image of the 1295 * processor's caching systems." 1296 * 1297 * How *do* they make this stuff up? 1298 */ 1299 cpi->cpi_ncache = sizeof (*cp) * 1300 BITX(cp->cp_eax, 7, 0); 1301 if (cpi->cpi_ncache == 0) 1302 break; 1303 cpi->cpi_ncache--; /* skip count byte */ 1304 1305 /* 1306 * Well, for now, rather than attempt to implement 1307 * this slightly dubious algorithm, we just look 1308 * at the first 15 .. 1309 */ 1310 if (cpi->cpi_ncache > (sizeof (*cp) - 1)) 1311 cpi->cpi_ncache = sizeof (*cp) - 1; 1312 1313 dp = cpi->cpi_cacheinfo; 1314 if (BITX(cp->cp_eax, 31, 31) == 0) { 1315 uint8_t *p = (void *)&cp->cp_eax; 1316 for (i = 1; i < 3; i++) 1317 if (p[i] != 0) 1318 *dp++ = p[i]; 1319 } 1320 if (BITX(cp->cp_ebx, 31, 31) == 0) { 1321 uint8_t *p = (void *)&cp->cp_ebx; 1322 for (i = 0; i < 4; i++) 1323 if (p[i] != 0) 1324 *dp++ = p[i]; 1325 } 1326 if (BITX(cp->cp_ecx, 31, 31) == 0) { 1327 uint8_t *p = (void *)&cp->cp_ecx; 1328 for (i = 0; i < 4; i++) 1329 if (p[i] != 0) 1330 *dp++ = p[i]; 1331 } 1332 if (BITX(cp->cp_edx, 31, 31) == 0) { 1333 uint8_t *p = (void *)&cp->cp_edx; 1334 for (i = 0; i < 4; i++) 1335 if (p[i] != 0) 1336 *dp++ = p[i]; 1337 } 1338 break; 1339 1340 case 3: /* Processor serial number, if PSN supported */ 1341 break; 1342 1343 case 4: /* Deterministic cache parameters */ 1344 break; 1345 1346 case 5: /* Monitor/Mwait parameters */ 1347 { 1348 size_t mwait_size; 1349 1350 /* 1351 * check cpi_mwait.support which was set in cpuid_pass1 1352 */ 1353 if (!(cpi->cpi_mwait.support & MWAIT_SUPPORT)) 1354 break; 1355 1356 /* 1357 * Protect ourself from insane mwait line size. 1358 * Workaround for incomplete hardware emulator(s). 1359 */ 1360 mwait_size = (size_t)MWAIT_SIZE_MAX(cpi); 1361 if (mwait_size < sizeof (uint32_t) || 1362 !ISP2(mwait_size)) { 1363 #if DEBUG 1364 cmn_err(CE_NOTE, "Cannot handle cpu %d mwait " 1365 "size %ld", 1366 cpu->cpu_id, (long)mwait_size); 1367 #endif 1368 break; 1369 } 1370 1371 cpi->cpi_mwait.mon_min = (size_t)MWAIT_SIZE_MIN(cpi); 1372 cpi->cpi_mwait.mon_max = mwait_size; 1373 if (MWAIT_EXTENSION(cpi)) { 1374 cpi->cpi_mwait.support |= MWAIT_EXTENSIONS; 1375 if (MWAIT_INT_ENABLE(cpi)) 1376 cpi->cpi_mwait.support |= 1377 MWAIT_ECX_INT_ENABLE; 1378 } 1379 break; 1380 } 1381 default: 1382 break; 1383 } 1384 } 1385 1386 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) 1387 goto pass2_done; 1388 1389 if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD) 1390 nmax = NMAX_CPI_EXTD; 1391 /* 1392 * Copy the extended properties, fixing them as we go. 1393 * (We already handled n == 0 and n == 1 in pass 1) 1394 */ 1395 iptr = (void *)cpi->cpi_brandstr; 1396 for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) { 1397 cp->cp_eax = 0x80000000 + n; 1398 (void) __cpuid_insn(cp); 1399 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000000 + n, cp); 1400 switch (n) { 1401 case 2: 1402 case 3: 1403 case 4: 1404 /* 1405 * Extract the brand string 1406 */ 1407 *iptr++ = cp->cp_eax; 1408 *iptr++ = cp->cp_ebx; 1409 *iptr++ = cp->cp_ecx; 1410 *iptr++ = cp->cp_edx; 1411 break; 1412 case 5: 1413 switch (cpi->cpi_vendor) { 1414 case X86_VENDOR_AMD: 1415 /* 1416 * The Athlon and Duron were the first 1417 * parts to report the sizes of the 1418 * TLB for large pages. Before then, 1419 * we don't trust the data. 1420 */ 1421 if (cpi->cpi_family < 6 || 1422 (cpi->cpi_family == 6 && 1423 cpi->cpi_model < 1)) 1424 cp->cp_eax = 0; 1425 break; 1426 default: 1427 break; 1428 } 1429 break; 1430 case 6: 1431 switch (cpi->cpi_vendor) { 1432 case X86_VENDOR_AMD: 1433 /* 1434 * The Athlon and Duron were the first 1435 * AMD parts with L2 TLB's. 1436 * Before then, don't trust the data. 1437 */ 1438 if (cpi->cpi_family < 6 || 1439 cpi->cpi_family == 6 && 1440 cpi->cpi_model < 1) 1441 cp->cp_eax = cp->cp_ebx = 0; 1442 /* 1443 * AMD Duron rev A0 reports L2 1444 * cache size incorrectly as 1K 1445 * when it is really 64K 1446 */ 1447 if (cpi->cpi_family == 6 && 1448 cpi->cpi_model == 3 && 1449 cpi->cpi_step == 0) { 1450 cp->cp_ecx &= 0xffff; 1451 cp->cp_ecx |= 0x400000; 1452 } 1453 break; 1454 case X86_VENDOR_Cyrix: /* VIA C3 */ 1455 /* 1456 * VIA C3 processors are a bit messed 1457 * up w.r.t. encoding cache sizes in %ecx 1458 */ 1459 if (cpi->cpi_family != 6) 1460 break; 1461 /* 1462 * model 7 and 8 were incorrectly encoded 1463 * 1464 * xxx is model 8 really broken? 1465 */ 1466 if (cpi->cpi_model == 7 || 1467 cpi->cpi_model == 8) 1468 cp->cp_ecx = 1469 BITX(cp->cp_ecx, 31, 24) << 16 | 1470 BITX(cp->cp_ecx, 23, 16) << 12 | 1471 BITX(cp->cp_ecx, 15, 8) << 8 | 1472 BITX(cp->cp_ecx, 7, 0); 1473 /* 1474 * model 9 stepping 1 has wrong associativity 1475 */ 1476 if (cpi->cpi_model == 9 && cpi->cpi_step == 1) 1477 cp->cp_ecx |= 8 << 12; 1478 break; 1479 case X86_VENDOR_Intel: 1480 /* 1481 * Extended L2 Cache features function. 1482 * First appeared on Prescott. 1483 */ 1484 default: 1485 break; 1486 } 1487 break; 1488 default: 1489 break; 1490 } 1491 } 1492 1493 pass2_done: 1494 cpi->cpi_pass = 2; 1495 } 1496 1497 static const char * 1498 intel_cpubrand(const struct cpuid_info *cpi) 1499 { 1500 int i; 1501 1502 if ((x86_feature & X86_CPUID) == 0 || 1503 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 1504 return ("i486"); 1505 1506 switch (cpi->cpi_family) { 1507 case 5: 1508 return ("Intel Pentium(r)"); 1509 case 6: 1510 switch (cpi->cpi_model) { 1511 uint_t celeron, xeon; 1512 const struct cpuid_regs *cp; 1513 case 0: 1514 case 1: 1515 case 2: 1516 return ("Intel Pentium(r) Pro"); 1517 case 3: 1518 case 4: 1519 return ("Intel Pentium(r) II"); 1520 case 6: 1521 return ("Intel Celeron(r)"); 1522 case 5: 1523 case 7: 1524 celeron = xeon = 0; 1525 cp = &cpi->cpi_std[2]; /* cache info */ 1526 1527 for (i = 1; i < 3; i++) { 1528 uint_t tmp; 1529 1530 tmp = (cp->cp_eax >> (8 * i)) & 0xff; 1531 if (tmp == 0x40) 1532 celeron++; 1533 if (tmp >= 0x44 && tmp <= 0x45) 1534 xeon++; 1535 } 1536 1537 for (i = 0; i < 2; i++) { 1538 uint_t tmp; 1539 1540 tmp = (cp->cp_ebx >> (8 * i)) & 0xff; 1541 if (tmp == 0x40) 1542 celeron++; 1543 else if (tmp >= 0x44 && tmp <= 0x45) 1544 xeon++; 1545 } 1546 1547 for (i = 0; i < 4; i++) { 1548 uint_t tmp; 1549 1550 tmp = (cp->cp_ecx >> (8 * i)) & 0xff; 1551 if (tmp == 0x40) 1552 celeron++; 1553 else if (tmp >= 0x44 && tmp <= 0x45) 1554 xeon++; 1555 } 1556 1557 for (i = 0; i < 4; i++) { 1558 uint_t tmp; 1559 1560 tmp = (cp->cp_edx >> (8 * i)) & 0xff; 1561 if (tmp == 0x40) 1562 celeron++; 1563 else if (tmp >= 0x44 && tmp <= 0x45) 1564 xeon++; 1565 } 1566 1567 if (celeron) 1568 return ("Intel Celeron(r)"); 1569 if (xeon) 1570 return (cpi->cpi_model == 5 ? 1571 "Intel Pentium(r) II Xeon(tm)" : 1572 "Intel Pentium(r) III Xeon(tm)"); 1573 return (cpi->cpi_model == 5 ? 1574 "Intel Pentium(r) II or Pentium(r) II Xeon(tm)" : 1575 "Intel Pentium(r) III or Pentium(r) III Xeon(tm)"); 1576 default: 1577 break; 1578 } 1579 default: 1580 break; 1581 } 1582 1583 /* BrandID is present if the field is nonzero */ 1584 if (cpi->cpi_brandid != 0) { 1585 static const struct { 1586 uint_t bt_bid; 1587 const char *bt_str; 1588 } brand_tbl[] = { 1589 { 0x1, "Intel(r) Celeron(r)" }, 1590 { 0x2, "Intel(r) Pentium(r) III" }, 1591 { 0x3, "Intel(r) Pentium(r) III Xeon(tm)" }, 1592 { 0x4, "Intel(r) Pentium(r) III" }, 1593 { 0x6, "Mobile Intel(r) Pentium(r) III" }, 1594 { 0x7, "Mobile Intel(r) Celeron(r)" }, 1595 { 0x8, "Intel(r) Pentium(r) 4" }, 1596 { 0x9, "Intel(r) Pentium(r) 4" }, 1597 { 0xa, "Intel(r) Celeron(r)" }, 1598 { 0xb, "Intel(r) Xeon(tm)" }, 1599 { 0xc, "Intel(r) Xeon(tm) MP" }, 1600 { 0xe, "Mobile Intel(r) Pentium(r) 4" }, 1601 { 0xf, "Mobile Intel(r) Celeron(r)" }, 1602 { 0x11, "Mobile Genuine Intel(r)" }, 1603 { 0x12, "Intel(r) Celeron(r) M" }, 1604 { 0x13, "Mobile Intel(r) Celeron(r)" }, 1605 { 0x14, "Intel(r) Celeron(r)" }, 1606 { 0x15, "Mobile Genuine Intel(r)" }, 1607 { 0x16, "Intel(r) Pentium(r) M" }, 1608 { 0x17, "Mobile Intel(r) Celeron(r)" } 1609 }; 1610 uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]); 1611 uint_t sgn; 1612 1613 sgn = (cpi->cpi_family << 8) | 1614 (cpi->cpi_model << 4) | cpi->cpi_step; 1615 1616 for (i = 0; i < btblmax; i++) 1617 if (brand_tbl[i].bt_bid == cpi->cpi_brandid) 1618 break; 1619 if (i < btblmax) { 1620 if (sgn == 0x6b1 && cpi->cpi_brandid == 3) 1621 return ("Intel(r) Celeron(r)"); 1622 if (sgn < 0xf13 && cpi->cpi_brandid == 0xb) 1623 return ("Intel(r) Xeon(tm) MP"); 1624 if (sgn < 0xf13 && cpi->cpi_brandid == 0xe) 1625 return ("Intel(r) Xeon(tm)"); 1626 return (brand_tbl[i].bt_str); 1627 } 1628 } 1629 1630 return (NULL); 1631 } 1632 1633 static const char * 1634 amd_cpubrand(const struct cpuid_info *cpi) 1635 { 1636 if ((x86_feature & X86_CPUID) == 0 || 1637 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 1638 return ("i486 compatible"); 1639 1640 switch (cpi->cpi_family) { 1641 case 5: 1642 switch (cpi->cpi_model) { 1643 case 0: 1644 case 1: 1645 case 2: 1646 case 3: 1647 case 4: 1648 case 5: 1649 return ("AMD-K5(r)"); 1650 case 6: 1651 case 7: 1652 return ("AMD-K6(r)"); 1653 case 8: 1654 return ("AMD-K6(r)-2"); 1655 case 9: 1656 return ("AMD-K6(r)-III"); 1657 default: 1658 return ("AMD (family 5)"); 1659 } 1660 case 6: 1661 switch (cpi->cpi_model) { 1662 case 1: 1663 return ("AMD-K7(tm)"); 1664 case 0: 1665 case 2: 1666 case 4: 1667 return ("AMD Athlon(tm)"); 1668 case 3: 1669 case 7: 1670 return ("AMD Duron(tm)"); 1671 case 6: 1672 case 8: 1673 case 10: 1674 /* 1675 * Use the L2 cache size to distinguish 1676 */ 1677 return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ? 1678 "AMD Athlon(tm)" : "AMD Duron(tm)"); 1679 default: 1680 return ("AMD (family 6)"); 1681 } 1682 default: 1683 break; 1684 } 1685 1686 if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 && 1687 cpi->cpi_brandid != 0) { 1688 switch (BITX(cpi->cpi_brandid, 7, 5)) { 1689 case 3: 1690 return ("AMD Opteron(tm) UP 1xx"); 1691 case 4: 1692 return ("AMD Opteron(tm) DP 2xx"); 1693 case 5: 1694 return ("AMD Opteron(tm) MP 8xx"); 1695 default: 1696 return ("AMD Opteron(tm)"); 1697 } 1698 } 1699 1700 return (NULL); 1701 } 1702 1703 static const char * 1704 cyrix_cpubrand(struct cpuid_info *cpi, uint_t type) 1705 { 1706 if ((x86_feature & X86_CPUID) == 0 || 1707 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5 || 1708 type == X86_TYPE_CYRIX_486) 1709 return ("i486 compatible"); 1710 1711 switch (type) { 1712 case X86_TYPE_CYRIX_6x86: 1713 return ("Cyrix 6x86"); 1714 case X86_TYPE_CYRIX_6x86L: 1715 return ("Cyrix 6x86L"); 1716 case X86_TYPE_CYRIX_6x86MX: 1717 return ("Cyrix 6x86MX"); 1718 case X86_TYPE_CYRIX_GXm: 1719 return ("Cyrix GXm"); 1720 case X86_TYPE_CYRIX_MediaGX: 1721 return ("Cyrix MediaGX"); 1722 case X86_TYPE_CYRIX_MII: 1723 return ("Cyrix M2"); 1724 case X86_TYPE_VIA_CYRIX_III: 1725 return ("VIA Cyrix M3"); 1726 default: 1727 /* 1728 * Have another wild guess .. 1729 */ 1730 if (cpi->cpi_family == 4 && cpi->cpi_model == 9) 1731 return ("Cyrix 5x86"); 1732 else if (cpi->cpi_family == 5) { 1733 switch (cpi->cpi_model) { 1734 case 2: 1735 return ("Cyrix 6x86"); /* Cyrix M1 */ 1736 case 4: 1737 return ("Cyrix MediaGX"); 1738 default: 1739 break; 1740 } 1741 } else if (cpi->cpi_family == 6) { 1742 switch (cpi->cpi_model) { 1743 case 0: 1744 return ("Cyrix 6x86MX"); /* Cyrix M2? */ 1745 case 5: 1746 case 6: 1747 case 7: 1748 case 8: 1749 case 9: 1750 return ("VIA C3"); 1751 default: 1752 break; 1753 } 1754 } 1755 break; 1756 } 1757 return (NULL); 1758 } 1759 1760 /* 1761 * This only gets called in the case that the CPU extended 1762 * feature brand string (0x80000002, 0x80000003, 0x80000004) 1763 * aren't available, or contain null bytes for some reason. 1764 */ 1765 static void 1766 fabricate_brandstr(struct cpuid_info *cpi) 1767 { 1768 const char *brand = NULL; 1769 1770 switch (cpi->cpi_vendor) { 1771 case X86_VENDOR_Intel: 1772 brand = intel_cpubrand(cpi); 1773 break; 1774 case X86_VENDOR_AMD: 1775 brand = amd_cpubrand(cpi); 1776 break; 1777 case X86_VENDOR_Cyrix: 1778 brand = cyrix_cpubrand(cpi, x86_type); 1779 break; 1780 case X86_VENDOR_NexGen: 1781 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 1782 brand = "NexGen Nx586"; 1783 break; 1784 case X86_VENDOR_Centaur: 1785 if (cpi->cpi_family == 5) 1786 switch (cpi->cpi_model) { 1787 case 4: 1788 brand = "Centaur C6"; 1789 break; 1790 case 8: 1791 brand = "Centaur C2"; 1792 break; 1793 case 9: 1794 brand = "Centaur C3"; 1795 break; 1796 default: 1797 break; 1798 } 1799 break; 1800 case X86_VENDOR_Rise: 1801 if (cpi->cpi_family == 5 && 1802 (cpi->cpi_model == 0 || cpi->cpi_model == 2)) 1803 brand = "Rise mP6"; 1804 break; 1805 case X86_VENDOR_SiS: 1806 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 1807 brand = "SiS 55x"; 1808 break; 1809 case X86_VENDOR_TM: 1810 if (cpi->cpi_family == 5 && cpi->cpi_model == 4) 1811 brand = "Transmeta Crusoe TM3x00 or TM5x00"; 1812 break; 1813 case X86_VENDOR_NSC: 1814 case X86_VENDOR_UMC: 1815 default: 1816 break; 1817 } 1818 if (brand) { 1819 (void) strcpy((char *)cpi->cpi_brandstr, brand); 1820 return; 1821 } 1822 1823 /* 1824 * If all else fails ... 1825 */ 1826 (void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr), 1827 "%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family, 1828 cpi->cpi_model, cpi->cpi_step); 1829 } 1830 1831 /* 1832 * This routine is called just after kernel memory allocation 1833 * becomes available on cpu0, and as part of mp_startup() on 1834 * the other cpus. 1835 * 1836 * Fixup the brand string, and collect any information from cpuid 1837 * that requires dynamicically allocated storage to represent. 1838 */ 1839 /*ARGSUSED*/ 1840 void 1841 cpuid_pass3(cpu_t *cpu) 1842 { 1843 int i, max, shft, level, size; 1844 struct cpuid_regs regs; 1845 struct cpuid_regs *cp; 1846 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1847 1848 ASSERT(cpi->cpi_pass == 2); 1849 1850 /* 1851 * Function 4: Deterministic cache parameters 1852 * 1853 * Take this opportunity to detect the number of threads 1854 * sharing the last level cache, and construct a corresponding 1855 * cache id. The respective cpuid_info members are initialized 1856 * to the default case of "no last level cache sharing". 1857 */ 1858 cpi->cpi_ncpu_shr_last_cache = 1; 1859 cpi->cpi_last_lvl_cacheid = cpu->cpu_id; 1860 1861 if (cpi->cpi_maxeax >= 4 && cpi->cpi_vendor == X86_VENDOR_Intel) { 1862 1863 /* 1864 * Find the # of elements (size) returned by fn 4, and along 1865 * the way detect last level cache sharing details. 1866 */ 1867 bzero(®s, sizeof (regs)); 1868 cp = ®s; 1869 for (i = 0, max = 0; i < CPI_FN4_ECX_MAX; i++) { 1870 cp->cp_eax = 4; 1871 cp->cp_ecx = i; 1872 1873 (void) __cpuid_insn(cp); 1874 1875 if (CPI_CACHE_TYPE(cp) == 0) 1876 break; 1877 level = CPI_CACHE_LVL(cp); 1878 if (level > max) { 1879 max = level; 1880 cpi->cpi_ncpu_shr_last_cache = 1881 CPI_NTHR_SHR_CACHE(cp) + 1; 1882 } 1883 } 1884 cpi->cpi_std_4_size = size = i; 1885 1886 /* 1887 * Allocate the cpi_std_4 array. The first element 1888 * references the regs for fn 4, %ecx == 0, which 1889 * cpuid_pass2() stashed in cpi->cpi_std[4]. 1890 */ 1891 if (size > 0) { 1892 cpi->cpi_std_4 = 1893 kmem_alloc(size * sizeof (cp), KM_SLEEP); 1894 cpi->cpi_std_4[0] = &cpi->cpi_std[4]; 1895 1896 /* 1897 * Allocate storage to hold the additional regs 1898 * for function 4, %ecx == 1 .. cpi_std_4_size. 1899 * 1900 * The regs for fn 4, %ecx == 0 has already 1901 * been allocated as indicated above. 1902 */ 1903 for (i = 1; i < size; i++) { 1904 cp = cpi->cpi_std_4[i] = 1905 kmem_zalloc(sizeof (regs), KM_SLEEP); 1906 cp->cp_eax = 4; 1907 cp->cp_ecx = i; 1908 1909 (void) __cpuid_insn(cp); 1910 } 1911 } 1912 /* 1913 * Determine the number of bits needed to represent 1914 * the number of CPUs sharing the last level cache. 1915 * 1916 * Shift off that number of bits from the APIC id to 1917 * derive the cache id. 1918 */ 1919 shft = 0; 1920 for (i = 1; i < cpi->cpi_ncpu_shr_last_cache; i <<= 1) 1921 shft++; 1922 cpi->cpi_last_lvl_cacheid = CPI_APIC_ID(cpi) >> shft; 1923 } 1924 1925 /* 1926 * Now fixup the brand string 1927 */ 1928 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) { 1929 fabricate_brandstr(cpi); 1930 } else { 1931 1932 /* 1933 * If we successfully extracted a brand string from the cpuid 1934 * instruction, clean it up by removing leading spaces and 1935 * similar junk. 1936 */ 1937 if (cpi->cpi_brandstr[0]) { 1938 size_t maxlen = sizeof (cpi->cpi_brandstr); 1939 char *src, *dst; 1940 1941 dst = src = (char *)cpi->cpi_brandstr; 1942 src[maxlen - 1] = '\0'; 1943 /* 1944 * strip leading spaces 1945 */ 1946 while (*src == ' ') 1947 src++; 1948 /* 1949 * Remove any 'Genuine' or "Authentic" prefixes 1950 */ 1951 if (strncmp(src, "Genuine ", 8) == 0) 1952 src += 8; 1953 if (strncmp(src, "Authentic ", 10) == 0) 1954 src += 10; 1955 1956 /* 1957 * Now do an in-place copy. 1958 * Map (R) to (r) and (TM) to (tm). 1959 * The era of teletypes is long gone, and there's 1960 * -really- no need to shout. 1961 */ 1962 while (*src != '\0') { 1963 if (src[0] == '(') { 1964 if (strncmp(src + 1, "R)", 2) == 0) { 1965 (void) strncpy(dst, "(r)", 3); 1966 src += 3; 1967 dst += 3; 1968 continue; 1969 } 1970 if (strncmp(src + 1, "TM)", 3) == 0) { 1971 (void) strncpy(dst, "(tm)", 4); 1972 src += 4; 1973 dst += 4; 1974 continue; 1975 } 1976 } 1977 *dst++ = *src++; 1978 } 1979 *dst = '\0'; 1980 1981 /* 1982 * Finally, remove any trailing spaces 1983 */ 1984 while (--dst > cpi->cpi_brandstr) 1985 if (*dst == ' ') 1986 *dst = '\0'; 1987 else 1988 break; 1989 } else 1990 fabricate_brandstr(cpi); 1991 } 1992 cpi->cpi_pass = 3; 1993 } 1994 1995 /* 1996 * This routine is called out of bind_hwcap() much later in the life 1997 * of the kernel (post_startup()). The job of this routine is to resolve 1998 * the hardware feature support and kernel support for those features into 1999 * what we're actually going to tell applications via the aux vector. 2000 */ 2001 uint_t 2002 cpuid_pass4(cpu_t *cpu) 2003 { 2004 struct cpuid_info *cpi; 2005 uint_t hwcap_flags = 0; 2006 2007 if (cpu == NULL) 2008 cpu = CPU; 2009 cpi = cpu->cpu_m.mcpu_cpi; 2010 2011 ASSERT(cpi->cpi_pass == 3); 2012 2013 if (cpi->cpi_maxeax >= 1) { 2014 uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES]; 2015 uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES]; 2016 2017 *edx = CPI_FEATURES_EDX(cpi); 2018 *ecx = CPI_FEATURES_ECX(cpi); 2019 2020 /* 2021 * [these require explicit kernel support] 2022 */ 2023 if ((x86_feature & X86_SEP) == 0) 2024 *edx &= ~CPUID_INTC_EDX_SEP; 2025 2026 if ((x86_feature & X86_SSE) == 0) 2027 *edx &= ~(CPUID_INTC_EDX_FXSR|CPUID_INTC_EDX_SSE); 2028 if ((x86_feature & X86_SSE2) == 0) 2029 *edx &= ~CPUID_INTC_EDX_SSE2; 2030 2031 if ((x86_feature & X86_HTT) == 0) 2032 *edx &= ~CPUID_INTC_EDX_HTT; 2033 2034 if ((x86_feature & X86_SSE3) == 0) 2035 *ecx &= ~CPUID_INTC_ECX_SSE3; 2036 2037 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 2038 if ((x86_feature & X86_SSSE3) == 0) 2039 *ecx &= ~CPUID_INTC_ECX_SSSE3; 2040 if ((x86_feature & X86_SSE4_1) == 0) 2041 *ecx &= ~CPUID_INTC_ECX_SSE4_1; 2042 if ((x86_feature & X86_SSE4_2) == 0) 2043 *ecx &= ~CPUID_INTC_ECX_SSE4_2; 2044 } 2045 2046 /* 2047 * [no explicit support required beyond x87 fp context] 2048 */ 2049 if (!fpu_exists) 2050 *edx &= ~(CPUID_INTC_EDX_FPU | CPUID_INTC_EDX_MMX); 2051 2052 /* 2053 * Now map the supported feature vector to things that we 2054 * think userland will care about. 2055 */ 2056 if (*edx & CPUID_INTC_EDX_SEP) 2057 hwcap_flags |= AV_386_SEP; 2058 if (*edx & CPUID_INTC_EDX_SSE) 2059 hwcap_flags |= AV_386_FXSR | AV_386_SSE; 2060 if (*edx & CPUID_INTC_EDX_SSE2) 2061 hwcap_flags |= AV_386_SSE2; 2062 if (*ecx & CPUID_INTC_ECX_SSE3) 2063 hwcap_flags |= AV_386_SSE3; 2064 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 2065 if (*ecx & CPUID_INTC_ECX_SSSE3) 2066 hwcap_flags |= AV_386_SSSE3; 2067 if (*ecx & CPUID_INTC_ECX_SSE4_1) 2068 hwcap_flags |= AV_386_SSE4_1; 2069 if (*ecx & CPUID_INTC_ECX_SSE4_2) 2070 hwcap_flags |= AV_386_SSE4_2; 2071 } 2072 if (*ecx & CPUID_INTC_ECX_POPCNT) 2073 hwcap_flags |= AV_386_POPCNT; 2074 if (*edx & CPUID_INTC_EDX_FPU) 2075 hwcap_flags |= AV_386_FPU; 2076 if (*edx & CPUID_INTC_EDX_MMX) 2077 hwcap_flags |= AV_386_MMX; 2078 2079 if (*edx & CPUID_INTC_EDX_TSC) 2080 hwcap_flags |= AV_386_TSC; 2081 if (*edx & CPUID_INTC_EDX_CX8) 2082 hwcap_flags |= AV_386_CX8; 2083 if (*edx & CPUID_INTC_EDX_CMOV) 2084 hwcap_flags |= AV_386_CMOV; 2085 if (*ecx & CPUID_INTC_ECX_MON) 2086 hwcap_flags |= AV_386_MON; 2087 if (*ecx & CPUID_INTC_ECX_CX16) 2088 hwcap_flags |= AV_386_CX16; 2089 } 2090 2091 if (x86_feature & X86_HTT) 2092 hwcap_flags |= AV_386_PAUSE; 2093 2094 if (cpi->cpi_xmaxeax < 0x80000001) 2095 goto pass4_done; 2096 2097 switch (cpi->cpi_vendor) { 2098 struct cpuid_regs cp; 2099 uint32_t *edx, *ecx; 2100 2101 case X86_VENDOR_Intel: 2102 /* 2103 * Seems like Intel duplicated what we necessary 2104 * here to make the initial crop of 64-bit OS's work. 2105 * Hopefully, those are the only "extended" bits 2106 * they'll add. 2107 */ 2108 /*FALLTHROUGH*/ 2109 2110 case X86_VENDOR_AMD: 2111 edx = &cpi->cpi_support[AMD_EDX_FEATURES]; 2112 ecx = &cpi->cpi_support[AMD_ECX_FEATURES]; 2113 2114 *edx = CPI_FEATURES_XTD_EDX(cpi); 2115 *ecx = CPI_FEATURES_XTD_ECX(cpi); 2116 2117 /* 2118 * [these features require explicit kernel support] 2119 */ 2120 switch (cpi->cpi_vendor) { 2121 case X86_VENDOR_Intel: 2122 break; 2123 2124 case X86_VENDOR_AMD: 2125 if ((x86_feature & X86_TSCP) == 0) 2126 *edx &= ~CPUID_AMD_EDX_TSCP; 2127 if ((x86_feature & X86_SSE4A) == 0) 2128 *ecx &= ~CPUID_AMD_ECX_SSE4A; 2129 break; 2130 2131 default: 2132 break; 2133 } 2134 2135 /* 2136 * [no explicit support required beyond 2137 * x87 fp context and exception handlers] 2138 */ 2139 if (!fpu_exists) 2140 *edx &= ~(CPUID_AMD_EDX_MMXamd | 2141 CPUID_AMD_EDX_3DNow | CPUID_AMD_EDX_3DNowx); 2142 2143 if ((x86_feature & X86_NX) == 0) 2144 *edx &= ~CPUID_AMD_EDX_NX; 2145 #if !defined(__amd64) 2146 *edx &= ~CPUID_AMD_EDX_LM; 2147 #endif 2148 /* 2149 * Now map the supported feature vector to 2150 * things that we think userland will care about. 2151 */ 2152 #if defined(__amd64) 2153 if (*edx & CPUID_AMD_EDX_SYSC) 2154 hwcap_flags |= AV_386_AMD_SYSC; 2155 #endif 2156 if (*edx & CPUID_AMD_EDX_MMXamd) 2157 hwcap_flags |= AV_386_AMD_MMX; 2158 if (*edx & CPUID_AMD_EDX_3DNow) 2159 hwcap_flags |= AV_386_AMD_3DNow; 2160 if (*edx & CPUID_AMD_EDX_3DNowx) 2161 hwcap_flags |= AV_386_AMD_3DNowx; 2162 2163 switch (cpi->cpi_vendor) { 2164 case X86_VENDOR_AMD: 2165 if (*edx & CPUID_AMD_EDX_TSCP) 2166 hwcap_flags |= AV_386_TSCP; 2167 if (*ecx & CPUID_AMD_ECX_AHF64) 2168 hwcap_flags |= AV_386_AHF; 2169 if (*ecx & CPUID_AMD_ECX_SSE4A) 2170 hwcap_flags |= AV_386_AMD_SSE4A; 2171 if (*ecx & CPUID_AMD_ECX_LZCNT) 2172 hwcap_flags |= AV_386_AMD_LZCNT; 2173 break; 2174 2175 case X86_VENDOR_Intel: 2176 /* 2177 * Aarrgh. 2178 * Intel uses a different bit in the same word. 2179 */ 2180 if (*ecx & CPUID_INTC_ECX_AHF64) 2181 hwcap_flags |= AV_386_AHF; 2182 break; 2183 2184 default: 2185 break; 2186 } 2187 break; 2188 2189 case X86_VENDOR_TM: 2190 cp.cp_eax = 0x80860001; 2191 (void) __cpuid_insn(&cp); 2192 cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx; 2193 break; 2194 2195 default: 2196 break; 2197 } 2198 2199 pass4_done: 2200 cpi->cpi_pass = 4; 2201 return (hwcap_flags); 2202 } 2203 2204 2205 /* 2206 * Simulate the cpuid instruction using the data we previously 2207 * captured about this CPU. We try our best to return the truth 2208 * about the hardware, independently of kernel support. 2209 */ 2210 uint32_t 2211 cpuid_insn(cpu_t *cpu, struct cpuid_regs *cp) 2212 { 2213 struct cpuid_info *cpi; 2214 struct cpuid_regs *xcp; 2215 2216 if (cpu == NULL) 2217 cpu = CPU; 2218 cpi = cpu->cpu_m.mcpu_cpi; 2219 2220 ASSERT(cpuid_checkpass(cpu, 3)); 2221 2222 /* 2223 * CPUID data is cached in two separate places: cpi_std for standard 2224 * CPUID functions, and cpi_extd for extended CPUID functions. 2225 */ 2226 if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD) 2227 xcp = &cpi->cpi_std[cp->cp_eax]; 2228 else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax && 2229 cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD) 2230 xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000]; 2231 else 2232 /* 2233 * The caller is asking for data from an input parameter which 2234 * the kernel has not cached. In this case we go fetch from 2235 * the hardware and return the data directly to the user. 2236 */ 2237 return (__cpuid_insn(cp)); 2238 2239 cp->cp_eax = xcp->cp_eax; 2240 cp->cp_ebx = xcp->cp_ebx; 2241 cp->cp_ecx = xcp->cp_ecx; 2242 cp->cp_edx = xcp->cp_edx; 2243 return (cp->cp_eax); 2244 } 2245 2246 int 2247 cpuid_checkpass(cpu_t *cpu, int pass) 2248 { 2249 return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL && 2250 cpu->cpu_m.mcpu_cpi->cpi_pass >= pass); 2251 } 2252 2253 int 2254 cpuid_getbrandstr(cpu_t *cpu, char *s, size_t n) 2255 { 2256 ASSERT(cpuid_checkpass(cpu, 3)); 2257 2258 return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr)); 2259 } 2260 2261 int 2262 cpuid_is_cmt(cpu_t *cpu) 2263 { 2264 if (cpu == NULL) 2265 cpu = CPU; 2266 2267 ASSERT(cpuid_checkpass(cpu, 1)); 2268 2269 return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0); 2270 } 2271 2272 /* 2273 * AMD and Intel both implement the 64-bit variant of the syscall 2274 * instruction (syscallq), so if there's -any- support for syscall, 2275 * cpuid currently says "yes, we support this". 2276 * 2277 * However, Intel decided to -not- implement the 32-bit variant of the 2278 * syscall instruction, so we provide a predicate to allow our caller 2279 * to test that subtlety here. 2280 * 2281 * XXPV Currently, 32-bit syscall instructions don't work via the hypervisor, 2282 * even in the case where the hardware would in fact support it. 2283 */ 2284 /*ARGSUSED*/ 2285 int 2286 cpuid_syscall32_insn(cpu_t *cpu) 2287 { 2288 ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1)); 2289 2290 #if !defined(__xpv) 2291 if (cpu == NULL) 2292 cpu = CPU; 2293 2294 /*CSTYLED*/ 2295 { 2296 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2297 2298 if (cpi->cpi_vendor == X86_VENDOR_AMD && 2299 cpi->cpi_xmaxeax >= 0x80000001 && 2300 (CPI_FEATURES_XTD_EDX(cpi) & CPUID_AMD_EDX_SYSC)) 2301 return (1); 2302 } 2303 #endif 2304 return (0); 2305 } 2306 2307 int 2308 cpuid_getidstr(cpu_t *cpu, char *s, size_t n) 2309 { 2310 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2311 2312 static const char fmt[] = 2313 "x86 (%s %X family %d model %d step %d clock %d MHz)"; 2314 static const char fmt_ht[] = 2315 "x86 (chipid 0x%x %s %X family %d model %d step %d clock %d MHz)"; 2316 2317 ASSERT(cpuid_checkpass(cpu, 1)); 2318 2319 if (cpuid_is_cmt(cpu)) 2320 return (snprintf(s, n, fmt_ht, cpi->cpi_chipid, 2321 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, 2322 cpi->cpi_family, cpi->cpi_model, 2323 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 2324 return (snprintf(s, n, fmt, 2325 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, 2326 cpi->cpi_family, cpi->cpi_model, 2327 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 2328 } 2329 2330 const char * 2331 cpuid_getvendorstr(cpu_t *cpu) 2332 { 2333 ASSERT(cpuid_checkpass(cpu, 1)); 2334 return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr); 2335 } 2336 2337 uint_t 2338 cpuid_getvendor(cpu_t *cpu) 2339 { 2340 ASSERT(cpuid_checkpass(cpu, 1)); 2341 return (cpu->cpu_m.mcpu_cpi->cpi_vendor); 2342 } 2343 2344 uint_t 2345 cpuid_getfamily(cpu_t *cpu) 2346 { 2347 ASSERT(cpuid_checkpass(cpu, 1)); 2348 return (cpu->cpu_m.mcpu_cpi->cpi_family); 2349 } 2350 2351 uint_t 2352 cpuid_getmodel(cpu_t *cpu) 2353 { 2354 ASSERT(cpuid_checkpass(cpu, 1)); 2355 return (cpu->cpu_m.mcpu_cpi->cpi_model); 2356 } 2357 2358 uint_t 2359 cpuid_get_ncpu_per_chip(cpu_t *cpu) 2360 { 2361 ASSERT(cpuid_checkpass(cpu, 1)); 2362 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip); 2363 } 2364 2365 uint_t 2366 cpuid_get_ncore_per_chip(cpu_t *cpu) 2367 { 2368 ASSERT(cpuid_checkpass(cpu, 1)); 2369 return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip); 2370 } 2371 2372 uint_t 2373 cpuid_get_ncpu_sharing_last_cache(cpu_t *cpu) 2374 { 2375 ASSERT(cpuid_checkpass(cpu, 2)); 2376 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_shr_last_cache); 2377 } 2378 2379 id_t 2380 cpuid_get_last_lvl_cacheid(cpu_t *cpu) 2381 { 2382 ASSERT(cpuid_checkpass(cpu, 2)); 2383 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid); 2384 } 2385 2386 uint_t 2387 cpuid_getstep(cpu_t *cpu) 2388 { 2389 ASSERT(cpuid_checkpass(cpu, 1)); 2390 return (cpu->cpu_m.mcpu_cpi->cpi_step); 2391 } 2392 2393 uint_t 2394 cpuid_getsig(struct cpu *cpu) 2395 { 2396 ASSERT(cpuid_checkpass(cpu, 1)); 2397 return (cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_eax); 2398 } 2399 2400 uint32_t 2401 cpuid_getchiprev(struct cpu *cpu) 2402 { 2403 ASSERT(cpuid_checkpass(cpu, 1)); 2404 return (cpu->cpu_m.mcpu_cpi->cpi_chiprev); 2405 } 2406 2407 const char * 2408 cpuid_getchiprevstr(struct cpu *cpu) 2409 { 2410 ASSERT(cpuid_checkpass(cpu, 1)); 2411 return (cpu->cpu_m.mcpu_cpi->cpi_chiprevstr); 2412 } 2413 2414 uint32_t 2415 cpuid_getsockettype(struct cpu *cpu) 2416 { 2417 ASSERT(cpuid_checkpass(cpu, 1)); 2418 return (cpu->cpu_m.mcpu_cpi->cpi_socket); 2419 } 2420 2421 int 2422 cpuid_get_chipid(cpu_t *cpu) 2423 { 2424 ASSERT(cpuid_checkpass(cpu, 1)); 2425 2426 if (cpuid_is_cmt(cpu)) 2427 return (cpu->cpu_m.mcpu_cpi->cpi_chipid); 2428 return (cpu->cpu_id); 2429 } 2430 2431 id_t 2432 cpuid_get_coreid(cpu_t *cpu) 2433 { 2434 ASSERT(cpuid_checkpass(cpu, 1)); 2435 return (cpu->cpu_m.mcpu_cpi->cpi_coreid); 2436 } 2437 2438 int 2439 cpuid_get_clogid(cpu_t *cpu) 2440 { 2441 ASSERT(cpuid_checkpass(cpu, 1)); 2442 return (cpu->cpu_m.mcpu_cpi->cpi_clogid); 2443 } 2444 2445 void 2446 cpuid_get_addrsize(cpu_t *cpu, uint_t *pabits, uint_t *vabits) 2447 { 2448 struct cpuid_info *cpi; 2449 2450 if (cpu == NULL) 2451 cpu = CPU; 2452 cpi = cpu->cpu_m.mcpu_cpi; 2453 2454 ASSERT(cpuid_checkpass(cpu, 1)); 2455 2456 if (pabits) 2457 *pabits = cpi->cpi_pabits; 2458 if (vabits) 2459 *vabits = cpi->cpi_vabits; 2460 } 2461 2462 /* 2463 * Returns the number of data TLB entries for a corresponding 2464 * pagesize. If it can't be computed, or isn't known, the 2465 * routine returns zero. If you ask about an architecturally 2466 * impossible pagesize, the routine will panic (so that the 2467 * hat implementor knows that things are inconsistent.) 2468 */ 2469 uint_t 2470 cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize) 2471 { 2472 struct cpuid_info *cpi; 2473 uint_t dtlb_nent = 0; 2474 2475 if (cpu == NULL) 2476 cpu = CPU; 2477 cpi = cpu->cpu_m.mcpu_cpi; 2478 2479 ASSERT(cpuid_checkpass(cpu, 1)); 2480 2481 /* 2482 * Check the L2 TLB info 2483 */ 2484 if (cpi->cpi_xmaxeax >= 0x80000006) { 2485 struct cpuid_regs *cp = &cpi->cpi_extd[6]; 2486 2487 switch (pagesize) { 2488 2489 case 4 * 1024: 2490 /* 2491 * All zero in the top 16 bits of the register 2492 * indicates a unified TLB. Size is in low 16 bits. 2493 */ 2494 if ((cp->cp_ebx & 0xffff0000) == 0) 2495 dtlb_nent = cp->cp_ebx & 0x0000ffff; 2496 else 2497 dtlb_nent = BITX(cp->cp_ebx, 27, 16); 2498 break; 2499 2500 case 2 * 1024 * 1024: 2501 if ((cp->cp_eax & 0xffff0000) == 0) 2502 dtlb_nent = cp->cp_eax & 0x0000ffff; 2503 else 2504 dtlb_nent = BITX(cp->cp_eax, 27, 16); 2505 break; 2506 2507 default: 2508 panic("unknown L2 pagesize"); 2509 /*NOTREACHED*/ 2510 } 2511 } 2512 2513 if (dtlb_nent != 0) 2514 return (dtlb_nent); 2515 2516 /* 2517 * No L2 TLB support for this size, try L1. 2518 */ 2519 if (cpi->cpi_xmaxeax >= 0x80000005) { 2520 struct cpuid_regs *cp = &cpi->cpi_extd[5]; 2521 2522 switch (pagesize) { 2523 case 4 * 1024: 2524 dtlb_nent = BITX(cp->cp_ebx, 23, 16); 2525 break; 2526 case 2 * 1024 * 1024: 2527 dtlb_nent = BITX(cp->cp_eax, 23, 16); 2528 break; 2529 default: 2530 panic("unknown L1 d-TLB pagesize"); 2531 /*NOTREACHED*/ 2532 } 2533 } 2534 2535 return (dtlb_nent); 2536 } 2537 2538 /* 2539 * Return 0 if the erratum is not present or not applicable, positive 2540 * if it is, and negative if the status of the erratum is unknown. 2541 * 2542 * See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm) 2543 * Processors" #25759, Rev 3.57, August 2005 2544 */ 2545 int 2546 cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum) 2547 { 2548 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2549 uint_t eax; 2550 2551 /* 2552 * Bail out if this CPU isn't an AMD CPU, or if it's 2553 * a legacy (32-bit) AMD CPU. 2554 */ 2555 if (cpi->cpi_vendor != X86_VENDOR_AMD || 2556 cpi->cpi_family == 4 || cpi->cpi_family == 5 || 2557 cpi->cpi_family == 6) 2558 2559 return (0); 2560 2561 eax = cpi->cpi_std[1].cp_eax; 2562 2563 #define SH_B0(eax) (eax == 0xf40 || eax == 0xf50) 2564 #define SH_B3(eax) (eax == 0xf51) 2565 #define B(eax) (SH_B0(eax) || SH_B3(eax)) 2566 2567 #define SH_C0(eax) (eax == 0xf48 || eax == 0xf58) 2568 2569 #define SH_CG(eax) (eax == 0xf4a || eax == 0xf5a || eax == 0xf7a) 2570 #define DH_CG(eax) (eax == 0xfc0 || eax == 0xfe0 || eax == 0xff0) 2571 #define CH_CG(eax) (eax == 0xf82 || eax == 0xfb2) 2572 #define CG(eax) (SH_CG(eax) || DH_CG(eax) || CH_CG(eax)) 2573 2574 #define SH_D0(eax) (eax == 0x10f40 || eax == 0x10f50 || eax == 0x10f70) 2575 #define DH_D0(eax) (eax == 0x10fc0 || eax == 0x10ff0) 2576 #define CH_D0(eax) (eax == 0x10f80 || eax == 0x10fb0) 2577 #define D0(eax) (SH_D0(eax) || DH_D0(eax) || CH_D0(eax)) 2578 2579 #define SH_E0(eax) (eax == 0x20f50 || eax == 0x20f40 || eax == 0x20f70) 2580 #define JH_E1(eax) (eax == 0x20f10) /* JH8_E0 had 0x20f30 */ 2581 #define DH_E3(eax) (eax == 0x20fc0 || eax == 0x20ff0) 2582 #define SH_E4(eax) (eax == 0x20f51 || eax == 0x20f71) 2583 #define BH_E4(eax) (eax == 0x20fb1) 2584 #define SH_E5(eax) (eax == 0x20f42) 2585 #define DH_E6(eax) (eax == 0x20ff2 || eax == 0x20fc2) 2586 #define JH_E6(eax) (eax == 0x20f12 || eax == 0x20f32) 2587 #define EX(eax) (SH_E0(eax) || JH_E1(eax) || DH_E3(eax) || \ 2588 SH_E4(eax) || BH_E4(eax) || SH_E5(eax) || \ 2589 DH_E6(eax) || JH_E6(eax)) 2590 2591 switch (erratum) { 2592 case 1: 2593 return (cpi->cpi_family < 0x10); 2594 case 51: /* what does the asterisk mean? */ 2595 return (B(eax) || SH_C0(eax) || CG(eax)); 2596 case 52: 2597 return (B(eax)); 2598 case 57: 2599 return (cpi->cpi_family <= 0x10); 2600 case 58: 2601 return (B(eax)); 2602 case 60: 2603 return (cpi->cpi_family <= 0x10); 2604 case 61: 2605 case 62: 2606 case 63: 2607 case 64: 2608 case 65: 2609 case 66: 2610 case 68: 2611 case 69: 2612 case 70: 2613 case 71: 2614 return (B(eax)); 2615 case 72: 2616 return (SH_B0(eax)); 2617 case 74: 2618 return (B(eax)); 2619 case 75: 2620 return (cpi->cpi_family < 0x10); 2621 case 76: 2622 return (B(eax)); 2623 case 77: 2624 return (cpi->cpi_family <= 0x10); 2625 case 78: 2626 return (B(eax) || SH_C0(eax)); 2627 case 79: 2628 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2629 case 80: 2630 case 81: 2631 case 82: 2632 return (B(eax)); 2633 case 83: 2634 return (B(eax) || SH_C0(eax) || CG(eax)); 2635 case 85: 2636 return (cpi->cpi_family < 0x10); 2637 case 86: 2638 return (SH_C0(eax) || CG(eax)); 2639 case 88: 2640 #if !defined(__amd64) 2641 return (0); 2642 #else 2643 return (B(eax) || SH_C0(eax)); 2644 #endif 2645 case 89: 2646 return (cpi->cpi_family < 0x10); 2647 case 90: 2648 return (B(eax) || SH_C0(eax) || CG(eax)); 2649 case 91: 2650 case 92: 2651 return (B(eax) || SH_C0(eax)); 2652 case 93: 2653 return (SH_C0(eax)); 2654 case 94: 2655 return (B(eax) || SH_C0(eax) || CG(eax)); 2656 case 95: 2657 #if !defined(__amd64) 2658 return (0); 2659 #else 2660 return (B(eax) || SH_C0(eax)); 2661 #endif 2662 case 96: 2663 return (B(eax) || SH_C0(eax) || CG(eax)); 2664 case 97: 2665 case 98: 2666 return (SH_C0(eax) || CG(eax)); 2667 case 99: 2668 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2669 case 100: 2670 return (B(eax) || SH_C0(eax)); 2671 case 101: 2672 case 103: 2673 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2674 case 104: 2675 return (SH_C0(eax) || CG(eax) || D0(eax)); 2676 case 105: 2677 case 106: 2678 case 107: 2679 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2680 case 108: 2681 return (DH_CG(eax)); 2682 case 109: 2683 return (SH_C0(eax) || CG(eax) || D0(eax)); 2684 case 110: 2685 return (D0(eax) || EX(eax)); 2686 case 111: 2687 return (CG(eax)); 2688 case 112: 2689 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2690 case 113: 2691 return (eax == 0x20fc0); 2692 case 114: 2693 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 2694 case 115: 2695 return (SH_E0(eax) || JH_E1(eax)); 2696 case 116: 2697 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 2698 case 117: 2699 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2700 case 118: 2701 return (SH_E0(eax) || JH_E1(eax) || SH_E4(eax) || BH_E4(eax) || 2702 JH_E6(eax)); 2703 case 121: 2704 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2705 case 122: 2706 return (cpi->cpi_family < 0x10); 2707 case 123: 2708 return (JH_E1(eax) || BH_E4(eax) || JH_E6(eax)); 2709 case 131: 2710 return (cpi->cpi_family < 0x10); 2711 case 6336786: 2712 /* 2713 * Test for AdvPowerMgmtInfo.TscPStateInvariant 2714 * if this is a K8 family or newer processor 2715 */ 2716 if (CPI_FAMILY(cpi) == 0xf) { 2717 struct cpuid_regs regs; 2718 regs.cp_eax = 0x80000007; 2719 (void) __cpuid_insn(®s); 2720 return (!(regs.cp_edx & 0x100)); 2721 } 2722 return (0); 2723 case 6323525: 2724 return (((((eax >> 12) & 0xff00) + (eax & 0xf00)) | 2725 (((eax >> 4) & 0xf) | ((eax >> 12) & 0xf0))) < 0xf40); 2726 2727 default: 2728 return (-1); 2729 } 2730 } 2731 2732 static const char assoc_str[] = "associativity"; 2733 static const char line_str[] = "line-size"; 2734 static const char size_str[] = "size"; 2735 2736 static void 2737 add_cache_prop(dev_info_t *devi, const char *label, const char *type, 2738 uint32_t val) 2739 { 2740 char buf[128]; 2741 2742 /* 2743 * ndi_prop_update_int() is used because it is desirable for 2744 * DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set. 2745 */ 2746 if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf)) 2747 (void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val); 2748 } 2749 2750 /* 2751 * Intel-style cache/tlb description 2752 * 2753 * Standard cpuid level 2 gives a randomly ordered 2754 * selection of tags that index into a table that describes 2755 * cache and tlb properties. 2756 */ 2757 2758 static const char l1_icache_str[] = "l1-icache"; 2759 static const char l1_dcache_str[] = "l1-dcache"; 2760 static const char l2_cache_str[] = "l2-cache"; 2761 static const char l3_cache_str[] = "l3-cache"; 2762 static const char itlb4k_str[] = "itlb-4K"; 2763 static const char dtlb4k_str[] = "dtlb-4K"; 2764 static const char itlb4M_str[] = "itlb-4M"; 2765 static const char dtlb4M_str[] = "dtlb-4M"; 2766 static const char itlb424_str[] = "itlb-4K-2M-4M"; 2767 static const char dtlb44_str[] = "dtlb-4K-4M"; 2768 static const char sl1_dcache_str[] = "sectored-l1-dcache"; 2769 static const char sl2_cache_str[] = "sectored-l2-cache"; 2770 static const char itrace_str[] = "itrace-cache"; 2771 static const char sl3_cache_str[] = "sectored-l3-cache"; 2772 2773 static const struct cachetab { 2774 uint8_t ct_code; 2775 uint8_t ct_assoc; 2776 uint16_t ct_line_size; 2777 size_t ct_size; 2778 const char *ct_label; 2779 } intel_ctab[] = { 2780 /* maintain descending order! */ 2781 { 0xb4, 4, 0, 256, dtlb4k_str }, 2782 { 0xb3, 4, 0, 128, dtlb4k_str }, 2783 { 0xb0, 4, 0, 128, itlb4k_str }, 2784 { 0x87, 8, 64, 1024*1024, l2_cache_str}, 2785 { 0x86, 4, 64, 512*1024, l2_cache_str}, 2786 { 0x85, 8, 32, 2*1024*1024, l2_cache_str}, 2787 { 0x84, 8, 32, 1024*1024, l2_cache_str}, 2788 { 0x83, 8, 32, 512*1024, l2_cache_str}, 2789 { 0x82, 8, 32, 256*1024, l2_cache_str}, 2790 { 0x7f, 2, 64, 512*1024, l2_cache_str}, 2791 { 0x7d, 8, 64, 2*1024*1024, sl2_cache_str}, 2792 { 0x7c, 8, 64, 1024*1024, sl2_cache_str}, 2793 { 0x7b, 8, 64, 512*1024, sl2_cache_str}, 2794 { 0x7a, 8, 64, 256*1024, sl2_cache_str}, 2795 { 0x79, 8, 64, 128*1024, sl2_cache_str}, 2796 { 0x78, 8, 64, 1024*1024, l2_cache_str}, 2797 { 0x73, 8, 0, 64*1024, itrace_str}, 2798 { 0x72, 8, 0, 32*1024, itrace_str}, 2799 { 0x71, 8, 0, 16*1024, itrace_str}, 2800 { 0x70, 8, 0, 12*1024, itrace_str}, 2801 { 0x68, 4, 64, 32*1024, sl1_dcache_str}, 2802 { 0x67, 4, 64, 16*1024, sl1_dcache_str}, 2803 { 0x66, 4, 64, 8*1024, sl1_dcache_str}, 2804 { 0x60, 8, 64, 16*1024, sl1_dcache_str}, 2805 { 0x5d, 0, 0, 256, dtlb44_str}, 2806 { 0x5c, 0, 0, 128, dtlb44_str}, 2807 { 0x5b, 0, 0, 64, dtlb44_str}, 2808 { 0x52, 0, 0, 256, itlb424_str}, 2809 { 0x51, 0, 0, 128, itlb424_str}, 2810 { 0x50, 0, 0, 64, itlb424_str}, 2811 { 0x4d, 16, 64, 16*1024*1024, l3_cache_str}, 2812 { 0x4c, 12, 64, 12*1024*1024, l3_cache_str}, 2813 { 0x4b, 16, 64, 8*1024*1024, l3_cache_str}, 2814 { 0x4a, 12, 64, 6*1024*1024, l3_cache_str}, 2815 { 0x49, 16, 64, 4*1024*1024, l3_cache_str}, 2816 { 0x47, 8, 64, 8*1024*1024, l3_cache_str}, 2817 { 0x46, 4, 64, 4*1024*1024, l3_cache_str}, 2818 { 0x45, 4, 32, 2*1024*1024, l2_cache_str}, 2819 { 0x44, 4, 32, 1024*1024, l2_cache_str}, 2820 { 0x43, 4, 32, 512*1024, l2_cache_str}, 2821 { 0x42, 4, 32, 256*1024, l2_cache_str}, 2822 { 0x41, 4, 32, 128*1024, l2_cache_str}, 2823 { 0x3e, 4, 64, 512*1024, sl2_cache_str}, 2824 { 0x3d, 6, 64, 384*1024, sl2_cache_str}, 2825 { 0x3c, 4, 64, 256*1024, sl2_cache_str}, 2826 { 0x3b, 2, 64, 128*1024, sl2_cache_str}, 2827 { 0x3a, 6, 64, 192*1024, sl2_cache_str}, 2828 { 0x39, 4, 64, 128*1024, sl2_cache_str}, 2829 { 0x30, 8, 64, 32*1024, l1_icache_str}, 2830 { 0x2c, 8, 64, 32*1024, l1_dcache_str}, 2831 { 0x29, 8, 64, 4096*1024, sl3_cache_str}, 2832 { 0x25, 8, 64, 2048*1024, sl3_cache_str}, 2833 { 0x23, 8, 64, 1024*1024, sl3_cache_str}, 2834 { 0x22, 4, 64, 512*1024, sl3_cache_str}, 2835 { 0x0c, 4, 32, 16*1024, l1_dcache_str}, 2836 { 0x0b, 4, 0, 4, itlb4M_str}, 2837 { 0x0a, 2, 32, 8*1024, l1_dcache_str}, 2838 { 0x08, 4, 32, 16*1024, l1_icache_str}, 2839 { 0x06, 4, 32, 8*1024, l1_icache_str}, 2840 { 0x04, 4, 0, 8, dtlb4M_str}, 2841 { 0x03, 4, 0, 64, dtlb4k_str}, 2842 { 0x02, 4, 0, 2, itlb4M_str}, 2843 { 0x01, 4, 0, 32, itlb4k_str}, 2844 { 0 } 2845 }; 2846 2847 static const struct cachetab cyrix_ctab[] = { 2848 { 0x70, 4, 0, 32, "tlb-4K" }, 2849 { 0x80, 4, 16, 16*1024, "l1-cache" }, 2850 { 0 } 2851 }; 2852 2853 /* 2854 * Search a cache table for a matching entry 2855 */ 2856 static const struct cachetab * 2857 find_cacheent(const struct cachetab *ct, uint_t code) 2858 { 2859 if (code != 0) { 2860 for (; ct->ct_code != 0; ct++) 2861 if (ct->ct_code <= code) 2862 break; 2863 if (ct->ct_code == code) 2864 return (ct); 2865 } 2866 return (NULL); 2867 } 2868 2869 /* 2870 * Walk the cacheinfo descriptor, applying 'func' to every valid element 2871 * The walk is terminated if the walker returns non-zero. 2872 */ 2873 static void 2874 intel_walk_cacheinfo(struct cpuid_info *cpi, 2875 void *arg, int (*func)(void *, const struct cachetab *)) 2876 { 2877 const struct cachetab *ct; 2878 uint8_t *dp; 2879 int i; 2880 2881 if ((dp = cpi->cpi_cacheinfo) == NULL) 2882 return; 2883 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { 2884 /* 2885 * For overloaded descriptor 0x49 we use cpuid function 4 2886 * if supported by the current processor, to update 2887 * cache information. 2888 */ 2889 if (*dp == 0x49 && cpi->cpi_maxeax >= 0x4) { 2890 intel_cpuid_4_cache_info(arg, cpi); 2891 continue; 2892 } 2893 2894 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { 2895 if (func(arg, ct) != 0) 2896 break; 2897 } 2898 } 2899 } 2900 2901 /* 2902 * (Like the Intel one, except for Cyrix CPUs) 2903 */ 2904 static void 2905 cyrix_walk_cacheinfo(struct cpuid_info *cpi, 2906 void *arg, int (*func)(void *, const struct cachetab *)) 2907 { 2908 const struct cachetab *ct; 2909 uint8_t *dp; 2910 int i; 2911 2912 if ((dp = cpi->cpi_cacheinfo) == NULL) 2913 return; 2914 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { 2915 /* 2916 * Search Cyrix-specific descriptor table first .. 2917 */ 2918 if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) { 2919 if (func(arg, ct) != 0) 2920 break; 2921 continue; 2922 } 2923 /* 2924 * .. else fall back to the Intel one 2925 */ 2926 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { 2927 if (func(arg, ct) != 0) 2928 break; 2929 continue; 2930 } 2931 } 2932 } 2933 2934 /* 2935 * A cacheinfo walker that adds associativity, line-size, and size properties 2936 * to the devinfo node it is passed as an argument. 2937 */ 2938 static int 2939 add_cacheent_props(void *arg, const struct cachetab *ct) 2940 { 2941 dev_info_t *devi = arg; 2942 2943 add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc); 2944 if (ct->ct_line_size != 0) 2945 add_cache_prop(devi, ct->ct_label, line_str, 2946 ct->ct_line_size); 2947 add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size); 2948 return (0); 2949 } 2950 2951 /* 2952 * Add L2 or L3 cache-information using cpuid function 4. This 2953 * function is called from intel_walk_cacheinfo() when descriptor 2954 * 0x49 is encountered. 2955 */ 2956 static void 2957 intel_cpuid_4_cache_info(void *arg, struct cpuid_info *cpi) 2958 { 2959 uint32_t level, i; 2960 2961 struct cachetab ct; 2962 2963 for (i = 0; i < cpi->cpi_std_4_size; i++) { 2964 level = CPI_CACHE_LVL(cpi->cpi_std_4[i]); 2965 2966 if (level == 2 || level == 3) { 2967 ct.ct_assoc = CPI_CACHE_WAYS(cpi->cpi_std_4[i]) + 1; 2968 ct.ct_line_size = 2969 CPI_CACHE_COH_LN_SZ(cpi->cpi_std_4[i]) + 1; 2970 ct.ct_size = ct.ct_assoc * 2971 (CPI_CACHE_PARTS(cpi->cpi_std_4[i]) + 1) * 2972 ct.ct_line_size * 2973 (cpi->cpi_std_4[i]->cp_ecx + 1); 2974 2975 if (level == 2) { 2976 ct.ct_label = l2_cache_str; 2977 } else if (level == 3) { 2978 ct.ct_label = l3_cache_str; 2979 } 2980 2981 (void) add_cacheent_props(arg, 2982 (const struct cachetab *) (&ct)); 2983 } 2984 } 2985 } 2986 2987 static const char fully_assoc[] = "fully-associative?"; 2988 2989 /* 2990 * AMD style cache/tlb description 2991 * 2992 * Extended functions 5 and 6 directly describe properties of 2993 * tlbs and various cache levels. 2994 */ 2995 static void 2996 add_amd_assoc(dev_info_t *devi, const char *label, uint_t assoc) 2997 { 2998 switch (assoc) { 2999 case 0: /* reserved; ignore */ 3000 break; 3001 default: 3002 add_cache_prop(devi, label, assoc_str, assoc); 3003 break; 3004 case 0xff: 3005 add_cache_prop(devi, label, fully_assoc, 1); 3006 break; 3007 } 3008 } 3009 3010 static void 3011 add_amd_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 3012 { 3013 if (size == 0) 3014 return; 3015 add_cache_prop(devi, label, size_str, size); 3016 add_amd_assoc(devi, label, assoc); 3017 } 3018 3019 static void 3020 add_amd_cache(dev_info_t *devi, const char *label, 3021 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 3022 { 3023 if (size == 0 || line_size == 0) 3024 return; 3025 add_amd_assoc(devi, label, assoc); 3026 /* 3027 * Most AMD parts have a sectored cache. Multiple cache lines are 3028 * associated with each tag. A sector consists of all cache lines 3029 * associated with a tag. For example, the AMD K6-III has a sector 3030 * size of 2 cache lines per tag. 3031 */ 3032 if (lines_per_tag != 0) 3033 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 3034 add_cache_prop(devi, label, line_str, line_size); 3035 add_cache_prop(devi, label, size_str, size * 1024); 3036 } 3037 3038 static void 3039 add_amd_l2_assoc(dev_info_t *devi, const char *label, uint_t assoc) 3040 { 3041 switch (assoc) { 3042 case 0: /* off */ 3043 break; 3044 case 1: 3045 case 2: 3046 case 4: 3047 add_cache_prop(devi, label, assoc_str, assoc); 3048 break; 3049 case 6: 3050 add_cache_prop(devi, label, assoc_str, 8); 3051 break; 3052 case 8: 3053 add_cache_prop(devi, label, assoc_str, 16); 3054 break; 3055 case 0xf: 3056 add_cache_prop(devi, label, fully_assoc, 1); 3057 break; 3058 default: /* reserved; ignore */ 3059 break; 3060 } 3061 } 3062 3063 static void 3064 add_amd_l2_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 3065 { 3066 if (size == 0 || assoc == 0) 3067 return; 3068 add_amd_l2_assoc(devi, label, assoc); 3069 add_cache_prop(devi, label, size_str, size); 3070 } 3071 3072 static void 3073 add_amd_l2_cache(dev_info_t *devi, const char *label, 3074 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 3075 { 3076 if (size == 0 || assoc == 0 || line_size == 0) 3077 return; 3078 add_amd_l2_assoc(devi, label, assoc); 3079 if (lines_per_tag != 0) 3080 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 3081 add_cache_prop(devi, label, line_str, line_size); 3082 add_cache_prop(devi, label, size_str, size * 1024); 3083 } 3084 3085 static void 3086 amd_cache_info(struct cpuid_info *cpi, dev_info_t *devi) 3087 { 3088 struct cpuid_regs *cp; 3089 3090 if (cpi->cpi_xmaxeax < 0x80000005) 3091 return; 3092 cp = &cpi->cpi_extd[5]; 3093 3094 /* 3095 * 4M/2M L1 TLB configuration 3096 * 3097 * We report the size for 2M pages because AMD uses two 3098 * TLB entries for one 4M page. 3099 */ 3100 add_amd_tlb(devi, "dtlb-2M", 3101 BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16)); 3102 add_amd_tlb(devi, "itlb-2M", 3103 BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0)); 3104 3105 /* 3106 * 4K L1 TLB configuration 3107 */ 3108 3109 switch (cpi->cpi_vendor) { 3110 uint_t nentries; 3111 case X86_VENDOR_TM: 3112 if (cpi->cpi_family >= 5) { 3113 /* 3114 * Crusoe processors have 256 TLB entries, but 3115 * cpuid data format constrains them to only 3116 * reporting 255 of them. 3117 */ 3118 if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255) 3119 nentries = 256; 3120 /* 3121 * Crusoe processors also have a unified TLB 3122 */ 3123 add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24), 3124 nentries); 3125 break; 3126 } 3127 /*FALLTHROUGH*/ 3128 default: 3129 add_amd_tlb(devi, itlb4k_str, 3130 BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16)); 3131 add_amd_tlb(devi, dtlb4k_str, 3132 BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0)); 3133 break; 3134 } 3135 3136 /* 3137 * data L1 cache configuration 3138 */ 3139 3140 add_amd_cache(devi, l1_dcache_str, 3141 BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16), 3142 BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0)); 3143 3144 /* 3145 * code L1 cache configuration 3146 */ 3147 3148 add_amd_cache(devi, l1_icache_str, 3149 BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16), 3150 BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0)); 3151 3152 if (cpi->cpi_xmaxeax < 0x80000006) 3153 return; 3154 cp = &cpi->cpi_extd[6]; 3155 3156 /* Check for a unified L2 TLB for large pages */ 3157 3158 if (BITX(cp->cp_eax, 31, 16) == 0) 3159 add_amd_l2_tlb(devi, "l2-tlb-2M", 3160 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3161 else { 3162 add_amd_l2_tlb(devi, "l2-dtlb-2M", 3163 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 3164 add_amd_l2_tlb(devi, "l2-itlb-2M", 3165 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3166 } 3167 3168 /* Check for a unified L2 TLB for 4K pages */ 3169 3170 if (BITX(cp->cp_ebx, 31, 16) == 0) { 3171 add_amd_l2_tlb(devi, "l2-tlb-4K", 3172 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3173 } else { 3174 add_amd_l2_tlb(devi, "l2-dtlb-4K", 3175 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 3176 add_amd_l2_tlb(devi, "l2-itlb-4K", 3177 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3178 } 3179 3180 add_amd_l2_cache(devi, l2_cache_str, 3181 BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12), 3182 BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0)); 3183 } 3184 3185 /* 3186 * There are two basic ways that the x86 world describes it cache 3187 * and tlb architecture - Intel's way and AMD's way. 3188 * 3189 * Return which flavor of cache architecture we should use 3190 */ 3191 static int 3192 x86_which_cacheinfo(struct cpuid_info *cpi) 3193 { 3194 switch (cpi->cpi_vendor) { 3195 case X86_VENDOR_Intel: 3196 if (cpi->cpi_maxeax >= 2) 3197 return (X86_VENDOR_Intel); 3198 break; 3199 case X86_VENDOR_AMD: 3200 /* 3201 * The K5 model 1 was the first part from AMD that reported 3202 * cache sizes via extended cpuid functions. 3203 */ 3204 if (cpi->cpi_family > 5 || 3205 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 3206 return (X86_VENDOR_AMD); 3207 break; 3208 case X86_VENDOR_TM: 3209 if (cpi->cpi_family >= 5) 3210 return (X86_VENDOR_AMD); 3211 /*FALLTHROUGH*/ 3212 default: 3213 /* 3214 * If they have extended CPU data for 0x80000005 3215 * then we assume they have AMD-format cache 3216 * information. 3217 * 3218 * If not, and the vendor happens to be Cyrix, 3219 * then try our-Cyrix specific handler. 3220 * 3221 * If we're not Cyrix, then assume we're using Intel's 3222 * table-driven format instead. 3223 */ 3224 if (cpi->cpi_xmaxeax >= 0x80000005) 3225 return (X86_VENDOR_AMD); 3226 else if (cpi->cpi_vendor == X86_VENDOR_Cyrix) 3227 return (X86_VENDOR_Cyrix); 3228 else if (cpi->cpi_maxeax >= 2) 3229 return (X86_VENDOR_Intel); 3230 break; 3231 } 3232 return (-1); 3233 } 3234 3235 /* 3236 * create a node for the given cpu under the prom root node. 3237 * Also, create a cpu node in the device tree. 3238 */ 3239 static dev_info_t *cpu_nex_devi = NULL; 3240 static kmutex_t cpu_node_lock; 3241 3242 /* 3243 * Called from post_startup() and mp_startup() 3244 */ 3245 void 3246 add_cpunode2devtree(processorid_t cpu_id, struct cpuid_info *cpi) 3247 { 3248 dev_info_t *cpu_devi; 3249 int create; 3250 3251 mutex_enter(&cpu_node_lock); 3252 3253 /* 3254 * create a nexus node for all cpus identified as 'cpu_id' under 3255 * the root node. 3256 */ 3257 if (cpu_nex_devi == NULL) { 3258 if (ndi_devi_alloc(ddi_root_node(), "cpus", 3259 (pnode_t)DEVI_SID_NODEID, &cpu_nex_devi) != NDI_SUCCESS) { 3260 mutex_exit(&cpu_node_lock); 3261 return; 3262 } 3263 (void) ndi_devi_online(cpu_nex_devi, 0); 3264 } 3265 3266 /* 3267 * create a child node for cpu identified as 'cpu_id' 3268 */ 3269 cpu_devi = ddi_add_child(cpu_nex_devi, "cpu", DEVI_SID_NODEID, 3270 cpu_id); 3271 if (cpu_devi == NULL) { 3272 mutex_exit(&cpu_node_lock); 3273 return; 3274 } 3275 3276 /* device_type */ 3277 3278 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3279 "device_type", "cpu"); 3280 3281 /* reg */ 3282 3283 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3284 "reg", cpu_id); 3285 3286 /* cpu-mhz, and clock-frequency */ 3287 3288 if (cpu_freq > 0) { 3289 long long mul; 3290 3291 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3292 "cpu-mhz", cpu_freq); 3293 3294 if ((mul = cpu_freq * 1000000LL) <= INT_MAX) 3295 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3296 "clock-frequency", (int)mul); 3297 } 3298 3299 (void) ndi_devi_online(cpu_devi, 0); 3300 3301 if ((x86_feature & X86_CPUID) == 0) { 3302 mutex_exit(&cpu_node_lock); 3303 return; 3304 } 3305 3306 /* vendor-id */ 3307 3308 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3309 "vendor-id", cpi->cpi_vendorstr); 3310 3311 if (cpi->cpi_maxeax == 0) { 3312 mutex_exit(&cpu_node_lock); 3313 return; 3314 } 3315 3316 /* 3317 * family, model, and step 3318 */ 3319 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3320 "family", CPI_FAMILY(cpi)); 3321 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3322 "cpu-model", CPI_MODEL(cpi)); 3323 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3324 "stepping-id", CPI_STEP(cpi)); 3325 3326 /* type */ 3327 3328 switch (cpi->cpi_vendor) { 3329 case X86_VENDOR_Intel: 3330 create = 1; 3331 break; 3332 default: 3333 create = 0; 3334 break; 3335 } 3336 if (create) 3337 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3338 "type", CPI_TYPE(cpi)); 3339 3340 /* ext-family */ 3341 3342 switch (cpi->cpi_vendor) { 3343 case X86_VENDOR_Intel: 3344 case X86_VENDOR_AMD: 3345 create = cpi->cpi_family >= 0xf; 3346 break; 3347 default: 3348 create = 0; 3349 break; 3350 } 3351 if (create) 3352 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3353 "ext-family", CPI_FAMILY_XTD(cpi)); 3354 3355 /* ext-model */ 3356 3357 switch (cpi->cpi_vendor) { 3358 case X86_VENDOR_Intel: 3359 create = CPI_MODEL(cpi) == 0xf; 3360 break; 3361 case X86_VENDOR_AMD: 3362 create = CPI_FAMILY(cpi) == 0xf; 3363 break; 3364 default: 3365 create = 0; 3366 break; 3367 } 3368 if (create) 3369 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3370 "ext-model", CPI_MODEL_XTD(cpi)); 3371 3372 /* generation */ 3373 3374 switch (cpi->cpi_vendor) { 3375 case X86_VENDOR_AMD: 3376 /* 3377 * AMD K5 model 1 was the first part to support this 3378 */ 3379 create = cpi->cpi_xmaxeax >= 0x80000001; 3380 break; 3381 default: 3382 create = 0; 3383 break; 3384 } 3385 if (create) 3386 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3387 "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8)); 3388 3389 /* brand-id */ 3390 3391 switch (cpi->cpi_vendor) { 3392 case X86_VENDOR_Intel: 3393 /* 3394 * brand id first appeared on Pentium III Xeon model 8, 3395 * and Celeron model 8 processors and Opteron 3396 */ 3397 create = cpi->cpi_family > 6 || 3398 (cpi->cpi_family == 6 && cpi->cpi_model >= 8); 3399 break; 3400 case X86_VENDOR_AMD: 3401 create = cpi->cpi_family >= 0xf; 3402 break; 3403 default: 3404 create = 0; 3405 break; 3406 } 3407 if (create && cpi->cpi_brandid != 0) { 3408 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3409 "brand-id", cpi->cpi_brandid); 3410 } 3411 3412 /* chunks, and apic-id */ 3413 3414 switch (cpi->cpi_vendor) { 3415 /* 3416 * first available on Pentium IV and Opteron (K8) 3417 */ 3418 case X86_VENDOR_Intel: 3419 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 3420 break; 3421 case X86_VENDOR_AMD: 3422 create = cpi->cpi_family >= 0xf; 3423 break; 3424 default: 3425 create = 0; 3426 break; 3427 } 3428 if (create) { 3429 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3430 "chunks", CPI_CHUNKS(cpi)); 3431 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3432 "apic-id", CPI_APIC_ID(cpi)); 3433 if (cpi->cpi_chipid >= 0) { 3434 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3435 "chip#", cpi->cpi_chipid); 3436 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3437 "clog#", cpi->cpi_clogid); 3438 } 3439 } 3440 3441 /* cpuid-features */ 3442 3443 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3444 "cpuid-features", CPI_FEATURES_EDX(cpi)); 3445 3446 3447 /* cpuid-features-ecx */ 3448 3449 switch (cpi->cpi_vendor) { 3450 case X86_VENDOR_Intel: 3451 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 3452 break; 3453 default: 3454 create = 0; 3455 break; 3456 } 3457 if (create) 3458 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3459 "cpuid-features-ecx", CPI_FEATURES_ECX(cpi)); 3460 3461 /* ext-cpuid-features */ 3462 3463 switch (cpi->cpi_vendor) { 3464 case X86_VENDOR_Intel: 3465 case X86_VENDOR_AMD: 3466 case X86_VENDOR_Cyrix: 3467 case X86_VENDOR_TM: 3468 case X86_VENDOR_Centaur: 3469 create = cpi->cpi_xmaxeax >= 0x80000001; 3470 break; 3471 default: 3472 create = 0; 3473 break; 3474 } 3475 if (create) { 3476 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3477 "ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi)); 3478 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3479 "ext-cpuid-features-ecx", CPI_FEATURES_XTD_ECX(cpi)); 3480 } 3481 3482 /* 3483 * Brand String first appeared in Intel Pentium IV, AMD K5 3484 * model 1, and Cyrix GXm. On earlier models we try and 3485 * simulate something similar .. so this string should always 3486 * same -something- about the processor, however lame. 3487 */ 3488 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3489 "brand-string", cpi->cpi_brandstr); 3490 3491 /* 3492 * Finally, cache and tlb information 3493 */ 3494 switch (x86_which_cacheinfo(cpi)) { 3495 case X86_VENDOR_Intel: 3496 intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 3497 break; 3498 case X86_VENDOR_Cyrix: 3499 cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 3500 break; 3501 case X86_VENDOR_AMD: 3502 amd_cache_info(cpi, cpu_devi); 3503 break; 3504 default: 3505 break; 3506 } 3507 3508 mutex_exit(&cpu_node_lock); 3509 } 3510 3511 struct l2info { 3512 int *l2i_csz; 3513 int *l2i_lsz; 3514 int *l2i_assoc; 3515 int l2i_ret; 3516 }; 3517 3518 /* 3519 * A cacheinfo walker that fetches the size, line-size and associativity 3520 * of the L2 cache 3521 */ 3522 static int 3523 intel_l2cinfo(void *arg, const struct cachetab *ct) 3524 { 3525 struct l2info *l2i = arg; 3526 int *ip; 3527 3528 if (ct->ct_label != l2_cache_str && 3529 ct->ct_label != sl2_cache_str) 3530 return (0); /* not an L2 -- keep walking */ 3531 3532 if ((ip = l2i->l2i_csz) != NULL) 3533 *ip = ct->ct_size; 3534 if ((ip = l2i->l2i_lsz) != NULL) 3535 *ip = ct->ct_line_size; 3536 if ((ip = l2i->l2i_assoc) != NULL) 3537 *ip = ct->ct_assoc; 3538 l2i->l2i_ret = ct->ct_size; 3539 return (1); /* was an L2 -- terminate walk */ 3540 } 3541 3542 /* 3543 * AMD L2/L3 Cache and TLB Associativity Field Definition: 3544 * 3545 * Unlike the associativity for the L1 cache and tlb where the 8 bit 3546 * value is the associativity, the associativity for the L2 cache and 3547 * tlb is encoded in the following table. The 4 bit L2 value serves as 3548 * an index into the amd_afd[] array to determine the associativity. 3549 * -1 is undefined. 0 is fully associative. 3550 */ 3551 3552 static int amd_afd[] = 3553 {-1, 1, 2, -1, 4, -1, 8, -1, 16, -1, 32, 48, 64, 96, 128, 0}; 3554 3555 static void 3556 amd_l2cacheinfo(struct cpuid_info *cpi, struct l2info *l2i) 3557 { 3558 struct cpuid_regs *cp; 3559 uint_t size, assoc; 3560 int i; 3561 int *ip; 3562 3563 if (cpi->cpi_xmaxeax < 0x80000006) 3564 return; 3565 cp = &cpi->cpi_extd[6]; 3566 3567 if ((i = BITX(cp->cp_ecx, 15, 12)) != 0 && 3568 (size = BITX(cp->cp_ecx, 31, 16)) != 0) { 3569 uint_t cachesz = size * 1024; 3570 assoc = amd_afd[i]; 3571 3572 ASSERT(assoc != -1); 3573 3574 if ((ip = l2i->l2i_csz) != NULL) 3575 *ip = cachesz; 3576 if ((ip = l2i->l2i_lsz) != NULL) 3577 *ip = BITX(cp->cp_ecx, 7, 0); 3578 if ((ip = l2i->l2i_assoc) != NULL) 3579 *ip = assoc; 3580 l2i->l2i_ret = cachesz; 3581 } 3582 } 3583 3584 int 3585 getl2cacheinfo(cpu_t *cpu, int *csz, int *lsz, int *assoc) 3586 { 3587 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 3588 struct l2info __l2info, *l2i = &__l2info; 3589 3590 l2i->l2i_csz = csz; 3591 l2i->l2i_lsz = lsz; 3592 l2i->l2i_assoc = assoc; 3593 l2i->l2i_ret = -1; 3594 3595 switch (x86_which_cacheinfo(cpi)) { 3596 case X86_VENDOR_Intel: 3597 intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 3598 break; 3599 case X86_VENDOR_Cyrix: 3600 cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 3601 break; 3602 case X86_VENDOR_AMD: 3603 amd_l2cacheinfo(cpi, l2i); 3604 break; 3605 default: 3606 break; 3607 } 3608 return (l2i->l2i_ret); 3609 } 3610 3611 #if !defined(__xpv) 3612 3613 uint32_t * 3614 cpuid_mwait_alloc(cpu_t *cpu) 3615 { 3616 uint32_t *ret; 3617 size_t mwait_size; 3618 3619 ASSERT(cpuid_checkpass(cpu, 2)); 3620 3621 mwait_size = cpu->cpu_m.mcpu_cpi->cpi_mwait.mon_max; 3622 if (mwait_size == 0) 3623 return (NULL); 3624 3625 /* 3626 * kmem_alloc() returns cache line size aligned data for mwait_size 3627 * allocations. mwait_size is currently cache line sized. Neither 3628 * of these implementation details are guarantied to be true in the 3629 * future. 3630 * 3631 * First try allocating mwait_size as kmem_alloc() currently returns 3632 * correctly aligned memory. If kmem_alloc() does not return 3633 * mwait_size aligned memory, then use mwait_size ROUNDUP. 3634 * 3635 * Set cpi_mwait.buf_actual and cpi_mwait.size_actual in case we 3636 * decide to free this memory. 3637 */ 3638 ret = kmem_zalloc(mwait_size, KM_SLEEP); 3639 if (ret == (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size)) { 3640 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret; 3641 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size; 3642 *ret = MWAIT_RUNNING; 3643 return (ret); 3644 } else { 3645 kmem_free(ret, mwait_size); 3646 ret = kmem_zalloc(mwait_size * 2, KM_SLEEP); 3647 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret; 3648 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size * 2; 3649 ret = (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size); 3650 *ret = MWAIT_RUNNING; 3651 return (ret); 3652 } 3653 } 3654 3655 void 3656 cpuid_mwait_free(cpu_t *cpu) 3657 { 3658 ASSERT(cpuid_checkpass(cpu, 2)); 3659 3660 if (cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual != NULL && 3661 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual > 0) { 3662 kmem_free(cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual, 3663 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual); 3664 } 3665 3666 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = NULL; 3667 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = 0; 3668 } 3669 3670 void 3671 patch_tsc_read(int flag) 3672 { 3673 size_t cnt; 3674 3675 switch (flag) { 3676 case X86_NO_TSC: 3677 cnt = &_no_rdtsc_end - &_no_rdtsc_start; 3678 (void) memcpy((void *)tsc_read, (void *)&_no_rdtsc_start, cnt); 3679 break; 3680 case X86_HAVE_TSCP: 3681 cnt = &_tscp_end - &_tscp_start; 3682 (void) memcpy((void *)tsc_read, (void *)&_tscp_start, cnt); 3683 break; 3684 case X86_TSC_MFENCE: 3685 cnt = &_tsc_mfence_end - &_tsc_mfence_start; 3686 (void) memcpy((void *)tsc_read, 3687 (void *)&_tsc_mfence_start, cnt); 3688 break; 3689 default: 3690 break; 3691 } 3692 } 3693 3694 #endif /* !__xpv */ 3695