1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 /* 26 * Copyright (c) 2009, Intel Corporation. 27 * All rights reserved. 28 */ 29 30 /* 31 * Various routines to handle identification 32 * and classification of x86 processors. 33 */ 34 35 #include <sys/types.h> 36 #include <sys/archsystm.h> 37 #include <sys/x86_archext.h> 38 #include <sys/kmem.h> 39 #include <sys/systm.h> 40 #include <sys/cmn_err.h> 41 #include <sys/sunddi.h> 42 #include <sys/sunndi.h> 43 #include <sys/cpuvar.h> 44 #include <sys/processor.h> 45 #include <sys/sysmacros.h> 46 #include <sys/pg.h> 47 #include <sys/fp.h> 48 #include <sys/controlregs.h> 49 #include <sys/auxv_386.h> 50 #include <sys/bitmap.h> 51 #include <sys/memnode.h> 52 53 #ifdef __xpv 54 #include <sys/hypervisor.h> 55 #else 56 #include <sys/ontrap.h> 57 #endif 58 59 /* 60 * Pass 0 of cpuid feature analysis happens in locore. It contains special code 61 * to recognize Cyrix processors that are not cpuid-compliant, and to deal with 62 * them accordingly. For most modern processors, feature detection occurs here 63 * in pass 1. 64 * 65 * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup() 66 * for the boot CPU and does the basic analysis that the early kernel needs. 67 * x86_feature is set based on the return value of cpuid_pass1() of the boot 68 * CPU. 69 * 70 * Pass 1 includes: 71 * 72 * o Determining vendor/model/family/stepping and setting x86_type and 73 * x86_vendor accordingly. 74 * o Processing the feature flags returned by the cpuid instruction while 75 * applying any workarounds or tricks for the specific processor. 76 * o Mapping the feature flags into Solaris feature bits (X86_*). 77 * o Processing extended feature flags if supported by the processor, 78 * again while applying specific processor knowledge. 79 * o Determining the CMT characteristics of the system. 80 * 81 * Pass 1 is done on non-boot CPUs during their initialization and the results 82 * are used only as a meager attempt at ensuring that all processors within the 83 * system support the same features. 84 * 85 * Pass 2 of cpuid feature analysis happens just at the beginning 86 * of startup(). It just copies in and corrects the remainder 87 * of the cpuid data we depend on: standard cpuid functions that we didn't 88 * need for pass1 feature analysis, and extended cpuid functions beyond the 89 * simple feature processing done in pass1. 90 * 91 * Pass 3 of cpuid analysis is invoked after basic kernel services; in 92 * particular kernel memory allocation has been made available. It creates a 93 * readable brand string based on the data collected in the first two passes. 94 * 95 * Pass 4 of cpuid analysis is invoked after post_startup() when all 96 * the support infrastructure for various hardware features has been 97 * initialized. It determines which processor features will be reported 98 * to userland via the aux vector. 99 * 100 * All passes are executed on all CPUs, but only the boot CPU determines what 101 * features the kernel will use. 102 * 103 * Much of the worst junk in this file is for the support of processors 104 * that didn't really implement the cpuid instruction properly. 105 * 106 * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon, 107 * the pass numbers. Accordingly, changes to the pass code may require changes 108 * to the accessor code. 109 */ 110 111 uint_t x86_feature = 0; 112 uint_t x86_vendor = X86_VENDOR_IntelClone; 113 uint_t x86_type = X86_TYPE_OTHER; 114 uint_t x86_clflush_size = 0; 115 116 uint_t pentiumpro_bug4046376; 117 uint_t pentiumpro_bug4064495; 118 119 uint_t enable486; 120 /* 121 * This is set to platform type Solaris is running on. 122 */ 123 static int platform_type = HW_NATIVE; 124 125 /* 126 * monitor/mwait info. 127 * 128 * size_actual and buf_actual are the real address and size allocated to get 129 * proper mwait_buf alignement. buf_actual and size_actual should be passed 130 * to kmem_free(). Currently kmem_alloc() and mwait happen to both use 131 * processor cache-line alignment, but this is not guarantied in the furture. 132 */ 133 struct mwait_info { 134 size_t mon_min; /* min size to avoid missed wakeups */ 135 size_t mon_max; /* size to avoid false wakeups */ 136 size_t size_actual; /* size actually allocated */ 137 void *buf_actual; /* memory actually allocated */ 138 uint32_t support; /* processor support of monitor/mwait */ 139 }; 140 141 /* 142 * These constants determine how many of the elements of the 143 * cpuid we cache in the cpuid_info data structure; the 144 * remaining elements are accessible via the cpuid instruction. 145 */ 146 147 #define NMAX_CPI_STD 6 /* eax = 0 .. 5 */ 148 #define NMAX_CPI_EXTD 9 /* eax = 0x80000000 .. 0x80000008 */ 149 150 struct cpuid_info { 151 uint_t cpi_pass; /* last pass completed */ 152 /* 153 * standard function information 154 */ 155 uint_t cpi_maxeax; /* fn 0: %eax */ 156 char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */ 157 uint_t cpi_vendor; /* enum of cpi_vendorstr */ 158 159 uint_t cpi_family; /* fn 1: extended family */ 160 uint_t cpi_model; /* fn 1: extended model */ 161 uint_t cpi_step; /* fn 1: stepping */ 162 chipid_t cpi_chipid; /* fn 1: %ebx: chip # on ht cpus */ 163 uint_t cpi_brandid; /* fn 1: %ebx: brand ID */ 164 int cpi_clogid; /* fn 1: %ebx: thread # */ 165 uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */ 166 uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */ 167 uint_t cpi_ncache; /* fn 2: number of elements */ 168 uint_t cpi_ncpu_shr_last_cache; /* fn 4: %eax: ncpus sharing cache */ 169 id_t cpi_last_lvl_cacheid; /* fn 4: %eax: derived cache id */ 170 uint_t cpi_std_4_size; /* fn 4: number of fn 4 elements */ 171 struct cpuid_regs **cpi_std_4; /* fn 4: %ecx == 0 .. fn4_size */ 172 struct cpuid_regs cpi_std[NMAX_CPI_STD]; /* 0 .. 5 */ 173 /* 174 * extended function information 175 */ 176 uint_t cpi_xmaxeax; /* fn 0x80000000: %eax */ 177 char cpi_brandstr[49]; /* fn 0x8000000[234] */ 178 uint8_t cpi_pabits; /* fn 0x80000006: %eax */ 179 uint8_t cpi_vabits; /* fn 0x80000006: %eax */ 180 struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x8000000[0-8] */ 181 id_t cpi_coreid; /* same coreid => strands share core */ 182 int cpi_pkgcoreid; /* core number within single package */ 183 uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */ 184 /* Intel: fn 4: %eax[31-26] */ 185 /* 186 * supported feature information 187 */ 188 uint32_t cpi_support[5]; 189 #define STD_EDX_FEATURES 0 190 #define AMD_EDX_FEATURES 1 191 #define TM_EDX_FEATURES 2 192 #define STD_ECX_FEATURES 3 193 #define AMD_ECX_FEATURES 4 194 /* 195 * Synthesized information, where known. 196 */ 197 uint32_t cpi_chiprev; /* See X86_CHIPREV_* in x86_archext.h */ 198 const char *cpi_chiprevstr; /* May be NULL if chiprev unknown */ 199 uint32_t cpi_socket; /* Chip package/socket type */ 200 201 struct mwait_info cpi_mwait; /* fn 5: monitor/mwait info */ 202 uint32_t cpi_apicid; 203 }; 204 205 206 static struct cpuid_info cpuid_info0; 207 208 /* 209 * These bit fields are defined by the Intel Application Note AP-485 210 * "Intel Processor Identification and the CPUID Instruction" 211 */ 212 #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20) 213 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16) 214 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12) 215 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8) 216 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0) 217 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4) 218 219 #define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx) 220 #define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx) 221 #define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx) 222 #define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx) 223 224 #define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0) 225 #define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7) 226 #define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16) 227 #define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24) 228 229 #define CPI_MAXEAX_MAX 0x100 /* sanity control */ 230 #define CPI_XMAXEAX_MAX 0x80000100 231 #define CPI_FN4_ECX_MAX 0x20 /* sanity: max fn 4 levels */ 232 #define CPI_FNB_ECX_MAX 0x20 /* sanity: max fn B levels */ 233 234 /* 235 * Function 4 (Deterministic Cache Parameters) macros 236 * Defined by Intel Application Note AP-485 237 */ 238 #define CPI_NUM_CORES(regs) BITX((regs)->cp_eax, 31, 26) 239 #define CPI_NTHR_SHR_CACHE(regs) BITX((regs)->cp_eax, 25, 14) 240 #define CPI_FULL_ASSOC_CACHE(regs) BITX((regs)->cp_eax, 9, 9) 241 #define CPI_SELF_INIT_CACHE(regs) BITX((regs)->cp_eax, 8, 8) 242 #define CPI_CACHE_LVL(regs) BITX((regs)->cp_eax, 7, 5) 243 #define CPI_CACHE_TYPE(regs) BITX((regs)->cp_eax, 4, 0) 244 #define CPI_CPU_LEVEL_TYPE(regs) BITX((regs)->cp_ecx, 15, 8) 245 246 #define CPI_CACHE_WAYS(regs) BITX((regs)->cp_ebx, 31, 22) 247 #define CPI_CACHE_PARTS(regs) BITX((regs)->cp_ebx, 21, 12) 248 #define CPI_CACHE_COH_LN_SZ(regs) BITX((regs)->cp_ebx, 11, 0) 249 250 #define CPI_CACHE_SETS(regs) BITX((regs)->cp_ecx, 31, 0) 251 252 #define CPI_PREFCH_STRIDE(regs) BITX((regs)->cp_edx, 9, 0) 253 254 255 /* 256 * A couple of shorthand macros to identify "later" P6-family chips 257 * like the Pentium M and Core. First, the "older" P6-based stuff 258 * (loosely defined as "pre-Pentium-4"): 259 * P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon 260 */ 261 262 #define IS_LEGACY_P6(cpi) ( \ 263 cpi->cpi_family == 6 && \ 264 (cpi->cpi_model == 1 || \ 265 cpi->cpi_model == 3 || \ 266 cpi->cpi_model == 5 || \ 267 cpi->cpi_model == 6 || \ 268 cpi->cpi_model == 7 || \ 269 cpi->cpi_model == 8 || \ 270 cpi->cpi_model == 0xA || \ 271 cpi->cpi_model == 0xB) \ 272 ) 273 274 /* A "new F6" is everything with family 6 that's not the above */ 275 #define IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi)) 276 277 /* Extended family/model support */ 278 #define IS_EXTENDED_MODEL_INTEL(cpi) (cpi->cpi_family == 0x6 || \ 279 cpi->cpi_family >= 0xf) 280 281 /* 282 * Info for monitor/mwait idle loop. 283 * 284 * See cpuid section of "Intel 64 and IA-32 Architectures Software Developer's 285 * Manual Volume 2A: Instruction Set Reference, A-M" #25366-022US, November 286 * 2006. 287 * See MONITOR/MWAIT section of "AMD64 Architecture Programmer's Manual 288 * Documentation Updates" #33633, Rev 2.05, December 2006. 289 */ 290 #define MWAIT_SUPPORT (0x00000001) /* mwait supported */ 291 #define MWAIT_EXTENSIONS (0x00000002) /* extenstion supported */ 292 #define MWAIT_ECX_INT_ENABLE (0x00000004) /* ecx 1 extension supported */ 293 #define MWAIT_SUPPORTED(cpi) ((cpi)->cpi_std[1].cp_ecx & CPUID_INTC_ECX_MON) 294 #define MWAIT_INT_ENABLE(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x2) 295 #define MWAIT_EXTENSION(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x1) 296 #define MWAIT_SIZE_MIN(cpi) BITX((cpi)->cpi_std[5].cp_eax, 15, 0) 297 #define MWAIT_SIZE_MAX(cpi) BITX((cpi)->cpi_std[5].cp_ebx, 15, 0) 298 /* 299 * Number of sub-cstates for a given c-state. 300 */ 301 #define MWAIT_NUM_SUBC_STATES(cpi, c_state) \ 302 BITX((cpi)->cpi_std[5].cp_edx, c_state + 3, c_state) 303 304 /* 305 * Functions we consune from cpuid_subr.c; don't publish these in a header 306 * file to try and keep people using the expected cpuid_* interfaces. 307 */ 308 extern uint32_t _cpuid_skt(uint_t, uint_t, uint_t, uint_t); 309 extern uint32_t _cpuid_chiprev(uint_t, uint_t, uint_t, uint_t); 310 extern const char *_cpuid_chiprevstr(uint_t, uint_t, uint_t, uint_t); 311 extern uint_t _cpuid_vendorstr_to_vendorcode(char *); 312 313 /* 314 * Apply up various platform-dependent restrictions where the 315 * underlying platform restrictions mean the CPU can be marked 316 * as less capable than its cpuid instruction would imply. 317 */ 318 #if defined(__xpv) 319 static void 320 platform_cpuid_mangle(uint_t vendor, uint32_t eax, struct cpuid_regs *cp) 321 { 322 switch (eax) { 323 case 1: { 324 uint32_t mcamask = DOMAIN_IS_INITDOMAIN(xen_info) ? 325 0 : CPUID_INTC_EDX_MCA; 326 cp->cp_edx &= 327 ~(mcamask | 328 CPUID_INTC_EDX_PSE | 329 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE | 330 CPUID_INTC_EDX_SEP | CPUID_INTC_EDX_MTRR | 331 CPUID_INTC_EDX_PGE | CPUID_INTC_EDX_PAT | 332 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP | 333 CPUID_INTC_EDX_PSE36 | CPUID_INTC_EDX_HTT); 334 break; 335 } 336 337 case 0x80000001: 338 cp->cp_edx &= 339 ~(CPUID_AMD_EDX_PSE | 340 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE | 341 CPUID_AMD_EDX_MTRR | CPUID_AMD_EDX_PGE | 342 CPUID_AMD_EDX_PAT | CPUID_AMD_EDX_PSE36 | 343 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP | 344 CPUID_AMD_EDX_TSCP); 345 cp->cp_ecx &= ~CPUID_AMD_ECX_CMP_LGCY; 346 break; 347 default: 348 break; 349 } 350 351 switch (vendor) { 352 case X86_VENDOR_Intel: 353 switch (eax) { 354 case 4: 355 /* 356 * Zero out the (ncores-per-chip - 1) field 357 */ 358 cp->cp_eax &= 0x03fffffff; 359 break; 360 default: 361 break; 362 } 363 break; 364 case X86_VENDOR_AMD: 365 switch (eax) { 366 case 0x80000008: 367 /* 368 * Zero out the (ncores-per-chip - 1) field 369 */ 370 cp->cp_ecx &= 0xffffff00; 371 break; 372 default: 373 break; 374 } 375 break; 376 default: 377 break; 378 } 379 } 380 #else 381 #define platform_cpuid_mangle(vendor, eax, cp) /* nothing */ 382 #endif 383 384 /* 385 * Some undocumented ways of patching the results of the cpuid 386 * instruction to permit running Solaris 10 on future cpus that 387 * we don't currently support. Could be set to non-zero values 388 * via settings in eeprom. 389 */ 390 391 uint32_t cpuid_feature_ecx_include; 392 uint32_t cpuid_feature_ecx_exclude; 393 uint32_t cpuid_feature_edx_include; 394 uint32_t cpuid_feature_edx_exclude; 395 396 void 397 cpuid_alloc_space(cpu_t *cpu) 398 { 399 /* 400 * By convention, cpu0 is the boot cpu, which is set up 401 * before memory allocation is available. All other cpus get 402 * their cpuid_info struct allocated here. 403 */ 404 ASSERT(cpu->cpu_id != 0); 405 cpu->cpu_m.mcpu_cpi = 406 kmem_zalloc(sizeof (*cpu->cpu_m.mcpu_cpi), KM_SLEEP); 407 } 408 409 void 410 cpuid_free_space(cpu_t *cpu) 411 { 412 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 413 int i; 414 415 ASSERT(cpu->cpu_id != 0); 416 417 /* 418 * Free up any function 4 related dynamic storage 419 */ 420 for (i = 1; i < cpi->cpi_std_4_size; i++) 421 kmem_free(cpi->cpi_std_4[i], sizeof (struct cpuid_regs)); 422 if (cpi->cpi_std_4_size > 0) 423 kmem_free(cpi->cpi_std_4, 424 cpi->cpi_std_4_size * sizeof (struct cpuid_regs *)); 425 426 kmem_free(cpu->cpu_m.mcpu_cpi, sizeof (*cpu->cpu_m.mcpu_cpi)); 427 } 428 429 #if !defined(__xpv) 430 431 static void 432 determine_platform() 433 { 434 struct cpuid_regs cp; 435 char *xen_str; 436 uint32_t xen_signature[4]; 437 438 /* 439 * In a fully virtualized domain, Xen's pseudo-cpuid function 440 * 0x40000000 returns a string representing the Xen signature in 441 * %ebx, %ecx, and %edx. %eax contains the maximum supported cpuid 442 * function. 443 */ 444 cp.cp_eax = 0x40000000; 445 (void) __cpuid_insn(&cp); 446 xen_signature[0] = cp.cp_ebx; 447 xen_signature[1] = cp.cp_ecx; 448 xen_signature[2] = cp.cp_edx; 449 xen_signature[3] = 0; 450 xen_str = (char *)xen_signature; 451 if (strcmp("XenVMMXenVMM", xen_str) == 0 && cp.cp_eax <= 0x40000002) { 452 platform_type = HW_XEN_HVM; 453 } else if (vmware_platform()) { /* running under vmware hypervisor? */ 454 platform_type = HW_VMWARE; 455 } 456 } 457 458 int 459 get_hwenv(void) 460 { 461 return (platform_type); 462 } 463 464 int 465 is_controldom(void) 466 { 467 return (0); 468 } 469 470 #else 471 472 int 473 get_hwenv(void) 474 { 475 return (HW_XEN_PV); 476 } 477 478 int 479 is_controldom(void) 480 { 481 return (DOMAIN_IS_INITDOMAIN(xen_info)); 482 } 483 484 #endif /* __xpv */ 485 486 uint_t 487 cpuid_pass1(cpu_t *cpu) 488 { 489 uint32_t mask_ecx, mask_edx; 490 uint_t feature = X86_CPUID; 491 struct cpuid_info *cpi; 492 struct cpuid_regs *cp; 493 int xcpuid; 494 #if !defined(__xpv) 495 extern int idle_cpu_prefer_mwait; 496 #endif 497 498 /* 499 * Space statically allocated for cpu0, ensure pointer is set 500 */ 501 if (cpu->cpu_id == 0) 502 cpu->cpu_m.mcpu_cpi = &cpuid_info0; 503 cpi = cpu->cpu_m.mcpu_cpi; 504 ASSERT(cpi != NULL); 505 cp = &cpi->cpi_std[0]; 506 cp->cp_eax = 0; 507 cpi->cpi_maxeax = __cpuid_insn(cp); 508 { 509 uint32_t *iptr = (uint32_t *)cpi->cpi_vendorstr; 510 *iptr++ = cp->cp_ebx; 511 *iptr++ = cp->cp_edx; 512 *iptr++ = cp->cp_ecx; 513 *(char *)&cpi->cpi_vendorstr[12] = '\0'; 514 } 515 516 cpi->cpi_vendor = _cpuid_vendorstr_to_vendorcode(cpi->cpi_vendorstr); 517 x86_vendor = cpi->cpi_vendor; /* for compatibility */ 518 519 /* 520 * Limit the range in case of weird hardware 521 */ 522 if (cpi->cpi_maxeax > CPI_MAXEAX_MAX) 523 cpi->cpi_maxeax = CPI_MAXEAX_MAX; 524 if (cpi->cpi_maxeax < 1) 525 goto pass1_done; 526 527 cp = &cpi->cpi_std[1]; 528 cp->cp_eax = 1; 529 (void) __cpuid_insn(cp); 530 531 /* 532 * Extract identifying constants for easy access. 533 */ 534 cpi->cpi_model = CPI_MODEL(cpi); 535 cpi->cpi_family = CPI_FAMILY(cpi); 536 537 if (cpi->cpi_family == 0xf) 538 cpi->cpi_family += CPI_FAMILY_XTD(cpi); 539 540 /* 541 * Beware: AMD uses "extended model" iff base *FAMILY* == 0xf. 542 * Intel, and presumably everyone else, uses model == 0xf, as 543 * one would expect (max value means possible overflow). Sigh. 544 */ 545 546 switch (cpi->cpi_vendor) { 547 case X86_VENDOR_Intel: 548 if (IS_EXTENDED_MODEL_INTEL(cpi)) 549 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 550 break; 551 case X86_VENDOR_AMD: 552 if (CPI_FAMILY(cpi) == 0xf) 553 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 554 break; 555 default: 556 if (cpi->cpi_model == 0xf) 557 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 558 break; 559 } 560 561 cpi->cpi_step = CPI_STEP(cpi); 562 cpi->cpi_brandid = CPI_BRANDID(cpi); 563 564 /* 565 * *default* assumptions: 566 * - believe %edx feature word 567 * - ignore %ecx feature word 568 * - 32-bit virtual and physical addressing 569 */ 570 mask_edx = 0xffffffff; 571 mask_ecx = 0; 572 573 cpi->cpi_pabits = cpi->cpi_vabits = 32; 574 575 switch (cpi->cpi_vendor) { 576 case X86_VENDOR_Intel: 577 if (cpi->cpi_family == 5) 578 x86_type = X86_TYPE_P5; 579 else if (IS_LEGACY_P6(cpi)) { 580 x86_type = X86_TYPE_P6; 581 pentiumpro_bug4046376 = 1; 582 pentiumpro_bug4064495 = 1; 583 /* 584 * Clear the SEP bit when it was set erroneously 585 */ 586 if (cpi->cpi_model < 3 && cpi->cpi_step < 3) 587 cp->cp_edx &= ~CPUID_INTC_EDX_SEP; 588 } else if (IS_NEW_F6(cpi) || cpi->cpi_family == 0xf) { 589 x86_type = X86_TYPE_P4; 590 /* 591 * We don't currently depend on any of the %ecx 592 * features until Prescott, so we'll only check 593 * this from P4 onwards. We might want to revisit 594 * that idea later. 595 */ 596 mask_ecx = 0xffffffff; 597 } else if (cpi->cpi_family > 0xf) 598 mask_ecx = 0xffffffff; 599 /* 600 * We don't support MONITOR/MWAIT if leaf 5 is not available 601 * to obtain the monitor linesize. 602 */ 603 if (cpi->cpi_maxeax < 5) 604 mask_ecx &= ~CPUID_INTC_ECX_MON; 605 break; 606 case X86_VENDOR_IntelClone: 607 default: 608 break; 609 case X86_VENDOR_AMD: 610 #if defined(OPTERON_ERRATUM_108) 611 if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) { 612 cp->cp_eax = (0xf0f & cp->cp_eax) | 0xc0; 613 cpi->cpi_model = 0xc; 614 } else 615 #endif 616 if (cpi->cpi_family == 5) { 617 /* 618 * AMD K5 and K6 619 * 620 * These CPUs have an incomplete implementation 621 * of MCA/MCE which we mask away. 622 */ 623 mask_edx &= ~(CPUID_INTC_EDX_MCE | CPUID_INTC_EDX_MCA); 624 625 /* 626 * Model 0 uses the wrong (APIC) bit 627 * to indicate PGE. Fix it here. 628 */ 629 if (cpi->cpi_model == 0) { 630 if (cp->cp_edx & 0x200) { 631 cp->cp_edx &= ~0x200; 632 cp->cp_edx |= CPUID_INTC_EDX_PGE; 633 } 634 } 635 636 /* 637 * Early models had problems w/ MMX; disable. 638 */ 639 if (cpi->cpi_model < 6) 640 mask_edx &= ~CPUID_INTC_EDX_MMX; 641 } 642 643 /* 644 * For newer families, SSE3 and CX16, at least, are valid; 645 * enable all 646 */ 647 if (cpi->cpi_family >= 0xf) 648 mask_ecx = 0xffffffff; 649 /* 650 * We don't support MONITOR/MWAIT if leaf 5 is not available 651 * to obtain the monitor linesize. 652 */ 653 if (cpi->cpi_maxeax < 5) 654 mask_ecx &= ~CPUID_INTC_ECX_MON; 655 656 #if !defined(__xpv) 657 /* 658 * Do not use MONITOR/MWAIT to halt in the idle loop on any AMD 659 * processors. AMD does not intend MWAIT to be used in the cpu 660 * idle loop on current and future processors. 10h and future 661 * AMD processors use more power in MWAIT than HLT. 662 * Pre-family-10h Opterons do not have the MWAIT instruction. 663 */ 664 idle_cpu_prefer_mwait = 0; 665 #endif 666 667 break; 668 case X86_VENDOR_TM: 669 /* 670 * workaround the NT workaround in CMS 4.1 671 */ 672 if (cpi->cpi_family == 5 && cpi->cpi_model == 4 && 673 (cpi->cpi_step == 2 || cpi->cpi_step == 3)) 674 cp->cp_edx |= CPUID_INTC_EDX_CX8; 675 break; 676 case X86_VENDOR_Centaur: 677 /* 678 * workaround the NT workarounds again 679 */ 680 if (cpi->cpi_family == 6) 681 cp->cp_edx |= CPUID_INTC_EDX_CX8; 682 break; 683 case X86_VENDOR_Cyrix: 684 /* 685 * We rely heavily on the probing in locore 686 * to actually figure out what parts, if any, 687 * of the Cyrix cpuid instruction to believe. 688 */ 689 switch (x86_type) { 690 case X86_TYPE_CYRIX_486: 691 mask_edx = 0; 692 break; 693 case X86_TYPE_CYRIX_6x86: 694 mask_edx = 0; 695 break; 696 case X86_TYPE_CYRIX_6x86L: 697 mask_edx = 698 CPUID_INTC_EDX_DE | 699 CPUID_INTC_EDX_CX8; 700 break; 701 case X86_TYPE_CYRIX_6x86MX: 702 mask_edx = 703 CPUID_INTC_EDX_DE | 704 CPUID_INTC_EDX_MSR | 705 CPUID_INTC_EDX_CX8 | 706 CPUID_INTC_EDX_PGE | 707 CPUID_INTC_EDX_CMOV | 708 CPUID_INTC_EDX_MMX; 709 break; 710 case X86_TYPE_CYRIX_GXm: 711 mask_edx = 712 CPUID_INTC_EDX_MSR | 713 CPUID_INTC_EDX_CX8 | 714 CPUID_INTC_EDX_CMOV | 715 CPUID_INTC_EDX_MMX; 716 break; 717 case X86_TYPE_CYRIX_MediaGX: 718 break; 719 case X86_TYPE_CYRIX_MII: 720 case X86_TYPE_VIA_CYRIX_III: 721 mask_edx = 722 CPUID_INTC_EDX_DE | 723 CPUID_INTC_EDX_TSC | 724 CPUID_INTC_EDX_MSR | 725 CPUID_INTC_EDX_CX8 | 726 CPUID_INTC_EDX_PGE | 727 CPUID_INTC_EDX_CMOV | 728 CPUID_INTC_EDX_MMX; 729 break; 730 default: 731 break; 732 } 733 break; 734 } 735 736 #if defined(__xpv) 737 /* 738 * Do not support MONITOR/MWAIT under a hypervisor 739 */ 740 mask_ecx &= ~CPUID_INTC_ECX_MON; 741 #endif /* __xpv */ 742 743 /* 744 * Now we've figured out the masks that determine 745 * which bits we choose to believe, apply the masks 746 * to the feature words, then map the kernel's view 747 * of these feature words into its feature word. 748 */ 749 cp->cp_edx &= mask_edx; 750 cp->cp_ecx &= mask_ecx; 751 752 /* 753 * apply any platform restrictions (we don't call this 754 * immediately after __cpuid_insn here, because we need the 755 * workarounds applied above first) 756 */ 757 platform_cpuid_mangle(cpi->cpi_vendor, 1, cp); 758 759 /* 760 * fold in overrides from the "eeprom" mechanism 761 */ 762 cp->cp_edx |= cpuid_feature_edx_include; 763 cp->cp_edx &= ~cpuid_feature_edx_exclude; 764 765 cp->cp_ecx |= cpuid_feature_ecx_include; 766 cp->cp_ecx &= ~cpuid_feature_ecx_exclude; 767 768 if (cp->cp_edx & CPUID_INTC_EDX_PSE) 769 feature |= X86_LARGEPAGE; 770 if (cp->cp_edx & CPUID_INTC_EDX_TSC) 771 feature |= X86_TSC; 772 if (cp->cp_edx & CPUID_INTC_EDX_MSR) 773 feature |= X86_MSR; 774 if (cp->cp_edx & CPUID_INTC_EDX_MTRR) 775 feature |= X86_MTRR; 776 if (cp->cp_edx & CPUID_INTC_EDX_PGE) 777 feature |= X86_PGE; 778 if (cp->cp_edx & CPUID_INTC_EDX_CMOV) 779 feature |= X86_CMOV; 780 if (cp->cp_edx & CPUID_INTC_EDX_MMX) 781 feature |= X86_MMX; 782 if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 && 783 (cp->cp_edx & CPUID_INTC_EDX_MCA) != 0) 784 feature |= X86_MCA; 785 if (cp->cp_edx & CPUID_INTC_EDX_PAE) 786 feature |= X86_PAE; 787 if (cp->cp_edx & CPUID_INTC_EDX_CX8) 788 feature |= X86_CX8; 789 if (cp->cp_ecx & CPUID_INTC_ECX_CX16) 790 feature |= X86_CX16; 791 if (cp->cp_edx & CPUID_INTC_EDX_PAT) 792 feature |= X86_PAT; 793 if (cp->cp_edx & CPUID_INTC_EDX_SEP) 794 feature |= X86_SEP; 795 if (cp->cp_edx & CPUID_INTC_EDX_FXSR) { 796 /* 797 * In our implementation, fxsave/fxrstor 798 * are prerequisites before we'll even 799 * try and do SSE things. 800 */ 801 if (cp->cp_edx & CPUID_INTC_EDX_SSE) 802 feature |= X86_SSE; 803 if (cp->cp_edx & CPUID_INTC_EDX_SSE2) 804 feature |= X86_SSE2; 805 if (cp->cp_ecx & CPUID_INTC_ECX_SSE3) 806 feature |= X86_SSE3; 807 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 808 if (cp->cp_ecx & CPUID_INTC_ECX_SSSE3) 809 feature |= X86_SSSE3; 810 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_1) 811 feature |= X86_SSE4_1; 812 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_2) 813 feature |= X86_SSE4_2; 814 } 815 } 816 if (cp->cp_edx & CPUID_INTC_EDX_DE) 817 feature |= X86_DE; 818 #if !defined(__xpv) 819 if (cp->cp_ecx & CPUID_INTC_ECX_MON) { 820 821 /* 822 * We require the CLFLUSH instruction for erratum workaround 823 * to use MONITOR/MWAIT. 824 */ 825 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) { 826 cpi->cpi_mwait.support |= MWAIT_SUPPORT; 827 feature |= X86_MWAIT; 828 } else { 829 extern int idle_cpu_assert_cflush_monitor; 830 831 /* 832 * All processors we are aware of which have 833 * MONITOR/MWAIT also have CLFLUSH. 834 */ 835 if (idle_cpu_assert_cflush_monitor) { 836 ASSERT((cp->cp_ecx & CPUID_INTC_ECX_MON) && 837 (cp->cp_edx & CPUID_INTC_EDX_CLFSH)); 838 } 839 } 840 } 841 #endif /* __xpv */ 842 843 /* 844 * Only need it first time, rest of the cpus would follow suite. 845 * we only capture this for the bootcpu. 846 */ 847 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) { 848 feature |= X86_CLFSH; 849 x86_clflush_size = (BITX(cp->cp_ebx, 15, 8) * 8); 850 } 851 852 if (feature & X86_PAE) 853 cpi->cpi_pabits = 36; 854 855 /* 856 * Hyperthreading configuration is slightly tricky on Intel 857 * and pure clones, and even trickier on AMD. 858 * 859 * (AMD chose to set the HTT bit on their CMP processors, 860 * even though they're not actually hyperthreaded. Thus it 861 * takes a bit more work to figure out what's really going 862 * on ... see the handling of the CMP_LGCY bit below) 863 */ 864 if (cp->cp_edx & CPUID_INTC_EDX_HTT) { 865 cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi); 866 if (cpi->cpi_ncpu_per_chip > 1) 867 feature |= X86_HTT; 868 } else { 869 cpi->cpi_ncpu_per_chip = 1; 870 } 871 872 /* 873 * Work on the "extended" feature information, doing 874 * some basic initialization for cpuid_pass2() 875 */ 876 xcpuid = 0; 877 switch (cpi->cpi_vendor) { 878 case X86_VENDOR_Intel: 879 if (IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf) 880 xcpuid++; 881 break; 882 case X86_VENDOR_AMD: 883 if (cpi->cpi_family > 5 || 884 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 885 xcpuid++; 886 break; 887 case X86_VENDOR_Cyrix: 888 /* 889 * Only these Cyrix CPUs are -known- to support 890 * extended cpuid operations. 891 */ 892 if (x86_type == X86_TYPE_VIA_CYRIX_III || 893 x86_type == X86_TYPE_CYRIX_GXm) 894 xcpuid++; 895 break; 896 case X86_VENDOR_Centaur: 897 case X86_VENDOR_TM: 898 default: 899 xcpuid++; 900 break; 901 } 902 903 if (xcpuid) { 904 cp = &cpi->cpi_extd[0]; 905 cp->cp_eax = 0x80000000; 906 cpi->cpi_xmaxeax = __cpuid_insn(cp); 907 } 908 909 if (cpi->cpi_xmaxeax & 0x80000000) { 910 911 if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX) 912 cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX; 913 914 switch (cpi->cpi_vendor) { 915 case X86_VENDOR_Intel: 916 case X86_VENDOR_AMD: 917 if (cpi->cpi_xmaxeax < 0x80000001) 918 break; 919 cp = &cpi->cpi_extd[1]; 920 cp->cp_eax = 0x80000001; 921 (void) __cpuid_insn(cp); 922 923 if (cpi->cpi_vendor == X86_VENDOR_AMD && 924 cpi->cpi_family == 5 && 925 cpi->cpi_model == 6 && 926 cpi->cpi_step == 6) { 927 /* 928 * K6 model 6 uses bit 10 to indicate SYSC 929 * Later models use bit 11. Fix it here. 930 */ 931 if (cp->cp_edx & 0x400) { 932 cp->cp_edx &= ~0x400; 933 cp->cp_edx |= CPUID_AMD_EDX_SYSC; 934 } 935 } 936 937 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000001, cp); 938 939 /* 940 * Compute the additions to the kernel's feature word. 941 */ 942 if (cp->cp_edx & CPUID_AMD_EDX_NX) 943 feature |= X86_NX; 944 945 /* 946 * Regardless whether or not we boot 64-bit, 947 * we should have a way to identify whether 948 * the CPU is capable of running 64-bit. 949 */ 950 if (cp->cp_edx & CPUID_AMD_EDX_LM) 951 feature |= X86_64; 952 953 #if defined(__amd64) 954 /* 1 GB large page - enable only for 64 bit kernel */ 955 if (cp->cp_edx & CPUID_AMD_EDX_1GPG) 956 feature |= X86_1GPG; 957 #endif 958 959 if ((cpi->cpi_vendor == X86_VENDOR_AMD) && 960 (cpi->cpi_std[1].cp_edx & CPUID_INTC_EDX_FXSR) && 961 (cp->cp_ecx & CPUID_AMD_ECX_SSE4A)) 962 feature |= X86_SSE4A; 963 964 /* 965 * If both the HTT and CMP_LGCY bits are set, 966 * then we're not actually HyperThreaded. Read 967 * "AMD CPUID Specification" for more details. 968 */ 969 if (cpi->cpi_vendor == X86_VENDOR_AMD && 970 (feature & X86_HTT) && 971 (cp->cp_ecx & CPUID_AMD_ECX_CMP_LGCY)) { 972 feature &= ~X86_HTT; 973 feature |= X86_CMP; 974 } 975 #if defined(__amd64) 976 /* 977 * It's really tricky to support syscall/sysret in 978 * the i386 kernel; we rely on sysenter/sysexit 979 * instead. In the amd64 kernel, things are -way- 980 * better. 981 */ 982 if (cp->cp_edx & CPUID_AMD_EDX_SYSC) 983 feature |= X86_ASYSC; 984 985 /* 986 * While we're thinking about system calls, note 987 * that AMD processors don't support sysenter 988 * in long mode at all, so don't try to program them. 989 */ 990 if (x86_vendor == X86_VENDOR_AMD) 991 feature &= ~X86_SEP; 992 #endif 993 if (cp->cp_edx & CPUID_AMD_EDX_TSCP) 994 feature |= X86_TSCP; 995 break; 996 default: 997 break; 998 } 999 1000 /* 1001 * Get CPUID data about processor cores and hyperthreads. 1002 */ 1003 switch (cpi->cpi_vendor) { 1004 case X86_VENDOR_Intel: 1005 if (cpi->cpi_maxeax >= 4) { 1006 cp = &cpi->cpi_std[4]; 1007 cp->cp_eax = 4; 1008 cp->cp_ecx = 0; 1009 (void) __cpuid_insn(cp); 1010 platform_cpuid_mangle(cpi->cpi_vendor, 4, cp); 1011 } 1012 /*FALLTHROUGH*/ 1013 case X86_VENDOR_AMD: 1014 if (cpi->cpi_xmaxeax < 0x80000008) 1015 break; 1016 cp = &cpi->cpi_extd[8]; 1017 cp->cp_eax = 0x80000008; 1018 (void) __cpuid_insn(cp); 1019 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000008, cp); 1020 1021 /* 1022 * Virtual and physical address limits from 1023 * cpuid override previously guessed values. 1024 */ 1025 cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0); 1026 cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8); 1027 break; 1028 default: 1029 break; 1030 } 1031 1032 /* 1033 * Derive the number of cores per chip 1034 */ 1035 switch (cpi->cpi_vendor) { 1036 case X86_VENDOR_Intel: 1037 if (cpi->cpi_maxeax < 4) { 1038 cpi->cpi_ncore_per_chip = 1; 1039 break; 1040 } else { 1041 cpi->cpi_ncore_per_chip = 1042 BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1; 1043 } 1044 break; 1045 case X86_VENDOR_AMD: 1046 if (cpi->cpi_xmaxeax < 0x80000008) { 1047 cpi->cpi_ncore_per_chip = 1; 1048 break; 1049 } else { 1050 /* 1051 * On family 0xf cpuid fn 2 ECX[7:0] "NC" is 1052 * 1 less than the number of physical cores on 1053 * the chip. In family 0x10 this value can 1054 * be affected by "downcoring" - it reflects 1055 * 1 less than the number of cores actually 1056 * enabled on this node. 1057 */ 1058 cpi->cpi_ncore_per_chip = 1059 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1; 1060 } 1061 break; 1062 default: 1063 cpi->cpi_ncore_per_chip = 1; 1064 break; 1065 } 1066 1067 /* 1068 * Get CPUID data about TSC Invariance in Deep C-State. 1069 */ 1070 switch (cpi->cpi_vendor) { 1071 case X86_VENDOR_Intel: 1072 if (cpi->cpi_maxeax >= 7) { 1073 cp = &cpi->cpi_extd[7]; 1074 cp->cp_eax = 0x80000007; 1075 cp->cp_ecx = 0; 1076 (void) __cpuid_insn(cp); 1077 } 1078 break; 1079 default: 1080 break; 1081 } 1082 } else { 1083 cpi->cpi_ncore_per_chip = 1; 1084 } 1085 1086 /* 1087 * If more than one core, then this processor is CMP. 1088 */ 1089 if (cpi->cpi_ncore_per_chip > 1) 1090 feature |= X86_CMP; 1091 1092 /* 1093 * If the number of cores is the same as the number 1094 * of CPUs, then we cannot have HyperThreading. 1095 */ 1096 if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip) 1097 feature &= ~X86_HTT; 1098 1099 if ((feature & (X86_HTT | X86_CMP)) == 0) { 1100 /* 1101 * Single-core single-threaded processors. 1102 */ 1103 cpi->cpi_chipid = -1; 1104 cpi->cpi_clogid = 0; 1105 cpi->cpi_coreid = cpu->cpu_id; 1106 cpi->cpi_pkgcoreid = 0; 1107 } else if (cpi->cpi_ncpu_per_chip > 1) { 1108 uint_t i; 1109 uint_t chipid_shift = 0; 1110 uint_t coreid_shift = 0; 1111 uint_t apic_id = CPI_APIC_ID(cpi); 1112 1113 for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1) 1114 chipid_shift++; 1115 cpi->cpi_chipid = apic_id >> chipid_shift; 1116 cpi->cpi_clogid = apic_id & ((1 << chipid_shift) - 1); 1117 1118 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 1119 if (feature & X86_CMP) { 1120 /* 1121 * Multi-core (and possibly multi-threaded) 1122 * processors. 1123 */ 1124 uint_t ncpu_per_core; 1125 if (cpi->cpi_ncore_per_chip == 1) 1126 ncpu_per_core = cpi->cpi_ncpu_per_chip; 1127 else if (cpi->cpi_ncore_per_chip > 1) 1128 ncpu_per_core = cpi->cpi_ncpu_per_chip / 1129 cpi->cpi_ncore_per_chip; 1130 /* 1131 * 8bit APIC IDs on dual core Pentiums 1132 * look like this: 1133 * 1134 * +-----------------------+------+------+ 1135 * | Physical Package ID | MC | HT | 1136 * +-----------------------+------+------+ 1137 * <------- chipid --------> 1138 * <------- coreid ---------------> 1139 * <--- clogid --> 1140 * <------> 1141 * pkgcoreid 1142 * 1143 * Where the number of bits necessary to 1144 * represent MC and HT fields together equals 1145 * to the minimum number of bits necessary to 1146 * store the value of cpi->cpi_ncpu_per_chip. 1147 * Of those bits, the MC part uses the number 1148 * of bits necessary to store the value of 1149 * cpi->cpi_ncore_per_chip. 1150 */ 1151 for (i = 1; i < ncpu_per_core; i <<= 1) 1152 coreid_shift++; 1153 cpi->cpi_coreid = apic_id >> coreid_shift; 1154 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> 1155 coreid_shift; 1156 } else if (feature & X86_HTT) { 1157 /* 1158 * Single-core multi-threaded processors. 1159 */ 1160 cpi->cpi_coreid = cpi->cpi_chipid; 1161 cpi->cpi_pkgcoreid = 0; 1162 } 1163 } else if (cpi->cpi_vendor == X86_VENDOR_AMD) { 1164 /* 1165 * AMD CMP chips currently have a single thread per 1166 * core, with 2 cores on family 0xf and 2, 3 or 4 1167 * cores on family 0x10. 1168 * 1169 * Since no two cpus share a core we must assign a 1170 * distinct coreid per cpu, and we do this by using 1171 * the cpu_id. This scheme does not, however, 1172 * guarantee that sibling cores of a chip will have 1173 * sequential coreids starting at a multiple of the 1174 * number of cores per chip - that is usually the 1175 * case, but if the ACPI MADT table is presented 1176 * in a different order then we need to perform a 1177 * few more gymnastics for the pkgcoreid. 1178 * 1179 * In family 0xf CMPs there are 2 cores on all nodes 1180 * present - no mixing of single and dual core parts. 1181 * 1182 * In family 0x10 CMPs cpuid fn 2 ECX[15:12] 1183 * "ApicIdCoreIdSize[3:0]" tells us how 1184 * many least-significant bits in the ApicId 1185 * are used to represent the core number 1186 * within the node. Cores are always 1187 * numbered sequentially from 0 regardless 1188 * of how many or which are disabled, and 1189 * there seems to be no way to discover the 1190 * real core id when some are disabled. 1191 */ 1192 cpi->cpi_coreid = cpu->cpu_id; 1193 1194 if (cpi->cpi_family == 0x10 && 1195 cpi->cpi_xmaxeax >= 0x80000008) { 1196 int coreidsz = 1197 BITX((cpi)->cpi_extd[8].cp_ecx, 15, 12); 1198 1199 cpi->cpi_pkgcoreid = 1200 apic_id & ((1 << coreidsz) - 1); 1201 } else { 1202 cpi->cpi_pkgcoreid = cpi->cpi_clogid; 1203 } 1204 } else { 1205 /* 1206 * All other processors are currently 1207 * assumed to have single cores. 1208 */ 1209 cpi->cpi_coreid = cpi->cpi_chipid; 1210 cpi->cpi_pkgcoreid = 0; 1211 } 1212 } 1213 1214 cpi->cpi_apicid = CPI_APIC_ID(cpi); 1215 1216 /* 1217 * Synthesize chip "revision" and socket type 1218 */ 1219 cpi->cpi_chiprev = _cpuid_chiprev(cpi->cpi_vendor, cpi->cpi_family, 1220 cpi->cpi_model, cpi->cpi_step); 1221 cpi->cpi_chiprevstr = _cpuid_chiprevstr(cpi->cpi_vendor, 1222 cpi->cpi_family, cpi->cpi_model, cpi->cpi_step); 1223 cpi->cpi_socket = _cpuid_skt(cpi->cpi_vendor, cpi->cpi_family, 1224 cpi->cpi_model, cpi->cpi_step); 1225 1226 pass1_done: 1227 #if !defined(__xpv) 1228 determine_platform(); 1229 #endif 1230 cpi->cpi_pass = 1; 1231 return (feature); 1232 } 1233 1234 /* 1235 * Make copies of the cpuid table entries we depend on, in 1236 * part for ease of parsing now, in part so that we have only 1237 * one place to correct any of it, in part for ease of 1238 * later export to userland, and in part so we can look at 1239 * this stuff in a crash dump. 1240 */ 1241 1242 /*ARGSUSED*/ 1243 void 1244 cpuid_pass2(cpu_t *cpu) 1245 { 1246 uint_t n, nmax; 1247 int i; 1248 struct cpuid_regs *cp; 1249 uint8_t *dp; 1250 uint32_t *iptr; 1251 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1252 1253 ASSERT(cpi->cpi_pass == 1); 1254 1255 if (cpi->cpi_maxeax < 1) 1256 goto pass2_done; 1257 1258 if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD) 1259 nmax = NMAX_CPI_STD; 1260 /* 1261 * (We already handled n == 0 and n == 1 in pass 1) 1262 */ 1263 for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) { 1264 cp->cp_eax = n; 1265 1266 /* 1267 * CPUID function 4 expects %ecx to be initialized 1268 * with an index which indicates which cache to return 1269 * information about. The OS is expected to call function 4 1270 * with %ecx set to 0, 1, 2, ... until it returns with 1271 * EAX[4:0] set to 0, which indicates there are no more 1272 * caches. 1273 * 1274 * Here, populate cpi_std[4] with the information returned by 1275 * function 4 when %ecx == 0, and do the rest in cpuid_pass3() 1276 * when dynamic memory allocation becomes available. 1277 * 1278 * Note: we need to explicitly initialize %ecx here, since 1279 * function 4 may have been previously invoked. 1280 */ 1281 if (n == 4) 1282 cp->cp_ecx = 0; 1283 1284 (void) __cpuid_insn(cp); 1285 platform_cpuid_mangle(cpi->cpi_vendor, n, cp); 1286 switch (n) { 1287 case 2: 1288 /* 1289 * "the lower 8 bits of the %eax register 1290 * contain a value that identifies the number 1291 * of times the cpuid [instruction] has to be 1292 * executed to obtain a complete image of the 1293 * processor's caching systems." 1294 * 1295 * How *do* they make this stuff up? 1296 */ 1297 cpi->cpi_ncache = sizeof (*cp) * 1298 BITX(cp->cp_eax, 7, 0); 1299 if (cpi->cpi_ncache == 0) 1300 break; 1301 cpi->cpi_ncache--; /* skip count byte */ 1302 1303 /* 1304 * Well, for now, rather than attempt to implement 1305 * this slightly dubious algorithm, we just look 1306 * at the first 15 .. 1307 */ 1308 if (cpi->cpi_ncache > (sizeof (*cp) - 1)) 1309 cpi->cpi_ncache = sizeof (*cp) - 1; 1310 1311 dp = cpi->cpi_cacheinfo; 1312 if (BITX(cp->cp_eax, 31, 31) == 0) { 1313 uint8_t *p = (void *)&cp->cp_eax; 1314 for (i = 1; i < 4; i++) 1315 if (p[i] != 0) 1316 *dp++ = p[i]; 1317 } 1318 if (BITX(cp->cp_ebx, 31, 31) == 0) { 1319 uint8_t *p = (void *)&cp->cp_ebx; 1320 for (i = 0; i < 4; i++) 1321 if (p[i] != 0) 1322 *dp++ = p[i]; 1323 } 1324 if (BITX(cp->cp_ecx, 31, 31) == 0) { 1325 uint8_t *p = (void *)&cp->cp_ecx; 1326 for (i = 0; i < 4; i++) 1327 if (p[i] != 0) 1328 *dp++ = p[i]; 1329 } 1330 if (BITX(cp->cp_edx, 31, 31) == 0) { 1331 uint8_t *p = (void *)&cp->cp_edx; 1332 for (i = 0; i < 4; i++) 1333 if (p[i] != 0) 1334 *dp++ = p[i]; 1335 } 1336 break; 1337 1338 case 3: /* Processor serial number, if PSN supported */ 1339 break; 1340 1341 case 4: /* Deterministic cache parameters */ 1342 break; 1343 1344 case 5: /* Monitor/Mwait parameters */ 1345 { 1346 size_t mwait_size; 1347 1348 /* 1349 * check cpi_mwait.support which was set in cpuid_pass1 1350 */ 1351 if (!(cpi->cpi_mwait.support & MWAIT_SUPPORT)) 1352 break; 1353 1354 /* 1355 * Protect ourself from insane mwait line size. 1356 * Workaround for incomplete hardware emulator(s). 1357 */ 1358 mwait_size = (size_t)MWAIT_SIZE_MAX(cpi); 1359 if (mwait_size < sizeof (uint32_t) || 1360 !ISP2(mwait_size)) { 1361 #if DEBUG 1362 cmn_err(CE_NOTE, "Cannot handle cpu %d mwait " 1363 "size %ld", cpu->cpu_id, (long)mwait_size); 1364 #endif 1365 break; 1366 } 1367 1368 cpi->cpi_mwait.mon_min = (size_t)MWAIT_SIZE_MIN(cpi); 1369 cpi->cpi_mwait.mon_max = mwait_size; 1370 if (MWAIT_EXTENSION(cpi)) { 1371 cpi->cpi_mwait.support |= MWAIT_EXTENSIONS; 1372 if (MWAIT_INT_ENABLE(cpi)) 1373 cpi->cpi_mwait.support |= 1374 MWAIT_ECX_INT_ENABLE; 1375 } 1376 break; 1377 } 1378 default: 1379 break; 1380 } 1381 } 1382 1383 if (cpi->cpi_maxeax >= 0xB && cpi->cpi_vendor == X86_VENDOR_Intel) { 1384 struct cpuid_regs regs; 1385 1386 cp = ®s; 1387 cp->cp_eax = 0xB; 1388 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0; 1389 1390 (void) __cpuid_insn(cp); 1391 1392 /* 1393 * Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero, which 1394 * indicates that the extended topology enumeration leaf is 1395 * available. 1396 */ 1397 if (cp->cp_ebx) { 1398 uint32_t x2apic_id; 1399 uint_t coreid_shift = 0; 1400 uint_t ncpu_per_core = 1; 1401 uint_t chipid_shift = 0; 1402 uint_t ncpu_per_chip = 1; 1403 uint_t i; 1404 uint_t level; 1405 1406 for (i = 0; i < CPI_FNB_ECX_MAX; i++) { 1407 cp->cp_eax = 0xB; 1408 cp->cp_ecx = i; 1409 1410 (void) __cpuid_insn(cp); 1411 level = CPI_CPU_LEVEL_TYPE(cp); 1412 1413 if (level == 1) { 1414 x2apic_id = cp->cp_edx; 1415 coreid_shift = BITX(cp->cp_eax, 4, 0); 1416 ncpu_per_core = BITX(cp->cp_ebx, 15, 0); 1417 } else if (level == 2) { 1418 x2apic_id = cp->cp_edx; 1419 chipid_shift = BITX(cp->cp_eax, 4, 0); 1420 ncpu_per_chip = BITX(cp->cp_ebx, 15, 0); 1421 } 1422 } 1423 1424 cpi->cpi_apicid = x2apic_id; 1425 cpi->cpi_ncpu_per_chip = ncpu_per_chip; 1426 cpi->cpi_ncore_per_chip = ncpu_per_chip / 1427 ncpu_per_core; 1428 cpi->cpi_chipid = x2apic_id >> chipid_shift; 1429 cpi->cpi_clogid = x2apic_id & ((1 << chipid_shift) - 1); 1430 cpi->cpi_coreid = x2apic_id >> coreid_shift; 1431 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift; 1432 } 1433 1434 /* Make cp NULL so that we don't stumble on others */ 1435 cp = NULL; 1436 } 1437 1438 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) 1439 goto pass2_done; 1440 1441 if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD) 1442 nmax = NMAX_CPI_EXTD; 1443 /* 1444 * Copy the extended properties, fixing them as we go. 1445 * (We already handled n == 0 and n == 1 in pass 1) 1446 */ 1447 iptr = (void *)cpi->cpi_brandstr; 1448 for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) { 1449 cp->cp_eax = 0x80000000 + n; 1450 (void) __cpuid_insn(cp); 1451 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000000 + n, cp); 1452 switch (n) { 1453 case 2: 1454 case 3: 1455 case 4: 1456 /* 1457 * Extract the brand string 1458 */ 1459 *iptr++ = cp->cp_eax; 1460 *iptr++ = cp->cp_ebx; 1461 *iptr++ = cp->cp_ecx; 1462 *iptr++ = cp->cp_edx; 1463 break; 1464 case 5: 1465 switch (cpi->cpi_vendor) { 1466 case X86_VENDOR_AMD: 1467 /* 1468 * The Athlon and Duron were the first 1469 * parts to report the sizes of the 1470 * TLB for large pages. Before then, 1471 * we don't trust the data. 1472 */ 1473 if (cpi->cpi_family < 6 || 1474 (cpi->cpi_family == 6 && 1475 cpi->cpi_model < 1)) 1476 cp->cp_eax = 0; 1477 break; 1478 default: 1479 break; 1480 } 1481 break; 1482 case 6: 1483 switch (cpi->cpi_vendor) { 1484 case X86_VENDOR_AMD: 1485 /* 1486 * The Athlon and Duron were the first 1487 * AMD parts with L2 TLB's. 1488 * Before then, don't trust the data. 1489 */ 1490 if (cpi->cpi_family < 6 || 1491 cpi->cpi_family == 6 && 1492 cpi->cpi_model < 1) 1493 cp->cp_eax = cp->cp_ebx = 0; 1494 /* 1495 * AMD Duron rev A0 reports L2 1496 * cache size incorrectly as 1K 1497 * when it is really 64K 1498 */ 1499 if (cpi->cpi_family == 6 && 1500 cpi->cpi_model == 3 && 1501 cpi->cpi_step == 0) { 1502 cp->cp_ecx &= 0xffff; 1503 cp->cp_ecx |= 0x400000; 1504 } 1505 break; 1506 case X86_VENDOR_Cyrix: /* VIA C3 */ 1507 /* 1508 * VIA C3 processors are a bit messed 1509 * up w.r.t. encoding cache sizes in %ecx 1510 */ 1511 if (cpi->cpi_family != 6) 1512 break; 1513 /* 1514 * model 7 and 8 were incorrectly encoded 1515 * 1516 * xxx is model 8 really broken? 1517 */ 1518 if (cpi->cpi_model == 7 || 1519 cpi->cpi_model == 8) 1520 cp->cp_ecx = 1521 BITX(cp->cp_ecx, 31, 24) << 16 | 1522 BITX(cp->cp_ecx, 23, 16) << 12 | 1523 BITX(cp->cp_ecx, 15, 8) << 8 | 1524 BITX(cp->cp_ecx, 7, 0); 1525 /* 1526 * model 9 stepping 1 has wrong associativity 1527 */ 1528 if (cpi->cpi_model == 9 && cpi->cpi_step == 1) 1529 cp->cp_ecx |= 8 << 12; 1530 break; 1531 case X86_VENDOR_Intel: 1532 /* 1533 * Extended L2 Cache features function. 1534 * First appeared on Prescott. 1535 */ 1536 default: 1537 break; 1538 } 1539 break; 1540 default: 1541 break; 1542 } 1543 } 1544 1545 pass2_done: 1546 cpi->cpi_pass = 2; 1547 } 1548 1549 static const char * 1550 intel_cpubrand(const struct cpuid_info *cpi) 1551 { 1552 int i; 1553 1554 if ((x86_feature & X86_CPUID) == 0 || 1555 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 1556 return ("i486"); 1557 1558 switch (cpi->cpi_family) { 1559 case 5: 1560 return ("Intel Pentium(r)"); 1561 case 6: 1562 switch (cpi->cpi_model) { 1563 uint_t celeron, xeon; 1564 const struct cpuid_regs *cp; 1565 case 0: 1566 case 1: 1567 case 2: 1568 return ("Intel Pentium(r) Pro"); 1569 case 3: 1570 case 4: 1571 return ("Intel Pentium(r) II"); 1572 case 6: 1573 return ("Intel Celeron(r)"); 1574 case 5: 1575 case 7: 1576 celeron = xeon = 0; 1577 cp = &cpi->cpi_std[2]; /* cache info */ 1578 1579 for (i = 1; i < 4; i++) { 1580 uint_t tmp; 1581 1582 tmp = (cp->cp_eax >> (8 * i)) & 0xff; 1583 if (tmp == 0x40) 1584 celeron++; 1585 if (tmp >= 0x44 && tmp <= 0x45) 1586 xeon++; 1587 } 1588 1589 for (i = 0; i < 2; i++) { 1590 uint_t tmp; 1591 1592 tmp = (cp->cp_ebx >> (8 * i)) & 0xff; 1593 if (tmp == 0x40) 1594 celeron++; 1595 else if (tmp >= 0x44 && tmp <= 0x45) 1596 xeon++; 1597 } 1598 1599 for (i = 0; i < 4; i++) { 1600 uint_t tmp; 1601 1602 tmp = (cp->cp_ecx >> (8 * i)) & 0xff; 1603 if (tmp == 0x40) 1604 celeron++; 1605 else if (tmp >= 0x44 && tmp <= 0x45) 1606 xeon++; 1607 } 1608 1609 for (i = 0; i < 4; i++) { 1610 uint_t tmp; 1611 1612 tmp = (cp->cp_edx >> (8 * i)) & 0xff; 1613 if (tmp == 0x40) 1614 celeron++; 1615 else if (tmp >= 0x44 && tmp <= 0x45) 1616 xeon++; 1617 } 1618 1619 if (celeron) 1620 return ("Intel Celeron(r)"); 1621 if (xeon) 1622 return (cpi->cpi_model == 5 ? 1623 "Intel Pentium(r) II Xeon(tm)" : 1624 "Intel Pentium(r) III Xeon(tm)"); 1625 return (cpi->cpi_model == 5 ? 1626 "Intel Pentium(r) II or Pentium(r) II Xeon(tm)" : 1627 "Intel Pentium(r) III or Pentium(r) III Xeon(tm)"); 1628 default: 1629 break; 1630 } 1631 default: 1632 break; 1633 } 1634 1635 /* BrandID is present if the field is nonzero */ 1636 if (cpi->cpi_brandid != 0) { 1637 static const struct { 1638 uint_t bt_bid; 1639 const char *bt_str; 1640 } brand_tbl[] = { 1641 { 0x1, "Intel(r) Celeron(r)" }, 1642 { 0x2, "Intel(r) Pentium(r) III" }, 1643 { 0x3, "Intel(r) Pentium(r) III Xeon(tm)" }, 1644 { 0x4, "Intel(r) Pentium(r) III" }, 1645 { 0x6, "Mobile Intel(r) Pentium(r) III" }, 1646 { 0x7, "Mobile Intel(r) Celeron(r)" }, 1647 { 0x8, "Intel(r) Pentium(r) 4" }, 1648 { 0x9, "Intel(r) Pentium(r) 4" }, 1649 { 0xa, "Intel(r) Celeron(r)" }, 1650 { 0xb, "Intel(r) Xeon(tm)" }, 1651 { 0xc, "Intel(r) Xeon(tm) MP" }, 1652 { 0xe, "Mobile Intel(r) Pentium(r) 4" }, 1653 { 0xf, "Mobile Intel(r) Celeron(r)" }, 1654 { 0x11, "Mobile Genuine Intel(r)" }, 1655 { 0x12, "Intel(r) Celeron(r) M" }, 1656 { 0x13, "Mobile Intel(r) Celeron(r)" }, 1657 { 0x14, "Intel(r) Celeron(r)" }, 1658 { 0x15, "Mobile Genuine Intel(r)" }, 1659 { 0x16, "Intel(r) Pentium(r) M" }, 1660 { 0x17, "Mobile Intel(r) Celeron(r)" } 1661 }; 1662 uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]); 1663 uint_t sgn; 1664 1665 sgn = (cpi->cpi_family << 8) | 1666 (cpi->cpi_model << 4) | cpi->cpi_step; 1667 1668 for (i = 0; i < btblmax; i++) 1669 if (brand_tbl[i].bt_bid == cpi->cpi_brandid) 1670 break; 1671 if (i < btblmax) { 1672 if (sgn == 0x6b1 && cpi->cpi_brandid == 3) 1673 return ("Intel(r) Celeron(r)"); 1674 if (sgn < 0xf13 && cpi->cpi_brandid == 0xb) 1675 return ("Intel(r) Xeon(tm) MP"); 1676 if (sgn < 0xf13 && cpi->cpi_brandid == 0xe) 1677 return ("Intel(r) Xeon(tm)"); 1678 return (brand_tbl[i].bt_str); 1679 } 1680 } 1681 1682 return (NULL); 1683 } 1684 1685 static const char * 1686 amd_cpubrand(const struct cpuid_info *cpi) 1687 { 1688 if ((x86_feature & X86_CPUID) == 0 || 1689 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 1690 return ("i486 compatible"); 1691 1692 switch (cpi->cpi_family) { 1693 case 5: 1694 switch (cpi->cpi_model) { 1695 case 0: 1696 case 1: 1697 case 2: 1698 case 3: 1699 case 4: 1700 case 5: 1701 return ("AMD-K5(r)"); 1702 case 6: 1703 case 7: 1704 return ("AMD-K6(r)"); 1705 case 8: 1706 return ("AMD-K6(r)-2"); 1707 case 9: 1708 return ("AMD-K6(r)-III"); 1709 default: 1710 return ("AMD (family 5)"); 1711 } 1712 case 6: 1713 switch (cpi->cpi_model) { 1714 case 1: 1715 return ("AMD-K7(tm)"); 1716 case 0: 1717 case 2: 1718 case 4: 1719 return ("AMD Athlon(tm)"); 1720 case 3: 1721 case 7: 1722 return ("AMD Duron(tm)"); 1723 case 6: 1724 case 8: 1725 case 10: 1726 /* 1727 * Use the L2 cache size to distinguish 1728 */ 1729 return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ? 1730 "AMD Athlon(tm)" : "AMD Duron(tm)"); 1731 default: 1732 return ("AMD (family 6)"); 1733 } 1734 default: 1735 break; 1736 } 1737 1738 if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 && 1739 cpi->cpi_brandid != 0) { 1740 switch (BITX(cpi->cpi_brandid, 7, 5)) { 1741 case 3: 1742 return ("AMD Opteron(tm) UP 1xx"); 1743 case 4: 1744 return ("AMD Opteron(tm) DP 2xx"); 1745 case 5: 1746 return ("AMD Opteron(tm) MP 8xx"); 1747 default: 1748 return ("AMD Opteron(tm)"); 1749 } 1750 } 1751 1752 return (NULL); 1753 } 1754 1755 static const char * 1756 cyrix_cpubrand(struct cpuid_info *cpi, uint_t type) 1757 { 1758 if ((x86_feature & X86_CPUID) == 0 || 1759 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5 || 1760 type == X86_TYPE_CYRIX_486) 1761 return ("i486 compatible"); 1762 1763 switch (type) { 1764 case X86_TYPE_CYRIX_6x86: 1765 return ("Cyrix 6x86"); 1766 case X86_TYPE_CYRIX_6x86L: 1767 return ("Cyrix 6x86L"); 1768 case X86_TYPE_CYRIX_6x86MX: 1769 return ("Cyrix 6x86MX"); 1770 case X86_TYPE_CYRIX_GXm: 1771 return ("Cyrix GXm"); 1772 case X86_TYPE_CYRIX_MediaGX: 1773 return ("Cyrix MediaGX"); 1774 case X86_TYPE_CYRIX_MII: 1775 return ("Cyrix M2"); 1776 case X86_TYPE_VIA_CYRIX_III: 1777 return ("VIA Cyrix M3"); 1778 default: 1779 /* 1780 * Have another wild guess .. 1781 */ 1782 if (cpi->cpi_family == 4 && cpi->cpi_model == 9) 1783 return ("Cyrix 5x86"); 1784 else if (cpi->cpi_family == 5) { 1785 switch (cpi->cpi_model) { 1786 case 2: 1787 return ("Cyrix 6x86"); /* Cyrix M1 */ 1788 case 4: 1789 return ("Cyrix MediaGX"); 1790 default: 1791 break; 1792 } 1793 } else if (cpi->cpi_family == 6) { 1794 switch (cpi->cpi_model) { 1795 case 0: 1796 return ("Cyrix 6x86MX"); /* Cyrix M2? */ 1797 case 5: 1798 case 6: 1799 case 7: 1800 case 8: 1801 case 9: 1802 return ("VIA C3"); 1803 default: 1804 break; 1805 } 1806 } 1807 break; 1808 } 1809 return (NULL); 1810 } 1811 1812 /* 1813 * This only gets called in the case that the CPU extended 1814 * feature brand string (0x80000002, 0x80000003, 0x80000004) 1815 * aren't available, or contain null bytes for some reason. 1816 */ 1817 static void 1818 fabricate_brandstr(struct cpuid_info *cpi) 1819 { 1820 const char *brand = NULL; 1821 1822 switch (cpi->cpi_vendor) { 1823 case X86_VENDOR_Intel: 1824 brand = intel_cpubrand(cpi); 1825 break; 1826 case X86_VENDOR_AMD: 1827 brand = amd_cpubrand(cpi); 1828 break; 1829 case X86_VENDOR_Cyrix: 1830 brand = cyrix_cpubrand(cpi, x86_type); 1831 break; 1832 case X86_VENDOR_NexGen: 1833 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 1834 brand = "NexGen Nx586"; 1835 break; 1836 case X86_VENDOR_Centaur: 1837 if (cpi->cpi_family == 5) 1838 switch (cpi->cpi_model) { 1839 case 4: 1840 brand = "Centaur C6"; 1841 break; 1842 case 8: 1843 brand = "Centaur C2"; 1844 break; 1845 case 9: 1846 brand = "Centaur C3"; 1847 break; 1848 default: 1849 break; 1850 } 1851 break; 1852 case X86_VENDOR_Rise: 1853 if (cpi->cpi_family == 5 && 1854 (cpi->cpi_model == 0 || cpi->cpi_model == 2)) 1855 brand = "Rise mP6"; 1856 break; 1857 case X86_VENDOR_SiS: 1858 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 1859 brand = "SiS 55x"; 1860 break; 1861 case X86_VENDOR_TM: 1862 if (cpi->cpi_family == 5 && cpi->cpi_model == 4) 1863 brand = "Transmeta Crusoe TM3x00 or TM5x00"; 1864 break; 1865 case X86_VENDOR_NSC: 1866 case X86_VENDOR_UMC: 1867 default: 1868 break; 1869 } 1870 if (brand) { 1871 (void) strcpy((char *)cpi->cpi_brandstr, brand); 1872 return; 1873 } 1874 1875 /* 1876 * If all else fails ... 1877 */ 1878 (void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr), 1879 "%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family, 1880 cpi->cpi_model, cpi->cpi_step); 1881 } 1882 1883 /* 1884 * This routine is called just after kernel memory allocation 1885 * becomes available on cpu0, and as part of mp_startup() on 1886 * the other cpus. 1887 * 1888 * Fixup the brand string, and collect any information from cpuid 1889 * that requires dynamicically allocated storage to represent. 1890 */ 1891 /*ARGSUSED*/ 1892 void 1893 cpuid_pass3(cpu_t *cpu) 1894 { 1895 int i, max, shft, level, size; 1896 struct cpuid_regs regs; 1897 struct cpuid_regs *cp; 1898 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1899 1900 ASSERT(cpi->cpi_pass == 2); 1901 1902 /* 1903 * Function 4: Deterministic cache parameters 1904 * 1905 * Take this opportunity to detect the number of threads 1906 * sharing the last level cache, and construct a corresponding 1907 * cache id. The respective cpuid_info members are initialized 1908 * to the default case of "no last level cache sharing". 1909 */ 1910 cpi->cpi_ncpu_shr_last_cache = 1; 1911 cpi->cpi_last_lvl_cacheid = cpu->cpu_id; 1912 1913 if (cpi->cpi_maxeax >= 4 && cpi->cpi_vendor == X86_VENDOR_Intel) { 1914 1915 /* 1916 * Find the # of elements (size) returned by fn 4, and along 1917 * the way detect last level cache sharing details. 1918 */ 1919 bzero(®s, sizeof (regs)); 1920 cp = ®s; 1921 for (i = 0, max = 0; i < CPI_FN4_ECX_MAX; i++) { 1922 cp->cp_eax = 4; 1923 cp->cp_ecx = i; 1924 1925 (void) __cpuid_insn(cp); 1926 1927 if (CPI_CACHE_TYPE(cp) == 0) 1928 break; 1929 level = CPI_CACHE_LVL(cp); 1930 if (level > max) { 1931 max = level; 1932 cpi->cpi_ncpu_shr_last_cache = 1933 CPI_NTHR_SHR_CACHE(cp) + 1; 1934 } 1935 } 1936 cpi->cpi_std_4_size = size = i; 1937 1938 /* 1939 * Allocate the cpi_std_4 array. The first element 1940 * references the regs for fn 4, %ecx == 0, which 1941 * cpuid_pass2() stashed in cpi->cpi_std[4]. 1942 */ 1943 if (size > 0) { 1944 cpi->cpi_std_4 = 1945 kmem_alloc(size * sizeof (cp), KM_SLEEP); 1946 cpi->cpi_std_4[0] = &cpi->cpi_std[4]; 1947 1948 /* 1949 * Allocate storage to hold the additional regs 1950 * for function 4, %ecx == 1 .. cpi_std_4_size. 1951 * 1952 * The regs for fn 4, %ecx == 0 has already 1953 * been allocated as indicated above. 1954 */ 1955 for (i = 1; i < size; i++) { 1956 cp = cpi->cpi_std_4[i] = 1957 kmem_zalloc(sizeof (regs), KM_SLEEP); 1958 cp->cp_eax = 4; 1959 cp->cp_ecx = i; 1960 1961 (void) __cpuid_insn(cp); 1962 } 1963 } 1964 /* 1965 * Determine the number of bits needed to represent 1966 * the number of CPUs sharing the last level cache. 1967 * 1968 * Shift off that number of bits from the APIC id to 1969 * derive the cache id. 1970 */ 1971 shft = 0; 1972 for (i = 1; i < cpi->cpi_ncpu_shr_last_cache; i <<= 1) 1973 shft++; 1974 cpi->cpi_last_lvl_cacheid = cpi->cpi_apicid >> shft; 1975 } 1976 1977 /* 1978 * Now fixup the brand string 1979 */ 1980 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) { 1981 fabricate_brandstr(cpi); 1982 } else { 1983 1984 /* 1985 * If we successfully extracted a brand string from the cpuid 1986 * instruction, clean it up by removing leading spaces and 1987 * similar junk. 1988 */ 1989 if (cpi->cpi_brandstr[0]) { 1990 size_t maxlen = sizeof (cpi->cpi_brandstr); 1991 char *src, *dst; 1992 1993 dst = src = (char *)cpi->cpi_brandstr; 1994 src[maxlen - 1] = '\0'; 1995 /* 1996 * strip leading spaces 1997 */ 1998 while (*src == ' ') 1999 src++; 2000 /* 2001 * Remove any 'Genuine' or "Authentic" prefixes 2002 */ 2003 if (strncmp(src, "Genuine ", 8) == 0) 2004 src += 8; 2005 if (strncmp(src, "Authentic ", 10) == 0) 2006 src += 10; 2007 2008 /* 2009 * Now do an in-place copy. 2010 * Map (R) to (r) and (TM) to (tm). 2011 * The era of teletypes is long gone, and there's 2012 * -really- no need to shout. 2013 */ 2014 while (*src != '\0') { 2015 if (src[0] == '(') { 2016 if (strncmp(src + 1, "R)", 2) == 0) { 2017 (void) strncpy(dst, "(r)", 3); 2018 src += 3; 2019 dst += 3; 2020 continue; 2021 } 2022 if (strncmp(src + 1, "TM)", 3) == 0) { 2023 (void) strncpy(dst, "(tm)", 4); 2024 src += 4; 2025 dst += 4; 2026 continue; 2027 } 2028 } 2029 *dst++ = *src++; 2030 } 2031 *dst = '\0'; 2032 2033 /* 2034 * Finally, remove any trailing spaces 2035 */ 2036 while (--dst > cpi->cpi_brandstr) 2037 if (*dst == ' ') 2038 *dst = '\0'; 2039 else 2040 break; 2041 } else 2042 fabricate_brandstr(cpi); 2043 } 2044 cpi->cpi_pass = 3; 2045 } 2046 2047 /* 2048 * This routine is called out of bind_hwcap() much later in the life 2049 * of the kernel (post_startup()). The job of this routine is to resolve 2050 * the hardware feature support and kernel support for those features into 2051 * what we're actually going to tell applications via the aux vector. 2052 */ 2053 uint_t 2054 cpuid_pass4(cpu_t *cpu) 2055 { 2056 struct cpuid_info *cpi; 2057 uint_t hwcap_flags = 0; 2058 2059 if (cpu == NULL) 2060 cpu = CPU; 2061 cpi = cpu->cpu_m.mcpu_cpi; 2062 2063 ASSERT(cpi->cpi_pass == 3); 2064 2065 if (cpi->cpi_maxeax >= 1) { 2066 uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES]; 2067 uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES]; 2068 2069 *edx = CPI_FEATURES_EDX(cpi); 2070 *ecx = CPI_FEATURES_ECX(cpi); 2071 2072 /* 2073 * [these require explicit kernel support] 2074 */ 2075 if ((x86_feature & X86_SEP) == 0) 2076 *edx &= ~CPUID_INTC_EDX_SEP; 2077 2078 if ((x86_feature & X86_SSE) == 0) 2079 *edx &= ~(CPUID_INTC_EDX_FXSR|CPUID_INTC_EDX_SSE); 2080 if ((x86_feature & X86_SSE2) == 0) 2081 *edx &= ~CPUID_INTC_EDX_SSE2; 2082 2083 if ((x86_feature & X86_HTT) == 0) 2084 *edx &= ~CPUID_INTC_EDX_HTT; 2085 2086 if ((x86_feature & X86_SSE3) == 0) 2087 *ecx &= ~CPUID_INTC_ECX_SSE3; 2088 2089 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 2090 if ((x86_feature & X86_SSSE3) == 0) 2091 *ecx &= ~CPUID_INTC_ECX_SSSE3; 2092 if ((x86_feature & X86_SSE4_1) == 0) 2093 *ecx &= ~CPUID_INTC_ECX_SSE4_1; 2094 if ((x86_feature & X86_SSE4_2) == 0) 2095 *ecx &= ~CPUID_INTC_ECX_SSE4_2; 2096 } 2097 2098 /* 2099 * [no explicit support required beyond x87 fp context] 2100 */ 2101 if (!fpu_exists) 2102 *edx &= ~(CPUID_INTC_EDX_FPU | CPUID_INTC_EDX_MMX); 2103 2104 /* 2105 * Now map the supported feature vector to things that we 2106 * think userland will care about. 2107 */ 2108 if (*edx & CPUID_INTC_EDX_SEP) 2109 hwcap_flags |= AV_386_SEP; 2110 if (*edx & CPUID_INTC_EDX_SSE) 2111 hwcap_flags |= AV_386_FXSR | AV_386_SSE; 2112 if (*edx & CPUID_INTC_EDX_SSE2) 2113 hwcap_flags |= AV_386_SSE2; 2114 if (*ecx & CPUID_INTC_ECX_SSE3) 2115 hwcap_flags |= AV_386_SSE3; 2116 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 2117 if (*ecx & CPUID_INTC_ECX_SSSE3) 2118 hwcap_flags |= AV_386_SSSE3; 2119 if (*ecx & CPUID_INTC_ECX_SSE4_1) 2120 hwcap_flags |= AV_386_SSE4_1; 2121 if (*ecx & CPUID_INTC_ECX_SSE4_2) 2122 hwcap_flags |= AV_386_SSE4_2; 2123 if (*ecx & CPUID_INTC_ECX_MOVBE) 2124 hwcap_flags |= AV_386_MOVBE; 2125 } 2126 if (*ecx & CPUID_INTC_ECX_POPCNT) 2127 hwcap_flags |= AV_386_POPCNT; 2128 if (*edx & CPUID_INTC_EDX_FPU) 2129 hwcap_flags |= AV_386_FPU; 2130 if (*edx & CPUID_INTC_EDX_MMX) 2131 hwcap_flags |= AV_386_MMX; 2132 2133 if (*edx & CPUID_INTC_EDX_TSC) 2134 hwcap_flags |= AV_386_TSC; 2135 if (*edx & CPUID_INTC_EDX_CX8) 2136 hwcap_flags |= AV_386_CX8; 2137 if (*edx & CPUID_INTC_EDX_CMOV) 2138 hwcap_flags |= AV_386_CMOV; 2139 if (*ecx & CPUID_INTC_ECX_MON) 2140 hwcap_flags |= AV_386_MON; 2141 if (*ecx & CPUID_INTC_ECX_CX16) 2142 hwcap_flags |= AV_386_CX16; 2143 } 2144 2145 if (x86_feature & X86_HTT) 2146 hwcap_flags |= AV_386_PAUSE; 2147 2148 if (cpi->cpi_xmaxeax < 0x80000001) 2149 goto pass4_done; 2150 2151 switch (cpi->cpi_vendor) { 2152 struct cpuid_regs cp; 2153 uint32_t *edx, *ecx; 2154 2155 case X86_VENDOR_Intel: 2156 /* 2157 * Seems like Intel duplicated what we necessary 2158 * here to make the initial crop of 64-bit OS's work. 2159 * Hopefully, those are the only "extended" bits 2160 * they'll add. 2161 */ 2162 /*FALLTHROUGH*/ 2163 2164 case X86_VENDOR_AMD: 2165 edx = &cpi->cpi_support[AMD_EDX_FEATURES]; 2166 ecx = &cpi->cpi_support[AMD_ECX_FEATURES]; 2167 2168 *edx = CPI_FEATURES_XTD_EDX(cpi); 2169 *ecx = CPI_FEATURES_XTD_ECX(cpi); 2170 2171 /* 2172 * [these features require explicit kernel support] 2173 */ 2174 switch (cpi->cpi_vendor) { 2175 case X86_VENDOR_Intel: 2176 if ((x86_feature & X86_TSCP) == 0) 2177 *edx &= ~CPUID_AMD_EDX_TSCP; 2178 break; 2179 2180 case X86_VENDOR_AMD: 2181 if ((x86_feature & X86_TSCP) == 0) 2182 *edx &= ~CPUID_AMD_EDX_TSCP; 2183 if ((x86_feature & X86_SSE4A) == 0) 2184 *ecx &= ~CPUID_AMD_ECX_SSE4A; 2185 break; 2186 2187 default: 2188 break; 2189 } 2190 2191 /* 2192 * [no explicit support required beyond 2193 * x87 fp context and exception handlers] 2194 */ 2195 if (!fpu_exists) 2196 *edx &= ~(CPUID_AMD_EDX_MMXamd | 2197 CPUID_AMD_EDX_3DNow | CPUID_AMD_EDX_3DNowx); 2198 2199 if ((x86_feature & X86_NX) == 0) 2200 *edx &= ~CPUID_AMD_EDX_NX; 2201 #if !defined(__amd64) 2202 *edx &= ~CPUID_AMD_EDX_LM; 2203 #endif 2204 /* 2205 * Now map the supported feature vector to 2206 * things that we think userland will care about. 2207 */ 2208 #if defined(__amd64) 2209 if (*edx & CPUID_AMD_EDX_SYSC) 2210 hwcap_flags |= AV_386_AMD_SYSC; 2211 #endif 2212 if (*edx & CPUID_AMD_EDX_MMXamd) 2213 hwcap_flags |= AV_386_AMD_MMX; 2214 if (*edx & CPUID_AMD_EDX_3DNow) 2215 hwcap_flags |= AV_386_AMD_3DNow; 2216 if (*edx & CPUID_AMD_EDX_3DNowx) 2217 hwcap_flags |= AV_386_AMD_3DNowx; 2218 2219 switch (cpi->cpi_vendor) { 2220 case X86_VENDOR_AMD: 2221 if (*edx & CPUID_AMD_EDX_TSCP) 2222 hwcap_flags |= AV_386_TSCP; 2223 if (*ecx & CPUID_AMD_ECX_AHF64) 2224 hwcap_flags |= AV_386_AHF; 2225 if (*ecx & CPUID_AMD_ECX_SSE4A) 2226 hwcap_flags |= AV_386_AMD_SSE4A; 2227 if (*ecx & CPUID_AMD_ECX_LZCNT) 2228 hwcap_flags |= AV_386_AMD_LZCNT; 2229 break; 2230 2231 case X86_VENDOR_Intel: 2232 if (*edx & CPUID_AMD_EDX_TSCP) 2233 hwcap_flags |= AV_386_TSCP; 2234 /* 2235 * Aarrgh. 2236 * Intel uses a different bit in the same word. 2237 */ 2238 if (*ecx & CPUID_INTC_ECX_AHF64) 2239 hwcap_flags |= AV_386_AHF; 2240 break; 2241 2242 default: 2243 break; 2244 } 2245 break; 2246 2247 case X86_VENDOR_TM: 2248 cp.cp_eax = 0x80860001; 2249 (void) __cpuid_insn(&cp); 2250 cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx; 2251 break; 2252 2253 default: 2254 break; 2255 } 2256 2257 pass4_done: 2258 cpi->cpi_pass = 4; 2259 return (hwcap_flags); 2260 } 2261 2262 2263 /* 2264 * Simulate the cpuid instruction using the data we previously 2265 * captured about this CPU. We try our best to return the truth 2266 * about the hardware, independently of kernel support. 2267 */ 2268 uint32_t 2269 cpuid_insn(cpu_t *cpu, struct cpuid_regs *cp) 2270 { 2271 struct cpuid_info *cpi; 2272 struct cpuid_regs *xcp; 2273 2274 if (cpu == NULL) 2275 cpu = CPU; 2276 cpi = cpu->cpu_m.mcpu_cpi; 2277 2278 ASSERT(cpuid_checkpass(cpu, 3)); 2279 2280 /* 2281 * CPUID data is cached in two separate places: cpi_std for standard 2282 * CPUID functions, and cpi_extd for extended CPUID functions. 2283 */ 2284 if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD) 2285 xcp = &cpi->cpi_std[cp->cp_eax]; 2286 else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax && 2287 cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD) 2288 xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000]; 2289 else 2290 /* 2291 * The caller is asking for data from an input parameter which 2292 * the kernel has not cached. In this case we go fetch from 2293 * the hardware and return the data directly to the user. 2294 */ 2295 return (__cpuid_insn(cp)); 2296 2297 cp->cp_eax = xcp->cp_eax; 2298 cp->cp_ebx = xcp->cp_ebx; 2299 cp->cp_ecx = xcp->cp_ecx; 2300 cp->cp_edx = xcp->cp_edx; 2301 return (cp->cp_eax); 2302 } 2303 2304 int 2305 cpuid_checkpass(cpu_t *cpu, int pass) 2306 { 2307 return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL && 2308 cpu->cpu_m.mcpu_cpi->cpi_pass >= pass); 2309 } 2310 2311 int 2312 cpuid_getbrandstr(cpu_t *cpu, char *s, size_t n) 2313 { 2314 ASSERT(cpuid_checkpass(cpu, 3)); 2315 2316 return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr)); 2317 } 2318 2319 int 2320 cpuid_is_cmt(cpu_t *cpu) 2321 { 2322 if (cpu == NULL) 2323 cpu = CPU; 2324 2325 ASSERT(cpuid_checkpass(cpu, 1)); 2326 2327 return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0); 2328 } 2329 2330 /* 2331 * AMD and Intel both implement the 64-bit variant of the syscall 2332 * instruction (syscallq), so if there's -any- support for syscall, 2333 * cpuid currently says "yes, we support this". 2334 * 2335 * However, Intel decided to -not- implement the 32-bit variant of the 2336 * syscall instruction, so we provide a predicate to allow our caller 2337 * to test that subtlety here. 2338 * 2339 * XXPV Currently, 32-bit syscall instructions don't work via the hypervisor, 2340 * even in the case where the hardware would in fact support it. 2341 */ 2342 /*ARGSUSED*/ 2343 int 2344 cpuid_syscall32_insn(cpu_t *cpu) 2345 { 2346 ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1)); 2347 2348 #if !defined(__xpv) 2349 if (cpu == NULL) 2350 cpu = CPU; 2351 2352 /*CSTYLED*/ 2353 { 2354 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2355 2356 if (cpi->cpi_vendor == X86_VENDOR_AMD && 2357 cpi->cpi_xmaxeax >= 0x80000001 && 2358 (CPI_FEATURES_XTD_EDX(cpi) & CPUID_AMD_EDX_SYSC)) 2359 return (1); 2360 } 2361 #endif 2362 return (0); 2363 } 2364 2365 int 2366 cpuid_getidstr(cpu_t *cpu, char *s, size_t n) 2367 { 2368 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2369 2370 static const char fmt[] = 2371 "x86 (%s %X family %d model %d step %d clock %d MHz)"; 2372 static const char fmt_ht[] = 2373 "x86 (chipid 0x%x %s %X family %d model %d step %d clock %d MHz)"; 2374 2375 ASSERT(cpuid_checkpass(cpu, 1)); 2376 2377 if (cpuid_is_cmt(cpu)) 2378 return (snprintf(s, n, fmt_ht, cpi->cpi_chipid, 2379 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, 2380 cpi->cpi_family, cpi->cpi_model, 2381 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 2382 return (snprintf(s, n, fmt, 2383 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, 2384 cpi->cpi_family, cpi->cpi_model, 2385 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 2386 } 2387 2388 const char * 2389 cpuid_getvendorstr(cpu_t *cpu) 2390 { 2391 ASSERT(cpuid_checkpass(cpu, 1)); 2392 return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr); 2393 } 2394 2395 uint_t 2396 cpuid_getvendor(cpu_t *cpu) 2397 { 2398 ASSERT(cpuid_checkpass(cpu, 1)); 2399 return (cpu->cpu_m.mcpu_cpi->cpi_vendor); 2400 } 2401 2402 uint_t 2403 cpuid_getfamily(cpu_t *cpu) 2404 { 2405 ASSERT(cpuid_checkpass(cpu, 1)); 2406 return (cpu->cpu_m.mcpu_cpi->cpi_family); 2407 } 2408 2409 uint_t 2410 cpuid_getmodel(cpu_t *cpu) 2411 { 2412 ASSERT(cpuid_checkpass(cpu, 1)); 2413 return (cpu->cpu_m.mcpu_cpi->cpi_model); 2414 } 2415 2416 uint_t 2417 cpuid_get_ncpu_per_chip(cpu_t *cpu) 2418 { 2419 ASSERT(cpuid_checkpass(cpu, 1)); 2420 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip); 2421 } 2422 2423 uint_t 2424 cpuid_get_ncore_per_chip(cpu_t *cpu) 2425 { 2426 ASSERT(cpuid_checkpass(cpu, 1)); 2427 return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip); 2428 } 2429 2430 uint_t 2431 cpuid_get_ncpu_sharing_last_cache(cpu_t *cpu) 2432 { 2433 ASSERT(cpuid_checkpass(cpu, 2)); 2434 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_shr_last_cache); 2435 } 2436 2437 id_t 2438 cpuid_get_last_lvl_cacheid(cpu_t *cpu) 2439 { 2440 ASSERT(cpuid_checkpass(cpu, 2)); 2441 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid); 2442 } 2443 2444 uint_t 2445 cpuid_getstep(cpu_t *cpu) 2446 { 2447 ASSERT(cpuid_checkpass(cpu, 1)); 2448 return (cpu->cpu_m.mcpu_cpi->cpi_step); 2449 } 2450 2451 uint_t 2452 cpuid_getsig(struct cpu *cpu) 2453 { 2454 ASSERT(cpuid_checkpass(cpu, 1)); 2455 return (cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_eax); 2456 } 2457 2458 uint32_t 2459 cpuid_getchiprev(struct cpu *cpu) 2460 { 2461 ASSERT(cpuid_checkpass(cpu, 1)); 2462 return (cpu->cpu_m.mcpu_cpi->cpi_chiprev); 2463 } 2464 2465 const char * 2466 cpuid_getchiprevstr(struct cpu *cpu) 2467 { 2468 ASSERT(cpuid_checkpass(cpu, 1)); 2469 return (cpu->cpu_m.mcpu_cpi->cpi_chiprevstr); 2470 } 2471 2472 uint32_t 2473 cpuid_getsockettype(struct cpu *cpu) 2474 { 2475 ASSERT(cpuid_checkpass(cpu, 1)); 2476 return (cpu->cpu_m.mcpu_cpi->cpi_socket); 2477 } 2478 2479 int 2480 cpuid_get_chipid(cpu_t *cpu) 2481 { 2482 ASSERT(cpuid_checkpass(cpu, 1)); 2483 2484 if (cpuid_is_cmt(cpu)) 2485 return (cpu->cpu_m.mcpu_cpi->cpi_chipid); 2486 return (cpu->cpu_id); 2487 } 2488 2489 id_t 2490 cpuid_get_coreid(cpu_t *cpu) 2491 { 2492 ASSERT(cpuid_checkpass(cpu, 1)); 2493 return (cpu->cpu_m.mcpu_cpi->cpi_coreid); 2494 } 2495 2496 int 2497 cpuid_get_pkgcoreid(cpu_t *cpu) 2498 { 2499 ASSERT(cpuid_checkpass(cpu, 1)); 2500 return (cpu->cpu_m.mcpu_cpi->cpi_pkgcoreid); 2501 } 2502 2503 int 2504 cpuid_get_clogid(cpu_t *cpu) 2505 { 2506 ASSERT(cpuid_checkpass(cpu, 1)); 2507 return (cpu->cpu_m.mcpu_cpi->cpi_clogid); 2508 } 2509 2510 void 2511 cpuid_get_addrsize(cpu_t *cpu, uint_t *pabits, uint_t *vabits) 2512 { 2513 struct cpuid_info *cpi; 2514 2515 if (cpu == NULL) 2516 cpu = CPU; 2517 cpi = cpu->cpu_m.mcpu_cpi; 2518 2519 ASSERT(cpuid_checkpass(cpu, 1)); 2520 2521 if (pabits) 2522 *pabits = cpi->cpi_pabits; 2523 if (vabits) 2524 *vabits = cpi->cpi_vabits; 2525 } 2526 2527 /* 2528 * Returns the number of data TLB entries for a corresponding 2529 * pagesize. If it can't be computed, or isn't known, the 2530 * routine returns zero. If you ask about an architecturally 2531 * impossible pagesize, the routine will panic (so that the 2532 * hat implementor knows that things are inconsistent.) 2533 */ 2534 uint_t 2535 cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize) 2536 { 2537 struct cpuid_info *cpi; 2538 uint_t dtlb_nent = 0; 2539 2540 if (cpu == NULL) 2541 cpu = CPU; 2542 cpi = cpu->cpu_m.mcpu_cpi; 2543 2544 ASSERT(cpuid_checkpass(cpu, 1)); 2545 2546 /* 2547 * Check the L2 TLB info 2548 */ 2549 if (cpi->cpi_xmaxeax >= 0x80000006) { 2550 struct cpuid_regs *cp = &cpi->cpi_extd[6]; 2551 2552 switch (pagesize) { 2553 2554 case 4 * 1024: 2555 /* 2556 * All zero in the top 16 bits of the register 2557 * indicates a unified TLB. Size is in low 16 bits. 2558 */ 2559 if ((cp->cp_ebx & 0xffff0000) == 0) 2560 dtlb_nent = cp->cp_ebx & 0x0000ffff; 2561 else 2562 dtlb_nent = BITX(cp->cp_ebx, 27, 16); 2563 break; 2564 2565 case 2 * 1024 * 1024: 2566 if ((cp->cp_eax & 0xffff0000) == 0) 2567 dtlb_nent = cp->cp_eax & 0x0000ffff; 2568 else 2569 dtlb_nent = BITX(cp->cp_eax, 27, 16); 2570 break; 2571 2572 default: 2573 panic("unknown L2 pagesize"); 2574 /*NOTREACHED*/ 2575 } 2576 } 2577 2578 if (dtlb_nent != 0) 2579 return (dtlb_nent); 2580 2581 /* 2582 * No L2 TLB support for this size, try L1. 2583 */ 2584 if (cpi->cpi_xmaxeax >= 0x80000005) { 2585 struct cpuid_regs *cp = &cpi->cpi_extd[5]; 2586 2587 switch (pagesize) { 2588 case 4 * 1024: 2589 dtlb_nent = BITX(cp->cp_ebx, 23, 16); 2590 break; 2591 case 2 * 1024 * 1024: 2592 dtlb_nent = BITX(cp->cp_eax, 23, 16); 2593 break; 2594 default: 2595 panic("unknown L1 d-TLB pagesize"); 2596 /*NOTREACHED*/ 2597 } 2598 } 2599 2600 return (dtlb_nent); 2601 } 2602 2603 /* 2604 * Return 0 if the erratum is not present or not applicable, positive 2605 * if it is, and negative if the status of the erratum is unknown. 2606 * 2607 * See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm) 2608 * Processors" #25759, Rev 3.57, August 2005 2609 */ 2610 int 2611 cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum) 2612 { 2613 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2614 uint_t eax; 2615 2616 /* 2617 * Bail out if this CPU isn't an AMD CPU, or if it's 2618 * a legacy (32-bit) AMD CPU. 2619 */ 2620 if (cpi->cpi_vendor != X86_VENDOR_AMD || 2621 cpi->cpi_family == 4 || cpi->cpi_family == 5 || 2622 cpi->cpi_family == 6) 2623 2624 return (0); 2625 2626 eax = cpi->cpi_std[1].cp_eax; 2627 2628 #define SH_B0(eax) (eax == 0xf40 || eax == 0xf50) 2629 #define SH_B3(eax) (eax == 0xf51) 2630 #define B(eax) (SH_B0(eax) || SH_B3(eax)) 2631 2632 #define SH_C0(eax) (eax == 0xf48 || eax == 0xf58) 2633 2634 #define SH_CG(eax) (eax == 0xf4a || eax == 0xf5a || eax == 0xf7a) 2635 #define DH_CG(eax) (eax == 0xfc0 || eax == 0xfe0 || eax == 0xff0) 2636 #define CH_CG(eax) (eax == 0xf82 || eax == 0xfb2) 2637 #define CG(eax) (SH_CG(eax) || DH_CG(eax) || CH_CG(eax)) 2638 2639 #define SH_D0(eax) (eax == 0x10f40 || eax == 0x10f50 || eax == 0x10f70) 2640 #define DH_D0(eax) (eax == 0x10fc0 || eax == 0x10ff0) 2641 #define CH_D0(eax) (eax == 0x10f80 || eax == 0x10fb0) 2642 #define D0(eax) (SH_D0(eax) || DH_D0(eax) || CH_D0(eax)) 2643 2644 #define SH_E0(eax) (eax == 0x20f50 || eax == 0x20f40 || eax == 0x20f70) 2645 #define JH_E1(eax) (eax == 0x20f10) /* JH8_E0 had 0x20f30 */ 2646 #define DH_E3(eax) (eax == 0x20fc0 || eax == 0x20ff0) 2647 #define SH_E4(eax) (eax == 0x20f51 || eax == 0x20f71) 2648 #define BH_E4(eax) (eax == 0x20fb1) 2649 #define SH_E5(eax) (eax == 0x20f42) 2650 #define DH_E6(eax) (eax == 0x20ff2 || eax == 0x20fc2) 2651 #define JH_E6(eax) (eax == 0x20f12 || eax == 0x20f32) 2652 #define EX(eax) (SH_E0(eax) || JH_E1(eax) || DH_E3(eax) || \ 2653 SH_E4(eax) || BH_E4(eax) || SH_E5(eax) || \ 2654 DH_E6(eax) || JH_E6(eax)) 2655 2656 #define DR_AX(eax) (eax == 0x100f00 || eax == 0x100f01 || eax == 0x100f02) 2657 #define DR_B0(eax) (eax == 0x100f20) 2658 #define DR_B1(eax) (eax == 0x100f21) 2659 #define DR_BA(eax) (eax == 0x100f2a) 2660 #define DR_B2(eax) (eax == 0x100f22) 2661 #define DR_B3(eax) (eax == 0x100f23) 2662 #define RB_C0(eax) (eax == 0x100f40) 2663 2664 switch (erratum) { 2665 case 1: 2666 return (cpi->cpi_family < 0x10); 2667 case 51: /* what does the asterisk mean? */ 2668 return (B(eax) || SH_C0(eax) || CG(eax)); 2669 case 52: 2670 return (B(eax)); 2671 case 57: 2672 return (cpi->cpi_family <= 0x11); 2673 case 58: 2674 return (B(eax)); 2675 case 60: 2676 return (cpi->cpi_family <= 0x11); 2677 case 61: 2678 case 62: 2679 case 63: 2680 case 64: 2681 case 65: 2682 case 66: 2683 case 68: 2684 case 69: 2685 case 70: 2686 case 71: 2687 return (B(eax)); 2688 case 72: 2689 return (SH_B0(eax)); 2690 case 74: 2691 return (B(eax)); 2692 case 75: 2693 return (cpi->cpi_family < 0x10); 2694 case 76: 2695 return (B(eax)); 2696 case 77: 2697 return (cpi->cpi_family <= 0x11); 2698 case 78: 2699 return (B(eax) || SH_C0(eax)); 2700 case 79: 2701 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2702 case 80: 2703 case 81: 2704 case 82: 2705 return (B(eax)); 2706 case 83: 2707 return (B(eax) || SH_C0(eax) || CG(eax)); 2708 case 85: 2709 return (cpi->cpi_family < 0x10); 2710 case 86: 2711 return (SH_C0(eax) || CG(eax)); 2712 case 88: 2713 #if !defined(__amd64) 2714 return (0); 2715 #else 2716 return (B(eax) || SH_C0(eax)); 2717 #endif 2718 case 89: 2719 return (cpi->cpi_family < 0x10); 2720 case 90: 2721 return (B(eax) || SH_C0(eax) || CG(eax)); 2722 case 91: 2723 case 92: 2724 return (B(eax) || SH_C0(eax)); 2725 case 93: 2726 return (SH_C0(eax)); 2727 case 94: 2728 return (B(eax) || SH_C0(eax) || CG(eax)); 2729 case 95: 2730 #if !defined(__amd64) 2731 return (0); 2732 #else 2733 return (B(eax) || SH_C0(eax)); 2734 #endif 2735 case 96: 2736 return (B(eax) || SH_C0(eax) || CG(eax)); 2737 case 97: 2738 case 98: 2739 return (SH_C0(eax) || CG(eax)); 2740 case 99: 2741 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2742 case 100: 2743 return (B(eax) || SH_C0(eax)); 2744 case 101: 2745 case 103: 2746 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2747 case 104: 2748 return (SH_C0(eax) || CG(eax) || D0(eax)); 2749 case 105: 2750 case 106: 2751 case 107: 2752 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2753 case 108: 2754 return (DH_CG(eax)); 2755 case 109: 2756 return (SH_C0(eax) || CG(eax) || D0(eax)); 2757 case 110: 2758 return (D0(eax) || EX(eax)); 2759 case 111: 2760 return (CG(eax)); 2761 case 112: 2762 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2763 case 113: 2764 return (eax == 0x20fc0); 2765 case 114: 2766 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 2767 case 115: 2768 return (SH_E0(eax) || JH_E1(eax)); 2769 case 116: 2770 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 2771 case 117: 2772 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2773 case 118: 2774 return (SH_E0(eax) || JH_E1(eax) || SH_E4(eax) || BH_E4(eax) || 2775 JH_E6(eax)); 2776 case 121: 2777 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2778 case 122: 2779 return (cpi->cpi_family < 0x10 || cpi->cpi_family == 0x11); 2780 case 123: 2781 return (JH_E1(eax) || BH_E4(eax) || JH_E6(eax)); 2782 case 131: 2783 return (cpi->cpi_family < 0x10); 2784 case 6336786: 2785 /* 2786 * Test for AdvPowerMgmtInfo.TscPStateInvariant 2787 * if this is a K8 family or newer processor 2788 */ 2789 if (CPI_FAMILY(cpi) == 0xf) { 2790 struct cpuid_regs regs; 2791 regs.cp_eax = 0x80000007; 2792 (void) __cpuid_insn(®s); 2793 return (!(regs.cp_edx & 0x100)); 2794 } 2795 return (0); 2796 case 6323525: 2797 return (((((eax >> 12) & 0xff00) + (eax & 0xf00)) | 2798 (((eax >> 4) & 0xf) | ((eax >> 12) & 0xf0))) < 0xf40); 2799 2800 case 6671130: 2801 /* 2802 * check for processors (pre-Shanghai) that do not provide 2803 * optimal management of 1gb ptes in its tlb. 2804 */ 2805 return (cpi->cpi_family == 0x10 && cpi->cpi_model < 4); 2806 2807 case 298: 2808 return (DR_AX(eax) || DR_B0(eax) || DR_B1(eax) || DR_BA(eax) || 2809 DR_B2(eax) || RB_C0(eax)); 2810 2811 default: 2812 return (-1); 2813 2814 } 2815 } 2816 2817 /* 2818 * Determine if specified erratum is present via OSVW (OS Visible Workaround). 2819 * Return 1 if erratum is present, 0 if not present and -1 if indeterminate. 2820 */ 2821 int 2822 osvw_opteron_erratum(cpu_t *cpu, uint_t erratum) 2823 { 2824 struct cpuid_info *cpi; 2825 uint_t osvwid; 2826 static int osvwfeature = -1; 2827 uint64_t osvwlength; 2828 2829 2830 cpi = cpu->cpu_m.mcpu_cpi; 2831 2832 /* confirm OSVW supported */ 2833 if (osvwfeature == -1) { 2834 osvwfeature = cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW; 2835 } else { 2836 /* assert that osvw feature setting is consistent on all cpus */ 2837 ASSERT(osvwfeature == 2838 (cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW)); 2839 } 2840 if (!osvwfeature) 2841 return (-1); 2842 2843 osvwlength = rdmsr(MSR_AMD_OSVW_ID_LEN) & OSVW_ID_LEN_MASK; 2844 2845 switch (erratum) { 2846 case 298: /* osvwid is 0 */ 2847 osvwid = 0; 2848 if (osvwlength <= (uint64_t)osvwid) { 2849 /* osvwid 0 is unknown */ 2850 return (-1); 2851 } 2852 2853 /* 2854 * Check the OSVW STATUS MSR to determine the state 2855 * of the erratum where: 2856 * 0 - fixed by HW 2857 * 1 - BIOS has applied the workaround when BIOS 2858 * workaround is available. (Or for other errata, 2859 * OS workaround is required.) 2860 * For a value of 1, caller will confirm that the 2861 * erratum 298 workaround has indeed been applied by BIOS. 2862 * 2863 * A 1 may be set in cpus that have a HW fix 2864 * in a mixed cpu system. Regarding erratum 298: 2865 * In a multiprocessor platform, the workaround above 2866 * should be applied to all processors regardless of 2867 * silicon revision when an affected processor is 2868 * present. 2869 */ 2870 2871 return (rdmsr(MSR_AMD_OSVW_STATUS + 2872 (osvwid / OSVW_ID_CNT_PER_MSR)) & 2873 (1ULL << (osvwid % OSVW_ID_CNT_PER_MSR))); 2874 2875 default: 2876 return (-1); 2877 } 2878 } 2879 2880 static const char assoc_str[] = "associativity"; 2881 static const char line_str[] = "line-size"; 2882 static const char size_str[] = "size"; 2883 2884 static void 2885 add_cache_prop(dev_info_t *devi, const char *label, const char *type, 2886 uint32_t val) 2887 { 2888 char buf[128]; 2889 2890 /* 2891 * ndi_prop_update_int() is used because it is desirable for 2892 * DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set. 2893 */ 2894 if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf)) 2895 (void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val); 2896 } 2897 2898 /* 2899 * Intel-style cache/tlb description 2900 * 2901 * Standard cpuid level 2 gives a randomly ordered 2902 * selection of tags that index into a table that describes 2903 * cache and tlb properties. 2904 */ 2905 2906 static const char l1_icache_str[] = "l1-icache"; 2907 static const char l1_dcache_str[] = "l1-dcache"; 2908 static const char l2_cache_str[] = "l2-cache"; 2909 static const char l3_cache_str[] = "l3-cache"; 2910 static const char itlb4k_str[] = "itlb-4K"; 2911 static const char dtlb4k_str[] = "dtlb-4K"; 2912 static const char itlb2M_str[] = "itlb-2M"; 2913 static const char itlb4M_str[] = "itlb-4M"; 2914 static const char dtlb4M_str[] = "dtlb-4M"; 2915 static const char dtlb24_str[] = "dtlb0-2M-4M"; 2916 static const char itlb424_str[] = "itlb-4K-2M-4M"; 2917 static const char itlb24_str[] = "itlb-2M-4M"; 2918 static const char dtlb44_str[] = "dtlb-4K-4M"; 2919 static const char sl1_dcache_str[] = "sectored-l1-dcache"; 2920 static const char sl2_cache_str[] = "sectored-l2-cache"; 2921 static const char itrace_str[] = "itrace-cache"; 2922 static const char sl3_cache_str[] = "sectored-l3-cache"; 2923 static const char sh_l2_tlb4k_str[] = "shared-l2-tlb-4k"; 2924 2925 static const struct cachetab { 2926 uint8_t ct_code; 2927 uint8_t ct_assoc; 2928 uint16_t ct_line_size; 2929 size_t ct_size; 2930 const char *ct_label; 2931 } intel_ctab[] = { 2932 /* 2933 * maintain descending order! 2934 * 2935 * Codes ignored - Reason 2936 * ---------------------- 2937 * 40H - intel_cpuid_4_cache_info() disambiguates l2/l3 cache 2938 * f0H/f1H - Currently we do not interpret prefetch size by design 2939 */ 2940 { 0xe4, 16, 64, 8*1024*1024, l3_cache_str}, 2941 { 0xe3, 16, 64, 4*1024*1024, l3_cache_str}, 2942 { 0xe2, 16, 64, 2*1024*1024, l3_cache_str}, 2943 { 0xde, 12, 64, 6*1024*1024, l3_cache_str}, 2944 { 0xdd, 12, 64, 3*1024*1024, l3_cache_str}, 2945 { 0xdc, 12, 64, ((1*1024*1024)+(512*1024)), l3_cache_str}, 2946 { 0xd8, 8, 64, 4*1024*1024, l3_cache_str}, 2947 { 0xd7, 8, 64, 2*1024*1024, l3_cache_str}, 2948 { 0xd6, 8, 64, 1*1024*1024, l3_cache_str}, 2949 { 0xd2, 4, 64, 2*1024*1024, l3_cache_str}, 2950 { 0xd1, 4, 64, 1*1024*1024, l3_cache_str}, 2951 { 0xd0, 4, 64, 512*1024, l3_cache_str}, 2952 { 0xca, 4, 0, 512, sh_l2_tlb4k_str}, 2953 { 0xc0, 4, 0, 8, dtlb44_str }, 2954 { 0xba, 4, 0, 64, dtlb4k_str }, 2955 { 0xb4, 4, 0, 256, dtlb4k_str }, 2956 { 0xb3, 4, 0, 128, dtlb4k_str }, 2957 { 0xb2, 4, 0, 64, itlb4k_str }, 2958 { 0xb0, 4, 0, 128, itlb4k_str }, 2959 { 0x87, 8, 64, 1024*1024, l2_cache_str}, 2960 { 0x86, 4, 64, 512*1024, l2_cache_str}, 2961 { 0x85, 8, 32, 2*1024*1024, l2_cache_str}, 2962 { 0x84, 8, 32, 1024*1024, l2_cache_str}, 2963 { 0x83, 8, 32, 512*1024, l2_cache_str}, 2964 { 0x82, 8, 32, 256*1024, l2_cache_str}, 2965 { 0x80, 8, 64, 512*1024, l2_cache_str}, 2966 { 0x7f, 2, 64, 512*1024, l2_cache_str}, 2967 { 0x7d, 8, 64, 2*1024*1024, sl2_cache_str}, 2968 { 0x7c, 8, 64, 1024*1024, sl2_cache_str}, 2969 { 0x7b, 8, 64, 512*1024, sl2_cache_str}, 2970 { 0x7a, 8, 64, 256*1024, sl2_cache_str}, 2971 { 0x79, 8, 64, 128*1024, sl2_cache_str}, 2972 { 0x78, 8, 64, 1024*1024, l2_cache_str}, 2973 { 0x73, 8, 0, 64*1024, itrace_str}, 2974 { 0x72, 8, 0, 32*1024, itrace_str}, 2975 { 0x71, 8, 0, 16*1024, itrace_str}, 2976 { 0x70, 8, 0, 12*1024, itrace_str}, 2977 { 0x68, 4, 64, 32*1024, sl1_dcache_str}, 2978 { 0x67, 4, 64, 16*1024, sl1_dcache_str}, 2979 { 0x66, 4, 64, 8*1024, sl1_dcache_str}, 2980 { 0x60, 8, 64, 16*1024, sl1_dcache_str}, 2981 { 0x5d, 0, 0, 256, dtlb44_str}, 2982 { 0x5c, 0, 0, 128, dtlb44_str}, 2983 { 0x5b, 0, 0, 64, dtlb44_str}, 2984 { 0x5a, 4, 0, 32, dtlb24_str}, 2985 { 0x59, 0, 0, 16, dtlb4k_str}, 2986 { 0x57, 4, 0, 16, dtlb4k_str}, 2987 { 0x56, 4, 0, 16, dtlb4M_str}, 2988 { 0x55, 0, 0, 7, itlb24_str}, 2989 { 0x52, 0, 0, 256, itlb424_str}, 2990 { 0x51, 0, 0, 128, itlb424_str}, 2991 { 0x50, 0, 0, 64, itlb424_str}, 2992 { 0x4f, 0, 0, 32, itlb4k_str}, 2993 { 0x4e, 24, 64, 6*1024*1024, l2_cache_str}, 2994 { 0x4d, 16, 64, 16*1024*1024, l3_cache_str}, 2995 { 0x4c, 12, 64, 12*1024*1024, l3_cache_str}, 2996 { 0x4b, 16, 64, 8*1024*1024, l3_cache_str}, 2997 { 0x4a, 12, 64, 6*1024*1024, l3_cache_str}, 2998 { 0x49, 16, 64, 4*1024*1024, l3_cache_str}, 2999 { 0x48, 12, 64, 3*1024*1024, l2_cache_str}, 3000 { 0x47, 8, 64, 8*1024*1024, l3_cache_str}, 3001 { 0x46, 4, 64, 4*1024*1024, l3_cache_str}, 3002 { 0x45, 4, 32, 2*1024*1024, l2_cache_str}, 3003 { 0x44, 4, 32, 1024*1024, l2_cache_str}, 3004 { 0x43, 4, 32, 512*1024, l2_cache_str}, 3005 { 0x42, 4, 32, 256*1024, l2_cache_str}, 3006 { 0x41, 4, 32, 128*1024, l2_cache_str}, 3007 { 0x3e, 4, 64, 512*1024, sl2_cache_str}, 3008 { 0x3d, 6, 64, 384*1024, sl2_cache_str}, 3009 { 0x3c, 4, 64, 256*1024, sl2_cache_str}, 3010 { 0x3b, 2, 64, 128*1024, sl2_cache_str}, 3011 { 0x3a, 6, 64, 192*1024, sl2_cache_str}, 3012 { 0x39, 4, 64, 128*1024, sl2_cache_str}, 3013 { 0x30, 8, 64, 32*1024, l1_icache_str}, 3014 { 0x2c, 8, 64, 32*1024, l1_dcache_str}, 3015 { 0x29, 8, 64, 4096*1024, sl3_cache_str}, 3016 { 0x25, 8, 64, 2048*1024, sl3_cache_str}, 3017 { 0x23, 8, 64, 1024*1024, sl3_cache_str}, 3018 { 0x22, 4, 64, 512*1024, sl3_cache_str}, 3019 { 0x0e, 6, 64, 24*1024, l1_dcache_str}, 3020 { 0x0d, 4, 32, 16*1024, l1_dcache_str}, 3021 { 0x0c, 4, 32, 16*1024, l1_dcache_str}, 3022 { 0x0b, 4, 0, 4, itlb4M_str}, 3023 { 0x0a, 2, 32, 8*1024, l1_dcache_str}, 3024 { 0x08, 4, 32, 16*1024, l1_icache_str}, 3025 { 0x06, 4, 32, 8*1024, l1_icache_str}, 3026 { 0x05, 4, 0, 32, dtlb4M_str}, 3027 { 0x04, 4, 0, 8, dtlb4M_str}, 3028 { 0x03, 4, 0, 64, dtlb4k_str}, 3029 { 0x02, 4, 0, 2, itlb4M_str}, 3030 { 0x01, 4, 0, 32, itlb4k_str}, 3031 { 0 } 3032 }; 3033 3034 static const struct cachetab cyrix_ctab[] = { 3035 { 0x70, 4, 0, 32, "tlb-4K" }, 3036 { 0x80, 4, 16, 16*1024, "l1-cache" }, 3037 { 0 } 3038 }; 3039 3040 /* 3041 * Search a cache table for a matching entry 3042 */ 3043 static const struct cachetab * 3044 find_cacheent(const struct cachetab *ct, uint_t code) 3045 { 3046 if (code != 0) { 3047 for (; ct->ct_code != 0; ct++) 3048 if (ct->ct_code <= code) 3049 break; 3050 if (ct->ct_code == code) 3051 return (ct); 3052 } 3053 return (NULL); 3054 } 3055 3056 /* 3057 * Populate cachetab entry with L2 or L3 cache-information using 3058 * cpuid function 4. This function is called from intel_walk_cacheinfo() 3059 * when descriptor 0x49 is encountered. It returns 0 if no such cache 3060 * information is found. 3061 */ 3062 static int 3063 intel_cpuid_4_cache_info(struct cachetab *ct, struct cpuid_info *cpi) 3064 { 3065 uint32_t level, i; 3066 int ret = 0; 3067 3068 for (i = 0; i < cpi->cpi_std_4_size; i++) { 3069 level = CPI_CACHE_LVL(cpi->cpi_std_4[i]); 3070 3071 if (level == 2 || level == 3) { 3072 ct->ct_assoc = CPI_CACHE_WAYS(cpi->cpi_std_4[i]) + 1; 3073 ct->ct_line_size = 3074 CPI_CACHE_COH_LN_SZ(cpi->cpi_std_4[i]) + 1; 3075 ct->ct_size = ct->ct_assoc * 3076 (CPI_CACHE_PARTS(cpi->cpi_std_4[i]) + 1) * 3077 ct->ct_line_size * 3078 (cpi->cpi_std_4[i]->cp_ecx + 1); 3079 3080 if (level == 2) { 3081 ct->ct_label = l2_cache_str; 3082 } else if (level == 3) { 3083 ct->ct_label = l3_cache_str; 3084 } 3085 ret = 1; 3086 } 3087 } 3088 3089 return (ret); 3090 } 3091 3092 /* 3093 * Walk the cacheinfo descriptor, applying 'func' to every valid element 3094 * The walk is terminated if the walker returns non-zero. 3095 */ 3096 static void 3097 intel_walk_cacheinfo(struct cpuid_info *cpi, 3098 void *arg, int (*func)(void *, const struct cachetab *)) 3099 { 3100 const struct cachetab *ct; 3101 struct cachetab des_49_ct, des_b1_ct; 3102 uint8_t *dp; 3103 int i; 3104 3105 if ((dp = cpi->cpi_cacheinfo) == NULL) 3106 return; 3107 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { 3108 /* 3109 * For overloaded descriptor 0x49 we use cpuid function 4 3110 * if supported by the current processor, to create 3111 * cache information. 3112 * For overloaded descriptor 0xb1 we use X86_PAE flag 3113 * to disambiguate the cache information. 3114 */ 3115 if (*dp == 0x49 && cpi->cpi_maxeax >= 0x4 && 3116 intel_cpuid_4_cache_info(&des_49_ct, cpi) == 1) { 3117 ct = &des_49_ct; 3118 } else if (*dp == 0xb1) { 3119 des_b1_ct.ct_code = 0xb1; 3120 des_b1_ct.ct_assoc = 4; 3121 des_b1_ct.ct_line_size = 0; 3122 if (x86_feature & X86_PAE) { 3123 des_b1_ct.ct_size = 8; 3124 des_b1_ct.ct_label = itlb2M_str; 3125 } else { 3126 des_b1_ct.ct_size = 4; 3127 des_b1_ct.ct_label = itlb4M_str; 3128 } 3129 ct = &des_b1_ct; 3130 } else { 3131 if ((ct = find_cacheent(intel_ctab, *dp)) == NULL) { 3132 continue; 3133 } 3134 } 3135 3136 if (func(arg, ct) != 0) { 3137 break; 3138 } 3139 } 3140 } 3141 3142 /* 3143 * (Like the Intel one, except for Cyrix CPUs) 3144 */ 3145 static void 3146 cyrix_walk_cacheinfo(struct cpuid_info *cpi, 3147 void *arg, int (*func)(void *, const struct cachetab *)) 3148 { 3149 const struct cachetab *ct; 3150 uint8_t *dp; 3151 int i; 3152 3153 if ((dp = cpi->cpi_cacheinfo) == NULL) 3154 return; 3155 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { 3156 /* 3157 * Search Cyrix-specific descriptor table first .. 3158 */ 3159 if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) { 3160 if (func(arg, ct) != 0) 3161 break; 3162 continue; 3163 } 3164 /* 3165 * .. else fall back to the Intel one 3166 */ 3167 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { 3168 if (func(arg, ct) != 0) 3169 break; 3170 continue; 3171 } 3172 } 3173 } 3174 3175 /* 3176 * A cacheinfo walker that adds associativity, line-size, and size properties 3177 * to the devinfo node it is passed as an argument. 3178 */ 3179 static int 3180 add_cacheent_props(void *arg, const struct cachetab *ct) 3181 { 3182 dev_info_t *devi = arg; 3183 3184 add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc); 3185 if (ct->ct_line_size != 0) 3186 add_cache_prop(devi, ct->ct_label, line_str, 3187 ct->ct_line_size); 3188 add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size); 3189 return (0); 3190 } 3191 3192 3193 static const char fully_assoc[] = "fully-associative?"; 3194 3195 /* 3196 * AMD style cache/tlb description 3197 * 3198 * Extended functions 5 and 6 directly describe properties of 3199 * tlbs and various cache levels. 3200 */ 3201 static void 3202 add_amd_assoc(dev_info_t *devi, const char *label, uint_t assoc) 3203 { 3204 switch (assoc) { 3205 case 0: /* reserved; ignore */ 3206 break; 3207 default: 3208 add_cache_prop(devi, label, assoc_str, assoc); 3209 break; 3210 case 0xff: 3211 add_cache_prop(devi, label, fully_assoc, 1); 3212 break; 3213 } 3214 } 3215 3216 static void 3217 add_amd_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 3218 { 3219 if (size == 0) 3220 return; 3221 add_cache_prop(devi, label, size_str, size); 3222 add_amd_assoc(devi, label, assoc); 3223 } 3224 3225 static void 3226 add_amd_cache(dev_info_t *devi, const char *label, 3227 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 3228 { 3229 if (size == 0 || line_size == 0) 3230 return; 3231 add_amd_assoc(devi, label, assoc); 3232 /* 3233 * Most AMD parts have a sectored cache. Multiple cache lines are 3234 * associated with each tag. A sector consists of all cache lines 3235 * associated with a tag. For example, the AMD K6-III has a sector 3236 * size of 2 cache lines per tag. 3237 */ 3238 if (lines_per_tag != 0) 3239 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 3240 add_cache_prop(devi, label, line_str, line_size); 3241 add_cache_prop(devi, label, size_str, size * 1024); 3242 } 3243 3244 static void 3245 add_amd_l2_assoc(dev_info_t *devi, const char *label, uint_t assoc) 3246 { 3247 switch (assoc) { 3248 case 0: /* off */ 3249 break; 3250 case 1: 3251 case 2: 3252 case 4: 3253 add_cache_prop(devi, label, assoc_str, assoc); 3254 break; 3255 case 6: 3256 add_cache_prop(devi, label, assoc_str, 8); 3257 break; 3258 case 8: 3259 add_cache_prop(devi, label, assoc_str, 16); 3260 break; 3261 case 0xf: 3262 add_cache_prop(devi, label, fully_assoc, 1); 3263 break; 3264 default: /* reserved; ignore */ 3265 break; 3266 } 3267 } 3268 3269 static void 3270 add_amd_l2_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 3271 { 3272 if (size == 0 || assoc == 0) 3273 return; 3274 add_amd_l2_assoc(devi, label, assoc); 3275 add_cache_prop(devi, label, size_str, size); 3276 } 3277 3278 static void 3279 add_amd_l2_cache(dev_info_t *devi, const char *label, 3280 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 3281 { 3282 if (size == 0 || assoc == 0 || line_size == 0) 3283 return; 3284 add_amd_l2_assoc(devi, label, assoc); 3285 if (lines_per_tag != 0) 3286 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 3287 add_cache_prop(devi, label, line_str, line_size); 3288 add_cache_prop(devi, label, size_str, size * 1024); 3289 } 3290 3291 static void 3292 amd_cache_info(struct cpuid_info *cpi, dev_info_t *devi) 3293 { 3294 struct cpuid_regs *cp; 3295 3296 if (cpi->cpi_xmaxeax < 0x80000005) 3297 return; 3298 cp = &cpi->cpi_extd[5]; 3299 3300 /* 3301 * 4M/2M L1 TLB configuration 3302 * 3303 * We report the size for 2M pages because AMD uses two 3304 * TLB entries for one 4M page. 3305 */ 3306 add_amd_tlb(devi, "dtlb-2M", 3307 BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16)); 3308 add_amd_tlb(devi, "itlb-2M", 3309 BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0)); 3310 3311 /* 3312 * 4K L1 TLB configuration 3313 */ 3314 3315 switch (cpi->cpi_vendor) { 3316 uint_t nentries; 3317 case X86_VENDOR_TM: 3318 if (cpi->cpi_family >= 5) { 3319 /* 3320 * Crusoe processors have 256 TLB entries, but 3321 * cpuid data format constrains them to only 3322 * reporting 255 of them. 3323 */ 3324 if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255) 3325 nentries = 256; 3326 /* 3327 * Crusoe processors also have a unified TLB 3328 */ 3329 add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24), 3330 nentries); 3331 break; 3332 } 3333 /*FALLTHROUGH*/ 3334 default: 3335 add_amd_tlb(devi, itlb4k_str, 3336 BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16)); 3337 add_amd_tlb(devi, dtlb4k_str, 3338 BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0)); 3339 break; 3340 } 3341 3342 /* 3343 * data L1 cache configuration 3344 */ 3345 3346 add_amd_cache(devi, l1_dcache_str, 3347 BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16), 3348 BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0)); 3349 3350 /* 3351 * code L1 cache configuration 3352 */ 3353 3354 add_amd_cache(devi, l1_icache_str, 3355 BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16), 3356 BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0)); 3357 3358 if (cpi->cpi_xmaxeax < 0x80000006) 3359 return; 3360 cp = &cpi->cpi_extd[6]; 3361 3362 /* Check for a unified L2 TLB for large pages */ 3363 3364 if (BITX(cp->cp_eax, 31, 16) == 0) 3365 add_amd_l2_tlb(devi, "l2-tlb-2M", 3366 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3367 else { 3368 add_amd_l2_tlb(devi, "l2-dtlb-2M", 3369 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 3370 add_amd_l2_tlb(devi, "l2-itlb-2M", 3371 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3372 } 3373 3374 /* Check for a unified L2 TLB for 4K pages */ 3375 3376 if (BITX(cp->cp_ebx, 31, 16) == 0) { 3377 add_amd_l2_tlb(devi, "l2-tlb-4K", 3378 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3379 } else { 3380 add_amd_l2_tlb(devi, "l2-dtlb-4K", 3381 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 3382 add_amd_l2_tlb(devi, "l2-itlb-4K", 3383 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3384 } 3385 3386 add_amd_l2_cache(devi, l2_cache_str, 3387 BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12), 3388 BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0)); 3389 } 3390 3391 /* 3392 * There are two basic ways that the x86 world describes it cache 3393 * and tlb architecture - Intel's way and AMD's way. 3394 * 3395 * Return which flavor of cache architecture we should use 3396 */ 3397 static int 3398 x86_which_cacheinfo(struct cpuid_info *cpi) 3399 { 3400 switch (cpi->cpi_vendor) { 3401 case X86_VENDOR_Intel: 3402 if (cpi->cpi_maxeax >= 2) 3403 return (X86_VENDOR_Intel); 3404 break; 3405 case X86_VENDOR_AMD: 3406 /* 3407 * The K5 model 1 was the first part from AMD that reported 3408 * cache sizes via extended cpuid functions. 3409 */ 3410 if (cpi->cpi_family > 5 || 3411 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 3412 return (X86_VENDOR_AMD); 3413 break; 3414 case X86_VENDOR_TM: 3415 if (cpi->cpi_family >= 5) 3416 return (X86_VENDOR_AMD); 3417 /*FALLTHROUGH*/ 3418 default: 3419 /* 3420 * If they have extended CPU data for 0x80000005 3421 * then we assume they have AMD-format cache 3422 * information. 3423 * 3424 * If not, and the vendor happens to be Cyrix, 3425 * then try our-Cyrix specific handler. 3426 * 3427 * If we're not Cyrix, then assume we're using Intel's 3428 * table-driven format instead. 3429 */ 3430 if (cpi->cpi_xmaxeax >= 0x80000005) 3431 return (X86_VENDOR_AMD); 3432 else if (cpi->cpi_vendor == X86_VENDOR_Cyrix) 3433 return (X86_VENDOR_Cyrix); 3434 else if (cpi->cpi_maxeax >= 2) 3435 return (X86_VENDOR_Intel); 3436 break; 3437 } 3438 return (-1); 3439 } 3440 3441 /* 3442 * create a node for the given cpu under the prom root node. 3443 * Also, create a cpu node in the device tree. 3444 */ 3445 static dev_info_t *cpu_nex_devi = NULL; 3446 static kmutex_t cpu_node_lock; 3447 3448 /* 3449 * Called from post_startup() and mp_startup() 3450 */ 3451 void 3452 add_cpunode2devtree(processorid_t cpu_id, struct cpuid_info *cpi) 3453 { 3454 dev_info_t *cpu_devi; 3455 int create; 3456 3457 mutex_enter(&cpu_node_lock); 3458 3459 /* 3460 * create a nexus node for all cpus identified as 'cpu_id' under 3461 * the root node. 3462 */ 3463 if (cpu_nex_devi == NULL) { 3464 if (ndi_devi_alloc(ddi_root_node(), "cpus", 3465 (pnode_t)DEVI_SID_NODEID, &cpu_nex_devi) != NDI_SUCCESS) { 3466 mutex_exit(&cpu_node_lock); 3467 return; 3468 } 3469 (void) ndi_devi_online(cpu_nex_devi, 0); 3470 } 3471 3472 /* 3473 * create a child node for cpu identified as 'cpu_id' 3474 */ 3475 cpu_devi = ddi_add_child(cpu_nex_devi, "cpu", DEVI_SID_NODEID, 3476 cpu_id); 3477 if (cpu_devi == NULL) { 3478 mutex_exit(&cpu_node_lock); 3479 return; 3480 } 3481 3482 /* device_type */ 3483 3484 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3485 "device_type", "cpu"); 3486 3487 /* reg */ 3488 3489 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3490 "reg", cpu_id); 3491 3492 /* cpu-mhz, and clock-frequency */ 3493 3494 if (cpu_freq > 0) { 3495 long long mul; 3496 3497 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3498 "cpu-mhz", cpu_freq); 3499 3500 if ((mul = cpu_freq * 1000000LL) <= INT_MAX) 3501 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3502 "clock-frequency", (int)mul); 3503 } 3504 3505 (void) ndi_devi_online(cpu_devi, 0); 3506 3507 if ((x86_feature & X86_CPUID) == 0) { 3508 mutex_exit(&cpu_node_lock); 3509 return; 3510 } 3511 3512 /* vendor-id */ 3513 3514 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3515 "vendor-id", cpi->cpi_vendorstr); 3516 3517 if (cpi->cpi_maxeax == 0) { 3518 mutex_exit(&cpu_node_lock); 3519 return; 3520 } 3521 3522 /* 3523 * family, model, and step 3524 */ 3525 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3526 "family", CPI_FAMILY(cpi)); 3527 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3528 "cpu-model", CPI_MODEL(cpi)); 3529 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3530 "stepping-id", CPI_STEP(cpi)); 3531 3532 /* type */ 3533 3534 switch (cpi->cpi_vendor) { 3535 case X86_VENDOR_Intel: 3536 create = 1; 3537 break; 3538 default: 3539 create = 0; 3540 break; 3541 } 3542 if (create) 3543 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3544 "type", CPI_TYPE(cpi)); 3545 3546 /* ext-family */ 3547 3548 switch (cpi->cpi_vendor) { 3549 case X86_VENDOR_Intel: 3550 case X86_VENDOR_AMD: 3551 create = cpi->cpi_family >= 0xf; 3552 break; 3553 default: 3554 create = 0; 3555 break; 3556 } 3557 if (create) 3558 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3559 "ext-family", CPI_FAMILY_XTD(cpi)); 3560 3561 /* ext-model */ 3562 3563 switch (cpi->cpi_vendor) { 3564 case X86_VENDOR_Intel: 3565 create = IS_EXTENDED_MODEL_INTEL(cpi); 3566 break; 3567 case X86_VENDOR_AMD: 3568 create = CPI_FAMILY(cpi) == 0xf; 3569 break; 3570 default: 3571 create = 0; 3572 break; 3573 } 3574 if (create) 3575 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3576 "ext-model", CPI_MODEL_XTD(cpi)); 3577 3578 /* generation */ 3579 3580 switch (cpi->cpi_vendor) { 3581 case X86_VENDOR_AMD: 3582 /* 3583 * AMD K5 model 1 was the first part to support this 3584 */ 3585 create = cpi->cpi_xmaxeax >= 0x80000001; 3586 break; 3587 default: 3588 create = 0; 3589 break; 3590 } 3591 if (create) 3592 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3593 "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8)); 3594 3595 /* brand-id */ 3596 3597 switch (cpi->cpi_vendor) { 3598 case X86_VENDOR_Intel: 3599 /* 3600 * brand id first appeared on Pentium III Xeon model 8, 3601 * and Celeron model 8 processors and Opteron 3602 */ 3603 create = cpi->cpi_family > 6 || 3604 (cpi->cpi_family == 6 && cpi->cpi_model >= 8); 3605 break; 3606 case X86_VENDOR_AMD: 3607 create = cpi->cpi_family >= 0xf; 3608 break; 3609 default: 3610 create = 0; 3611 break; 3612 } 3613 if (create && cpi->cpi_brandid != 0) { 3614 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3615 "brand-id", cpi->cpi_brandid); 3616 } 3617 3618 /* chunks, and apic-id */ 3619 3620 switch (cpi->cpi_vendor) { 3621 /* 3622 * first available on Pentium IV and Opteron (K8) 3623 */ 3624 case X86_VENDOR_Intel: 3625 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 3626 break; 3627 case X86_VENDOR_AMD: 3628 create = cpi->cpi_family >= 0xf; 3629 break; 3630 default: 3631 create = 0; 3632 break; 3633 } 3634 if (create) { 3635 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3636 "chunks", CPI_CHUNKS(cpi)); 3637 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3638 "apic-id", cpi->cpi_apicid); 3639 if (cpi->cpi_chipid >= 0) { 3640 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3641 "chip#", cpi->cpi_chipid); 3642 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3643 "clog#", cpi->cpi_clogid); 3644 } 3645 } 3646 3647 /* cpuid-features */ 3648 3649 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3650 "cpuid-features", CPI_FEATURES_EDX(cpi)); 3651 3652 3653 /* cpuid-features-ecx */ 3654 3655 switch (cpi->cpi_vendor) { 3656 case X86_VENDOR_Intel: 3657 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 3658 break; 3659 default: 3660 create = 0; 3661 break; 3662 } 3663 if (create) 3664 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3665 "cpuid-features-ecx", CPI_FEATURES_ECX(cpi)); 3666 3667 /* ext-cpuid-features */ 3668 3669 switch (cpi->cpi_vendor) { 3670 case X86_VENDOR_Intel: 3671 case X86_VENDOR_AMD: 3672 case X86_VENDOR_Cyrix: 3673 case X86_VENDOR_TM: 3674 case X86_VENDOR_Centaur: 3675 create = cpi->cpi_xmaxeax >= 0x80000001; 3676 break; 3677 default: 3678 create = 0; 3679 break; 3680 } 3681 if (create) { 3682 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3683 "ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi)); 3684 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3685 "ext-cpuid-features-ecx", CPI_FEATURES_XTD_ECX(cpi)); 3686 } 3687 3688 /* 3689 * Brand String first appeared in Intel Pentium IV, AMD K5 3690 * model 1, and Cyrix GXm. On earlier models we try and 3691 * simulate something similar .. so this string should always 3692 * same -something- about the processor, however lame. 3693 */ 3694 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3695 "brand-string", cpi->cpi_brandstr); 3696 3697 /* 3698 * Finally, cache and tlb information 3699 */ 3700 switch (x86_which_cacheinfo(cpi)) { 3701 case X86_VENDOR_Intel: 3702 intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 3703 break; 3704 case X86_VENDOR_Cyrix: 3705 cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 3706 break; 3707 case X86_VENDOR_AMD: 3708 amd_cache_info(cpi, cpu_devi); 3709 break; 3710 default: 3711 break; 3712 } 3713 3714 mutex_exit(&cpu_node_lock); 3715 } 3716 3717 struct l2info { 3718 int *l2i_csz; 3719 int *l2i_lsz; 3720 int *l2i_assoc; 3721 int l2i_ret; 3722 }; 3723 3724 /* 3725 * A cacheinfo walker that fetches the size, line-size and associativity 3726 * of the L2 cache 3727 */ 3728 static int 3729 intel_l2cinfo(void *arg, const struct cachetab *ct) 3730 { 3731 struct l2info *l2i = arg; 3732 int *ip; 3733 3734 if (ct->ct_label != l2_cache_str && 3735 ct->ct_label != sl2_cache_str) 3736 return (0); /* not an L2 -- keep walking */ 3737 3738 if ((ip = l2i->l2i_csz) != NULL) 3739 *ip = ct->ct_size; 3740 if ((ip = l2i->l2i_lsz) != NULL) 3741 *ip = ct->ct_line_size; 3742 if ((ip = l2i->l2i_assoc) != NULL) 3743 *ip = ct->ct_assoc; 3744 l2i->l2i_ret = ct->ct_size; 3745 return (1); /* was an L2 -- terminate walk */ 3746 } 3747 3748 /* 3749 * AMD L2/L3 Cache and TLB Associativity Field Definition: 3750 * 3751 * Unlike the associativity for the L1 cache and tlb where the 8 bit 3752 * value is the associativity, the associativity for the L2 cache and 3753 * tlb is encoded in the following table. The 4 bit L2 value serves as 3754 * an index into the amd_afd[] array to determine the associativity. 3755 * -1 is undefined. 0 is fully associative. 3756 */ 3757 3758 static int amd_afd[] = 3759 {-1, 1, 2, -1, 4, -1, 8, -1, 16, -1, 32, 48, 64, 96, 128, 0}; 3760 3761 static void 3762 amd_l2cacheinfo(struct cpuid_info *cpi, struct l2info *l2i) 3763 { 3764 struct cpuid_regs *cp; 3765 uint_t size, assoc; 3766 int i; 3767 int *ip; 3768 3769 if (cpi->cpi_xmaxeax < 0x80000006) 3770 return; 3771 cp = &cpi->cpi_extd[6]; 3772 3773 if ((i = BITX(cp->cp_ecx, 15, 12)) != 0 && 3774 (size = BITX(cp->cp_ecx, 31, 16)) != 0) { 3775 uint_t cachesz = size * 1024; 3776 assoc = amd_afd[i]; 3777 3778 ASSERT(assoc != -1); 3779 3780 if ((ip = l2i->l2i_csz) != NULL) 3781 *ip = cachesz; 3782 if ((ip = l2i->l2i_lsz) != NULL) 3783 *ip = BITX(cp->cp_ecx, 7, 0); 3784 if ((ip = l2i->l2i_assoc) != NULL) 3785 *ip = assoc; 3786 l2i->l2i_ret = cachesz; 3787 } 3788 } 3789 3790 int 3791 getl2cacheinfo(cpu_t *cpu, int *csz, int *lsz, int *assoc) 3792 { 3793 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 3794 struct l2info __l2info, *l2i = &__l2info; 3795 3796 l2i->l2i_csz = csz; 3797 l2i->l2i_lsz = lsz; 3798 l2i->l2i_assoc = assoc; 3799 l2i->l2i_ret = -1; 3800 3801 switch (x86_which_cacheinfo(cpi)) { 3802 case X86_VENDOR_Intel: 3803 intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 3804 break; 3805 case X86_VENDOR_Cyrix: 3806 cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 3807 break; 3808 case X86_VENDOR_AMD: 3809 amd_l2cacheinfo(cpi, l2i); 3810 break; 3811 default: 3812 break; 3813 } 3814 return (l2i->l2i_ret); 3815 } 3816 3817 #if !defined(__xpv) 3818 3819 uint32_t * 3820 cpuid_mwait_alloc(cpu_t *cpu) 3821 { 3822 uint32_t *ret; 3823 size_t mwait_size; 3824 3825 ASSERT(cpuid_checkpass(cpu, 2)); 3826 3827 mwait_size = cpu->cpu_m.mcpu_cpi->cpi_mwait.mon_max; 3828 if (mwait_size == 0) 3829 return (NULL); 3830 3831 /* 3832 * kmem_alloc() returns cache line size aligned data for mwait_size 3833 * allocations. mwait_size is currently cache line sized. Neither 3834 * of these implementation details are guarantied to be true in the 3835 * future. 3836 * 3837 * First try allocating mwait_size as kmem_alloc() currently returns 3838 * correctly aligned memory. If kmem_alloc() does not return 3839 * mwait_size aligned memory, then use mwait_size ROUNDUP. 3840 * 3841 * Set cpi_mwait.buf_actual and cpi_mwait.size_actual in case we 3842 * decide to free this memory. 3843 */ 3844 ret = kmem_zalloc(mwait_size, KM_SLEEP); 3845 if (ret == (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size)) { 3846 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret; 3847 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size; 3848 *ret = MWAIT_RUNNING; 3849 return (ret); 3850 } else { 3851 kmem_free(ret, mwait_size); 3852 ret = kmem_zalloc(mwait_size * 2, KM_SLEEP); 3853 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret; 3854 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size * 2; 3855 ret = (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size); 3856 *ret = MWAIT_RUNNING; 3857 return (ret); 3858 } 3859 } 3860 3861 void 3862 cpuid_mwait_free(cpu_t *cpu) 3863 { 3864 ASSERT(cpuid_checkpass(cpu, 2)); 3865 3866 if (cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual != NULL && 3867 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual > 0) { 3868 kmem_free(cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual, 3869 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual); 3870 } 3871 3872 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = NULL; 3873 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = 0; 3874 } 3875 3876 void 3877 patch_tsc_read(int flag) 3878 { 3879 size_t cnt; 3880 3881 switch (flag) { 3882 case X86_NO_TSC: 3883 cnt = &_no_rdtsc_end - &_no_rdtsc_start; 3884 (void) memcpy((void *)tsc_read, (void *)&_no_rdtsc_start, cnt); 3885 break; 3886 case X86_HAVE_TSCP: 3887 cnt = &_tscp_end - &_tscp_start; 3888 (void) memcpy((void *)tsc_read, (void *)&_tscp_start, cnt); 3889 break; 3890 case X86_TSC_MFENCE: 3891 cnt = &_tsc_mfence_end - &_tsc_mfence_start; 3892 (void) memcpy((void *)tsc_read, 3893 (void *)&_tsc_mfence_start, cnt); 3894 break; 3895 case X86_TSC_LFENCE: 3896 cnt = &_tsc_lfence_end - &_tsc_lfence_start; 3897 (void) memcpy((void *)tsc_read, 3898 (void *)&_tsc_lfence_start, cnt); 3899 break; 3900 default: 3901 break; 3902 } 3903 } 3904 3905 int 3906 cpuid_deep_cstates_supported(void) 3907 { 3908 struct cpuid_info *cpi; 3909 struct cpuid_regs regs; 3910 3911 ASSERT(cpuid_checkpass(CPU, 1)); 3912 3913 cpi = CPU->cpu_m.mcpu_cpi; 3914 3915 if (!(x86_feature & X86_CPUID)) 3916 return (0); 3917 3918 switch (cpi->cpi_vendor) { 3919 case X86_VENDOR_Intel: 3920 if (cpi->cpi_xmaxeax < 0x80000007) 3921 return (0); 3922 3923 /* 3924 * TSC run at a constant rate in all ACPI C-states? 3925 */ 3926 regs.cp_eax = 0x80000007; 3927 (void) __cpuid_insn(®s); 3928 return (regs.cp_edx & CPUID_TSC_CSTATE_INVARIANCE); 3929 3930 default: 3931 return (0); 3932 } 3933 } 3934 3935 #endif /* !__xpv */ 3936 3937 void 3938 post_startup_cpu_fixups(void) 3939 { 3940 #ifndef __xpv 3941 /* 3942 * Some AMD processors support C1E state. Entering this state will 3943 * cause the local APIC timer to stop, which we can't deal with at 3944 * this time. 3945 */ 3946 if (cpuid_getvendor(CPU) == X86_VENDOR_AMD) { 3947 on_trap_data_t otd; 3948 uint64_t reg; 3949 3950 if (!on_trap(&otd, OT_DATA_ACCESS)) { 3951 reg = rdmsr(MSR_AMD_INT_PENDING_CMP_HALT); 3952 /* Disable C1E state if it is enabled by BIOS */ 3953 if ((reg >> AMD_ACTONCMPHALT_SHIFT) & 3954 AMD_ACTONCMPHALT_MASK) { 3955 reg &= ~(AMD_ACTONCMPHALT_MASK << 3956 AMD_ACTONCMPHALT_SHIFT); 3957 wrmsr(MSR_AMD_INT_PENDING_CMP_HALT, reg); 3958 } 3959 } 3960 no_trap(); 3961 } 3962 #endif /* !__xpv */ 3963 } 3964 3965 /* 3966 * Starting with the Westmere processor the local 3967 * APIC timer will continue running in all C-states, 3968 * including the deepest C-states. 3969 */ 3970 int 3971 cpuid_arat_supported(void) 3972 { 3973 struct cpuid_info *cpi; 3974 struct cpuid_regs regs; 3975 3976 ASSERT(cpuid_checkpass(CPU, 1)); 3977 ASSERT(x86_feature & X86_CPUID); 3978 3979 cpi = CPU->cpu_m.mcpu_cpi; 3980 3981 switch (cpi->cpi_vendor) { 3982 case X86_VENDOR_Intel: 3983 /* 3984 * Always-running Local APIC Timer is 3985 * indicated by CPUID.6.EAX[2]. 3986 */ 3987 if (cpi->cpi_maxeax >= 6) { 3988 regs.cp_eax = 6; 3989 (void) cpuid_insn(NULL, ®s); 3990 return (regs.cp_eax & CPUID_CSTATE_ARAT); 3991 } else { 3992 return (0); 3993 } 3994 default: 3995 return (0); 3996 } 3997 } 3998 3999 #if defined(__amd64) && !defined(__xpv) 4000 /* 4001 * Patch in versions of bcopy for high performance Intel Nhm processors 4002 * and later... 4003 */ 4004 void 4005 patch_memops(uint_t vendor) 4006 { 4007 size_t cnt, i; 4008 caddr_t to, from; 4009 4010 if ((vendor == X86_VENDOR_Intel) && ((x86_feature & X86_SSE4_2) != 0)) { 4011 cnt = &bcopy_patch_end - &bcopy_patch_start; 4012 to = &bcopy_ck_size; 4013 from = &bcopy_patch_start; 4014 for (i = 0; i < cnt; i++) { 4015 *to++ = *from++; 4016 } 4017 } 4018 } 4019 #endif /* __amd64 && !__xpv */ 4020