1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * Various routines to handle identification 31 * and classification of x86 processors. 32 */ 33 34 #include <sys/types.h> 35 #include <sys/archsystm.h> 36 #include <sys/x86_archext.h> 37 #include <sys/kmem.h> 38 #include <sys/systm.h> 39 #include <sys/cmn_err.h> 40 #include <sys/sunddi.h> 41 #include <sys/sunndi.h> 42 #include <sys/cpuvar.h> 43 #include <sys/processor.h> 44 #include <sys/chip.h> 45 #include <sys/fp.h> 46 #include <sys/controlregs.h> 47 #include <sys/auxv_386.h> 48 #include <sys/bitmap.h> 49 #include <sys/controlregs.h> 50 #include <sys/memnode.h> 51 52 /* 53 * Pass 0 of cpuid feature analysis happens in locore. It contains special code 54 * to recognize Cyrix processors that are not cpuid-compliant, and to deal with 55 * them accordingly. For most modern processors, feature detection occurs here 56 * in pass 1. 57 * 58 * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup() 59 * for the boot CPU and does the basic analysis that the early kernel needs. 60 * x86_feature is set based on the return value of cpuid_pass1() of the boot 61 * CPU. 62 * 63 * Pass 1 includes: 64 * 65 * o Determining vendor/model/family/stepping and setting x86_type and 66 * x86_vendor accordingly. 67 * o Processing the feature flags returned by the cpuid instruction while 68 * applying any workarounds or tricks for the specific processor. 69 * o Mapping the feature flags into Solaris feature bits (X86_*). 70 * o Processing extended feature flags if supported by the processor, 71 * again while applying specific processor knowledge. 72 * o Determining the CMT characteristics of the system. 73 * 74 * Pass 1 is done on non-boot CPUs during their initialization and the results 75 * are used only as a meager attempt at ensuring that all processors within the 76 * system support the same features. 77 * 78 * Pass 2 of cpuid feature analysis happens just at the beginning 79 * of startup(). It just copies in and corrects the remainder 80 * of the cpuid data we depend on: standard cpuid functions that we didn't 81 * need for pass1 feature analysis, and extended cpuid functions beyond the 82 * simple feature processing done in pass1. 83 * 84 * Pass 3 of cpuid analysis is invoked after basic kernel services; in 85 * particular kernel memory allocation has been made available. It creates a 86 * readable brand string based on the data collected in the first two passes. 87 * 88 * Pass 4 of cpuid analysis is invoked after post_startup() when all 89 * the support infrastructure for various hardware features has been 90 * initialized. It determines which processor features will be reported 91 * to userland via the aux vector. 92 * 93 * All passes are executed on all CPUs, but only the boot CPU determines what 94 * features the kernel will use. 95 * 96 * Much of the worst junk in this file is for the support of processors 97 * that didn't really implement the cpuid instruction properly. 98 * 99 * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon, 100 * the pass numbers. Accordingly, changes to the pass code may require changes 101 * to the accessor code. 102 */ 103 104 uint_t x86_feature = 0; 105 uint_t x86_vendor = X86_VENDOR_IntelClone; 106 uint_t x86_type = X86_TYPE_OTHER; 107 108 ulong_t cr4_value; 109 uint_t pentiumpro_bug4046376; 110 uint_t pentiumpro_bug4064495; 111 112 uint_t enable486; 113 114 /* 115 * This set of strings are for processors rumored to support the cpuid 116 * instruction, and is used by locore.s to figure out how to set x86_vendor 117 */ 118 const char CyrixInstead[] = "CyrixInstead"; 119 120 /* 121 * These constants determine how many of the elements of the 122 * cpuid we cache in the cpuid_info data structure; the 123 * remaining elements are accessible via the cpuid instruction. 124 */ 125 126 #define NMAX_CPI_STD 6 /* eax = 0 .. 5 */ 127 #define NMAX_CPI_EXTD 9 /* eax = 0x80000000 .. 0x80000008 */ 128 129 struct cpuid_info { 130 uint_t cpi_pass; /* last pass completed */ 131 /* 132 * standard function information 133 */ 134 uint_t cpi_maxeax; /* fn 0: %eax */ 135 char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */ 136 uint_t cpi_vendor; /* enum of cpi_vendorstr */ 137 138 uint_t cpi_family; /* fn 1: extended family */ 139 uint_t cpi_model; /* fn 1: extended model */ 140 uint_t cpi_step; /* fn 1: stepping */ 141 chipid_t cpi_chipid; /* fn 1: %ebx: chip # on ht cpus */ 142 uint_t cpi_brandid; /* fn 1: %ebx: brand ID */ 143 int cpi_clogid; /* fn 1: %ebx: thread # */ 144 uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */ 145 uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */ 146 uint_t cpi_ncache; /* fn 2: number of elements */ 147 struct cpuid_regs cpi_std[NMAX_CPI_STD]; /* 0 .. 5 */ 148 /* 149 * extended function information 150 */ 151 uint_t cpi_xmaxeax; /* fn 0x80000000: %eax */ 152 char cpi_brandstr[49]; /* fn 0x8000000[234] */ 153 uint8_t cpi_pabits; /* fn 0x80000006: %eax */ 154 uint8_t cpi_vabits; /* fn 0x80000006: %eax */ 155 struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x8000000[0-8] */ 156 id_t cpi_coreid; 157 uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */ 158 /* Intel: fn 4: %eax[31-26] */ 159 /* 160 * supported feature information 161 */ 162 uint32_t cpi_support[4]; 163 #define STD_EDX_FEATURES 0 164 #define AMD_EDX_FEATURES 1 165 #define TM_EDX_FEATURES 2 166 #define STD_ECX_FEATURES 3 167 168 }; 169 170 171 static struct cpuid_info cpuid_info0; 172 173 /* 174 * These bit fields are defined by the Intel Application Note AP-485 175 * "Intel Processor Identification and the CPUID Instruction" 176 */ 177 #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20) 178 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16) 179 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12) 180 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8) 181 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0) 182 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4) 183 184 #define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx) 185 #define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx) 186 #define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx) 187 #define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx) 188 189 #define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0) 190 #define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7) 191 #define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16) 192 #define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24) 193 194 #define CPI_MAXEAX_MAX 0x100 /* sanity control */ 195 #define CPI_XMAXEAX_MAX 0x80000100 196 197 /* 198 * Some undocumented ways of patching the results of the cpuid 199 * instruction to permit running Solaris 10 on future cpus that 200 * we don't currently support. Could be set to non-zero values 201 * via settings in eeprom. 202 */ 203 204 uint32_t cpuid_feature_ecx_include; 205 uint32_t cpuid_feature_ecx_exclude; 206 uint32_t cpuid_feature_edx_include; 207 uint32_t cpuid_feature_edx_exclude; 208 209 uint_t 210 cpuid_pass1(cpu_t *cpu) 211 { 212 uint32_t mask_ecx, mask_edx; 213 uint_t feature = X86_CPUID; 214 struct cpuid_info *cpi; 215 struct cpuid_regs *cp; 216 int xcpuid; 217 218 /* 219 * By convention, cpu0 is the boot cpu, which is called 220 * before memory allocation is available. Other cpus are 221 * initialized when memory becomes available. 222 */ 223 if (cpu->cpu_id == 0) 224 cpu->cpu_m.mcpu_cpi = cpi = &cpuid_info0; 225 else 226 cpu->cpu_m.mcpu_cpi = cpi = 227 kmem_zalloc(sizeof (*cpi), KM_SLEEP); 228 229 cp = &cpi->cpi_std[0]; 230 cp->cp_eax = 0; 231 cpi->cpi_maxeax = __cpuid_insn(cp); 232 { 233 uint32_t *iptr = (uint32_t *)cpi->cpi_vendorstr; 234 *iptr++ = cp->cp_ebx; 235 *iptr++ = cp->cp_edx; 236 *iptr++ = cp->cp_ecx; 237 *(char *)&cpi->cpi_vendorstr[12] = '\0'; 238 } 239 240 /* 241 * Map the vendor string to a type code 242 */ 243 if (strcmp(cpi->cpi_vendorstr, "GenuineIntel") == 0) 244 cpi->cpi_vendor = X86_VENDOR_Intel; 245 else if (strcmp(cpi->cpi_vendorstr, "AuthenticAMD") == 0) 246 cpi->cpi_vendor = X86_VENDOR_AMD; 247 else if (strcmp(cpi->cpi_vendorstr, "GenuineTMx86") == 0) 248 cpi->cpi_vendor = X86_VENDOR_TM; 249 else if (strcmp(cpi->cpi_vendorstr, CyrixInstead) == 0) 250 /* 251 * CyrixInstead is a variable used by the Cyrix detection code 252 * in locore. 253 */ 254 cpi->cpi_vendor = X86_VENDOR_Cyrix; 255 else if (strcmp(cpi->cpi_vendorstr, "UMC UMC UMC ") == 0) 256 cpi->cpi_vendor = X86_VENDOR_UMC; 257 else if (strcmp(cpi->cpi_vendorstr, "NexGenDriven") == 0) 258 cpi->cpi_vendor = X86_VENDOR_NexGen; 259 else if (strcmp(cpi->cpi_vendorstr, "CentaurHauls") == 0) 260 cpi->cpi_vendor = X86_VENDOR_Centaur; 261 else if (strcmp(cpi->cpi_vendorstr, "RiseRiseRise") == 0) 262 cpi->cpi_vendor = X86_VENDOR_Rise; 263 else if (strcmp(cpi->cpi_vendorstr, "SiS SiS SiS ") == 0) 264 cpi->cpi_vendor = X86_VENDOR_SiS; 265 else if (strcmp(cpi->cpi_vendorstr, "Geode by NSC") == 0) 266 cpi->cpi_vendor = X86_VENDOR_NSC; 267 else 268 cpi->cpi_vendor = X86_VENDOR_IntelClone; 269 270 x86_vendor = cpi->cpi_vendor; /* for compatibility */ 271 272 /* 273 * Limit the range in case of weird hardware 274 */ 275 if (cpi->cpi_maxeax > CPI_MAXEAX_MAX) 276 cpi->cpi_maxeax = CPI_MAXEAX_MAX; 277 if (cpi->cpi_maxeax < 1) 278 goto pass1_done; 279 280 cp = &cpi->cpi_std[1]; 281 cp->cp_eax = 1; 282 (void) __cpuid_insn(cp); 283 284 /* 285 * Extract identifying constants for easy access. 286 */ 287 cpi->cpi_model = CPI_MODEL(cpi); 288 cpi->cpi_family = CPI_FAMILY(cpi); 289 290 if (cpi->cpi_family == 0xf) { 291 cpi->cpi_family += CPI_FAMILY_XTD(cpi); 292 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 293 } 294 295 cpi->cpi_step = CPI_STEP(cpi); 296 cpi->cpi_brandid = CPI_BRANDID(cpi); 297 298 /* 299 * *default* assumptions: 300 * - believe %edx feature word 301 * - ignore %ecx feature word 302 * - 32-bit virtual and physical addressing 303 */ 304 mask_edx = 0xffffffff; 305 mask_ecx = 0; 306 307 cpi->cpi_pabits = cpi->cpi_vabits = 32; 308 309 switch (cpi->cpi_vendor) { 310 case X86_VENDOR_Intel: 311 if (cpi->cpi_family == 5) 312 x86_type = X86_TYPE_P5; 313 else if (cpi->cpi_family == 6) { 314 x86_type = X86_TYPE_P6; 315 pentiumpro_bug4046376 = 1; 316 pentiumpro_bug4064495 = 1; 317 /* 318 * Clear the SEP bit when it was set erroneously 319 */ 320 if (cpi->cpi_model < 3 && cpi->cpi_step < 3) 321 cp->cp_edx &= ~CPUID_INTC_EDX_SEP; 322 } else if (cpi->cpi_family == 0xf) { 323 x86_type = X86_TYPE_P4; 324 /* 325 * We don't currently depend on any of the %ecx 326 * features until Prescott, so we'll only check 327 * this from P4 onwards. We might want to revisit 328 * that idea later. 329 */ 330 mask_ecx = 0xffffffff; 331 } else if (cpi->cpi_family > 0xf) 332 mask_ecx = 0xffffffff; 333 break; 334 case X86_VENDOR_IntelClone: 335 default: 336 break; 337 case X86_VENDOR_AMD: 338 #if defined(OPTERON_ERRATUM_108) 339 if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) { 340 cp->cp_eax = (0xf0f & cp->cp_eax) | 0xc0; 341 cpi->cpi_model = 0xc; 342 } else 343 #endif 344 if (cpi->cpi_family == 5) { 345 /* 346 * AMD K5 and K6 347 * 348 * These CPUs have an incomplete implementation 349 * of MCA/MCE which we mask away. 350 */ 351 mask_edx &= ~(CPUID_INTC_EDX_MCE | CPUID_INTC_EDX_MCA); 352 353 /* 354 * Model 0 uses the wrong (APIC) bit 355 * to indicate PGE. Fix it here. 356 */ 357 if (cpi->cpi_model == 0) { 358 if (cp->cp_edx & 0x200) { 359 cp->cp_edx &= ~0x200; 360 cp->cp_edx |= CPUID_INTC_EDX_PGE; 361 } 362 } 363 364 /* 365 * Early models had problems w/ MMX; disable. 366 */ 367 if (cpi->cpi_model < 6) 368 mask_edx &= ~CPUID_INTC_EDX_MMX; 369 } 370 371 /* 372 * For newer families, SSE3 and CX16, at least, are valid; 373 * enable all 374 */ 375 if (cpi->cpi_family >= 0xf) 376 mask_ecx = 0xffffffff; 377 break; 378 case X86_VENDOR_TM: 379 /* 380 * workaround the NT workaround in CMS 4.1 381 */ 382 if (cpi->cpi_family == 5 && cpi->cpi_model == 4 && 383 (cpi->cpi_step == 2 || cpi->cpi_step == 3)) 384 cp->cp_edx |= CPUID_INTC_EDX_CX8; 385 break; 386 case X86_VENDOR_Centaur: 387 /* 388 * workaround the NT workarounds again 389 */ 390 if (cpi->cpi_family == 6) 391 cp->cp_edx |= CPUID_INTC_EDX_CX8; 392 break; 393 case X86_VENDOR_Cyrix: 394 /* 395 * We rely heavily on the probing in locore 396 * to actually figure out what parts, if any, 397 * of the Cyrix cpuid instruction to believe. 398 */ 399 switch (x86_type) { 400 case X86_TYPE_CYRIX_486: 401 mask_edx = 0; 402 break; 403 case X86_TYPE_CYRIX_6x86: 404 mask_edx = 0; 405 break; 406 case X86_TYPE_CYRIX_6x86L: 407 mask_edx = 408 CPUID_INTC_EDX_DE | 409 CPUID_INTC_EDX_CX8; 410 break; 411 case X86_TYPE_CYRIX_6x86MX: 412 mask_edx = 413 CPUID_INTC_EDX_DE | 414 CPUID_INTC_EDX_MSR | 415 CPUID_INTC_EDX_CX8 | 416 CPUID_INTC_EDX_PGE | 417 CPUID_INTC_EDX_CMOV | 418 CPUID_INTC_EDX_MMX; 419 break; 420 case X86_TYPE_CYRIX_GXm: 421 mask_edx = 422 CPUID_INTC_EDX_MSR | 423 CPUID_INTC_EDX_CX8 | 424 CPUID_INTC_EDX_CMOV | 425 CPUID_INTC_EDX_MMX; 426 break; 427 case X86_TYPE_CYRIX_MediaGX: 428 break; 429 case X86_TYPE_CYRIX_MII: 430 case X86_TYPE_VIA_CYRIX_III: 431 mask_edx = 432 CPUID_INTC_EDX_DE | 433 CPUID_INTC_EDX_TSC | 434 CPUID_INTC_EDX_MSR | 435 CPUID_INTC_EDX_CX8 | 436 CPUID_INTC_EDX_PGE | 437 CPUID_INTC_EDX_CMOV | 438 CPUID_INTC_EDX_MMX; 439 break; 440 default: 441 break; 442 } 443 break; 444 } 445 446 /* 447 * Now we've figured out the masks that determine 448 * which bits we choose to believe, apply the masks 449 * to the feature words, then map the kernel's view 450 * of these feature words into its feature word. 451 */ 452 cp->cp_edx &= mask_edx; 453 cp->cp_ecx &= mask_ecx; 454 455 /* 456 * fold in fix ups 457 */ 458 459 cp->cp_edx |= cpuid_feature_edx_include; 460 cp->cp_edx &= ~cpuid_feature_edx_exclude; 461 462 463 cp->cp_ecx |= cpuid_feature_ecx_include; 464 cp->cp_ecx &= ~cpuid_feature_ecx_exclude; 465 466 if (cp->cp_edx & CPUID_INTC_EDX_PSE) 467 feature |= X86_LARGEPAGE; 468 if (cp->cp_edx & CPUID_INTC_EDX_TSC) 469 feature |= X86_TSC; 470 if (cp->cp_edx & CPUID_INTC_EDX_MSR) 471 feature |= X86_MSR; 472 if (cp->cp_edx & CPUID_INTC_EDX_MTRR) 473 feature |= X86_MTRR; 474 if (cp->cp_edx & CPUID_INTC_EDX_PGE) 475 feature |= X86_PGE; 476 if (cp->cp_edx & CPUID_INTC_EDX_CMOV) 477 feature |= X86_CMOV; 478 if (cp->cp_edx & CPUID_INTC_EDX_MMX) 479 feature |= X86_MMX; 480 if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 && 481 (cp->cp_edx & CPUID_INTC_EDX_MCA) != 0) 482 feature |= X86_MCA; 483 if (cp->cp_edx & CPUID_INTC_EDX_PAE) 484 feature |= X86_PAE; 485 if (cp->cp_edx & CPUID_INTC_EDX_CX8) 486 feature |= X86_CX8; 487 /* 488 * Once this bit was thought questionable, but it looks like it's 489 * back, as of Application Note 485 March 2005 (24161829.pdf) 490 */ 491 if (cp->cp_ecx & CPUID_INTC_ECX_CX16) 492 feature |= X86_CX16; 493 if (cp->cp_edx & CPUID_INTC_EDX_PAT) 494 feature |= X86_PAT; 495 if (cp->cp_edx & CPUID_INTC_EDX_SEP) 496 feature |= X86_SEP; 497 if (cp->cp_edx & CPUID_INTC_EDX_FXSR) { 498 /* 499 * In our implementation, fxsave/fxrstor 500 * are prerequisites before we'll even 501 * try and do SSE things. 502 */ 503 if (cp->cp_edx & CPUID_INTC_EDX_SSE) 504 feature |= X86_SSE; 505 if (cp->cp_edx & CPUID_INTC_EDX_SSE2) 506 feature |= X86_SSE2; 507 if (cp->cp_ecx & CPUID_INTC_ECX_SSE3) 508 feature |= X86_SSE3; 509 } 510 if (cp->cp_edx & CPUID_INTC_EDX_DE) 511 cr4_value |= CR4_DE; 512 513 if (feature & X86_PAE) 514 cpi->cpi_pabits = 36; 515 516 /* 517 * Hyperthreading configuration is slightly tricky on Intel 518 * and pure clones, and even trickier on AMD. 519 * 520 * (AMD chose to set the HTT bit on their CMP processors, 521 * even though they're not actually hyperthreaded. Thus it 522 * takes a bit more work to figure out what's really going 523 * on ... see the handling of the CMP_LEGACY bit below) 524 */ 525 if (cp->cp_edx & CPUID_INTC_EDX_HTT) { 526 cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi); 527 if (cpi->cpi_ncpu_per_chip > 1) 528 feature |= X86_HTT; 529 } else { 530 cpi->cpi_ncpu_per_chip = 1; 531 } 532 533 /* 534 * Work on the "extended" feature information, doing 535 * some basic initialization for cpuid_pass2() 536 */ 537 xcpuid = 0; 538 switch (cpi->cpi_vendor) { 539 case X86_VENDOR_Intel: 540 if (cpi->cpi_family >= 0xf) 541 xcpuid++; 542 break; 543 case X86_VENDOR_AMD: 544 if (cpi->cpi_family > 5 || 545 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 546 xcpuid++; 547 break; 548 case X86_VENDOR_Cyrix: 549 /* 550 * Only these Cyrix CPUs are -known- to support 551 * extended cpuid operations. 552 */ 553 if (x86_type == X86_TYPE_VIA_CYRIX_III || 554 x86_type == X86_TYPE_CYRIX_GXm) 555 xcpuid++; 556 break; 557 case X86_VENDOR_Centaur: 558 case X86_VENDOR_TM: 559 default: 560 xcpuid++; 561 break; 562 } 563 564 if (xcpuid) { 565 cp = &cpi->cpi_extd[0]; 566 cp->cp_eax = 0x80000000; 567 cpi->cpi_xmaxeax = __cpuid_insn(cp); 568 } 569 570 if (cpi->cpi_xmaxeax & 0x80000000) { 571 572 if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX) 573 cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX; 574 575 switch (cpi->cpi_vendor) { 576 case X86_VENDOR_Intel: 577 case X86_VENDOR_AMD: 578 if (cpi->cpi_xmaxeax < 0x80000001) 579 break; 580 cp = &cpi->cpi_extd[1]; 581 cp->cp_eax = 0x80000001; 582 (void) __cpuid_insn(cp); 583 if (cpi->cpi_vendor == X86_VENDOR_AMD && 584 cpi->cpi_family == 5 && 585 cpi->cpi_model == 6 && 586 cpi->cpi_step == 6) { 587 /* 588 * K6 model 6 uses bit 10 to indicate SYSC 589 * Later models use bit 11. Fix it here. 590 */ 591 if (cp->cp_edx & 0x400) { 592 cp->cp_edx &= ~0x400; 593 cp->cp_edx |= CPUID_AMD_EDX_SYSC; 594 } 595 } 596 597 /* 598 * Compute the additions to the kernel's feature word. 599 */ 600 if (cp->cp_edx & CPUID_AMD_EDX_NX) 601 feature |= X86_NX; 602 603 /* 604 * If both the HTT and CMP_LEGACY bits are set, 605 * then we're not actually HyperThreaded. Read 606 * "AMD CPUID Specification" for more details. 607 */ 608 if (cpi->cpi_vendor == X86_VENDOR_AMD && 609 (feature & X86_HTT) && 610 (cp->cp_ecx & CPUID_AMD_ECX_CMP_LEGACY)) { 611 feature &= ~X86_HTT; 612 feature |= X86_CMP; 613 } 614 #if defined(_LP64) 615 /* 616 * It's really tricky to support syscall/sysret in 617 * the i386 kernel; we rely on sysenter/sysexit 618 * instead. In the amd64 kernel, things are -way- 619 * better. 620 */ 621 if (cp->cp_edx & CPUID_AMD_EDX_SYSC) 622 feature |= X86_ASYSC; 623 624 /* 625 * While we're thinking about system calls, note 626 * that AMD processors don't support sysenter 627 * in long mode at all, so don't try to program them. 628 */ 629 if (x86_vendor == X86_VENDOR_AMD) 630 feature &= ~X86_SEP; 631 #endif 632 break; 633 default: 634 break; 635 } 636 637 /* 638 * Get CPUID data about processor cores and hyperthreads. 639 */ 640 switch (cpi->cpi_vendor) { 641 case X86_VENDOR_Intel: 642 if (cpi->cpi_maxeax >= 4) { 643 cp = &cpi->cpi_std[4]; 644 cp->cp_eax = 4; 645 cp->cp_ecx = 0; 646 (void) __cpuid_insn(cp); 647 } 648 /*FALLTHROUGH*/ 649 case X86_VENDOR_AMD: 650 if (cpi->cpi_xmaxeax < 0x80000008) 651 break; 652 cp = &cpi->cpi_extd[8]; 653 cp->cp_eax = 0x80000008; 654 (void) __cpuid_insn(cp); 655 /* 656 * Virtual and physical address limits from 657 * cpuid override previously guessed values. 658 */ 659 cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0); 660 cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8); 661 break; 662 default: 663 break; 664 } 665 666 switch (cpi->cpi_vendor) { 667 case X86_VENDOR_Intel: 668 if (cpi->cpi_maxeax < 4) { 669 cpi->cpi_ncore_per_chip = 1; 670 break; 671 } else { 672 cpi->cpi_ncore_per_chip = 673 BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1; 674 } 675 break; 676 case X86_VENDOR_AMD: 677 if (cpi->cpi_xmaxeax < 0x80000008) { 678 cpi->cpi_ncore_per_chip = 1; 679 break; 680 } else { 681 cpi->cpi_ncore_per_chip = 682 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1; 683 } 684 break; 685 default: 686 cpi->cpi_ncore_per_chip = 1; 687 break; 688 } 689 690 } 691 692 /* 693 * If more than one core, then this processor is CMP. 694 */ 695 if (cpi->cpi_ncore_per_chip > 1) 696 feature |= X86_CMP; 697 /* 698 * If the number of cores is the same as the number 699 * of CPUs, then we cannot have HyperThreading. 700 */ 701 if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip) 702 feature &= ~X86_HTT; 703 704 if ((feature & (X86_HTT | X86_CMP)) == 0) { 705 /* 706 * Single-core single-threaded processors. 707 */ 708 cpi->cpi_chipid = -1; 709 cpi->cpi_clogid = 0; 710 cpi->cpi_coreid = cpu->cpu_id; 711 } else if (cpi->cpi_ncpu_per_chip > 1) { 712 uint_t i; 713 uint_t chipid_shift = 0; 714 uint_t coreid_shift = 0; 715 uint_t apic_id = CPI_APIC_ID(cpi); 716 717 for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1) 718 chipid_shift++; 719 cpi->cpi_chipid = apic_id >> chipid_shift; 720 cpi->cpi_clogid = apic_id & ((1 << chipid_shift) - 1); 721 722 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 723 if (feature & X86_CMP) { 724 /* 725 * Multi-core (and possibly multi-threaded) 726 * processors. 727 */ 728 uint_t ncpu_per_core; 729 if (cpi->cpi_ncore_per_chip == 1) 730 ncpu_per_core = cpi->cpi_ncpu_per_chip; 731 else if (cpi->cpi_ncore_per_chip > 1) 732 ncpu_per_core = cpi->cpi_ncpu_per_chip / 733 cpi->cpi_ncore_per_chip; 734 /* 735 * 8bit APIC IDs on dual core Pentiums 736 * look like this: 737 * 738 * +-----------------------+------+------+ 739 * | Physical Package ID | MC | HT | 740 * +-----------------------+------+------+ 741 * <------- chipid --------> 742 * <------- coreid ---------------> 743 * <--- clogid --> 744 * 745 * Where the number of bits necessary to 746 * represent MC and HT fields together equals 747 * to the minimum number of bits necessary to 748 * store the value of cpi->cpi_ncpu_per_chip. 749 * Of those bits, the MC part uses the number 750 * of bits necessary to store the value of 751 * cpi->cpi_ncore_per_chip. 752 */ 753 for (i = 1; i < ncpu_per_core; i <<= 1) 754 coreid_shift++; 755 cpi->cpi_coreid = 756 apic_id & ((1 << coreid_shift) - 1); 757 } else if (feature & X86_HTT) { 758 /* 759 * Single-core multi-threaded processors. 760 */ 761 cpi->cpi_coreid = cpi->cpi_chipid; 762 } 763 } else if (cpi->cpi_vendor == X86_VENDOR_AMD) { 764 /* 765 * AMD currently only has dual-core processors with 766 * single-threaded cores. If they ever release 767 * multi-threaded processors, then this code 768 * will have to be updated. 769 */ 770 cpi->cpi_coreid = cpu->cpu_id; 771 } else { 772 /* 773 * All other processors are currently 774 * assumed to have single cores. 775 */ 776 cpi->cpi_coreid = cpi->cpi_chipid; 777 } 778 } 779 780 pass1_done: 781 cpi->cpi_pass = 1; 782 return (feature); 783 } 784 785 /* 786 * Make copies of the cpuid table entries we depend on, in 787 * part for ease of parsing now, in part so that we have only 788 * one place to correct any of it, in part for ease of 789 * later export to userland, and in part so we can look at 790 * this stuff in a crash dump. 791 */ 792 793 /*ARGSUSED*/ 794 void 795 cpuid_pass2(cpu_t *cpu) 796 { 797 uint_t n, nmax; 798 int i; 799 struct cpuid_regs *cp; 800 uint8_t *dp; 801 uint32_t *iptr; 802 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 803 804 ASSERT(cpi->cpi_pass == 1); 805 806 if (cpi->cpi_maxeax < 1) 807 goto pass2_done; 808 809 if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD) 810 nmax = NMAX_CPI_STD; 811 /* 812 * (We already handled n == 0 and n == 1 in pass 1) 813 */ 814 for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) { 815 cp->cp_eax = n; 816 (void) __cpuid_insn(cp); 817 switch (n) { 818 case 2: 819 /* 820 * "the lower 8 bits of the %eax register 821 * contain a value that identifies the number 822 * of times the cpuid [instruction] has to be 823 * executed to obtain a complete image of the 824 * processor's caching systems." 825 * 826 * How *do* they make this stuff up? 827 */ 828 cpi->cpi_ncache = sizeof (*cp) * 829 BITX(cp->cp_eax, 7, 0); 830 if (cpi->cpi_ncache == 0) 831 break; 832 cpi->cpi_ncache--; /* skip count byte */ 833 834 /* 835 * Well, for now, rather than attempt to implement 836 * this slightly dubious algorithm, we just look 837 * at the first 15 .. 838 */ 839 if (cpi->cpi_ncache > (sizeof (*cp) - 1)) 840 cpi->cpi_ncache = sizeof (*cp) - 1; 841 842 dp = cpi->cpi_cacheinfo; 843 if (BITX(cp->cp_eax, 31, 31) == 0) { 844 uint8_t *p = (void *)&cp->cp_eax; 845 for (i = 1; i < 3; i++) 846 if (p[i] != 0) 847 *dp++ = p[i]; 848 } 849 if (BITX(cp->cp_ebx, 31, 31) == 0) { 850 uint8_t *p = (void *)&cp->cp_ebx; 851 for (i = 0; i < 4; i++) 852 if (p[i] != 0) 853 *dp++ = p[i]; 854 } 855 if (BITX(cp->cp_ecx, 31, 31) == 0) { 856 uint8_t *p = (void *)&cp->cp_ecx; 857 for (i = 0; i < 4; i++) 858 if (p[i] != 0) 859 *dp++ = p[i]; 860 } 861 if (BITX(cp->cp_edx, 31, 31) == 0) { 862 uint8_t *p = (void *)&cp->cp_edx; 863 for (i = 0; i < 4; i++) 864 if (p[i] != 0) 865 *dp++ = p[i]; 866 } 867 break; 868 case 3: /* Processor serial number, if PSN supported */ 869 case 4: /* Deterministic cache parameters */ 870 case 5: /* Monitor/Mwait parameters */ 871 default: 872 break; 873 } 874 } 875 876 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) 877 goto pass2_done; 878 879 if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD) 880 nmax = NMAX_CPI_EXTD; 881 /* 882 * Copy the extended properties, fixing them as we go. 883 * (We already handled n == 0 and n == 1 in pass 1) 884 */ 885 iptr = (void *)cpi->cpi_brandstr; 886 for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) { 887 cp->cp_eax = 0x80000000 + n; 888 (void) __cpuid_insn(cp); 889 switch (n) { 890 case 2: 891 case 3: 892 case 4: 893 /* 894 * Extract the brand string 895 */ 896 *iptr++ = cp->cp_eax; 897 *iptr++ = cp->cp_ebx; 898 *iptr++ = cp->cp_ecx; 899 *iptr++ = cp->cp_edx; 900 break; 901 case 5: 902 switch (cpi->cpi_vendor) { 903 case X86_VENDOR_AMD: 904 /* 905 * The Athlon and Duron were the first 906 * parts to report the sizes of the 907 * TLB for large pages. Before then, 908 * we don't trust the data. 909 */ 910 if (cpi->cpi_family < 6 || 911 (cpi->cpi_family == 6 && 912 cpi->cpi_model < 1)) 913 cp->cp_eax = 0; 914 break; 915 default: 916 break; 917 } 918 break; 919 case 6: 920 switch (cpi->cpi_vendor) { 921 case X86_VENDOR_AMD: 922 /* 923 * The Athlon and Duron were the first 924 * AMD parts with L2 TLB's. 925 * Before then, don't trust the data. 926 */ 927 if (cpi->cpi_family < 6 || 928 cpi->cpi_family == 6 && 929 cpi->cpi_model < 1) 930 cp->cp_eax = cp->cp_ebx = 0; 931 /* 932 * AMD Duron rev A0 reports L2 933 * cache size incorrectly as 1K 934 * when it is really 64K 935 */ 936 if (cpi->cpi_family == 6 && 937 cpi->cpi_model == 3 && 938 cpi->cpi_step == 0) { 939 cp->cp_ecx &= 0xffff; 940 cp->cp_ecx |= 0x400000; 941 } 942 break; 943 case X86_VENDOR_Cyrix: /* VIA C3 */ 944 /* 945 * VIA C3 processors are a bit messed 946 * up w.r.t. encoding cache sizes in %ecx 947 */ 948 if (cpi->cpi_family != 6) 949 break; 950 /* 951 * model 7 and 8 were incorrectly encoded 952 * 953 * xxx is model 8 really broken? 954 */ 955 if (cpi->cpi_model == 7 || 956 cpi->cpi_model == 8) 957 cp->cp_ecx = 958 BITX(cp->cp_ecx, 31, 24) << 16 | 959 BITX(cp->cp_ecx, 23, 16) << 12 | 960 BITX(cp->cp_ecx, 15, 8) << 8 | 961 BITX(cp->cp_ecx, 7, 0); 962 /* 963 * model 9 stepping 1 has wrong associativity 964 */ 965 if (cpi->cpi_model == 9 && cpi->cpi_step == 1) 966 cp->cp_ecx |= 8 << 12; 967 break; 968 case X86_VENDOR_Intel: 969 /* 970 * Extended L2 Cache features function. 971 * First appeared on Prescott. 972 */ 973 default: 974 break; 975 } 976 break; 977 default: 978 break; 979 } 980 } 981 982 pass2_done: 983 cpi->cpi_pass = 2; 984 } 985 986 static const char * 987 intel_cpubrand(const struct cpuid_info *cpi) 988 { 989 int i; 990 991 if ((x86_feature & X86_CPUID) == 0 || 992 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 993 return ("i486"); 994 995 switch (cpi->cpi_family) { 996 case 5: 997 return ("Intel Pentium(r)"); 998 case 6: 999 switch (cpi->cpi_model) { 1000 uint_t celeron, xeon; 1001 const struct cpuid_regs *cp; 1002 case 0: 1003 case 1: 1004 case 2: 1005 return ("Intel Pentium(r) Pro"); 1006 case 3: 1007 case 4: 1008 return ("Intel Pentium(r) II"); 1009 case 6: 1010 return ("Intel Celeron(r)"); 1011 case 5: 1012 case 7: 1013 celeron = xeon = 0; 1014 cp = &cpi->cpi_std[2]; /* cache info */ 1015 1016 for (i = 1; i < 3; i++) { 1017 uint_t tmp; 1018 1019 tmp = (cp->cp_eax >> (8 * i)) & 0xff; 1020 if (tmp == 0x40) 1021 celeron++; 1022 if (tmp >= 0x44 && tmp <= 0x45) 1023 xeon++; 1024 } 1025 1026 for (i = 0; i < 2; i++) { 1027 uint_t tmp; 1028 1029 tmp = (cp->cp_ebx >> (8 * i)) & 0xff; 1030 if (tmp == 0x40) 1031 celeron++; 1032 else if (tmp >= 0x44 && tmp <= 0x45) 1033 xeon++; 1034 } 1035 1036 for (i = 0; i < 4; i++) { 1037 uint_t tmp; 1038 1039 tmp = (cp->cp_ecx >> (8 * i)) & 0xff; 1040 if (tmp == 0x40) 1041 celeron++; 1042 else if (tmp >= 0x44 && tmp <= 0x45) 1043 xeon++; 1044 } 1045 1046 for (i = 0; i < 4; i++) { 1047 uint_t tmp; 1048 1049 tmp = (cp->cp_edx >> (8 * i)) & 0xff; 1050 if (tmp == 0x40) 1051 celeron++; 1052 else if (tmp >= 0x44 && tmp <= 0x45) 1053 xeon++; 1054 } 1055 1056 if (celeron) 1057 return ("Intel Celeron(r)"); 1058 if (xeon) 1059 return (cpi->cpi_model == 5 ? 1060 "Intel Pentium(r) II Xeon(tm)" : 1061 "Intel Pentium(r) III Xeon(tm)"); 1062 return (cpi->cpi_model == 5 ? 1063 "Intel Pentium(r) II or Pentium(r) II Xeon(tm)" : 1064 "Intel Pentium(r) III or Pentium(r) III Xeon(tm)"); 1065 default: 1066 break; 1067 } 1068 default: 1069 break; 1070 } 1071 1072 if (cpi->cpi_family <= 0xf && cpi->cpi_model <= 0xf && 1073 cpi->cpi_brandid != 0) { 1074 static const struct { 1075 uint_t bt_bid; 1076 const char *bt_str; 1077 } brand_tbl[] = { 1078 { 0x1, "Intel(r) Celeron(r)" }, 1079 { 0x2, "Intel(r) Pentium(r) III" }, 1080 { 0x3, "Intel(r) Pentium(r) III Xeon(tm)" }, 1081 { 0x4, "Intel(r) Pentium(r) III" }, 1082 { 0x6, "Mobile Intel(r) Pentium(r) III" }, 1083 { 0x7, "Mobile Intel(r) Celeron(r)" }, 1084 { 0x8, "Intel(r) Pentium(r) 4" }, 1085 { 0x9, "Intel(r) Pentium(r) 4" }, 1086 { 0xa, "Intel(r) Celeron(r)" }, 1087 { 0xb, "Intel(r) Xeon(tm)" }, 1088 { 0xc, "Intel(r) Xeon(tm) MP" }, 1089 { 0xe, "Mobile Intel(r) Pentium(r) 4" }, 1090 { 0xf, "Mobile Intel(r) Celeron(r)" } 1091 }; 1092 uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]); 1093 uint_t sgn; 1094 1095 sgn = (cpi->cpi_family << 8) | 1096 (cpi->cpi_model << 4) | cpi->cpi_step; 1097 1098 for (i = 0; i < btblmax; i++) 1099 if (brand_tbl[i].bt_bid == cpi->cpi_brandid) 1100 break; 1101 if (i < btblmax) { 1102 if (sgn == 0x6b1 && cpi->cpi_brandid == 3) 1103 return ("Intel(r) Celeron(r)"); 1104 if (sgn < 0xf13 && cpi->cpi_brandid == 0xb) 1105 return ("Intel(r) Xeon(tm) MP"); 1106 if (sgn < 0xf13 && cpi->cpi_brandid == 0xe) 1107 return ("Intel(r) Xeon(tm)"); 1108 return (brand_tbl[i].bt_str); 1109 } 1110 } 1111 1112 return (NULL); 1113 } 1114 1115 static const char * 1116 amd_cpubrand(const struct cpuid_info *cpi) 1117 { 1118 if ((x86_feature & X86_CPUID) == 0 || 1119 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 1120 return ("i486 compatible"); 1121 1122 switch (cpi->cpi_family) { 1123 case 5: 1124 switch (cpi->cpi_model) { 1125 case 0: 1126 case 1: 1127 case 2: 1128 case 3: 1129 case 4: 1130 case 5: 1131 return ("AMD-K5(r)"); 1132 case 6: 1133 case 7: 1134 return ("AMD-K6(r)"); 1135 case 8: 1136 return ("AMD-K6(r)-2"); 1137 case 9: 1138 return ("AMD-K6(r)-III"); 1139 default: 1140 return ("AMD (family 5)"); 1141 } 1142 case 6: 1143 switch (cpi->cpi_model) { 1144 case 1: 1145 return ("AMD-K7(tm)"); 1146 case 0: 1147 case 2: 1148 case 4: 1149 return ("AMD Athlon(tm)"); 1150 case 3: 1151 case 7: 1152 return ("AMD Duron(tm)"); 1153 case 6: 1154 case 8: 1155 case 10: 1156 /* 1157 * Use the L2 cache size to distinguish 1158 */ 1159 return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ? 1160 "AMD Athlon(tm)" : "AMD Duron(tm)"); 1161 default: 1162 return ("AMD (family 6)"); 1163 } 1164 default: 1165 break; 1166 } 1167 1168 if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 && 1169 cpi->cpi_brandid != 0) { 1170 switch (BITX(cpi->cpi_brandid, 7, 5)) { 1171 case 3: 1172 return ("AMD Opteron(tm) UP 1xx"); 1173 case 4: 1174 return ("AMD Opteron(tm) DP 2xx"); 1175 case 5: 1176 return ("AMD Opteron(tm) MP 8xx"); 1177 default: 1178 return ("AMD Opteron(tm)"); 1179 } 1180 } 1181 1182 return (NULL); 1183 } 1184 1185 static const char * 1186 cyrix_cpubrand(struct cpuid_info *cpi, uint_t type) 1187 { 1188 if ((x86_feature & X86_CPUID) == 0 || 1189 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5 || 1190 type == X86_TYPE_CYRIX_486) 1191 return ("i486 compatible"); 1192 1193 switch (type) { 1194 case X86_TYPE_CYRIX_6x86: 1195 return ("Cyrix 6x86"); 1196 case X86_TYPE_CYRIX_6x86L: 1197 return ("Cyrix 6x86L"); 1198 case X86_TYPE_CYRIX_6x86MX: 1199 return ("Cyrix 6x86MX"); 1200 case X86_TYPE_CYRIX_GXm: 1201 return ("Cyrix GXm"); 1202 case X86_TYPE_CYRIX_MediaGX: 1203 return ("Cyrix MediaGX"); 1204 case X86_TYPE_CYRIX_MII: 1205 return ("Cyrix M2"); 1206 case X86_TYPE_VIA_CYRIX_III: 1207 return ("VIA Cyrix M3"); 1208 default: 1209 /* 1210 * Have another wild guess .. 1211 */ 1212 if (cpi->cpi_family == 4 && cpi->cpi_model == 9) 1213 return ("Cyrix 5x86"); 1214 else if (cpi->cpi_family == 5) { 1215 switch (cpi->cpi_model) { 1216 case 2: 1217 return ("Cyrix 6x86"); /* Cyrix M1 */ 1218 case 4: 1219 return ("Cyrix MediaGX"); 1220 default: 1221 break; 1222 } 1223 } else if (cpi->cpi_family == 6) { 1224 switch (cpi->cpi_model) { 1225 case 0: 1226 return ("Cyrix 6x86MX"); /* Cyrix M2? */ 1227 case 5: 1228 case 6: 1229 case 7: 1230 case 8: 1231 case 9: 1232 return ("VIA C3"); 1233 default: 1234 break; 1235 } 1236 } 1237 break; 1238 } 1239 return (NULL); 1240 } 1241 1242 /* 1243 * This only gets called in the case that the CPU extended 1244 * feature brand string (0x80000002, 0x80000003, 0x80000004) 1245 * aren't available, or contain null bytes for some reason. 1246 */ 1247 static void 1248 fabricate_brandstr(struct cpuid_info *cpi) 1249 { 1250 const char *brand = NULL; 1251 1252 switch (cpi->cpi_vendor) { 1253 case X86_VENDOR_Intel: 1254 brand = intel_cpubrand(cpi); 1255 break; 1256 case X86_VENDOR_AMD: 1257 brand = amd_cpubrand(cpi); 1258 break; 1259 case X86_VENDOR_Cyrix: 1260 brand = cyrix_cpubrand(cpi, x86_type); 1261 break; 1262 case X86_VENDOR_NexGen: 1263 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 1264 brand = "NexGen Nx586"; 1265 break; 1266 case X86_VENDOR_Centaur: 1267 if (cpi->cpi_family == 5) 1268 switch (cpi->cpi_model) { 1269 case 4: 1270 brand = "Centaur C6"; 1271 break; 1272 case 8: 1273 brand = "Centaur C2"; 1274 break; 1275 case 9: 1276 brand = "Centaur C3"; 1277 break; 1278 default: 1279 break; 1280 } 1281 break; 1282 case X86_VENDOR_Rise: 1283 if (cpi->cpi_family == 5 && 1284 (cpi->cpi_model == 0 || cpi->cpi_model == 2)) 1285 brand = "Rise mP6"; 1286 break; 1287 case X86_VENDOR_SiS: 1288 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 1289 brand = "SiS 55x"; 1290 break; 1291 case X86_VENDOR_TM: 1292 if (cpi->cpi_family == 5 && cpi->cpi_model == 4) 1293 brand = "Transmeta Crusoe TM3x00 or TM5x00"; 1294 break; 1295 case X86_VENDOR_NSC: 1296 case X86_VENDOR_UMC: 1297 default: 1298 break; 1299 } 1300 if (brand) { 1301 (void) strcpy((char *)cpi->cpi_brandstr, brand); 1302 return; 1303 } 1304 1305 /* 1306 * If all else fails ... 1307 */ 1308 (void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr), 1309 "%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family, 1310 cpi->cpi_model, cpi->cpi_step); 1311 } 1312 1313 /* 1314 * This routine is called just after kernel memory allocation 1315 * becomes available on cpu0, and as part of mp_startup() on 1316 * the other cpus. 1317 * 1318 * Fixup the brand string. 1319 */ 1320 /*ARGSUSED*/ 1321 void 1322 cpuid_pass3(cpu_t *cpu) 1323 { 1324 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1325 1326 ASSERT(cpi->cpi_pass == 2); 1327 1328 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) { 1329 fabricate_brandstr(cpi); 1330 goto pass3_done; 1331 } 1332 1333 /* 1334 * If we successfully extracted a brand string from the cpuid 1335 * instruction, clean it up by removing leading spaces and 1336 * similar junk. 1337 */ 1338 if (cpi->cpi_brandstr[0]) { 1339 size_t maxlen = sizeof (cpi->cpi_brandstr); 1340 char *src, *dst; 1341 1342 dst = src = (char *)cpi->cpi_brandstr; 1343 src[maxlen - 1] = '\0'; 1344 /* 1345 * strip leading spaces 1346 */ 1347 while (*src == ' ') 1348 src++; 1349 /* 1350 * Remove any 'Genuine' or "Authentic" prefixes 1351 */ 1352 if (strncmp(src, "Genuine ", 8) == 0) 1353 src += 8; 1354 if (strncmp(src, "Authentic ", 10) == 0) 1355 src += 10; 1356 1357 /* 1358 * Now do an in-place copy. 1359 * Map (R) to (r) and (TM) to (tm). 1360 * The era of teletypes is long gone, and there's 1361 * -really- no need to shout. 1362 */ 1363 while (*src != '\0') { 1364 if (src[0] == '(') { 1365 if (strncmp(src + 1, "R)", 2) == 0) { 1366 (void) strncpy(dst, "(r)", 3); 1367 src += 3; 1368 dst += 3; 1369 continue; 1370 } 1371 if (strncmp(src + 1, "TM)", 3) == 0) { 1372 (void) strncpy(dst, "(tm)", 4); 1373 src += 4; 1374 dst += 4; 1375 continue; 1376 } 1377 } 1378 *dst++ = *src++; 1379 } 1380 *dst = '\0'; 1381 1382 /* 1383 * Finally, remove any trailing spaces 1384 */ 1385 while (--dst > cpi->cpi_brandstr) 1386 if (*dst == ' ') 1387 *dst = '\0'; 1388 else 1389 break; 1390 } else 1391 fabricate_brandstr(cpi); 1392 1393 pass3_done: 1394 cpi->cpi_pass = 3; 1395 } 1396 1397 /* 1398 * This routine is called out of bind_hwcap() much later in the life 1399 * of the kernel (post_startup()). The job of this routine is to resolve 1400 * the hardware feature support and kernel support for those features into 1401 * what we're actually going to tell applications via the aux vector. 1402 */ 1403 uint_t 1404 cpuid_pass4(cpu_t *cpu) 1405 { 1406 struct cpuid_info *cpi; 1407 uint_t hwcap_flags = 0; 1408 1409 if (cpu == NULL) 1410 cpu = CPU; 1411 cpi = cpu->cpu_m.mcpu_cpi; 1412 1413 ASSERT(cpi->cpi_pass == 3); 1414 1415 if (cpi->cpi_maxeax >= 1) { 1416 uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES]; 1417 uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES]; 1418 1419 *edx = CPI_FEATURES_EDX(cpi); 1420 *ecx = CPI_FEATURES_ECX(cpi); 1421 1422 /* 1423 * [these require explicit kernel support] 1424 */ 1425 if ((x86_feature & X86_SEP) == 0) 1426 *edx &= ~CPUID_INTC_EDX_SEP; 1427 1428 if ((x86_feature & X86_SSE) == 0) 1429 *edx &= ~(CPUID_INTC_EDX_FXSR|CPUID_INTC_EDX_SSE); 1430 if ((x86_feature & X86_SSE2) == 0) 1431 *edx &= ~CPUID_INTC_EDX_SSE2; 1432 1433 if ((x86_feature & X86_HTT) == 0) 1434 *edx &= ~CPUID_INTC_EDX_HTT; 1435 1436 if ((x86_feature & X86_SSE3) == 0) 1437 *ecx &= ~CPUID_INTC_ECX_SSE3; 1438 1439 /* 1440 * [no explicit support required beyond x87 fp context] 1441 */ 1442 if (!fpu_exists) 1443 *edx &= ~(CPUID_INTC_EDX_FPU | CPUID_INTC_EDX_MMX); 1444 1445 /* 1446 * Now map the supported feature vector to things that we 1447 * think userland will care about. 1448 */ 1449 if (*edx & CPUID_INTC_EDX_SEP) 1450 hwcap_flags |= AV_386_SEP; 1451 if (*edx & CPUID_INTC_EDX_SSE) 1452 hwcap_flags |= AV_386_FXSR | AV_386_SSE; 1453 if (*edx & CPUID_INTC_EDX_SSE2) 1454 hwcap_flags |= AV_386_SSE2; 1455 if (*ecx & CPUID_INTC_ECX_SSE3) 1456 hwcap_flags |= AV_386_SSE3; 1457 1458 if (*edx & CPUID_INTC_EDX_FPU) 1459 hwcap_flags |= AV_386_FPU; 1460 if (*edx & CPUID_INTC_EDX_MMX) 1461 hwcap_flags |= AV_386_MMX; 1462 1463 if (*edx & CPUID_INTC_EDX_TSC) 1464 hwcap_flags |= AV_386_TSC; 1465 if (*edx & CPUID_INTC_EDX_CX8) 1466 hwcap_flags |= AV_386_CX8; 1467 if (*edx & CPUID_INTC_EDX_CMOV) 1468 hwcap_flags |= AV_386_CMOV; 1469 if (*ecx & CPUID_INTC_ECX_MON) 1470 hwcap_flags |= AV_386_MON; 1471 #if defined(CPUID_INTC_ECX_CX16) 1472 if (*ecx & CPUID_INTC_ECX_CX16) 1473 hwcap_flags |= AV_386_CX16; 1474 #endif 1475 } 1476 1477 if (x86_feature & X86_HTT) 1478 hwcap_flags |= AV_386_PAUSE; 1479 1480 if (cpi->cpi_xmaxeax < 0x80000001) 1481 goto pass4_done; 1482 1483 switch (cpi->cpi_vendor) { 1484 struct cpuid_regs cp; 1485 uint32_t *edx; 1486 1487 case X86_VENDOR_Intel: /* sigh */ 1488 case X86_VENDOR_AMD: 1489 edx = &cpi->cpi_support[AMD_EDX_FEATURES]; 1490 1491 *edx = CPI_FEATURES_XTD_EDX(cpi); 1492 1493 /* 1494 * [no explicit support required beyond 1495 * x87 fp context and exception handlers] 1496 */ 1497 if (!fpu_exists) 1498 *edx &= ~(CPUID_AMD_EDX_MMXamd | 1499 CPUID_AMD_EDX_3DNow | CPUID_AMD_EDX_3DNowx); 1500 1501 if ((x86_feature & X86_ASYSC) == 0) 1502 *edx &= ~CPUID_AMD_EDX_SYSC; 1503 if ((x86_feature & X86_NX) == 0) 1504 *edx &= ~CPUID_AMD_EDX_NX; 1505 #if !defined(_LP64) 1506 *edx &= ~CPUID_AMD_EDX_LM; 1507 #endif 1508 /* 1509 * Now map the supported feature vector to 1510 * things that we think userland will care about. 1511 */ 1512 if (*edx & CPUID_AMD_EDX_SYSC) 1513 hwcap_flags |= AV_386_AMD_SYSC; 1514 if (*edx & CPUID_AMD_EDX_MMXamd) 1515 hwcap_flags |= AV_386_AMD_MMX; 1516 if (*edx & CPUID_AMD_EDX_3DNow) 1517 hwcap_flags |= AV_386_AMD_3DNow; 1518 if (*edx & CPUID_AMD_EDX_3DNowx) 1519 hwcap_flags |= AV_386_AMD_3DNowx; 1520 break; 1521 1522 case X86_VENDOR_TM: 1523 cp.cp_eax = 0x80860001; 1524 (void) __cpuid_insn(&cp); 1525 cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx; 1526 break; 1527 1528 default: 1529 break; 1530 } 1531 1532 pass4_done: 1533 cpi->cpi_pass = 4; 1534 return (hwcap_flags); 1535 } 1536 1537 1538 /* 1539 * Simulate the cpuid instruction using the data we previously 1540 * captured about this CPU. We try our best to return the truth 1541 * about the hardware, independently of kernel support. 1542 */ 1543 uint32_t 1544 cpuid_insn(cpu_t *cpu, struct cpuid_regs *cp) 1545 { 1546 struct cpuid_info *cpi; 1547 struct cpuid_regs *xcp; 1548 1549 if (cpu == NULL) 1550 cpu = CPU; 1551 cpi = cpu->cpu_m.mcpu_cpi; 1552 1553 ASSERT(cpuid_checkpass(cpu, 3)); 1554 1555 /* 1556 * CPUID data is cached in two separate places: cpi_std for standard 1557 * CPUID functions, and cpi_extd for extended CPUID functions. 1558 */ 1559 if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD) 1560 xcp = &cpi->cpi_std[cp->cp_eax]; 1561 else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax && 1562 cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD) 1563 xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000]; 1564 else 1565 /* 1566 * The caller is asking for data from an input parameter which 1567 * the kernel has not cached. In this case we go fetch from 1568 * the hardware and return the data directly to the user. 1569 */ 1570 return (__cpuid_insn(cp)); 1571 1572 cp->cp_eax = xcp->cp_eax; 1573 cp->cp_ebx = xcp->cp_ebx; 1574 cp->cp_ecx = xcp->cp_ecx; 1575 cp->cp_edx = xcp->cp_edx; 1576 return (cp->cp_eax); 1577 } 1578 1579 int 1580 cpuid_checkpass(cpu_t *cpu, int pass) 1581 { 1582 return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL && 1583 cpu->cpu_m.mcpu_cpi->cpi_pass >= pass); 1584 } 1585 1586 int 1587 cpuid_getbrandstr(cpu_t *cpu, char *s, size_t n) 1588 { 1589 ASSERT(cpuid_checkpass(cpu, 3)); 1590 1591 return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr)); 1592 } 1593 1594 int 1595 cpuid_is_cmt(cpu_t *cpu) 1596 { 1597 if (cpu == NULL) 1598 cpu = CPU; 1599 1600 ASSERT(cpuid_checkpass(cpu, 1)); 1601 1602 return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0); 1603 } 1604 1605 /* 1606 * AMD and Intel both implement the 64-bit variant of the syscall 1607 * instruction (syscallq), so if there's -any- support for syscall, 1608 * cpuid currently says "yes, we support this". 1609 * 1610 * However, Intel decided to -not- implement the 32-bit variant of the 1611 * syscall instruction, so we provide a predicate to allow our caller 1612 * to test that subtlety here. 1613 */ 1614 /*ARGSUSED*/ 1615 int 1616 cpuid_syscall32_insn(cpu_t *cpu) 1617 { 1618 ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1)); 1619 1620 if (x86_feature & X86_ASYSC) 1621 return (x86_vendor != X86_VENDOR_Intel); 1622 return (0); 1623 } 1624 1625 int 1626 cpuid_getidstr(cpu_t *cpu, char *s, size_t n) 1627 { 1628 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1629 1630 static const char fmt[] = 1631 "x86 (%s family %d model %d step %d clock %d MHz)"; 1632 static const char fmt_ht[] = 1633 "x86 (chipid 0x%x %s family %d model %d step %d clock %d MHz)"; 1634 1635 ASSERT(cpuid_checkpass(cpu, 1)); 1636 1637 if (cpuid_is_cmt(cpu)) 1638 return (snprintf(s, n, fmt_ht, cpi->cpi_chipid, 1639 cpi->cpi_vendorstr, cpi->cpi_family, cpi->cpi_model, 1640 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 1641 return (snprintf(s, n, fmt, 1642 cpi->cpi_vendorstr, cpi->cpi_family, cpi->cpi_model, 1643 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 1644 } 1645 1646 const char * 1647 cpuid_getvendorstr(cpu_t *cpu) 1648 { 1649 ASSERT(cpuid_checkpass(cpu, 1)); 1650 return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr); 1651 } 1652 1653 uint_t 1654 cpuid_getvendor(cpu_t *cpu) 1655 { 1656 ASSERT(cpuid_checkpass(cpu, 1)); 1657 return (cpu->cpu_m.mcpu_cpi->cpi_vendor); 1658 } 1659 1660 uint_t 1661 cpuid_getfamily(cpu_t *cpu) 1662 { 1663 ASSERT(cpuid_checkpass(cpu, 1)); 1664 return (cpu->cpu_m.mcpu_cpi->cpi_family); 1665 } 1666 1667 uint_t 1668 cpuid_getmodel(cpu_t *cpu) 1669 { 1670 ASSERT(cpuid_checkpass(cpu, 1)); 1671 return (cpu->cpu_m.mcpu_cpi->cpi_model); 1672 } 1673 1674 uint_t 1675 cpuid_get_ncpu_per_chip(cpu_t *cpu) 1676 { 1677 ASSERT(cpuid_checkpass(cpu, 1)); 1678 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip); 1679 } 1680 1681 uint_t 1682 cpuid_get_ncore_per_chip(cpu_t *cpu) 1683 { 1684 ASSERT(cpuid_checkpass(cpu, 1)); 1685 return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip); 1686 } 1687 1688 uint_t 1689 cpuid_getstep(cpu_t *cpu) 1690 { 1691 ASSERT(cpuid_checkpass(cpu, 1)); 1692 return (cpu->cpu_m.mcpu_cpi->cpi_step); 1693 } 1694 1695 chipid_t 1696 chip_plat_get_chipid(cpu_t *cpu) 1697 { 1698 ASSERT(cpuid_checkpass(cpu, 1)); 1699 1700 if (cpuid_is_cmt(cpu)) 1701 return (cpu->cpu_m.mcpu_cpi->cpi_chipid); 1702 return (cpu->cpu_id); 1703 } 1704 1705 id_t 1706 chip_plat_get_coreid(cpu_t *cpu) 1707 { 1708 ASSERT(cpuid_checkpass(cpu, 1)); 1709 return (cpu->cpu_m.mcpu_cpi->cpi_coreid); 1710 } 1711 1712 int 1713 chip_plat_get_clogid(cpu_t *cpu) 1714 { 1715 ASSERT(cpuid_checkpass(cpu, 1)); 1716 return (cpu->cpu_m.mcpu_cpi->cpi_clogid); 1717 } 1718 1719 void 1720 cpuid_get_addrsize(cpu_t *cpu, uint_t *pabits, uint_t *vabits) 1721 { 1722 struct cpuid_info *cpi; 1723 1724 if (cpu == NULL) 1725 cpu = CPU; 1726 cpi = cpu->cpu_m.mcpu_cpi; 1727 1728 ASSERT(cpuid_checkpass(cpu, 1)); 1729 1730 if (pabits) 1731 *pabits = cpi->cpi_pabits; 1732 if (vabits) 1733 *vabits = cpi->cpi_vabits; 1734 } 1735 1736 /* 1737 * Returns the number of data TLB entries for a corresponding 1738 * pagesize. If it can't be computed, or isn't known, the 1739 * routine returns zero. If you ask about an architecturally 1740 * impossible pagesize, the routine will panic (so that the 1741 * hat implementor knows that things are inconsistent.) 1742 */ 1743 uint_t 1744 cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize) 1745 { 1746 struct cpuid_info *cpi; 1747 uint_t dtlb_nent = 0; 1748 1749 if (cpu == NULL) 1750 cpu = CPU; 1751 cpi = cpu->cpu_m.mcpu_cpi; 1752 1753 ASSERT(cpuid_checkpass(cpu, 1)); 1754 1755 /* 1756 * Check the L2 TLB info 1757 */ 1758 if (cpi->cpi_xmaxeax >= 0x80000006) { 1759 struct cpuid_regs *cp = &cpi->cpi_extd[6]; 1760 1761 switch (pagesize) { 1762 1763 case 4 * 1024: 1764 /* 1765 * All zero in the top 16 bits of the register 1766 * indicates a unified TLB. Size is in low 16 bits. 1767 */ 1768 if ((cp->cp_ebx & 0xffff0000) == 0) 1769 dtlb_nent = cp->cp_ebx & 0x0000ffff; 1770 else 1771 dtlb_nent = BITX(cp->cp_ebx, 27, 16); 1772 break; 1773 1774 case 2 * 1024 * 1024: 1775 if ((cp->cp_eax & 0xffff0000) == 0) 1776 dtlb_nent = cp->cp_eax & 0x0000ffff; 1777 else 1778 dtlb_nent = BITX(cp->cp_eax, 27, 16); 1779 break; 1780 1781 default: 1782 panic("unknown L2 pagesize"); 1783 /*NOTREACHED*/ 1784 } 1785 } 1786 1787 if (dtlb_nent != 0) 1788 return (dtlb_nent); 1789 1790 /* 1791 * No L2 TLB support for this size, try L1. 1792 */ 1793 if (cpi->cpi_xmaxeax >= 0x80000005) { 1794 struct cpuid_regs *cp = &cpi->cpi_extd[5]; 1795 1796 switch (pagesize) { 1797 case 4 * 1024: 1798 dtlb_nent = BITX(cp->cp_ebx, 23, 16); 1799 break; 1800 case 2 * 1024 * 1024: 1801 dtlb_nent = BITX(cp->cp_eax, 23, 16); 1802 break; 1803 default: 1804 panic("unknown L1 d-TLB pagesize"); 1805 /*NOTREACHED*/ 1806 } 1807 } 1808 1809 return (dtlb_nent); 1810 } 1811 1812 /* 1813 * Return 0 if the erratum is not present or not applicable, positive 1814 * if it is, and negative if the status of the erratum is unknown. 1815 * 1816 * See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm) 1817 * Processors" #25759, Rev 3.57, August 2005 1818 */ 1819 int 1820 cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum) 1821 { 1822 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1823 uint_t eax; 1824 1825 if (cpi->cpi_vendor != X86_VENDOR_AMD) 1826 return (0); 1827 1828 eax = cpi->cpi_std[1].cp_eax; 1829 1830 #define SH_B0(eax) (eax == 0xf40 || eax == 0xf50) 1831 #define SH_B3(eax) (eax == 0xf51) 1832 #define B(eax) (SH_B0(eax) | SH_B3(eax)) 1833 1834 #define SH_C0(eax) (eax == 0xf48 || eax == 0xf58) 1835 1836 #define SH_CG(eax) (eax == 0xf4a || eax == 0xf5a || eax == 0xf7a) 1837 #define DH_CG(eax) (eax == 0xfc0 || eax == 0xfe0 || eax == 0xff0) 1838 #define CH_CG(eax) (eax == 0xf82 || eax == 0xfb2) 1839 #define CG(eax) (SH_CG(eax) | DH_CG(eax) | CH_CG(eax)) 1840 1841 #define SH_D0(eax) (eax == 0x10f40 || eax == 0x10f50 || eax == 0x10f70) 1842 #define DH_D0(eax) (eax == 0x10fc0 || eax == 0x10ff0) 1843 #define CH_D0(eax) (eax == 0x10f80 || eax == 0x10fb0) 1844 #define D0(eax) (SH_D0(eax) | DH_D0(eax) | CH_D0(eax)) 1845 1846 #define SH_E0(eax) (eax == 0x20f50 || eax == 0x20f40 || eax == 0x20f70) 1847 #define JH_E1(eax) (eax == 0x20f10) /* JH8_E0 had 0x20f30 */ 1848 #define DH_E3(eax) (eax == 0x20fc0 || eax == 0x20ff0) 1849 #define SH_E4(eax) (eax == 0x20f51 || eax == 0x20f71) 1850 #define BH_E4(eax) (eax == 0x20fb1) 1851 #define SH_E5(eax) (eax == 0x20f42) 1852 #define DH_E6(eax) (eax == 0x20ff2 || eax == 0x20fc2) 1853 #define JH_E6(eax) (eax == 0x20f12 || eax == 0x20f32) 1854 #define EX(eax) (SH_E0(eax) | JH_E1(eax) | DH_E3(eax) | SH_E4(eax) | \ 1855 BH_E4(eax) | SH_E5(eax) | DH_E6(eax) | JH_E6(eax)) 1856 1857 switch (erratum) { 1858 case 1: 1859 return (1); 1860 case 51: /* what does the asterisk mean? */ 1861 return (B(eax) || SH_C0(eax) || CG(eax)); 1862 case 52: 1863 return (B(eax)); 1864 case 57: 1865 return (1); 1866 case 58: 1867 return (B(eax)); 1868 case 60: 1869 return (1); 1870 case 61: 1871 case 62: 1872 case 63: 1873 case 64: 1874 case 65: 1875 case 66: 1876 case 68: 1877 case 69: 1878 case 70: 1879 case 71: 1880 return (B(eax)); 1881 case 72: 1882 return (SH_B0(eax)); 1883 case 74: 1884 return (B(eax)); 1885 case 75: 1886 return (1); 1887 case 76: 1888 return (B(eax)); 1889 case 77: 1890 return (1); 1891 case 78: 1892 return (B(eax) || SH_C0(eax)); 1893 case 79: 1894 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 1895 case 80: 1896 case 81: 1897 case 82: 1898 return (B(eax)); 1899 case 83: 1900 return (B(eax) || SH_C0(eax) || CG(eax)); 1901 case 85: 1902 return (1); 1903 case 86: 1904 return (SH_C0(eax) || CG(eax)); 1905 case 88: 1906 #if !defined(__amd64) 1907 return (0); 1908 #else 1909 return (B(eax) || SH_C0(eax)); 1910 #endif 1911 case 89: 1912 return (1); 1913 case 90: 1914 return (B(eax) || SH_C0(eax) || CG(eax)); 1915 case 91: 1916 case 92: 1917 return (B(eax) || SH_C0(eax)); 1918 case 93: 1919 return (SH_C0(eax)); 1920 case 94: 1921 return (B(eax) || SH_C0(eax) || CG(eax)); 1922 case 95: 1923 #if !defined(__amd64) 1924 return (0); 1925 #else 1926 return (B(eax) || SH_C0(eax)); 1927 #endif 1928 case 96: 1929 return (B(eax) || SH_C0(eax) || CG(eax)); 1930 case 97: 1931 case 98: 1932 return (SH_C0(eax) || CG(eax)); 1933 case 99: 1934 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 1935 case 100: 1936 return (B(eax) || SH_C0(eax)); 1937 case 101: 1938 case 103: 1939 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 1940 case 104: 1941 return (SH_C0(eax) || CG(eax) || D0(eax)); 1942 case 105: 1943 case 106: 1944 case 107: 1945 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 1946 case 108: 1947 return (DH_CG(eax)); 1948 case 109: 1949 return (SH_C0(eax) || CG(eax) || D0(eax)); 1950 case 110: 1951 return (D0(eax) || EX(eax)); 1952 case 111: 1953 return (CG(eax)); 1954 case 112: 1955 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 1956 case 113: 1957 return (eax == 0x20fc0); 1958 case 114: 1959 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 1960 case 115: 1961 return (SH_E0(eax) || JH_E1(eax)); 1962 case 116: 1963 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 1964 case 117: 1965 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 1966 case 118: 1967 return (SH_E0(eax) || JH_E1(eax) || SH_E4(eax) || BH_E4(eax) || 1968 JH_E6(eax)); 1969 case 121: 1970 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 1971 case 122: 1972 return (SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 1973 case 123: 1974 return (JH_E1(eax) || BH_E4(eax) || JH_E6(eax)); 1975 case 131: 1976 return (1); 1977 case 6336786: 1978 /* 1979 * Test for AdvPowerMgmtInfo.TscPStateInvariant 1980 * if this is a K8 family processor 1981 */ 1982 if (CPI_FAMILY(cpi) == 0xf) { 1983 struct cpuid_regs regs; 1984 regs.cp_eax = 0x80000007; 1985 (void) __cpuid_insn(®s); 1986 return (!(regs.cp_edx & 0x100)); 1987 } 1988 return (0); 1989 default: 1990 return (-1); 1991 } 1992 } 1993 1994 static const char assoc_str[] = "associativity"; 1995 static const char line_str[] = "line-size"; 1996 static const char size_str[] = "size"; 1997 1998 static void 1999 add_cache_prop(dev_info_t *devi, const char *label, const char *type, 2000 uint32_t val) 2001 { 2002 char buf[128]; 2003 2004 /* 2005 * ndi_prop_update_int() is used because it is desirable for 2006 * DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set. 2007 */ 2008 if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf)) 2009 (void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val); 2010 } 2011 2012 /* 2013 * Intel-style cache/tlb description 2014 * 2015 * Standard cpuid level 2 gives a randomly ordered 2016 * selection of tags that index into a table that describes 2017 * cache and tlb properties. 2018 */ 2019 2020 static const char l1_icache_str[] = "l1-icache"; 2021 static const char l1_dcache_str[] = "l1-dcache"; 2022 static const char l2_cache_str[] = "l2-cache"; 2023 static const char itlb4k_str[] = "itlb-4K"; 2024 static const char dtlb4k_str[] = "dtlb-4K"; 2025 static const char itlb4M_str[] = "itlb-4M"; 2026 static const char dtlb4M_str[] = "dtlb-4M"; 2027 static const char itlb424_str[] = "itlb-4K-2M-4M"; 2028 static const char dtlb44_str[] = "dtlb-4K-4M"; 2029 static const char sl1_dcache_str[] = "sectored-l1-dcache"; 2030 static const char sl2_cache_str[] = "sectored-l2-cache"; 2031 static const char itrace_str[] = "itrace-cache"; 2032 static const char sl3_cache_str[] = "sectored-l3-cache"; 2033 2034 static const struct cachetab { 2035 uint8_t ct_code; 2036 uint8_t ct_assoc; 2037 uint16_t ct_line_size; 2038 size_t ct_size; 2039 const char *ct_label; 2040 } intel_ctab[] = { 2041 /* maintain descending order! */ 2042 { 0xb3, 4, 0, 128, dtlb4k_str }, 2043 { 0xb0, 4, 0, 128, itlb4k_str }, 2044 { 0x87, 8, 64, 1024*1024, l2_cache_str}, 2045 { 0x86, 4, 64, 512*1024, l2_cache_str}, 2046 { 0x85, 8, 32, 2*1024*1024, l2_cache_str}, 2047 { 0x84, 8, 32, 1024*1024, l2_cache_str}, 2048 { 0x83, 8, 32, 512*1024, l2_cache_str}, 2049 { 0x82, 8, 32, 256*1024, l2_cache_str}, 2050 { 0x81, 8, 32, 128*1024, l2_cache_str}, /* suspect! */ 2051 { 0x7f, 2, 64, 512*1024, l2_cache_str}, 2052 { 0x7d, 8, 64, 2*1024*1024, sl2_cache_str}, 2053 { 0x7c, 8, 64, 1024*1024, sl2_cache_str}, 2054 { 0x7b, 8, 64, 512*1024, sl2_cache_str}, 2055 { 0x7a, 8, 64, 256*1024, sl2_cache_str}, 2056 { 0x79, 8, 64, 128*1024, sl2_cache_str}, 2057 { 0x78, 8, 64, 1024*1024, l2_cache_str}, 2058 { 0x72, 8, 0, 32*1024, itrace_str}, 2059 { 0x71, 8, 0, 16*1024, itrace_str}, 2060 { 0x70, 8, 0, 12*1024, itrace_str}, 2061 { 0x68, 4, 64, 32*1024, sl1_dcache_str}, 2062 { 0x67, 4, 64, 16*1024, sl1_dcache_str}, 2063 { 0x66, 4, 64, 8*1024, sl1_dcache_str}, 2064 { 0x60, 8, 64, 16*1024, sl1_dcache_str}, 2065 { 0x5d, 0, 0, 256, dtlb44_str}, 2066 { 0x5c, 0, 0, 128, dtlb44_str}, 2067 { 0x5b, 0, 0, 64, dtlb44_str}, 2068 { 0x52, 0, 0, 256, itlb424_str}, 2069 { 0x51, 0, 0, 128, itlb424_str}, 2070 { 0x50, 0, 0, 64, itlb424_str}, 2071 { 0x45, 4, 32, 2*1024*1024, l2_cache_str}, 2072 { 0x44, 4, 32, 1024*1024, l2_cache_str}, 2073 { 0x43, 4, 32, 512*1024, l2_cache_str}, 2074 { 0x42, 4, 32, 256*1024, l2_cache_str}, 2075 { 0x41, 4, 32, 128*1024, l2_cache_str}, 2076 { 0x3c, 4, 64, 256*1024, sl2_cache_str}, 2077 { 0x3b, 2, 64, 128*1024, sl2_cache_str}, 2078 { 0x39, 4, 64, 128*1024, sl2_cache_str}, 2079 { 0x30, 8, 64, 32*1024, l1_icache_str}, 2080 { 0x2c, 8, 64, 32*1024, l1_dcache_str}, 2081 { 0x29, 8, 64, 4096*1024, sl3_cache_str}, 2082 { 0x25, 8, 64, 2048*1024, sl3_cache_str}, 2083 { 0x23, 8, 64, 1024*1024, sl3_cache_str}, 2084 { 0x22, 4, 64, 512*1024, sl3_cache_str}, 2085 { 0x0c, 4, 32, 16*1024, l1_dcache_str}, 2086 { 0x0a, 2, 32, 8*1024, l1_dcache_str}, 2087 { 0x08, 4, 32, 16*1024, l1_icache_str}, 2088 { 0x06, 4, 32, 8*1024, l1_icache_str}, 2089 { 0x04, 4, 0, 8, dtlb4M_str}, 2090 { 0x03, 4, 0, 64, dtlb4k_str}, 2091 { 0x02, 4, 0, 2, itlb4M_str}, 2092 { 0x01, 4, 0, 32, itlb4k_str}, 2093 { 0 } 2094 }; 2095 2096 static const struct cachetab cyrix_ctab[] = { 2097 { 0x70, 4, 0, 32, "tlb-4K" }, 2098 { 0x80, 4, 16, 16*1024, "l1-cache" }, 2099 { 0 } 2100 }; 2101 2102 /* 2103 * Search a cache table for a matching entry 2104 */ 2105 static const struct cachetab * 2106 find_cacheent(const struct cachetab *ct, uint_t code) 2107 { 2108 if (code != 0) { 2109 for (; ct->ct_code != 0; ct++) 2110 if (ct->ct_code <= code) 2111 break; 2112 if (ct->ct_code == code) 2113 return (ct); 2114 } 2115 return (NULL); 2116 } 2117 2118 /* 2119 * Walk the cacheinfo descriptor, applying 'func' to every valid element 2120 * The walk is terminated if the walker returns non-zero. 2121 */ 2122 static void 2123 intel_walk_cacheinfo(struct cpuid_info *cpi, 2124 void *arg, int (*func)(void *, const struct cachetab *)) 2125 { 2126 const struct cachetab *ct; 2127 uint8_t *dp; 2128 int i; 2129 2130 if ((dp = cpi->cpi_cacheinfo) == NULL) 2131 return; 2132 for (i = 0; i < cpi->cpi_ncache; i++, dp++) 2133 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { 2134 if (func(arg, ct) != 0) 2135 break; 2136 } 2137 } 2138 2139 /* 2140 * (Like the Intel one, except for Cyrix CPUs) 2141 */ 2142 static void 2143 cyrix_walk_cacheinfo(struct cpuid_info *cpi, 2144 void *arg, int (*func)(void *, const struct cachetab *)) 2145 { 2146 const struct cachetab *ct; 2147 uint8_t *dp; 2148 int i; 2149 2150 if ((dp = cpi->cpi_cacheinfo) == NULL) 2151 return; 2152 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { 2153 /* 2154 * Search Cyrix-specific descriptor table first .. 2155 */ 2156 if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) { 2157 if (func(arg, ct) != 0) 2158 break; 2159 continue; 2160 } 2161 /* 2162 * .. else fall back to the Intel one 2163 */ 2164 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { 2165 if (func(arg, ct) != 0) 2166 break; 2167 continue; 2168 } 2169 } 2170 } 2171 2172 /* 2173 * A cacheinfo walker that adds associativity, line-size, and size properties 2174 * to the devinfo node it is passed as an argument. 2175 */ 2176 static int 2177 add_cacheent_props(void *arg, const struct cachetab *ct) 2178 { 2179 dev_info_t *devi = arg; 2180 2181 add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc); 2182 if (ct->ct_line_size != 0) 2183 add_cache_prop(devi, ct->ct_label, line_str, 2184 ct->ct_line_size); 2185 add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size); 2186 return (0); 2187 } 2188 2189 static const char fully_assoc[] = "fully-associative?"; 2190 2191 /* 2192 * AMD style cache/tlb description 2193 * 2194 * Extended functions 5 and 6 directly describe properties of 2195 * tlbs and various cache levels. 2196 */ 2197 static void 2198 add_amd_assoc(dev_info_t *devi, const char *label, uint_t assoc) 2199 { 2200 switch (assoc) { 2201 case 0: /* reserved; ignore */ 2202 break; 2203 default: 2204 add_cache_prop(devi, label, assoc_str, assoc); 2205 break; 2206 case 0xff: 2207 add_cache_prop(devi, label, fully_assoc, 1); 2208 break; 2209 } 2210 } 2211 2212 static void 2213 add_amd_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 2214 { 2215 if (size == 0) 2216 return; 2217 add_cache_prop(devi, label, size_str, size); 2218 add_amd_assoc(devi, label, assoc); 2219 } 2220 2221 static void 2222 add_amd_cache(dev_info_t *devi, const char *label, 2223 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 2224 { 2225 if (size == 0 || line_size == 0) 2226 return; 2227 add_amd_assoc(devi, label, assoc); 2228 /* 2229 * Most AMD parts have a sectored cache. Multiple cache lines are 2230 * associated with each tag. A sector consists of all cache lines 2231 * associated with a tag. For example, the AMD K6-III has a sector 2232 * size of 2 cache lines per tag. 2233 */ 2234 if (lines_per_tag != 0) 2235 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 2236 add_cache_prop(devi, label, line_str, line_size); 2237 add_cache_prop(devi, label, size_str, size * 1024); 2238 } 2239 2240 static void 2241 add_amd_l2_assoc(dev_info_t *devi, const char *label, uint_t assoc) 2242 { 2243 switch (assoc) { 2244 case 0: /* off */ 2245 break; 2246 case 1: 2247 case 2: 2248 case 4: 2249 add_cache_prop(devi, label, assoc_str, assoc); 2250 break; 2251 case 6: 2252 add_cache_prop(devi, label, assoc_str, 8); 2253 break; 2254 case 8: 2255 add_cache_prop(devi, label, assoc_str, 16); 2256 break; 2257 case 0xf: 2258 add_cache_prop(devi, label, fully_assoc, 1); 2259 break; 2260 default: /* reserved; ignore */ 2261 break; 2262 } 2263 } 2264 2265 static void 2266 add_amd_l2_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 2267 { 2268 if (size == 0 || assoc == 0) 2269 return; 2270 add_amd_l2_assoc(devi, label, assoc); 2271 add_cache_prop(devi, label, size_str, size); 2272 } 2273 2274 static void 2275 add_amd_l2_cache(dev_info_t *devi, const char *label, 2276 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 2277 { 2278 if (size == 0 || assoc == 0 || line_size == 0) 2279 return; 2280 add_amd_l2_assoc(devi, label, assoc); 2281 if (lines_per_tag != 0) 2282 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 2283 add_cache_prop(devi, label, line_str, line_size); 2284 add_cache_prop(devi, label, size_str, size * 1024); 2285 } 2286 2287 static void 2288 amd_cache_info(struct cpuid_info *cpi, dev_info_t *devi) 2289 { 2290 struct cpuid_regs *cp; 2291 2292 if (cpi->cpi_xmaxeax < 0x80000005) 2293 return; 2294 cp = &cpi->cpi_extd[5]; 2295 2296 /* 2297 * 4M/2M L1 TLB configuration 2298 * 2299 * We report the size for 2M pages because AMD uses two 2300 * TLB entries for one 4M page. 2301 */ 2302 add_amd_tlb(devi, "dtlb-2M", 2303 BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16)); 2304 add_amd_tlb(devi, "itlb-2M", 2305 BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0)); 2306 2307 /* 2308 * 4K L1 TLB configuration 2309 */ 2310 2311 switch (cpi->cpi_vendor) { 2312 uint_t nentries; 2313 case X86_VENDOR_TM: 2314 if (cpi->cpi_family >= 5) { 2315 /* 2316 * Crusoe processors have 256 TLB entries, but 2317 * cpuid data format constrains them to only 2318 * reporting 255 of them. 2319 */ 2320 if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255) 2321 nentries = 256; 2322 /* 2323 * Crusoe processors also have a unified TLB 2324 */ 2325 add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24), 2326 nentries); 2327 break; 2328 } 2329 /*FALLTHROUGH*/ 2330 default: 2331 add_amd_tlb(devi, itlb4k_str, 2332 BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16)); 2333 add_amd_tlb(devi, dtlb4k_str, 2334 BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0)); 2335 break; 2336 } 2337 2338 /* 2339 * data L1 cache configuration 2340 */ 2341 2342 add_amd_cache(devi, l1_dcache_str, 2343 BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16), 2344 BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0)); 2345 2346 /* 2347 * code L1 cache configuration 2348 */ 2349 2350 add_amd_cache(devi, l1_icache_str, 2351 BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16), 2352 BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0)); 2353 2354 if (cpi->cpi_xmaxeax < 0x80000006) 2355 return; 2356 cp = &cpi->cpi_extd[6]; 2357 2358 /* Check for a unified L2 TLB for large pages */ 2359 2360 if (BITX(cp->cp_eax, 31, 16) == 0) 2361 add_amd_l2_tlb(devi, "l2-tlb-2M", 2362 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 2363 else { 2364 add_amd_l2_tlb(devi, "l2-dtlb-2M", 2365 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 2366 add_amd_l2_tlb(devi, "l2-itlb-2M", 2367 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 2368 } 2369 2370 /* Check for a unified L2 TLB for 4K pages */ 2371 2372 if (BITX(cp->cp_ebx, 31, 16) == 0) { 2373 add_amd_l2_tlb(devi, "l2-tlb-4K", 2374 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 2375 } else { 2376 add_amd_l2_tlb(devi, "l2-dtlb-4K", 2377 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 2378 add_amd_l2_tlb(devi, "l2-itlb-4K", 2379 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 2380 } 2381 2382 add_amd_l2_cache(devi, l2_cache_str, 2383 BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12), 2384 BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0)); 2385 } 2386 2387 /* 2388 * There are two basic ways that the x86 world describes it cache 2389 * and tlb architecture - Intel's way and AMD's way. 2390 * 2391 * Return which flavor of cache architecture we should use 2392 */ 2393 static int 2394 x86_which_cacheinfo(struct cpuid_info *cpi) 2395 { 2396 switch (cpi->cpi_vendor) { 2397 case X86_VENDOR_Intel: 2398 if (cpi->cpi_maxeax >= 2) 2399 return (X86_VENDOR_Intel); 2400 break; 2401 case X86_VENDOR_AMD: 2402 /* 2403 * The K5 model 1 was the first part from AMD that reported 2404 * cache sizes via extended cpuid functions. 2405 */ 2406 if (cpi->cpi_family > 5 || 2407 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 2408 return (X86_VENDOR_AMD); 2409 break; 2410 case X86_VENDOR_TM: 2411 if (cpi->cpi_family >= 5) 2412 return (X86_VENDOR_AMD); 2413 /*FALLTHROUGH*/ 2414 default: 2415 /* 2416 * If they have extended CPU data for 0x80000005 2417 * then we assume they have AMD-format cache 2418 * information. 2419 * 2420 * If not, and the vendor happens to be Cyrix, 2421 * then try our-Cyrix specific handler. 2422 * 2423 * If we're not Cyrix, then assume we're using Intel's 2424 * table-driven format instead. 2425 */ 2426 if (cpi->cpi_xmaxeax >= 0x80000005) 2427 return (X86_VENDOR_AMD); 2428 else if (cpi->cpi_vendor == X86_VENDOR_Cyrix) 2429 return (X86_VENDOR_Cyrix); 2430 else if (cpi->cpi_maxeax >= 2) 2431 return (X86_VENDOR_Intel); 2432 break; 2433 } 2434 return (-1); 2435 } 2436 2437 /* 2438 * create a node for the given cpu under the prom root node. 2439 * Also, create a cpu node in the device tree. 2440 */ 2441 static dev_info_t *cpu_nex_devi = NULL; 2442 static kmutex_t cpu_node_lock; 2443 2444 /* 2445 * Called from post_startup() and mp_startup() 2446 */ 2447 void 2448 add_cpunode2devtree(processorid_t cpu_id, struct cpuid_info *cpi) 2449 { 2450 dev_info_t *cpu_devi; 2451 int create; 2452 2453 mutex_enter(&cpu_node_lock); 2454 2455 /* 2456 * create a nexus node for all cpus identified as 'cpu_id' under 2457 * the root node. 2458 */ 2459 if (cpu_nex_devi == NULL) { 2460 if (ndi_devi_alloc(ddi_root_node(), "cpus", 2461 (pnode_t)DEVI_SID_NODEID, &cpu_nex_devi) != NDI_SUCCESS) { 2462 mutex_exit(&cpu_node_lock); 2463 return; 2464 } 2465 (void) ndi_devi_online(cpu_nex_devi, 0); 2466 } 2467 2468 /* 2469 * create a child node for cpu identified as 'cpu_id' 2470 */ 2471 cpu_devi = ddi_add_child(cpu_nex_devi, "cpu", DEVI_SID_NODEID, 2472 cpu_id); 2473 if (cpu_devi == NULL) { 2474 mutex_exit(&cpu_node_lock); 2475 return; 2476 } 2477 2478 /* device_type */ 2479 2480 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 2481 "device_type", "cpu"); 2482 2483 /* reg */ 2484 2485 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2486 "reg", cpu_id); 2487 2488 /* cpu-mhz, and clock-frequency */ 2489 2490 if (cpu_freq > 0) { 2491 long long mul; 2492 2493 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2494 "cpu-mhz", cpu_freq); 2495 2496 if ((mul = cpu_freq * 1000000LL) <= INT_MAX) 2497 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2498 "clock-frequency", (int)mul); 2499 } 2500 2501 (void) ndi_devi_online(cpu_devi, 0); 2502 2503 if ((x86_feature & X86_CPUID) == 0) { 2504 mutex_exit(&cpu_node_lock); 2505 return; 2506 } 2507 2508 /* vendor-id */ 2509 2510 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 2511 "vendor-id", cpi->cpi_vendorstr); 2512 2513 if (cpi->cpi_maxeax == 0) { 2514 mutex_exit(&cpu_node_lock); 2515 return; 2516 } 2517 2518 /* 2519 * family, model, and step 2520 */ 2521 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2522 "family", CPI_FAMILY(cpi)); 2523 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2524 "cpu-model", CPI_MODEL(cpi)); 2525 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2526 "stepping-id", CPI_STEP(cpi)); 2527 2528 /* type */ 2529 2530 switch (cpi->cpi_vendor) { 2531 case X86_VENDOR_Intel: 2532 create = 1; 2533 break; 2534 default: 2535 create = 0; 2536 break; 2537 } 2538 if (create) 2539 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2540 "type", CPI_TYPE(cpi)); 2541 2542 /* ext-family */ 2543 2544 switch (cpi->cpi_vendor) { 2545 case X86_VENDOR_Intel: 2546 case X86_VENDOR_AMD: 2547 create = cpi->cpi_family >= 0xf; 2548 break; 2549 default: 2550 create = 0; 2551 break; 2552 } 2553 if (create) 2554 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2555 "ext-family", CPI_FAMILY_XTD(cpi)); 2556 2557 /* ext-model */ 2558 2559 switch (cpi->cpi_vendor) { 2560 case X86_VENDOR_Intel: 2561 case X86_VENDOR_AMD: 2562 create = CPI_MODEL(cpi) == 0xf; 2563 break; 2564 default: 2565 create = 0; 2566 break; 2567 } 2568 if (create) 2569 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2570 "ext-model", CPI_MODEL_XTD(cpi)); 2571 2572 /* generation */ 2573 2574 switch (cpi->cpi_vendor) { 2575 case X86_VENDOR_AMD: 2576 /* 2577 * AMD K5 model 1 was the first part to support this 2578 */ 2579 create = cpi->cpi_xmaxeax >= 0x80000001; 2580 break; 2581 default: 2582 create = 0; 2583 break; 2584 } 2585 if (create) 2586 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2587 "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8)); 2588 2589 /* brand-id */ 2590 2591 switch (cpi->cpi_vendor) { 2592 case X86_VENDOR_Intel: 2593 /* 2594 * brand id first appeared on Pentium III Xeon model 8, 2595 * and Celeron model 8 processors and Opteron 2596 */ 2597 create = cpi->cpi_family > 6 || 2598 (cpi->cpi_family == 6 && cpi->cpi_model >= 8); 2599 break; 2600 case X86_VENDOR_AMD: 2601 create = cpi->cpi_family >= 0xf; 2602 break; 2603 default: 2604 create = 0; 2605 break; 2606 } 2607 if (create && cpi->cpi_brandid != 0) { 2608 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2609 "brand-id", cpi->cpi_brandid); 2610 } 2611 2612 /* chunks, and apic-id */ 2613 2614 switch (cpi->cpi_vendor) { 2615 case X86_VENDOR_Intel: 2616 case X86_VENDOR_AMD: 2617 /* 2618 * first available on Pentium IV and Opteron (K8) 2619 */ 2620 create = cpi->cpi_family >= 0xf; 2621 break; 2622 default: 2623 create = 0; 2624 break; 2625 } 2626 if (create) { 2627 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2628 "chunks", CPI_CHUNKS(cpi)); 2629 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2630 "apic-id", CPI_APIC_ID(cpi)); 2631 if (cpi->cpi_chipid >= 0) { 2632 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2633 "chip#", cpi->cpi_chipid); 2634 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2635 "clog#", cpi->cpi_clogid); 2636 } 2637 } 2638 2639 /* cpuid-features */ 2640 2641 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2642 "cpuid-features", CPI_FEATURES_EDX(cpi)); 2643 2644 2645 /* cpuid-features-ecx */ 2646 2647 switch (cpi->cpi_vendor) { 2648 case X86_VENDOR_Intel: 2649 create = cpi->cpi_family >= 0xf; 2650 break; 2651 default: 2652 create = 0; 2653 break; 2654 } 2655 if (create) 2656 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2657 "cpuid-features-ecx", CPI_FEATURES_ECX(cpi)); 2658 2659 /* ext-cpuid-features */ 2660 2661 switch (cpi->cpi_vendor) { 2662 case X86_VENDOR_AMD: 2663 case X86_VENDOR_Cyrix: 2664 case X86_VENDOR_TM: 2665 case X86_VENDOR_Centaur: 2666 /* 2667 * The extended cpuid features are not relevant on 2668 * Intel but are available from the AMD K5 model 1 2669 * and most Cyrix GXm and later. 2670 */ 2671 create = cpi->cpi_xmaxeax >= 0x80000001; 2672 break; 2673 default: 2674 create = 0; 2675 break; 2676 } 2677 if (create) 2678 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2679 "ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi)); 2680 2681 /* 2682 * Brand String first appeared in Intel Pentium IV, AMD K5 2683 * model 1, and Cyrix GXm. On earlier models we try and 2684 * simulate something similar .. so this string should always 2685 * same -something- about the processor, however lame. 2686 */ 2687 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 2688 "brand-string", cpi->cpi_brandstr); 2689 2690 /* 2691 * Finally, cache and tlb information 2692 */ 2693 switch (x86_which_cacheinfo(cpi)) { 2694 case X86_VENDOR_Intel: 2695 intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 2696 break; 2697 case X86_VENDOR_Cyrix: 2698 cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 2699 break; 2700 case X86_VENDOR_AMD: 2701 amd_cache_info(cpi, cpu_devi); 2702 break; 2703 default: 2704 break; 2705 } 2706 2707 mutex_exit(&cpu_node_lock); 2708 } 2709 2710 struct l2info { 2711 int *l2i_csz; 2712 int *l2i_lsz; 2713 int *l2i_assoc; 2714 int l2i_ret; 2715 }; 2716 2717 /* 2718 * A cacheinfo walker that fetches the size, line-size and associativity 2719 * of the L2 cache 2720 */ 2721 static int 2722 intel_l2cinfo(void *arg, const struct cachetab *ct) 2723 { 2724 struct l2info *l2i = arg; 2725 int *ip; 2726 2727 if (ct->ct_label != l2_cache_str && 2728 ct->ct_label != sl2_cache_str) 2729 return (0); /* not an L2 -- keep walking */ 2730 2731 if ((ip = l2i->l2i_csz) != NULL) 2732 *ip = ct->ct_size; 2733 if ((ip = l2i->l2i_lsz) != NULL) 2734 *ip = ct->ct_line_size; 2735 if ((ip = l2i->l2i_assoc) != NULL) 2736 *ip = ct->ct_assoc; 2737 l2i->l2i_ret = ct->ct_size; 2738 return (1); /* was an L2 -- terminate walk */ 2739 } 2740 2741 static void 2742 amd_l2cacheinfo(struct cpuid_info *cpi, struct l2info *l2i) 2743 { 2744 struct cpuid_regs *cp; 2745 uint_t size, assoc; 2746 int *ip; 2747 2748 if (cpi->cpi_xmaxeax < 0x80000006) 2749 return; 2750 cp = &cpi->cpi_extd[6]; 2751 2752 if ((assoc = BITX(cp->cp_ecx, 15, 12)) != 0 && 2753 (size = BITX(cp->cp_ecx, 31, 16)) != 0) { 2754 uint_t cachesz = size * 1024; 2755 2756 2757 if ((ip = l2i->l2i_csz) != NULL) 2758 *ip = cachesz; 2759 if ((ip = l2i->l2i_lsz) != NULL) 2760 *ip = BITX(cp->cp_ecx, 7, 0); 2761 if ((ip = l2i->l2i_assoc) != NULL) 2762 *ip = assoc; 2763 l2i->l2i_ret = cachesz; 2764 } 2765 } 2766 2767 int 2768 getl2cacheinfo(cpu_t *cpu, int *csz, int *lsz, int *assoc) 2769 { 2770 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2771 struct l2info __l2info, *l2i = &__l2info; 2772 2773 l2i->l2i_csz = csz; 2774 l2i->l2i_lsz = lsz; 2775 l2i->l2i_assoc = assoc; 2776 l2i->l2i_ret = -1; 2777 2778 switch (x86_which_cacheinfo(cpi)) { 2779 case X86_VENDOR_Intel: 2780 intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 2781 break; 2782 case X86_VENDOR_Cyrix: 2783 cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 2784 break; 2785 case X86_VENDOR_AMD: 2786 amd_l2cacheinfo(cpi, l2i); 2787 break; 2788 default: 2789 break; 2790 } 2791 return (l2i->l2i_ret); 2792 } 2793