1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #define PSMI_1_5 29 30 #include <sys/mutex.h> 31 #include <sys/types.h> 32 #include <sys/time.h> 33 #include <sys/machlock.h> 34 #include <sys/smp_impldefs.h> 35 #include <sys/uadmin.h> 36 #include <sys/promif.h> 37 #include <sys/psm.h> 38 #include <sys/pit.h> 39 #include <sys/psm_common.h> 40 #include <sys/atomic.h> 41 #include <sys/archsystm.h> 42 43 #define NSEC_IN_SEC 1000000000 44 45 /* 46 * Local Function Prototypes 47 */ 48 static void uppc_softinit(void); 49 static void uppc_picinit(); 50 static int uppc_clkinit(int); 51 static int uppc_addspl(int irqno, int ipl, int min_ipl, int max_ipl); 52 static int uppc_delspl(int irqno, int ipl, int min_ipl, int max_ipl); 53 static processorid_t uppc_get_next_processorid(processorid_t cpu_id); 54 static int uppc_get_clockirq(int ipl); 55 static int uppc_probe(void); 56 static int uppc_translate_irq(dev_info_t *dip, int irqno); 57 static void uppc_shutdown(int cmd, int fcn); 58 static void uppc_preshutdown(int cmd, int fcn); 59 static int uppc_init_acpi(void); 60 static void uppc_setspl(int); 61 static int uppc_intr_enter(int, int *); 62 static void uppc_intr_exit(int, int); 63 static hrtime_t uppc_gethrtime(); 64 65 static int uppc_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip, 66 int *pci_irqp, iflag_t *intr_flagp); 67 68 /* 69 * Global Data 70 */ 71 static struct standard_pic pics0; 72 int uppc_use_acpi = 1; /* Use ACPI by default */ 73 int uppc_enable_acpi = 0; 74 75 76 /* 77 * For interrupt link devices, if uppc_unconditional_srs is set, an irq resource 78 * will be assigned (via _SRS). If it is not set, use the current 79 * irq setting (via _CRS), but only if that irq is in the set of possible 80 * irqs (returned by _PRS) for the device. 81 */ 82 int uppc_unconditional_srs = 1; 83 84 /* 85 * For interrupt link devices, if uppc_prefer_crs is set when we are 86 * assigning an IRQ resource to a device, prefer the current IRQ setting 87 * over other possible irq settings under same conditions. 88 */ 89 int uppc_prefer_crs = 1; 90 91 int uppc_verbose = 0; 92 93 /* flag definitions for uppc_verbose */ 94 #define UPPC_VERBOSE_IRQ_FLAG 0x00000001 95 #define UPPC_VERBOSE_POWEROFF_FLAG 0x00000002 96 #define UPPC_VERBOSE_POWEROFF_PAUSE_FLAG 0x00000004 97 98 99 #define UPPC_VERBOSE_IRQ(fmt) \ 100 if (uppc_verbose & UPPC_VERBOSE_IRQ_FLAG) \ 101 cmn_err fmt; 102 103 #define UPPC_VERBOSE_POWEROFF(fmt) \ 104 if (uppc_verbose & UPPC_VERBOSE_POWEROFF_FLAG) \ 105 prom_printf fmt; 106 107 uchar_t uppc_reserved_irqlist[MAX_ISA_IRQ + 1]; 108 109 static uint16_t uppc_irq_shared_table[MAX_ISA_IRQ + 1]; 110 111 /* 112 * Contains SCI irqno from FADT after initialization 113 */ 114 static int uppc_sci = -1; 115 116 /* 117 * Local Static Data 118 */ 119 120 static lock_t uppc_gethrtime_lock; 121 static hrtime_t uppc_lasthrtime; 122 123 124 #ifdef UPPC_DEBUG 125 #define DENT 0x0001 126 127 static int uppc_debug = 0; 128 129 130 #endif 131 132 133 static struct psm_ops uppc_ops = { 134 uppc_probe, /* psm_probe */ 135 136 uppc_softinit, /* psm_init */ 137 uppc_picinit, /* psm_picinit */ 138 uppc_intr_enter, /* psm_intr_enter */ 139 uppc_intr_exit, /* psm_intr_exit */ 140 uppc_setspl, /* psm_setspl */ 141 uppc_addspl, /* psm_addspl */ 142 uppc_delspl, /* psm_delspl */ 143 (int (*)(processorid_t))NULL, /* psm_disable_intr */ 144 (void (*)(processorid_t))NULL, /* psm_enable_intr */ 145 (int (*)(int))NULL, /* psm_softlvl_to_irq */ 146 (void (*)(int))NULL, /* psm_set_softintr */ 147 (void (*)(processorid_t))NULL, /* psm_set_idlecpu */ 148 (void (*)(processorid_t))NULL, /* psm_unset_idlecpu */ 149 150 uppc_clkinit, /* psm_clkinit */ 151 uppc_get_clockirq, /* psm_get_clockirq */ 152 (void (*)(void))NULL, /* psm_hrtimeinit */ 153 uppc_gethrtime, /* psm_gethrtime */ 154 155 uppc_get_next_processorid, /* psm_get_next_processorid */ 156 (int (*)(processorid_t, caddr_t))NULL, /* psm_cpu_start */ 157 (int (*)(void))NULL, /* psm_post_cpu_start */ 158 uppc_shutdown, /* psm_shutdown */ 159 (int (*)(int, int))NULL, /* psm_get_ipivect */ 160 (void (*)(processorid_t, int))NULL, /* psm_send_ipi */ 161 162 uppc_translate_irq, /* psm_translate_irq */ 163 164 (void (*)(int, char *))NULL, /* psm_notify_error */ 165 (void (*)(int msg))NULL, /* psm_notify_func */ 166 (void (*)(hrtime_t time))NULL, /* psm_timer_reprogram */ 167 (void (*)(void))NULL, /* psm_timer_enable */ 168 (void (*)(void))NULL, /* psm_timer_disable */ 169 (void (*)(void *arg))NULL, /* psm_post_cyclic_setup */ 170 uppc_preshutdown, /* psm_preshutdown */ 171 172 (int (*)(dev_info_t *, ddi_intr_handle_impl_t *, 173 psm_intr_op_t, int *))NULL /* psm_intr_ops */ 174 }; 175 176 177 static struct psm_info uppc_info = { 178 PSM_INFO_VER01_5, /* version */ 179 PSM_OWN_SYS_DEFAULT, /* ownership */ 180 (struct psm_ops *)&uppc_ops, /* operation */ 181 "uppc", /* machine name */ 182 "UniProcessor PC", /* machine descriptions */ 183 }; 184 185 /* 186 * Configuration Data 187 */ 188 189 /* 190 * This is the loadable module wrapper. 191 */ 192 #include <sys/modctl.h> 193 194 static void *uppc_hdlp; 195 196 int 197 _init(void) 198 { 199 return (psm_mod_init(&uppc_hdlp, &uppc_info)); 200 } 201 202 int 203 _fini(void) 204 { 205 return (psm_mod_fini(&uppc_hdlp, &uppc_info)); 206 } 207 208 int 209 _info(struct modinfo *modinfop) 210 { 211 return (psm_mod_info(&uppc_hdlp, &uppc_info, modinfop)); 212 } 213 214 /* 215 * Autoconfiguration Routines 216 */ 217 218 static int 219 uppc_probe(void) 220 { 221 222 223 return (PSM_SUCCESS); 224 } 225 226 static void 227 uppc_softinit(void) 228 { 229 struct standard_pic *pp; 230 int i; 231 232 pp = &pics0; 233 234 235 if (uppc_use_acpi && uppc_init_acpi()) { 236 build_reserved_irqlist((uchar_t *)uppc_reserved_irqlist); 237 for (i = 0; i <= MAX_ISA_IRQ; i++) 238 uppc_irq_shared_table[i] = 0; 239 uppc_enable_acpi = 1; 240 } 241 242 /* 243 * initialize the ipl mask 244 */ 245 for (i = 0; i < (MAXIPL << 1); i += 2) { 246 /* enable slave lines on master */ 247 pp->c_iplmask[i] = 0xff; 248 pp->c_iplmask[i+1] = (0xff & ~(1 << MASTERLINE)); 249 } 250 } 251 252 /*ARGSUSED*/ 253 static int 254 uppc_clkinit(int hertz) 255 { 256 ulong_t clkticks = PIT_HZ / hz; 257 258 if (hertz == 0) 259 return (0); /* One shot mode not supported */ 260 261 /* 262 * program timer 0 263 */ 264 outb(PITCTL_PORT, (PIT_C0|PIT_NDIVMODE|PIT_READMODE)); 265 outb(PITCTR0_PORT, (uchar_t)clkticks); 266 outb(PITCTR0_PORT, (uchar_t)(clkticks>>8)); 267 268 return (NSEC_IN_SEC / hertz); 269 } 270 271 static void 272 uppc_picinit() 273 { 274 picsetup(); 275 276 /* 277 * If a valid SCI is present, manually addspl() 278 * since we're not set-up early enough in boot 279 * to do it "conventionally" (via add_avintr) 280 */ 281 if (uppc_sci >= 0) 282 (void) uppc_addspl(uppc_sci, SCI_IPL, SCI_IPL, SCI_IPL); 283 } 284 285 /*ARGSUSED3*/ 286 static int 287 uppc_addspl(int irqno, int ipl, int min_ipl, int max_ipl) 288 { 289 struct standard_pic *pp; 290 int i; 291 int startidx; 292 uchar_t vectmask; 293 294 if (irqno <= MAX_ISA_IRQ) 295 atomic_add_16(&uppc_irq_shared_table[irqno], 1); 296 297 if (ipl != min_ipl) 298 return (0); 299 300 if (irqno > 7) { 301 vectmask = 1 << (irqno - 8); 302 startidx = (ipl << 1); 303 } else { 304 vectmask = 1 << irqno; 305 startidx = (ipl << 1) + 1; 306 } 307 308 /* 309 * mask intr same or above ipl 310 * level MAXIPL has all intr off as init. default 311 */ 312 pp = &pics0; 313 for (i = startidx; i < (MAXIPL << 1); i += 2) { 314 if (pp->c_iplmask[i] & vectmask) 315 break; 316 pp->c_iplmask[i] |= vectmask; 317 } 318 319 /* 320 * unmask intr below ipl 321 */ 322 for (i = startidx-2; i >= 0; i -= 2) { 323 if (!(pp->c_iplmask[i] & vectmask)) 324 break; 325 pp->c_iplmask[i] &= ~vectmask; 326 } 327 return (0); 328 } 329 330 static int 331 uppc_delspl(int irqno, int ipl, int min_ipl, int max_ipl) 332 { 333 struct standard_pic *pp; 334 int i; 335 uchar_t vectmask; 336 337 if (irqno <= MAX_ISA_IRQ) 338 atomic_add_16(&uppc_irq_shared_table[irqno], -1); 339 340 /* 341 * skip if we are not deleting the last handler 342 * and the ipl is higher than minimum 343 */ 344 if ((max_ipl != PSM_INVALID_IPL) && (ipl >= min_ipl)) 345 return (0); 346 347 if (irqno > 7) { 348 vectmask = 1 << (irqno - 8); 349 i = 0; 350 } else { 351 vectmask = 1 << irqno; 352 i = 1; 353 } 354 355 pp = &pics0; 356 357 /* 358 * check any handlers left for this irqno 359 */ 360 if (max_ipl != PSM_INVALID_IPL) { 361 /* 362 * unmasks all levels below the lowest priority 363 */ 364 i += ((min_ipl - 1) << 1); 365 for (; i >= 0; i -= 2) { 366 if (!(pp->c_iplmask[i] & vectmask)) 367 break; 368 pp->c_iplmask[i] &= ~vectmask; 369 } 370 } else { 371 /* 372 * set mask to all levels 373 */ 374 for (; i < (MAXIPL << 1); i += 2) { 375 if (pp->c_iplmask[i] & vectmask) 376 break; 377 pp->c_iplmask[i] |= vectmask; 378 } 379 } 380 return (0); 381 } 382 383 static processorid_t 384 uppc_get_next_processorid(processorid_t cpu_id) 385 { 386 if (cpu_id == -1) 387 return (0); 388 return (-1); 389 } 390 391 /*ARGSUSED*/ 392 static int 393 uppc_get_clockirq(int ipl) 394 { 395 return (CLOCK_VECTOR); 396 } 397 398 399 static int 400 uppc_init_acpi(void) 401 { 402 int verboseflags = 0; 403 int sci; 404 iflag_t sci_flags; 405 406 /* 407 * Process SCI configuration here; this may return 408 * an error if acpi-user-options has specified 409 * legacy mode (use ACPI without ACPI mode or SCI) 410 */ 411 if (acpica_get_sci(&sci, &sci_flags) != AE_OK) 412 sci = -1; 413 414 /* 415 * Initialize sub-system - if error is returns, ACPI is not 416 * used. 417 */ 418 if (acpica_init() != AE_OK) 419 return (0); 420 421 /* 422 * uppc implies system is in PIC mode; set edge/level 423 * via ELCR based on return value from get_sci; this 424 * will default to level/low if no override present, 425 * as recommended by Intel ACPI CA team. 426 */ 427 if (sci >= 0) { 428 ASSERT((sci_flags.intr_el == INTR_EL_LEVEL) || 429 (sci_flags.intr_el == INTR_EL_EDGE)); 430 431 psm_set_elcr(sci, sci_flags.intr_el == INTR_EL_LEVEL); 432 } 433 434 /* 435 * Remember SCI for later use 436 */ 437 uppc_sci = sci; 438 439 if (uppc_verbose & UPPC_VERBOSE_IRQ_FLAG) 440 verboseflags |= PSM_VERBOSE_IRQ_FLAG; 441 442 if (uppc_verbose & UPPC_VERBOSE_POWEROFF_FLAG) 443 verboseflags |= PSM_VERBOSE_POWEROFF_FLAG; 444 445 if (uppc_verbose & UPPC_VERBOSE_POWEROFF_PAUSE_FLAG) 446 verboseflags |= PSM_VERBOSE_POWEROFF_PAUSE_FLAG; 447 448 if (acpi_psm_init(uppc_info.p_mach_idstring, verboseflags) == 449 ACPI_PSM_FAILURE) { 450 return (0); 451 } 452 453 return (1); 454 } 455 456 457 static void 458 uppc_preshutdown(int cmd, int fcn) 459 { 460 UPPC_VERBOSE_POWEROFF(("uppc_preshutdown(%d,%d);\n", cmd, fcn)); 461 462 } 463 464 static void 465 uppc_shutdown(int cmd, int fcn) 466 { 467 UPPC_VERBOSE_POWEROFF(("uppc_shutdown(%d,%d);\n", cmd, fcn)); 468 469 /* 470 * Return if passed a command other than A_SHUTDOWN or 471 * if we're not using ACPI. 472 */ 473 if ((cmd != A_SHUTDOWN) || (!uppc_enable_acpi)) 474 return; 475 476 /* switch system back into Legacy Mode */ 477 (void) AcpiDisable(); 478 479 if (fcn != AD_POWEROFF) 480 return; 481 482 (void) acpi_poweroff(); 483 } 484 485 static int 486 uppc_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid, 487 int ipin, int *pci_irqp, iflag_t *intr_flagp) 488 { 489 int status; 490 acpi_psm_lnk_t acpipsmlnk; 491 492 if ((status = acpi_get_irq_cache_ent(busid, devid, ipin, pci_irqp, 493 intr_flagp)) == ACPI_PSM_SUCCESS) { 494 UPPC_VERBOSE_IRQ((CE_CONT, "!uppc: Found irqno %d " 495 "from cache for device %s, instance #%d\n", *pci_irqp, 496 ddi_get_name(dip), ddi_get_instance(dip))); 497 return (status); 498 } 499 500 bzero(&acpipsmlnk, sizeof (acpi_psm_lnk_t)); 501 502 if ((status = acpi_translate_pci_irq(dip, ipin, pci_irqp, 503 intr_flagp, &acpipsmlnk)) == ACPI_PSM_FAILURE) { 504 UPPC_VERBOSE_IRQ((CE_CONT, "!uppc: " 505 " acpi_translate_pci_irq failed for device %s, instance" 506 " #%d\n", ddi_get_name(dip), ddi_get_instance(dip))); 507 508 return (status); 509 } 510 511 if (status == ACPI_PSM_PARTIAL && acpipsmlnk.lnkobj != NULL) { 512 status = uppc_acpi_irq_configure(&acpipsmlnk, dip, pci_irqp, 513 intr_flagp); 514 if (status != ACPI_PSM_SUCCESS) { 515 status = acpi_get_current_irq_resource(&acpipsmlnk, 516 pci_irqp, intr_flagp); 517 } 518 } 519 520 if (status == ACPI_PSM_SUCCESS) { 521 acpi_new_irq_cache_ent(busid, devid, ipin, *pci_irqp, 522 intr_flagp, &acpipsmlnk); 523 psm_set_elcr(*pci_irqp, 1); /* set IRQ to PCI mode */ 524 525 UPPC_VERBOSE_IRQ((CE_CONT, "!uppc: [ACPI] " 526 "new irq %d for device %s, instance #%d\n", 527 *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip))); 528 } 529 530 return (status); 531 } 532 533 /* 534 * Configures the irq for the interrupt link device identified by 535 * acpipsmlnkp. 536 * 537 * Gets the current and the list of possible irq settings for the 538 * device. If uppc_unconditional_srs is not set, and the current 539 * resource setting is in the list of possible irq settings, 540 * current irq resource setting is passed to the caller. 541 * 542 * Otherwise, picks an irq number from the list of possible irq 543 * settings, and sets the irq of the device to this value. 544 * If prefer_crs is set, among a set of irq numbers in the list that have 545 * the least number of devices sharing the interrupt, we pick current irq 546 * resource setting if it is a member of this set. 547 * 548 * Passes the irq number in the value pointed to by pci_irqp, and 549 * polarity and sensitivity in the structure pointed to by dipintrflagp 550 * to the caller. 551 * 552 * Note that if setting the irq resource failed, but successfuly obtained 553 * the current irq resource settings, passes the current irq resources 554 * and considers it a success. 555 * 556 * Returns: 557 * ACPI_PSM_SUCCESS on success. 558 * 559 * ACPI_PSM_FAILURE if an error occured during the configuration or 560 * if a suitable irq was not found for this device, or if setting the 561 * irq resource and obtaining the current resource fails. 562 * 563 */ 564 static int 565 uppc_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip, 566 int *pci_irqp, iflag_t *dipintr_flagp) 567 { 568 int i, min_share, foundnow, done = 0; 569 int32_t irq; 570 int32_t share_irq = -1; 571 int32_t chosen_irq = -1; 572 int cur_irq = -1; 573 acpi_irqlist_t *irqlistp; 574 acpi_irqlist_t *irqlistent; 575 576 if ((acpi_get_possible_irq_resources(acpipsmlnkp, &irqlistp)) 577 == ACPI_PSM_FAILURE) { 578 UPPC_VERBOSE_IRQ((CE_WARN, "!uppc: Unable to determine " 579 "or assign IRQ for device %s, instance #%d: The system was " 580 "unable to get the list of potential IRQs from ACPI.", 581 ddi_get_name(dip), ddi_get_instance(dip))); 582 583 return (ACPI_PSM_FAILURE); 584 } 585 586 if ((acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq, 587 dipintr_flagp) == ACPI_PSM_SUCCESS) && (!uppc_unconditional_srs) && 588 (cur_irq > 0)) { 589 590 if (acpi_irqlist_find_irq(irqlistp, cur_irq, NULL) 591 == ACPI_PSM_SUCCESS) { 592 593 acpi_free_irqlist(irqlistp); 594 ASSERT(pci_irqp != NULL); 595 *pci_irqp = cur_irq; 596 return (ACPI_PSM_SUCCESS); 597 } 598 UPPC_VERBOSE_IRQ((CE_WARN, "!uppc: Could not find the " 599 "current irq %d for device %s, instance #%d in ACPI's " 600 "list of possible irqs for this device. Picking one from " 601 " the latter list.", cur_irq, ddi_get_name(dip), 602 ddi_get_instance(dip))); 603 604 } 605 606 irqlistent = irqlistp; 607 min_share = 255; 608 609 while (irqlistent != NULL) { 610 611 for (foundnow = 0, i = 0; i < irqlistent->num_irqs; i++) { 612 613 irq = irqlistp->irqs[i]; 614 615 if ((irq > MAX_ISA_IRQ) || 616 (irqlistent->intr_flags.intr_el == INTR_EL_EDGE) || 617 (irq == 0)) 618 continue; 619 620 if (uppc_reserved_irqlist[irq]) 621 continue; 622 623 if (uppc_irq_shared_table[irq] == 0) { 624 chosen_irq = irq; 625 foundnow = 1; 626 if (!(uppc_prefer_crs) || (irq == cur_irq)) { 627 done = 1; 628 break; 629 } 630 } 631 632 if ((uppc_irq_shared_table[irq] < min_share) || 633 ((uppc_irq_shared_table[irq] == min_share) && 634 (cur_irq == irq) && (uppc_prefer_crs))) { 635 min_share = uppc_irq_shared_table[irq]; 636 share_irq = irq; 637 foundnow = 1; 638 } 639 } 640 641 /* If we found an IRQ in the inner loop, save the details */ 642 if (foundnow && ((chosen_irq != -1) || (share_irq != -1))) { 643 /* 644 * Copy the acpi_prs_private_t and flags from this 645 * irq list entry, since we found an irq from this 646 * entry. 647 */ 648 acpipsmlnkp->acpi_prs_prv = irqlistent->acpi_prs_prv; 649 *dipintr_flagp = irqlistent->intr_flags; 650 } 651 652 if (done) 653 break; 654 655 /* Load the next entry in the irqlist */ 656 irqlistent = irqlistent->next; 657 } 658 659 acpi_free_irqlist(irqlistp); 660 661 if (chosen_irq != -1) 662 irq = chosen_irq; 663 else if (share_irq != -1) 664 irq = share_irq; 665 else { 666 UPPC_VERBOSE_IRQ((CE_CONT, "!uppc: Could not find a " 667 "suitable irq from the list of possible irqs for device " 668 "%s, instance #%d in ACPI's list of possible\n", 669 ddi_get_name(dip), ddi_get_instance(dip))); 670 671 return (ACPI_PSM_FAILURE); 672 } 673 674 675 UPPC_VERBOSE_IRQ((CE_CONT, "!uppc: Setting irq %d for device %s " 676 "instance #%d\n", irq, ddi_get_name(dip), ddi_get_instance(dip))); 677 678 if ((acpi_set_irq_resource(acpipsmlnkp, irq)) == ACPI_PSM_SUCCESS) { 679 /* 680 * setting irq was successful, check to make sure CRS 681 * reflects that. If CRS does not agree with what we 682 * set, return the irq that was set. 683 */ 684 685 if (acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq, 686 dipintr_flagp) == ACPI_PSM_SUCCESS) { 687 688 if (cur_irq != irq) 689 UPPC_VERBOSE_IRQ((CE_WARN, "!uppc: " 690 "IRQ resource set (irqno %d) for device %s " 691 "instance #%d, differs from current " 692 "setting irqno %d", 693 irq, ddi_get_name(dip), 694 ddi_get_instance(dip), cur_irq)); 695 } 696 /* 697 * return the irq that was set, and not what CRS reports, 698 * since CRS has been seen to be bogus on some systems 699 */ 700 cur_irq = irq; 701 } else { 702 UPPC_VERBOSE_IRQ((CE_WARN, "!uppc: set resource irq %d " 703 "failed for device %s instance #%d", 704 irq, ddi_get_name(dip), ddi_get_instance(dip))); 705 if (cur_irq == -1) 706 return (ACPI_PSM_FAILURE); 707 } 708 709 ASSERT(pci_irqp != NULL); 710 *pci_irqp = cur_irq; 711 return (ACPI_PSM_SUCCESS); 712 } 713 714 715 /*ARGSUSED*/ 716 static int 717 uppc_translate_irq(dev_info_t *dip, int irqno) 718 { 719 char dev_type[16]; 720 int dev_len, pci_irq, devid, busid; 721 ddi_acc_handle_t cfg_handle; 722 uchar_t ipin, iline; 723 iflag_t intr_flag; 724 725 if (dip == NULL) { 726 UPPC_VERBOSE_IRQ((CE_CONT, "!uppc: irqno = %d" 727 " dip = NULL\n", irqno)); 728 return (irqno); 729 } 730 731 if (!uppc_enable_acpi) { 732 return (irqno); 733 } 734 735 dev_len = sizeof (dev_type); 736 if (ddi_getlongprop_buf(DDI_DEV_T_ANY, ddi_get_parent(dip), 737 DDI_PROP_DONTPASS, "device_type", (caddr_t)dev_type, 738 &dev_len) != DDI_PROP_SUCCESS) { 739 UPPC_VERBOSE_IRQ((CE_CONT, "!uppc: irqno %d" 740 "device %s instance %d no device_type\n", irqno, 741 ddi_get_name(dip), ddi_get_instance(dip))); 742 return (irqno); 743 } 744 745 if ((strcmp(dev_type, "pci") == 0) || 746 (strcmp(dev_type, "pciex") == 0)) { 747 748 /* pci device */ 749 if (acpica_get_bdf(dip, &busid, &devid, NULL) != 0) 750 return (irqno); 751 752 if (pci_config_setup(dip, &cfg_handle) != DDI_SUCCESS) 753 return (irqno); 754 755 ipin = pci_config_get8(cfg_handle, PCI_CONF_IPIN) - PCI_INTA; 756 iline = pci_config_get8(cfg_handle, PCI_CONF_ILINE); 757 if (uppc_acpi_translate_pci_irq(dip, busid, devid, 758 ipin, &pci_irq, &intr_flag) == ACPI_PSM_SUCCESS) { 759 760 UPPC_VERBOSE_IRQ((CE_CONT, "!uppc: [ACPI] new irq " 761 "%d old irq %d device %s, instance %d\n", pci_irq, 762 irqno, ddi_get_name(dip), ddi_get_instance(dip))); 763 764 /* 765 * Make sure pci_irq is within range. 766 * Otherwise, fall through and return irqno. 767 */ 768 if (pci_irq <= MAX_ISA_IRQ) { 769 if (iline != pci_irq) { 770 /* 771 * Update the device's ILINE byte, 772 * in case uppc_acpi_translate_pci_irq 773 * has choosen a different pci_irq 774 * than the BIOS has configured. 775 * Some chipsets use the value in 776 * ILINE to control interrupt routing, 777 * in conflict with the PCI spec. 778 */ 779 pci_config_put8(cfg_handle, 780 PCI_CONF_ILINE, pci_irq); 781 } 782 pci_config_teardown(&cfg_handle); 783 return (pci_irq); 784 } 785 } 786 pci_config_teardown(&cfg_handle); 787 788 /* FALLTHRU to common case - returning irqno */ 789 } else { 790 /* non-PCI; assumes ISA-style edge-triggered */ 791 psm_set_elcr(irqno, 0); /* set IRQ to ISA mode */ 792 793 UPPC_VERBOSE_IRQ((CE_CONT, "!uppc: non-pci," 794 "irqno %d device %s instance %d\n", irqno, 795 ddi_get_name(dip), ddi_get_instance(dip))); 796 } 797 798 return (irqno); 799 } 800 801 /* 802 * uppc_intr_enter() raises the ipl to the level of the current interrupt, 803 * and sends EOI to the pics. 804 * If interrupt is 7 or 15 and not spurious interrupt, send specific EOI 805 * else send non-specific EOI 806 * uppc_intr_enter() returns the new priority level, 807 * or -1 for spurious interrupt 808 */ 809 static int 810 uppc_intr_enter(int ipl, int *vector) 811 { 812 int newipl; 813 int intno; 814 815 intno = (*vector); 816 817 ASSERT(intno < 256); 818 819 newipl = autovect[intno].avh_hi_pri; 820 821 /* 822 * During wait_till_seen() periods when interrupt vector is being 823 * removed in remove_av(), the removed hardware interrupt could 824 * trigger and got here with newipl 0. It has to send EOI 825 * as usual but no need to call setspl and returns -1 like spurious. 826 */ 827 if ((intno & 7) != 7) { 828 if (newipl) 829 uppc_setspl(newipl); 830 outb(MCMD_PORT, PIC_NSEOI); 831 if (intno >= 8) { 832 outb(SCMD_PORT, PIC_NSEOI); 833 } 834 } else { /* int was 7 or 15 */ 835 if (newipl && newipl <= ipl) { /* Check for spurious int */ 836 if (intno != 7) 837 outb(MCMD_PORT, PIC_NSEOI); 838 return (-1); /* Spurious int */ 839 } else { 840 if (newipl) 841 uppc_setspl(newipl); 842 if (intno != 7) { 843 outb(MCMD_PORT, PIC_NSEOI); 844 outb(SCMD_PORT, PIC_SEOI_LVL7); 845 } else { 846 outb(MCMD_PORT, PIC_SEOI_LVL7); 847 } 848 } 849 } 850 851 if (newipl) 852 return (newipl); 853 else 854 return (-1); /* not real spurious int */ 855 } 856 857 /* 858 * uppc_intr_exit() restores the old interrupt 859 * priority level after processing an interrupt. 860 * It is called with interrupts disabled, and does not enable interrupts. 861 */ 862 /* ARGSUSED */ 863 static void 864 uppc_intr_exit(int ipl, int vector) 865 { 866 uppc_setspl(ipl); 867 } 868 869 /* 870 * uppc_setspl() loads new interrupt masks into the pics 871 * based on input ipl. 872 */ 873 /* ARGSUSED */ 874 static void 875 uppc_setspl(int ipl) 876 { 877 struct standard_pic *pp; 878 uint8_t smask, mmask; 879 uint8_t cursmask, curmmask; 880 881 pp = &pics0; 882 smask = pp->c_iplmask[ipl * 2]; 883 mmask = pp->c_iplmask[ipl * 2 + 1]; 884 cursmask = pp->c_curmask[0]; 885 curmmask = pp->c_curmask[1]; 886 if (cursmask == smask && curmmask == mmask) 887 return; 888 pp->c_curmask[0] = smask; 889 pp->c_curmask[1] = mmask; 890 891 if (cursmask != smask) { 892 /* 893 * program new slave pic mask 894 */ 895 outb(SIMR_PORT, smask); 896 } 897 if (curmmask != mmask) { 898 /* 899 * program new master pic mask 900 */ 901 outb(MIMR_PORT, mmask); 902 } 903 /* 904 * read master to allow pics to settle 905 */ 906 (void) inb(MIMR_PORT); 907 } 908 909 /* 910 * uppc_gethrtime() returns high resolution timer value 911 */ 912 static hrtime_t 913 uppc_gethrtime() 914 { 915 hrtime_t timeval, temp; 916 unsigned int ctr0; 917 ulong_t oflags; 918 919 oflags = intr_clear(); /* disable ints */ 920 lock_set(&uppc_gethrtime_lock); 921 retry: 922 temp = hrtime_base; 923 outb(PITCTL_PORT, 0); /* latch counter 0 */ 924 /* 925 * read counter 0 926 */ 927 ctr0 = inb(PITCTR0_PORT); 928 ctr0 |= inb(PITCTR0_PORT) << 8; 929 timeval = (hrtime_t)ctr0 * (NANOSEC / PIT_HZ); 930 if (temp != hrtime_base) 931 goto retry; 932 timeval -= temp; 933 if (timeval < uppc_lasthrtime) 934 timeval = uppc_lasthrtime; 935 uppc_lasthrtime = timeval; 936 lock_clear(&uppc_gethrtime_lock); 937 intr_restore(oflags); 938 return (timeval); 939 } 940