1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PCIFM_H 27 #define _SYS_PCIFM_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #include <sys/dditypes.h> /* for ddi_acc_handle_t */ 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 38 /* 39 * PCI device type defines. 40 */ 41 #define PCI_BRIDGE_DEV 0x02 42 #define PCIX_DEV 0x04 43 #define PCIEX_DEV 0x08 44 #define PCIEX_ADV_DEV 0x10 45 #define PCIEX_RC_DEV 0x20 46 #define PCIEX_2PCI_DEV 0x40 47 #define PCIEX_SWITCH_DEV 0x80 48 49 /* 50 * PCI and PCI-X valid flags 51 */ 52 #define PCI_ERR_STATUS_VALID 0x1 53 #define PCI_BDG_SEC_STAT_VALID 0x2 54 #define PCI_BDG_CTRL_VALID 0x4 55 #define PCIX_ERR_STATUS_VALID 0x8 56 #define PCIX_ERR_ECC_STS_VALID 0x10 57 #define PCIX_ERR_S_ECC_STS_VALID 0x20 58 #define PCIX_BDG_STATUS_VALID 0x40 59 #define PCIX_BDG_SEC_STATUS_VALID 0x80 60 61 /* 62 * PCI Express valid flags 63 */ 64 #define PCIE_ERR_STATUS_VALID 0x1 65 #define PCIE_CE_STATUS_VALID 0x2 66 #define PCIE_UE_STATUS_VALID 0x4 67 #define PCIE_RC_ERR_STATUS_VALID 0x8 68 #define PCIE_SUE_STATUS_VALID 0x10 69 #define PCIE_SUE_HDR_VALID 0x20 70 #define PCIE_UE_HDR_VALID 0x40 71 #define PCIE_SRC_ID_VALID 0x80 72 73 /* 74 * PCI(-X) structures used (by pci_ereport_setup, pci_ereport_post, and 75 * pci_ereport_teardown) to gather and report errors detected by PCI(-X) 76 * compliant devices. 77 */ 78 typedef struct pci_bdg_error_regs { 79 uint16_t pci_bdg_vflags; /* status valid bits */ 80 uint16_t pci_bdg_sec_stat; /* PCI secondary status reg */ 81 uint16_t pci_bdg_ctrl; /* PCI bridge control reg */ 82 } pci_bdg_error_regs_t; 83 84 typedef struct pci_error_regs { 85 uint16_t pci_vflags; /* status valid bits */ 86 uint8_t pci_cap_ptr; /* PCI Capability pointer */ 87 uint16_t pci_err_status; /* pci status register */ 88 uint16_t pci_cfg_comm; /* pci command register */ 89 pci_bdg_error_regs_t *pci_bdg_regs; 90 } pci_error_regs_t; 91 92 typedef struct pci_erpt { 93 ddi_acc_handle_t pe_hdl; /* Config space access handle */ 94 uint64_t pe_dflags; /* Device type flags */ 95 uint16_t pe_bdf; /* bus/device/function of device */ 96 pci_error_regs_t *pe_pci_regs; /* PCI generic error registers */ 97 void *pe_regs; /* Pointer to extended error regs */ 98 } pci_erpt_t; 99 100 typedef struct pcix_ecc_regs { 101 uint16_t pcix_ecc_vflags; /* pcix ecc valid flags */ 102 uint16_t pcix_ecc_bdf; /* pcix ecc bdf */ 103 uint32_t pcix_ecc_ctlstat; /* pcix ecc control status reg */ 104 uint32_t pcix_ecc_fstaddr; /* pcix ecc first address reg */ 105 uint32_t pcix_ecc_secaddr; /* pcix ecc second address reg */ 106 uint32_t pcix_ecc_attr; /* pcix ecc attributes reg */ 107 } pcix_ecc_regs_t; 108 109 typedef struct pcix_error_regs { 110 uint16_t pcix_vflags; /* pcix valid flags */ 111 uint8_t pcix_cap_ptr; /* pcix capability pointer */ 112 uint16_t pcix_ver; /* pcix version */ 113 uint16_t pcix_command; /* pcix command register */ 114 uint32_t pcix_status; /* pcix status register */ 115 pcix_ecc_regs_t *pcix_ecc_regs; /* pcix ecc registers */ 116 } pcix_error_regs_t; 117 118 typedef struct pcix_bdg_error_regs { 119 uint16_t pcix_bdg_vflags; /* pcix valid flags */ 120 uint8_t pcix_bdg_cap_ptr; /* pcix bridge capability pointer */ 121 uint16_t pcix_bdg_ver; /* pcix version */ 122 uint16_t pcix_bdg_sec_stat; /* pcix bridge secondary status reg */ 123 uint32_t pcix_bdg_stat; /* pcix bridge status reg */ 124 pcix_ecc_regs_t *pcix_bdg_ecc_regs[2]; /* pcix ecc registers */ 125 } pcix_bdg_error_regs_t; 126 127 /* 128 * PCI Express error register structures used (by pci_ereport_setup, 129 * pci_ereport_post, and pci_ereport_teardown) to gather and report errors 130 * detected by PCI Express compliant devices. 131 */ 132 typedef struct pcie_adv_bdg_error_regs { 133 uint32_t pcie_sue_status; /* pcie bridge secondary ue status */ 134 uint32_t pcie_sue_mask; /* pcie bridge secondary ue mask */ 135 uint32_t pcie_sue_sev; /* pcie bridge secondary ue severity */ 136 uint32_t pcie_sue_hdr0; /* pcie bridge secondary ue hdr log */ 137 uint32_t pcie_sue_hdr[3]; /* pcie bridge secondary ue hdr log */ 138 } pcie_adv_bdg_error_regs_t; 139 140 typedef struct pcie_adv_rc_error_regs { 141 uint32_t pcie_rc_err_status; /* pcie root complex error status reg */ 142 uint32_t pcie_rc_err_cmd; /* pcie root complex error cmd reg */ 143 uint16_t pcie_rc_ce_src_id; /* pcie root complex ce source id */ 144 uint16_t pcie_rc_ue_src_id; /* pcie root complex ue source id */ 145 } pcie_adv_rc_error_regs_t; 146 147 typedef struct pcie_adv_error_regs { 148 uint16_t pcie_adv_vflags; /* pcie advanced error valid flags */ 149 uint16_t pcie_adv_cap_ptr; /* pcie advanced capability pointer */ 150 uint16_t pcie_adv_bdf; /* pcie bdf */ 151 uint32_t pcie_adv_ctl; /* pcie advanced control reg */ 152 uint32_t pcie_ce_status; /* pcie ce error status reg */ 153 uint32_t pcie_ce_mask; /* pcie ce error mask reg */ 154 uint32_t pcie_ue_status; /* pcie ue error status reg */ 155 uint32_t pcie_ue_mask; /* pcie ue error mask reg */ 156 uint32_t pcie_ue_sev; /* pcie ue error severity reg */ 157 uint32_t pcie_ue_hdr0; /* pcie ue header log */ 158 uint32_t pcie_ue_hdr[3]; /* pcie ue header log */ 159 pcie_adv_bdg_error_regs_t *pcie_adv_bdg_regs; /* pcie bridge regs */ 160 pcie_adv_rc_error_regs_t *pcie_adv_rc_regs; /* pcie rc regs */ 161 } pcie_adv_error_regs_t; 162 163 typedef struct pcie_rc_error_regs { 164 uint32_t pcie_rc_status; /* root complex status register */ 165 uint16_t pcie_rc_ctl; /* root complex control register */ 166 } pcie_rc_error_regs_t; 167 168 typedef struct pcie_error_regs { 169 uint16_t pcie_vflags; /* pcie valid flags */ 170 uint8_t pcie_cap_ptr; /* PCI Express capability pointer */ 171 uint16_t pcie_cap; /* PCI Express capability register */ 172 uint16_t pcie_err_status; /* pcie device status register */ 173 uint16_t pcie_err_ctl; /* pcie error control register */ 174 uint16_t pcie_dev_cap; /* pcie device capabilities register */ 175 pcix_bdg_error_regs_t *pcix_bdg_regs; /* pcix bridge regs */ 176 pcie_rc_error_regs_t *pcie_rc_regs; /* pcie root complex regs */ 177 pcie_adv_error_regs_t *pcie_adv_regs; /* pcie advanced err regs */ 178 } pcie_error_regs_t; 179 180 /* 181 * pcie bus specific structure 182 */ 183 184 typedef struct pci_fme_bus_specific { 185 int pci_bs_type; 186 uint64_t pci_bs_addr; 187 uint16_t pci_bs_bdf; 188 int pci_bs_flags; 189 } pci_fme_bus_specific_t; 190 191 #define PCI_BS_ADDR_VALID 1 192 #define PCI_BS_BDF_VALID 2 193 194 /* 195 * target error queue defines 196 */ 197 #define TARGET_MAX_ERRS 6 198 #define TGT_PCI_SPACE_UNKNOWN 4 199 200 typedef struct pci_target_err { 201 uint64_t tgt_err_addr; 202 uint64_t tgt_err_ena; 203 uint64_t tgt_pci_addr; 204 uint32_t tgt_pci_space; 205 dev_info_t *tgt_dip; 206 char *tgt_err_class; 207 char *tgt_bridge_type; 208 } pci_target_err_t; 209 210 #define PCI_FM_SEV_INC(x) ((x) == DDI_FM_FATAL) ? fatal++ :\ 211 (((x) == DDI_FM_NONFATAL) ? nonfatal++ :\ 212 (((x) == DDI_FM_UNKNOWN) ? unknown++ : ok++)); 213 214 #define PCIEX_TYPE_CE 0x0 215 #define PCIEX_TYPE_UE 0x1 216 #define PCIEX_TYPE_GEN 0x2 217 #define PCIEX_TYPE_RC_UE_MSG 0x3 218 #define PCIEX_TYPE_RC_CE_MSG 0x4 219 #define PCIEX_TYPE_RC_MULT_MSG 0x5 220 221 #ifdef __cplusplus 222 } 223 #endif 224 225 #endif /* _SYS_PCIFM_H */ 226