1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PCIE_IMPL_H 27 #define _SYS_PCIE_IMPL_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #include <sys/pcie.h> 34 35 #define PCI_GET_BDF(dip) \ 36 PCIE_DIP2BUS(dip)->bus_bdf 37 #define PCI_GET_SEC_BUS(dip) \ 38 PCIE_DIP2BUS(dip)->bus_bdg_secbus 39 #define PCI_GET_PCIE2PCI_SECBUS(dip) \ 40 PCIE_DIP2BUS(dip)->bus_bdg_secbus 41 42 #define DEVI_PORT_TYPE_PCI \ 43 ((PCI_CLASS_BRIDGE << 16) | (PCI_BRIDGE_PCI << 8) | \ 44 PCI_BRIDGE_PCI_IF_PCI2PCI) 45 46 #define PCIE_DIP2BUS(dip) \ 47 (ndi_port_type(dip, B_TRUE, DEVI_PORT_TYPE_PCI) ? \ 48 PCIE_DIP2UPBUS(dip) : \ 49 ndi_port_type(dip, B_FALSE, DEVI_PORT_TYPE_PCI) ? \ 50 PCIE_DIP2DOWNBUS(dip) : NULL) 51 52 #define PCIE_DIP2UPBUS(dip) \ 53 ((pcie_bus_t *)ndi_get_bus_private(dip, B_TRUE)) 54 #define PCIE_DIP2DOWNBUS(dip) \ 55 ((pcie_bus_t *)ndi_get_bus_private(dip, B_FALSE)) 56 #define PCIE_DIP2PFD(dip) (PCIE_DIP2BUS(dip))->bus_pfd 57 #define PCIE_PFD2BUS(pfd_p) pfd_p->pe_bus_p 58 #define PCIE_PFD2DIP(pfd_p) PCIE_PFD2BUS(pfd_p)->bus_dip 59 #define PCIE_BUS2DIP(bus_p) bus_p->bus_dip 60 #define PCIE_BUS2PFD(bus_p) PCIE_DIP2PFD(PCIE_BUS2DIP(bus_p)) 61 62 #define PCIE_IS_PCIE(bus_p) (bus_p->bus_pcie_off) 63 #define PCIE_IS_PCIX(bus_p) (bus_p->bus_pcix_off) 64 #define PCIE_IS_PCI(bus_p) (!PCIE_IS_PCIE(bus_p)) 65 #define PCIE_HAS_AER(bus_p) (bus_p->bus_aer_off) 66 /* IS_ROOT = is RC or RP */ 67 #define PCIE_IS_ROOT(bus_p) (PCIE_IS_RC(bus_p) || PCIE_IS_RP(bus_p)) 68 69 #define PCIE_IS_HOTPLUG_CAPABLE(dip) \ 70 (PCIE_DIP2BUS(dip)->bus_hp_sup_modes) 71 72 #define PCIE_IS_HOTPLUG_ENABLED(dip) \ 73 ((PCIE_DIP2BUS(dip)->bus_hp_curr_mode == PCIE_PCI_HP_MODE) || \ 74 (PCIE_DIP2BUS(dip)->bus_hp_curr_mode == PCIE_NATIVE_HP_MODE)) 75 76 /* 77 * This is a pseudo pcie "device type", but it's needed to explain describe 78 * nodes such as PX and NPE, which aren't really PCI devices but do control or 79 * interaction with PCI error handling. 80 */ 81 #define PCIE_IS_RC(bus_p) \ 82 (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_RC_PSEUDO) 83 #define PCIE_IS_RP(bus_p) \ 84 ((bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_ROOT) && \ 85 PCIE_IS_PCIE(bus_p)) 86 #define PCIE_IS_SWU(bus_p) \ 87 (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_UP) 88 #define PCIE_IS_SWD(bus_p) \ 89 (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_DOWN) 90 #define PCIE_IS_SW(bus_p) \ 91 (PCIE_IS_SWU(bus_p) || PCIE_IS_SWD(bus_p)) 92 #define PCIE_IS_BDG(bus_p) (bus_p->bus_hdr_type == PCI_HEADER_ONE) 93 #define PCIE_IS_PCI_BDG(bus_p) (PCIE_IS_PCI(bus_p) && PCIE_IS_BDG(bus_p)) 94 #define PCIE_IS_PCIE_BDG(bus_p) \ 95 (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_PCIE2PCI) 96 #define PCIE_IS_PCI2PCIE(bus_p) \ 97 (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_PCI2PCIE) 98 #define PCIE_IS_PCIE_SEC(bus_p) \ 99 (PCIE_IS_PCIE(bus_p) && PCIE_IS_BDG(bus_p) && !PCIE_IS_PCIE_BDG(bus_p)) 100 #define PCIX_ECC_VERSION_CHECK(bus_p) \ 101 ((bus_p->bus_ecc_ver == PCI_PCIX_VER_1) || \ 102 (bus_p->bus_ecc_ver == PCI_PCIX_VER_2)) 103 104 #define PCIE_VENID(bus_p) (bus_p->bus_dev_ven_id & 0xffff) 105 #define PCIE_DEVID(bus_p) ((bus_p->bus_dev_ven_id >> 16) & 0xffff) 106 107 /* PCIE Cap/AER shortcuts */ 108 #define PCIE_GET(sz, bus_p, off) \ 109 pci_config_get ## sz(bus_p->bus_cfg_hdl, off) 110 #define PCIE_PUT(sz, bus_p, off, val) \ 111 pci_config_put ## sz(bus_p->bus_cfg_hdl, off, val) 112 #define PCIE_CAP_GET(sz, bus_p, off) \ 113 PCI_CAP_GET ## sz(bus_p->bus_cfg_hdl, NULL, bus_p->bus_pcie_off, off) 114 #define PCIE_CAP_PUT(sz, bus_p, off, val) \ 115 PCI_CAP_PUT ## sz(bus_p->bus_cfg_hdl, NULL, bus_p->bus_pcie_off, off, \ 116 val) 117 #define PCIE_AER_GET(sz, bus_p, off) \ 118 PCI_XCAP_GET ## sz(bus_p->bus_cfg_hdl, NULL, bus_p->bus_aer_off, off) 119 #define PCIE_AER_PUT(sz, bus_p, off, val) \ 120 PCI_XCAP_PUT ## sz(bus_p->bus_cfg_hdl, NULL, bus_p->bus_aer_off, off, \ 121 val) 122 #define PCIX_CAP_GET(sz, bus_p, off) \ 123 PCI_CAP_GET ## sz(bus_p->bus_cfg_hdl, NULL, bus_p->bus_pcix_off, off) 124 #define PCIX_CAP_PUT(sz, bus_p, off, val) \ 125 PCI_CAP_PUT ## sz(bus_p->bus_cfg_hdl, NULL, bus_p->bus_pcix_off, off, \ 126 val) 127 128 /* Translate PF error return values to DDI_FM values */ 129 #define PF_ERR2DDIFM_ERR(sts) \ 130 (sts & PF_ERR_FATAL_FLAGS ? DDI_FM_FATAL : \ 131 (sts == PF_ERR_NO_ERROR ? DDI_FM_OK : DDI_FM_NONFATAL)) 132 133 /* 134 * The following flag is used for Broadcom 5714/5715 bridge prefetch issue. 135 * This flag will be used both by px and pcieb nexus drivers. 136 */ 137 #define PX_DMAI_FLAGS_MAP_BUFZONE 0x40000 138 139 /* 140 * PCI(e/-X) structures used to to gather and report errors detected by 141 * PCI(e/-X) compliant devices. These registers only contain "dynamic" data. 142 * Static data such as Capability Offsets and Version #s is saved in the parent 143 * private data. 144 */ 145 #define PCI_ERR_REG(pfd_p) pfd_p->pe_pci_regs 146 #define PCI_BDG_ERR_REG(pfd_p) PCI_ERR_REG(pfd_p)->pci_bdg_regs 147 #define PCIX_ERR_REG(pfd_p) pfd_p->pe_ext.pe_pcix_regs 148 #define PCIX_ECC_REG(pfd_p) PCIX_ERR_REG(pfd_p)->pcix_ecc_regs 149 #define PCIX_BDG_ERR_REG(pfd_p) pfd_p->pe_pcix_bdg_regs 150 #define PCIX_BDG_ECC_REG(pfd_p, n) PCIX_BDG_ERR_REG(pfd_p)->pcix_bdg_ecc_regs[n] 151 #define PCIE_ERR_REG(pfd_p) pfd_p->pe_ext.pe_pcie_regs 152 #define PCIE_RP_REG(pfd_p) PCIE_ERR_REG(pfd_p)->pcie_rp_regs 153 #define PCIE_ROOT_FAULT(pfd_p) pfd_p->pe_root_fault 154 #define PCIE_ADV_REG(pfd_p) PCIE_ERR_REG(pfd_p)->pcie_adv_regs 155 #define PCIE_ADV_HDR(pfd_p, n) PCIE_ADV_REG(pfd_p)->pcie_ue_hdr[n] 156 #define PCIE_ADV_BDG_REG(pfd_p) \ 157 PCIE_ADV_REG(pfd_p)->pcie_ext.pcie_adv_bdg_regs 158 #define PCIE_ADV_BDG_HDR(pfd_p, n) PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_hdr[n] 159 #define PCIE_ADV_RP_REG(pfd_p) \ 160 PCIE_ADV_REG(pfd_p)->pcie_ext.pcie_adv_rp_regs 161 #define PFD_IS_ROOT(pfd_p) PCIE_IS_ROOT(PCIE_PFD2BUS(pfd_p)) 162 #define PFD_IS_RC(pfd_p) PCIE_IS_RC(PCIE_PFD2BUS(pfd_p)) 163 #define PFD_IS_RP(pfd_p) PCIE_IS_RP(PCIE_PFD2BUS(pfd_p)) 164 165 /* bus_hp_mode field */ 166 typedef enum { 167 PCIE_NONE_HP_MODE = 0x0, 168 PCIE_ACPI_HP_MODE = 0x1, 169 PCIE_PCI_HP_MODE = 0x2, 170 PCIE_NATIVE_HP_MODE = 0x4 171 } pcie_hp_mode_t; 172 173 typedef struct pf_pci_bdg_err_regs { 174 uint16_t pci_bdg_sec_stat; /* PCI secondary status reg */ 175 uint16_t pci_bdg_ctrl; /* PCI bridge control reg */ 176 } pf_pci_bdg_err_regs_t; 177 178 typedef struct pf_pci_err_regs { 179 uint16_t pci_err_status; /* pci status register */ 180 uint16_t pci_cfg_comm; /* pci command register */ 181 pf_pci_bdg_err_regs_t *pci_bdg_regs; 182 } pf_pci_err_regs_t; 183 184 typedef struct pf_pcix_ecc_regs { 185 uint32_t pcix_ecc_ctlstat; /* pcix ecc control status reg */ 186 uint32_t pcix_ecc_fstaddr; /* pcix ecc first address reg */ 187 uint32_t pcix_ecc_secaddr; /* pcix ecc second address reg */ 188 uint32_t pcix_ecc_attr; /* pcix ecc attributes reg */ 189 } pf_pcix_ecc_regs_t; 190 191 typedef struct pf_pcix_err_regs { 192 uint16_t pcix_command; /* pcix command register */ 193 uint32_t pcix_status; /* pcix status register */ 194 pf_pcix_ecc_regs_t *pcix_ecc_regs; /* pcix ecc registers */ 195 } pf_pcix_err_regs_t; 196 197 typedef struct pf_pcix_bdg_err_regs { 198 uint16_t pcix_bdg_sec_stat; /* pcix bridge secondary status reg */ 199 uint32_t pcix_bdg_stat; /* pcix bridge status reg */ 200 pf_pcix_ecc_regs_t *pcix_bdg_ecc_regs[2]; /* pcix ecc registers */ 201 } pf_pcix_bdg_err_regs_t; 202 203 typedef struct pf_pcie_adv_bdg_err_regs { 204 uint32_t pcie_sue_ctl; /* pcie bridge secondary ue control */ 205 uint32_t pcie_sue_status; /* pcie bridge secondary ue status */ 206 uint32_t pcie_sue_mask; /* pcie bridge secondary ue mask */ 207 uint32_t pcie_sue_sev; /* pcie bridge secondary ue severity */ 208 uint32_t pcie_sue_hdr[4]; /* pcie bridge secondary ue hdr log */ 209 uint32_t pcie_sue_tgt_trans; /* Fault trans type from SAER Logs */ 210 uint64_t pcie_sue_tgt_addr; /* Fault addr from SAER Logs */ 211 pcie_req_id_t pcie_sue_tgt_bdf; /* Fault bdf from SAER Logs */ 212 } pf_pcie_adv_bdg_err_regs_t; 213 214 typedef struct pf_pcie_adv_rp_err_regs { 215 uint32_t pcie_rp_err_status; /* pcie root complex error status reg */ 216 uint32_t pcie_rp_err_cmd; /* pcie root complex error cmd reg */ 217 uint16_t pcie_rp_ce_src_id; /* pcie root complex ce sourpe id */ 218 uint16_t pcie_rp_ue_src_id; /* pcie root complex ue sourpe id */ 219 } pf_pcie_adv_rp_err_regs_t; 220 221 typedef struct pf_pcie_adv_err_regs { 222 uint32_t pcie_adv_ctl; /* pcie advanced control reg */ 223 uint32_t pcie_ue_status; /* pcie ue error status reg */ 224 uint32_t pcie_ue_mask; /* pcie ue error mask reg */ 225 uint32_t pcie_ue_sev; /* pcie ue error severity reg */ 226 uint32_t pcie_ue_hdr[4]; /* pcie ue header log */ 227 uint32_t pcie_ce_status; /* pcie ce error status reg */ 228 uint32_t pcie_ce_mask; /* pcie ce error mask reg */ 229 union { 230 pf_pcie_adv_bdg_err_regs_t *pcie_adv_bdg_regs; /* bdg regs */ 231 pf_pcie_adv_rp_err_regs_t *pcie_adv_rp_regs; /* rp regs */ 232 } pcie_ext; 233 uint32_t pcie_ue_tgt_trans; /* Fault trans type from AER Logs */ 234 uint64_t pcie_ue_tgt_addr; /* Fault addr from AER Logs */ 235 pcie_req_id_t pcie_ue_tgt_bdf; /* Fault bdf from AER Logs */ 236 } pf_pcie_adv_err_regs_t; 237 238 typedef struct pf_pcie_rp_err_regs { 239 uint32_t pcie_rp_status; /* root complex status register */ 240 uint16_t pcie_rp_ctl; /* root complex control register */ 241 } pf_pcie_rp_err_regs_t; 242 243 typedef struct pf_pcie_err_regs { 244 uint16_t pcie_err_status; /* pcie device status register */ 245 uint16_t pcie_err_ctl; /* pcie error control register */ 246 uint32_t pcie_dev_cap; /* pcie device capabilities register */ 247 pf_pcie_rp_err_regs_t *pcie_rp_regs; /* pcie root complex regs */ 248 pf_pcie_adv_err_regs_t *pcie_adv_regs; /* pcie aer regs */ 249 } pf_pcie_err_regs_t; 250 251 typedef struct pf_root_fault { 252 pcie_req_id_t scan_bdf; /* BDF from error logs */ 253 uint64_t scan_addr; /* Addr from error logs */ 254 boolean_t full_scan; /* Option to do a full scan */ 255 } pf_root_fault_t; 256 257 typedef struct pf_data pf_data_t; 258 259 typedef struct pcie_bus { 260 /* Needed for PCI/PCIe fabric error handling */ 261 dev_info_t *bus_dip; 262 dev_info_t *bus_rp_dip; 263 ddi_acc_handle_t bus_cfg_hdl; /* error handling acc hdle */ 264 uint_t bus_fm_flags; 265 uint_t bus_soft_state; 266 267 /* Static PCI/PCIe information */ 268 pcie_req_id_t bus_bdf; 269 pcie_req_id_t bus_rp_bdf; /* BDF of device's Root Port */ 270 uint32_t bus_dev_ven_id; /* device/vendor ID */ 271 uint8_t bus_rev_id; /* revision ID */ 272 uint8_t bus_hdr_type; /* pci header type, see pci.h */ 273 uint16_t bus_dev_type; /* PCI-E dev type, see pcie.h */ 274 uint8_t bus_bdg_secbus; /* Bridge secondary bus num */ 275 uint16_t bus_pcie_off; /* PCIe Capability Offset */ 276 uint16_t bus_aer_off; /* PCIe Advanced Error Offset */ 277 uint16_t bus_pcix_off; /* PCIx Capability Offset */ 278 uint16_t bus_pci_hp_off; /* PCI HP (SHPC) Cap Offset */ 279 uint16_t bus_ecc_ver; /* PCIX ecc version */ 280 pci_bus_range_t bus_bus_range; /* pci bus-range property */ 281 ppb_ranges_t *bus_addr_ranges; /* pci range property */ 282 int bus_addr_entries; /* number of range prop */ 283 pci_regspec_t *bus_assigned_addr; /* "assigned-address" prop */ 284 int bus_assigned_entries; /* number of prop entries */ 285 286 /* Cache of last fault data */ 287 pf_data_t *bus_pfd; 288 289 int bus_mps; /* Maximum Payload Size */ 290 291 void *bus_plat_private; /* Platform specific */ 292 /* Hotplug specific fields */ 293 pcie_hp_mode_t bus_hp_sup_modes; /* HP modes supported */ 294 pcie_hp_mode_t bus_hp_curr_mode; /* HP mode used */ 295 void *bus_hp_ctrl; /* HP bus ctrl data */ 296 int bus_ari; /* ARI device */ 297 } pcie_bus_t; 298 299 struct pf_data { 300 boolean_t pe_lock; 301 boolean_t pe_valid; 302 uint32_t pe_severity_flags; /* Severity of error */ 303 pcie_bus_t *pe_bus_p; 304 pf_root_fault_t *pe_root_fault; /* Only valid for RC and RP */ 305 pf_pci_err_regs_t *pe_pci_regs; /* PCI error reg */ 306 union { 307 pf_pcix_err_regs_t *pe_pcix_regs; /* PCI-X error reg */ 308 pf_pcie_err_regs_t *pe_pcie_regs; /* PCIe error reg */ 309 } pe_ext; 310 pf_pcix_bdg_err_regs_t *pe_pcix_bdg_regs; /* PCI-X bridge regs */ 311 pf_data_t *pe_prev; /* Next error in queue */ 312 pf_data_t *pe_next; /* Next error in queue */ 313 boolean_t pe_rber_fatal; 314 }; 315 316 /* Information used while handling errors in the fabric. */ 317 typedef struct pf_impl { 318 ddi_fm_error_t *pf_derr; 319 pf_root_fault_t *pf_fault; /* captured fault bdf/addr to scan */ 320 pf_data_t *pf_dq_head_p; /* ptr to fault data queue */ 321 pf_data_t *pf_dq_tail_p; /* ptr pt last fault data q */ 322 uint32_t pf_total; /* total non RC pf_datas */ 323 } pf_impl_t; 324 325 /* bus_fm_flags field */ 326 #define PF_FM_READY (1 << 0) /* bus_fm_lock initialized */ 327 #define PF_FM_IS_NH (1 << 1) /* known as non-hardened */ 328 329 /* 330 * PCIe fabric handle lookup address flags. Used to define what type of 331 * transaction the address is for. These same value are defined again in 332 * fabric-xlate FM module. Do not modify these variables, without modifying 333 * those. 334 */ 335 #define PF_ADDR_DMA (1 << 0) 336 #define PF_ADDR_PIO (1 << 1) 337 #define PF_ADDR_CFG (1 << 2) 338 339 /* PCIe fabric error scanning status flags */ 340 #define PF_SCAN_SUCCESS (1 << 0) 341 #define PF_SCAN_CB_FAILURE (1 << 1) /* hardened device callback failure */ 342 #define PF_SCAN_NO_ERR_IN_CHILD (1 << 2) /* no errors in bridge sec stat reg */ 343 #define PF_SCAN_IN_DQ (1 << 3) /* already present in the faultq */ 344 #define PF_SCAN_DEADLOCK (1 << 4) /* deadlock detected */ 345 #define PF_SCAN_BAD_RESPONSE (1 << 5) /* Incorrect device response */ 346 347 /* PCIe fabric error handling severity return flags */ 348 #define PF_ERR_NO_ERROR (1 << 0) /* No error seen */ 349 #define PF_ERR_CE (1 << 1) /* Correctable Error */ 350 #define PF_ERR_NO_PANIC (1 << 2) /* Error should not panic sys */ 351 #define PF_ERR_MATCHED_DEVICE (1 << 3) /* Error Handled By Device */ 352 #define PF_ERR_MATCHED_RC (1 << 4) /* Error Handled By RC */ 353 #define PF_ERR_MATCHED_PARENT (1 << 5) /* Error Handled By Parent */ 354 #define PF_ERR_PANIC (1 << 6) /* Error should panic system */ 355 #define PF_ERR_PANIC_DEADLOCK (1 << 7) /* deadlock detected */ 356 357 #define PF_ERR_FATAL_FLAGS (PF_ERR_PANIC | PF_ERR_PANIC_DEADLOCK) 358 359 #define PF_HDL_FOUND 1 360 #define PF_HDL_NOTFOUND 2 361 362 /* 363 * PCIe Capability Device Type Pseudo Definitions. 364 * 365 * PCI_PSEUDO is used on real PCI devices. The Legacy PCI definition in the 366 * PCIe spec really refers to PCIe devices that *require* IO Space access. IO 367 * Space access is usually frowned upon now in PCIe, but there for legacy 368 * purposes. 369 */ 370 #define PCIE_PCIECAP_DEV_TYPE_RC_PSEUDO 0x100 371 #define PCIE_PCIECAP_DEV_TYPE_PCI_PSEUDO 0x101 372 373 #define PCIE_INVALID_BDF 0xFFFF 374 #define PCIE_CHECK_VALID_BDF(x) (x != PCIE_INVALID_BDF) 375 376 typedef struct { 377 dev_info_t *dip; 378 int highest_common_mps; 379 } pcie_max_supported_t; 380 381 /* 382 * Default interrupt priority for all PCI and PCIe nexus drivers including 383 * hotplug interrupts. 384 */ 385 #define PCIE_INTR_PRI (LOCK_LEVEL - 1) 386 387 /* 388 * XXX - PCIE_IS_PCIE check is required in order not to invoke these macros 389 * for non-standard PCI or PCI Express Hotplug Controllers. 390 */ 391 #define PCIE_ENABLE_ERRORS(dip) \ 392 if (PCIE_IS_PCIE(PCIE_DIP2BUS(dip))) { \ 393 pcie_enable_errors(dip); \ 394 (void) pcie_enable_ce(dip); \ 395 } 396 397 #define PCIE_DISABLE_ERRORS(dip) \ 398 if (PCIE_IS_PCIE(PCIE_DIP2BUS(dip))) { \ 399 pcie_disable_errors(dip); \ 400 } 401 402 #ifdef DEBUG 403 #define PCIE_DBG pcie_dbg 404 /* Common Debugging shortcuts */ 405 #define PCIE_DBG_CFG(dip, bus_p, name, sz, off, org) \ 406 PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \ 407 ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \ 408 PCIE_GET(sz, bus_p, off)) 409 #define PCIE_DBG_CAP(dip, bus_p, name, sz, off, org) \ 410 PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \ 411 ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \ 412 PCIE_CAP_GET(sz, bus_p, off)) 413 #define PCIE_DBG_AER(dip, bus_p, name, sz, off, org) \ 414 PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \ 415 ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \ 416 PCIE_AER_GET(sz, bus_p, off)) 417 418 #else /* DEBUG */ 419 420 #define PCIE_DBG_CFG 0 && 421 #define PCIE_DBG 0 && 422 #define PCIE_ARI_DBG 0 && 423 #define PCIE_DBG_CAP 0 && 424 #define PCIE_DBG_AER 0 && 425 426 #endif /* DEBUG */ 427 428 /* PCIe Friendly Functions */ 429 extern int pcie_init(dev_info_t *dip, caddr_t arg); 430 extern int pcie_uninit(dev_info_t *dip); 431 extern int pcie_intr(dev_info_t *dip); 432 extern int pcie_open(dev_info_t *dip, dev_t *devp, int flags, int otyp, 433 cred_t *credp); 434 extern int pcie_close(dev_info_t *dip, dev_t dev, int flags, int otyp, 435 cred_t *credp); 436 extern int pcie_ioctl(dev_info_t *dip, dev_t dev, int cmd, intptr_t arg, 437 int mode, cred_t *credp, int *rvalp); 438 extern int pcie_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op, 439 int flags, char *name, caddr_t valuep, int *lengthp); 440 441 extern void pcie_init_root_port_mps(dev_info_t *dip); 442 extern int pcie_initchild(dev_info_t *dip); 443 extern void pcie_uninitchild(dev_info_t *dip); 444 extern void pcie_clear_errors(dev_info_t *dip); 445 extern int pcie_postattach_child(dev_info_t *dip); 446 extern void pcie_enable_errors(dev_info_t *dip); 447 extern void pcie_disable_errors(dev_info_t *dip); 448 extern int pcie_enable_ce(dev_info_t *dip); 449 extern boolean_t pcie_bridge_is_link_disabled(dev_info_t *); 450 451 extern pcie_bus_t *pcie_init_bus(dev_info_t *cdip); 452 extern void pcie_fini_bus(dev_info_t *cdip); 453 extern void pcie_rc_init_bus(dev_info_t *dip); 454 extern void pcie_rc_fini_bus(dev_info_t *dip); 455 extern void pcie_rc_init_pfd(dev_info_t *dip, pf_data_t *pfd); 456 extern void pcie_rc_fini_pfd(pf_data_t *pfd); 457 extern boolean_t pcie_is_child(dev_info_t *dip, dev_info_t *rdip); 458 extern int pcie_get_bdf_from_dip(dev_info_t *dip, pcie_req_id_t *bdf); 459 extern dev_info_t *pcie_get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip); 460 extern uint32_t pcie_get_bdf_for_dma_xfer(dev_info_t *dip, dev_info_t *rdip); 461 extern int pcie_dev(dev_info_t *dip); 462 extern void pcie_get_fabric_mps(dev_info_t *rc_dip, dev_info_t *dip, 463 int *max_supported); 464 extern int pcie_root_port(dev_info_t *dip); 465 extern int pcie_initchild_mps(dev_info_t *dip); 466 extern void pcie_set_rber_fatal(dev_info_t *dip, boolean_t val); 467 extern boolean_t pcie_get_rber_fatal(dev_info_t *dip); 468 469 extern uint32_t pcie_get_aer_uce_mask(); 470 extern uint32_t pcie_get_aer_ce_mask(); 471 extern uint32_t pcie_get_aer_suce_mask(); 472 extern uint32_t pcie_get_serr_mask(); 473 extern void pcie_set_aer_uce_mask(uint32_t mask); 474 extern void pcie_set_aer_ce_mask(uint32_t mask); 475 extern void pcie_set_aer_suce_mask(uint32_t mask); 476 extern void pcie_set_serr_mask(uint32_t mask); 477 extern void pcie_init_plat(dev_info_t *dip); 478 extern void pcie_fini_plat(dev_info_t *dip); 479 extern int pcie_read_only_probe(dev_info_t *, char *, dev_info_t **); 480 extern dev_info_t *pcie_func_to_dip(dev_info_t *dip, pcie_req_id_t function); 481 extern int pcie_ari_disable(dev_info_t *dip); 482 extern int pcie_ari_enable(dev_info_t *dip); 483 484 #define PCIE_ARI_FORW_NOT_SUPPORTED 0 485 #define PCIE_ARI_FORW_SUPPORTED 1 486 487 extern int pcie_ari_supported(dev_info_t *dip); 488 489 #define PCIE_ARI_FORW_DISABLED 0 490 #define PCIE_ARI_FORW_ENABLED 1 491 492 extern int pcie_ari_is_enabled(dev_info_t *dip); 493 494 #define PCIE_NOT_ARI_DEVICE 0 495 #define PCIE_ARI_DEVICE 1 496 497 extern int pcie_ari_device(dev_info_t *dip); 498 extern int pcie_ari_get_next_function(dev_info_t *dip, int *func); 499 500 /* PCIe error handling functions */ 501 extern int pf_scan_fabric(dev_info_t *rpdip, ddi_fm_error_t *derr, 502 pf_data_t *root_pfd_p); 503 extern void pf_init(dev_info_t *, ddi_iblock_cookie_t, ddi_attach_cmd_t); 504 extern void pf_fini(dev_info_t *, ddi_detach_cmd_t); 505 extern int pf_hdl_lookup(dev_info_t *, uint64_t, uint32_t, uint64_t, 506 pcie_req_id_t); 507 extern int pf_tlp_decode(pcie_bus_t *, pf_pcie_adv_err_regs_t *); 508 509 #ifdef DEBUG 510 extern uint_t pcie_debug_flags; 511 extern void pcie_dbg(char *fmt, ...); 512 #endif /* DEBUG */ 513 514 #ifdef __cplusplus 515 } 516 #endif 517 518 #endif /* _SYS_PCIE_IMPL_H */ 519