xref: /titanic_50/usr/src/uts/common/sys/pci_impl.h (revision dae2dfb7b2bc52128c80617e060a0ba54ca46aba)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef _SYS_PCI_IMPL_H
27 #define	_SYS_PCI_IMPL_H
28 
29 #pragma ident	"%Z%%M%	%I%	%E% SMI"
30 
31 #include <sys/dditypes.h>
32 #include <sys/memlist.h>
33 
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37 
38 #if defined(__i386) || defined(__amd64)
39 
40 /*
41  * There are two ways to access the PCI configuration space on X86
42  * 	Access method 2 is the older method
43  *	Access method 1 is the newer method and is preferred because
44  *	  of the problems in trying to lock the configuration space
45  *	  for MP machines using method 2.  See PCI Local BUS Specification
46  *	  Revision 2.0 section 3.6.4.1 for more details.
47  *
48  * In addition, on IBM Sandalfoot and a few related machines there's
49  * still another mechanism.  See PReP 1.1 section 6.1.7.
50  */
51 
52 #define	PCI_MECHANISM_UNKNOWN		-1
53 #define	PCI_MECHANISM_NONE		0
54 #if defined(__i386) || defined(__amd64)
55 #define	PCI_MECHANISM_1 		1
56 #define	PCI_MECHANISM_2			2
57 #else
58 #error "Unknown processor type"
59 #endif
60 
61 
62 #ifndef FALSE
63 #define	FALSE   0
64 #endif
65 
66 #ifndef TRUE
67 #define	TRUE    1
68 #endif
69 
70 #define	PCI_FUNC_MASK			0x07
71 
72 /* these macros apply to Configuration Mechanism #1 */
73 #define	PCI_CONFADD		0xcf8
74 #define	PCI_PMC			0xcfb
75 #define	PCI_CONFDATA		0xcfc
76 #define	PCI_CONE		0x80000000
77 #define	PCI_CADDR1(bus, device, function, reg) \
78 		(PCI_CONE | (((bus) & 0xff) << 16) | (((device & 0x1f)) << 11) \
79 			    | (((function) & 0x7) << 8) | ((reg) & 0xfc))
80 
81 /* these macros apply to Configuration Mechanism #2 */
82 #define	PCI_CSE_PORT		0xcf8
83 #define	PCI_FORW_PORT		0xcfa
84 #define	PCI_CADDR2(device, indx) \
85 		(0xc000 | (((device) & 0xf) <<  8) | (indx))
86 
87 typedef struct 	pci_acc_cfblk {
88 	uchar_t	c_busnum;		/* bus number */
89 	uchar_t c_devnum;		/* device number */
90 	uchar_t c_funcnum;		/* function number */
91 	uchar_t c_fill;			/* reserve field */
92 } pci_acc_cfblk_t;
93 
94 struct pci_bus_resource {
95 	struct memlist *io_ports;	/* available free io res */
96 	struct memlist *io_ports_used;	/* used io res */
97 	struct memlist *mem_space;	/* available free mem res */
98 	struct memlist *mem_space_used;	/* used mem res */
99 	struct memlist *pmem_space; /* available free prefetchable mem res */
100 	struct memlist *pmem_space_used; /* used prefetchable mem res */
101 	struct memlist *bus_space;	/* available free bus res */
102 			/* bus_space_used not needed; can read from regs */
103 	dev_info_t *dip;	/* devinfo node */
104 	void *privdata;		/* private data for configuration */
105 	uchar_t par_bus;	/* parent bus number */
106 	uchar_t sub_bus;	/* highest bus number beyond this bridge */
107 	uchar_t root_addr;	/* legacy peer bus address assignment */
108 	uchar_t num_cbb;	/* # of CardBus Bridges on the bus */
109 	boolean_t io_reprogram;	/* need io reprog on this bus */
110 	boolean_t mem_reprogram;	/* need mem reprog on this bus */
111 	boolean_t subtractive;	/* subtractive PPB */
112 };
113 
114 extern struct pci_bus_resource *pci_bus_res;
115 
116 /*
117  * For now, x86-only to avoid conflicts with <sys/memlist_impl.h>
118  */
119 extern struct memlist *memlist_alloc(void);
120 extern void memlist_free(struct memlist *);
121 extern void memlist_free_all(struct memlist **);
122 extern void memlist_insert(struct memlist **, uint64_t, uint64_t);
123 extern int memlist_remove(struct memlist **, uint64_t, uint64_t);
124 extern uint64_t memlist_find(struct memlist **, uint64_t, int);
125 extern uint64_t memlist_find_with_startaddr(struct memlist **, uint64_t,
126     uint64_t, int);
127 extern void memlist_dump(struct memlist *);
128 extern void memlist_merge(struct memlist **, struct memlist **);
129 extern struct memlist *memlist_dup(struct memlist *);
130 extern int memlist_count(struct memlist *);
131 
132 #endif /* __i386 || __amd64 */
133 
134 /*
135  * PCI capability related definitions.
136  */
137 
138 /*
139  * Minimum number of dwords to be saved.
140  */
141 #define	PCI_MSI_MIN_WORDS	3
142 #define	PCI_PCIX_MIN_WORDS	2
143 #define	PCI_PCIE_MIN_WORDS	5
144 
145 /*
146  * Total number of dwords to be saved.
147  */
148 #define	PCI_PMCAP_NDWORDS	2
149 #define	PCI_AGP_NDWORDS		3
150 #define	PCI_SLOTID_NDWORDS	1
151 #define	PCI_MSIX_NDWORDS	3
152 #define	PCI_CAP_SZUNKNOWN	0
153 
154 #define	CAP_ID(confhdl, cap_ptr, xspace)		\
155 	((xspace) ? 0 : pci_config_get8((confhdl), (cap_ptr) + PCI_CAP_ID))
156 
157 #define	NEXT_CAP(confhdl, cap_ptr, xspace)	\
158 	((xspace) ? 0 :				\
159 	pci_config_get8((confhdl), (cap_ptr) + PCI_CAP_NEXT_PTR))
160 
161 extern int pci_resource_setup(dev_info_t *);
162 extern void pci_resource_destroy(dev_info_t *);
163 
164 #ifdef __cplusplus
165 }
166 #endif
167 
168 #endif /* _SYS_PCI_IMPL_H */
169