1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PCI_H 27 #define _SYS_PCI_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 /* 34 * PCI Configuration Header offsets 35 */ 36 #define PCI_CONF_VENID 0x0 /* vendor id, 2 bytes */ 37 #define PCI_CONF_DEVID 0x2 /* device id, 2 bytes */ 38 #define PCI_CONF_COMM 0x4 /* command register, 2 bytes */ 39 #define PCI_CONF_STAT 0x6 /* status register, 2 bytes */ 40 #define PCI_CONF_REVID 0x8 /* revision id, 1 byte */ 41 #define PCI_CONF_PROGCLASS 0x9 /* programming class code, 1 byte */ 42 #define PCI_CONF_SUBCLASS 0xA /* sub-class code, 1 byte */ 43 #define PCI_CONF_BASCLASS 0xB /* basic class code, 1 byte */ 44 #define PCI_CONF_CACHE_LINESZ 0xC /* cache line size, 1 byte */ 45 #define PCI_CONF_LATENCY_TIMER 0xD /* latency timer, 1 byte */ 46 #define PCI_CONF_HEADER 0xE /* header type, 1 byte */ 47 #define PCI_CONF_BIST 0xF /* builtin self test, 1 byte */ 48 49 /* 50 * Header type 0 offsets 51 */ 52 #define PCI_CONF_BASE0 0x10 /* base register 0, 4 bytes */ 53 #define PCI_CONF_BASE1 0x14 /* base register 1, 4 bytes */ 54 #define PCI_CONF_BASE2 0x18 /* base register 2, 4 bytes */ 55 #define PCI_CONF_BASE3 0x1c /* base register 3, 4 bytes */ 56 #define PCI_CONF_BASE4 0x20 /* base register 4, 4 bytes */ 57 #define PCI_CONF_BASE5 0x24 /* base register 5, 4 bytes */ 58 #define PCI_CONF_CIS 0x28 /* Cardbus CIS Pointer */ 59 #define PCI_CONF_SUBVENID 0x2c /* Subsystem Vendor ID */ 60 #define PCI_CONF_SUBSYSID 0x2e /* Subsystem ID */ 61 #define PCI_CONF_ROM 0x30 /* ROM base register, 4 bytes */ 62 #define PCI_CONF_CAP_PTR 0x34 /* capabilities pointer, 1 byte */ 63 #define PCI_CONF_ILINE 0x3c /* interrupt line, 1 byte */ 64 #define PCI_CONF_IPIN 0x3d /* interrupt pin, 1 byte */ 65 #define PCI_CONF_MIN_G 0x3e /* minimum grant, 1 byte */ 66 #define PCI_CONF_MAX_L 0x3f /* maximum grant, 1 byte */ 67 68 /* 69 * PCI to PCI bridge configuration space header format 70 */ 71 #define PCI_BCNF_PRIBUS 0x18 /* primary bus number */ 72 #define PCI_BCNF_SECBUS 0x19 /* secondary bus number */ 73 #define PCI_BCNF_SUBBUS 0x1a /* subordinate bus number */ 74 #define PCI_BCNF_LATENCY_TIMER 0x1b 75 #define PCI_BCNF_IO_BASE_LOW 0x1c 76 #define PCI_BCNF_IO_LIMIT_LOW 0x1d 77 #define PCI_BCNF_SEC_STATUS 0x1e 78 #define PCI_BCNF_MEM_BASE 0x20 79 #define PCI_BCNF_MEM_LIMIT 0x22 80 #define PCI_BCNF_PF_BASE_LOW 0x24 81 #define PCI_BCNF_PF_LIMIT_LOW 0x26 82 #define PCI_BCNF_PF_BASE_HIGH 0x28 83 #define PCI_BCNF_PF_LIMIT_HIGH 0x2c 84 #define PCI_BCNF_IO_BASE_HI 0x30 85 #define PCI_BCNF_IO_LIMIT_HI 0x32 86 #define PCI_BCNF_CAP_PTR 0x34 87 #define PCI_BCNF_ROM 0x38 88 #define PCI_BCNF_ILINE 0x3c 89 #define PCI_BCNF_IPIN 0x3d 90 #define PCI_BCNF_BCNTRL 0x3e 91 92 #define PCI_BCNF_BASE_NUM 0x2 93 94 /* 95 * PCI to PCI bridge control register (0x3e) format 96 */ 97 #define PCI_BCNF_BCNTRL_PARITY_ENABLE 0x1 98 #define PCI_BCNF_BCNTRL_SERR_ENABLE 0x2 99 #define PCI_BCNF_BCNTRL_ISA_ENABLE 0x4 100 #define PCI_BCNF_BCNTRL_VGA_ENABLE 0x8 101 #define PCI_BCNF_BCNTRL_MAST_AB_MODE 0x20 102 #define PCI_BCNF_BCNTRL_DTO_STAT 0x400 103 104 #define PCI_BCNF_BCNTRL_RESET 0x0040 105 #define PCI_BCNF_BCNTRL_B2B_ENAB 0x0080 106 107 #define PCI_BCNF_IO_MASK 0xf0 108 #define PCI_BCNF_MEM_MASK 0xfff0 109 110 /* 111 * Header type 2 (Cardbus) offsets 112 */ 113 #define PCI_CBUS_SOCK_REG 0x10 /* Cardbus socket regs, 4 bytes */ 114 #define PCI_CBUS_CAP_PTR 0x14 /* Capability ptr, 1 byte */ 115 #define PCI_CBUS_RESERVED1 0x15 /* Reserved, 1 byte */ 116 #define PCI_CBUS_SEC_STATUS 0x16 /* Secondary status, 2 bytes */ 117 #define PCI_CBUS_PCI_BUS_NO 0x18 /* PCI bus number, 1 byte */ 118 #define PCI_CBUS_CBUS_NO 0x19 /* Cardbus bus number, 1 byte */ 119 #define PCI_CBUS_SUB_BUS_NO 0x1a /* Subordinate bus number, 1 byte */ 120 #define PCI_CBUS_LATENCY_TIMER 0x1b /* Cardbus latency timer, 1 byte */ 121 #define PCI_CBUS_MEM_BASE0 0x1c /* Memory base reg 0, 4 bytes */ 122 #define PCI_CBUS_MEM_LIMIT0 0x20 /* Memory limit reg 0, 4 bytes */ 123 #define PCI_CBUS_MEM_BASE1 0x24 /* Memory base reg 1, 4 bytes */ 124 #define PCI_CBUS_MEM_LIMIT1 0x28 /* Memory limit reg 1, 4 bytes */ 125 #define PCI_CBUS_IO_BASE0 0x2c /* IO base reg 0, 4 bytes */ 126 #define PCI_CBUS_IO_LIMIT0 0x30 /* IO limit reg 0, 4 bytes */ 127 #define PCI_CBUS_IO_BASE1 0x34 /* IO base reg 1, 4 bytes */ 128 #define PCI_CBUS_IO_LIMIT1 0x38 /* IO limit reg 1, 4 bytes */ 129 #define PCI_CBUS_ILINE 0x3c /* interrupt line, 1 byte */ 130 #define PCI_CBUS_IPIN 0x3d /* interrupt pin, 1 byte */ 131 #define PCI_CBUS_BRIDGE_CTRL 0x3e /* Bridge control, 2 bytes */ 132 #define PCI_CBUS_SUBVENID 0x40 /* Subsystem Vendor ID, 2 bytes */ 133 #define PCI_CBUS_SUBSYSID 0x42 /* Subsystem ID, 2 bytes */ 134 #define PCI_CBUS_LEG_MODE_ADDR 0x44 /* PCCard 16bit IF legacy mode addr */ 135 136 #define PCI_CBUS_BASE_NUM 0x1 /* number of base registers */ 137 138 /* 139 * PCI command register bits 140 */ 141 #define PCI_COMM_IO 0x1 /* I/O access enable */ 142 #define PCI_COMM_MAE 0x2 /* memory access enable */ 143 #define PCI_COMM_ME 0x4 /* master enable */ 144 #define PCI_COMM_SPEC_CYC 0x8 145 #define PCI_COMM_MEMWR_INVAL 0x10 146 #define PCI_COMM_PALETTE_SNOOP 0x20 147 #define PCI_COMM_PARITY_DETECT 0x40 148 #define PCI_COMM_WAIT_CYC_ENAB 0x80 149 #define PCI_COMM_SERR_ENABLE 0x100 150 #define PCI_COMM_BACK2BACK_ENAB 0x200 151 #define PCI_COMM_INTX_DISABLE 0x400 /* INTx emulation disable */ 152 153 /* 154 * PCI Interrupt pin value 155 */ 156 #define PCI_INTA 1 157 #define PCI_INTB 2 158 #define PCI_INTC 3 159 #define PCI_INTD 4 160 161 /* 162 * PCI status register bits 163 */ 164 #define PCI_STAT_INTR 0x8 /* Interrupt state */ 165 #define PCI_STAT_CAP 0x10 /* Implements Capabilities */ 166 #define PCI_STAT_66MHZ 0x20 /* 66 MHz capable */ 167 #define PCI_STAT_UDF 0x40 /* UDF supported */ 168 #define PCI_STAT_FBBC 0x80 /* Fast Back-to-Back Capable */ 169 #define PCI_STAT_S_PERROR 0x100 /* Data Parity Reported */ 170 #define PCI_STAT_DEVSELT 0x600 /* Device select timing */ 171 #define PCI_STAT_S_TARG_AB 0x800 /* Signaled Target Abort */ 172 #define PCI_STAT_R_TARG_AB 0x1000 /* Received Target Abort */ 173 #define PCI_STAT_R_MAST_AB 0x2000 /* Received Master Abort */ 174 #define PCI_STAT_S_SYSERR 0x4000 /* Signaled System Error */ 175 #define PCI_STAT_PERROR 0x8000 /* Detected Parity Error */ 176 177 /* 178 * DEVSEL timing values 179 */ 180 #define PCI_STAT_DEVSELT_FAST 0x0000 181 #define PCI_STAT_DEVSELT_MEDIUM 0x0200 182 #define PCI_STAT_DEVSELT_SLOW 0x0400 183 184 /* 185 * BIST values 186 */ 187 #define PCI_BIST_SUPPORTED 0x80 188 #define PCI_BIST_GO 0x40 189 #define PCI_BIST_RESULT_M 0x0f 190 #define PCI_BIST_RESULT_OK 0x00 191 192 /* 193 * PCI class codes 194 */ 195 #define PCI_CLASS_NONE 0x0 /* class code for pre-2.0 devices */ 196 #define PCI_CLASS_MASS 0x1 /* Mass storage Controller class */ 197 #define PCI_CLASS_NET 0x2 /* Network Controller class */ 198 #define PCI_CLASS_DISPLAY 0x3 /* Display Controller class */ 199 #define PCI_CLASS_MM 0x4 /* Multimedia Controller class */ 200 #define PCI_CLASS_MEM 0x5 /* Memory Controller class */ 201 #define PCI_CLASS_BRIDGE 0x6 /* Bridge Controller class */ 202 #define PCI_CLASS_COMM 0x7 /* Communications Controller class */ 203 #define PCI_CLASS_PERIPH 0x8 /* Peripheral Controller class */ 204 #define PCI_CLASS_INPUT 0x9 /* Input Device class */ 205 #define PCI_CLASS_DOCK 0xa /* Docking Station class */ 206 #define PCI_CLASS_PROCESSOR 0xb /* Processor class */ 207 #define PCI_CLASS_SERIALBUS 0xc /* Serial Bus class */ 208 #define PCI_CLASS_WIRELESS 0xd /* Wireless Controller class */ 209 #define PCI_CLASS_INTIO 0xe /* Intelligent IO Controller class */ 210 #define PCI_CLASS_SATELLITE 0xf /* Satellite Communication class */ 211 #define PCI_CLASS_CRYPT 0x10 /* Encrytion/Decryption class */ 212 #define PCI_CLASS_SIGNAL 0x11 /* Signal Processing class */ 213 214 /* 215 * PCI Sub-class codes - base class 0x0 (no new devices should use this code). 216 */ 217 #define PCI_NONE_NOTVGA 0x0 /* All devices except VGA compatible */ 218 #define PCI_NONE_VGA 0x1 /* VGA compatible */ 219 220 /* 221 * PCI Sub-class codes - base class 0x1 (mass storage controllers) 222 */ 223 #define PCI_MASS_SCSI 0x0 /* SCSI bus Controller */ 224 #define PCI_MASS_IDE 0x1 /* IDE Controller */ 225 #define PCI_MASS_FD 0x2 /* Floppy disk Controller */ 226 #define PCI_MASS_IPI 0x3 /* IPI bus Controller */ 227 #define PCI_MASS_RAID 0x4 /* RAID Controller */ 228 #define PCI_MASS_ATA 0x5 /* ATA Controller */ 229 #define PCI_MASS_SATA 0x6 /* Serial ATA */ 230 #define PCI_MASS_SAS 0x7 /* Serial Attached SCSI (SAS) Cntrlr */ 231 #define PCI_MASS_OTHER 0x80 /* Other Mass Storage Controller */ 232 233 /* 234 * programming interface for IDE (subclass 1) 235 */ 236 #define PCI_IDE_IF_NATIVE_PRI 0x1 /* primary channel is native */ 237 #define PCI_IDE_IF_PROG_PRI 0x2 /* primary can operate in either mode */ 238 #define PCI_IDE_IF_NATIVE_SEC 0x4 /* secondary channel is native */ 239 #define PCI_IDE_IF_PROG_SEC 0x8 /* sec. can operate in either mode */ 240 #define PCI_IDE_IF_MASK 0xf /* programming interface mask */ 241 242 243 /* 244 * programming interface for ATA (subclass 5) 245 */ 246 #define PCI_ATA_IF_SINGLE_DMA 0x20 /* ATA controller with single DMA */ 247 #define PCI_ATA_IF_CHAINED_DMA 0x30 /* ATA controller with chained DMA */ 248 249 /* 250 * programming interface for ATA (subclass 6) for SATA 251 */ 252 #define PCI_SATA_VS_INTERFACE 0x0 /* SATA Ctlr Vendor Specific Intfc */ 253 #define PCI_SATA_AHCI_INTERFACE 0x1 /* SATA Ctlr AHCI 1.0 Interface */ 254 #define PCI_SATA_SSB_INTERFACE 0x2 /* Serial Storage Bus Interface */ 255 256 /* 257 * programming interface for ATA (subclass 7) for SAS 258 */ 259 #define PCI_SAS_CONTROLLER 0x0 /* SAS Controller */ 260 #define PCI_SAS_BUS_INTERFACE 0x1 /* Serial Storage Bus Interface */ 261 262 /* 263 * PCI Sub-class codes - base class 0x2 (Network controllers) 264 */ 265 #define PCI_NET_ENET 0x0 /* Ethernet Controller */ 266 #define PCI_NET_TOKEN 0x1 /* Token Ring Controller */ 267 #define PCI_NET_FDDI 0x2 /* FDDI Controller */ 268 #define PCI_NET_ATM 0x3 /* ATM Controller */ 269 #define PCI_NET_ISDN 0x4 /* ISDN Controller */ 270 #define PCI_NET_WFIP 0x5 /* WorldFip Controller */ 271 #define PCI_NET_PICMG 0x6 /* PICMG 2.14 Multi Computing */ 272 #define PCI_NET_OTHER 0x80 /* Other Network Controller */ 273 274 /* 275 * PCI Sub-class codes - base class 03 (display controllers) 276 */ 277 #define PCI_DISPLAY_VGA 0x0 /* VGA device */ 278 #define PCI_DISPLAY_XGA 0x1 /* XGA device */ 279 #define PCI_DISPLAY_3D 0x2 /* 3D controller */ 280 #define PCI_DISPLAY_OTHER 0x80 /* Other Display Device */ 281 282 /* 283 * programming interface for display for display class (subclass 0) VGA ctrlrs 284 */ 285 #define PCI_DISPLAY_IF_VGA 0x0 /* VGA compatible */ 286 #define PCI_DISPLAY_IF_8514 0x1 /* 8514 compatible */ 287 288 /* 289 * PCI Sub-class codes - base class 0x4 (multi-media devices) 290 */ 291 #define PCI_MM_VIDEO 0x0 /* Video device */ 292 #define PCI_MM_AUDIO 0x1 /* Audio device */ 293 #define PCI_MM_TELEPHONY 0x2 /* Computer Telephony device */ 294 #define PCI_MM_MIXED_MODE 0x3 /* Mixed Mode device */ 295 #define PCI_MM_OTHER 0x80 /* Other Multimedia Device */ 296 297 /* 298 * PCI Sub-class codes - base class 0x5 (memory controllers) 299 */ 300 #define PCI_MEM_RAM 0x0 /* RAM device */ 301 #define PCI_MEM_FLASH 0x1 /* FLASH device */ 302 #define PCI_MEM_OTHER 0x80 /* Other Memory Controller */ 303 304 /* 305 * PCI Sub-class codes - base class 0x6 (Bridge devices) 306 */ 307 #define PCI_BRIDGE_HOST 0x0 /* Host/PCI Bridge */ 308 #define PCI_BRIDGE_ISA 0x1 /* PCI/ISA Bridge */ 309 #define PCI_BRIDGE_EISA 0x2 /* PCI/EISA Bridge */ 310 #define PCI_BRIDGE_MC 0x3 /* PCI/MC Bridge */ 311 #define PCI_BRIDGE_PCI 0x4 /* PCI/PCI Bridge */ 312 #define PCI_BRIDGE_PCMCIA 0x5 /* PCI/PCMCIA Bridge */ 313 #define PCI_BRIDGE_NUBUS 0x6 /* PCI/NUBUS Bridge */ 314 #define PCI_BRIDGE_CARDBUS 0x7 /* PCI/CARDBUS Bridge */ 315 #define PCI_BRIDGE_RACE 0x8 /* RACE-way Bridge */ 316 #define PCI_BRIDGE_STPCI 0x9 /* Semi-transparent PCI/PCI Bridge */ 317 #define PCI_BRIDGE_IB 0xA /* InfiniBand/PCI host Bridge */ 318 #define PCI_BRIDGE_AS 0xB /* AS/PCI host Bridge */ 319 #define PCI_BRIDGE_OTHER 0x80 /* PCI/Other Bridge Device */ 320 321 /* 322 * programming interface for Bridges class 0x6 (subclass 4) PCI-PCI bridge 323 */ 324 #define PCI_BRIDGE_PCI_IF_PCI2PCI 0x0 /* PCI-PCI bridge */ 325 #define PCI_BRIDGE_PCI_IF_SUBDECODE 0x1 /* Subtractive Decode */ 326 /* PCI/PCI bridge */ 327 328 /* 329 * programming interface for Bridges class 0x6 (subclass 08) RACEway bridge 330 */ 331 #define PCI_BRIDGE_RACE_IF_TRANSPARENT 0x0 /* Transport mode */ 332 #define PCI_BRIDGE_RACE_IF_ENDPOINT 0x1 /* Endpoint mode */ 333 334 /* 335 * programming interface for Bridges class 0x6 (subclass 09) 336 * Semi-transparent PCI-to-PCI bridge 337 */ 338 #define PCI_BRIDGE_STPCI_IF_PRIMARY 0x40 /* primary PCI side bus */ 339 /* facing system processor */ 340 #define PCI_BRIDGE_STPCI_IF_SECONDARY 0x80 /* secondary PCI side bus */ 341 /* facing system processor */ 342 343 /* 344 * programming interface for Bridges class 0x6 (subclass 0B) AS bridge 345 */ 346 #define PCI_BRIDGE_AS_CUSTOM_INTFC 0x0 /* Custom interface */ 347 #define PCI_BRIDGE_AS_PORTAL_INTFC 0x1 /* ASI-SIG Portal Interface */ 348 349 /* 350 * PCI Sub-class codes - base class 0x7 (communication devices) 351 */ 352 #define PCI_COMM_GENERIC_XT 0x0 /* XT Compatible Serial Controller */ 353 #define PCI_COMM_PARALLEL 0x1 /* Parallel Port Controller */ 354 #define PCI_COMM_MSC 0x2 /* Multiport Serial Controller */ 355 #define PCI_COMM_MODEM 0x3 /* Modem Controller */ 356 #define PCI_COMM_GPIB 0x4 /* GPIB Controller */ 357 #define PCI_COMM_SMARTCARD 0x5 /* Smart Card Controller */ 358 #define PCI_COMM_OTHER 0x80 /* Other Communications Controller */ 359 360 /* 361 * Programming interfaces for class 0x7 / subclass 0x0 (Serial) 362 */ 363 #define PCI_COMM_SERIAL_IF_GENERIC 0x0 /* Generic XT-compat serial */ 364 #define PCI_COMM_SERIAL_IF_16450 0x1 /* 16450-compat serial ctrlr */ 365 #define PCI_COMM_SERIAL_IF_16550 0x2 /* 16550-compat serial ctrlr */ 366 #define PCI_COMM_SERIAL_IF_16650 0x3 /* 16650-compat serial ctrlr */ 367 #define PCI_COMM_SERIAL_IF_16750 0x4 /* 16750-compat serial ctrlr */ 368 #define PCI_COMM_SERIAL_IF_16850 0x5 /* 16850-compat serial ctrlr */ 369 #define PCI_COMM_SERIAL_IF_16950 0x6 /* 16950-compat serial ctrlr */ 370 371 /* 372 * Programming interfaces for class 0x7 / subclass 0x1 (Parallel) 373 */ 374 #define PCI_COMM_PARALLEL_IF_GENERIC 0x0 /* Generic Parallel port */ 375 #define PCI_COMM_PARALLEL_IF_BIDIRECT 0x1 /* Bi-directional Parallel */ 376 #define PCI_COMM_PARALLEL_IF_ECP 0x2 /* ECP 1.X Parallel port */ 377 #define PCI_COMM_PARALLEL_IF_1284 0x3 /* IEEE 1284 Parallel port */ 378 #define PCI_COMM_PARALLEL_IF_1284_TARG 0xFE /* IEEE 1284 target device */ 379 380 /* 381 * Programming interfaces for class 0x7 / subclass 0x3 (Modem) 382 */ 383 #define PCI_COMM_MODEM_IF_GENERIC 0x0 /* Generic Modem */ 384 #define PCI_COMM_MODEM_IF_HAYES_16450 0x1 /* Hayes 16450-compat Modem */ 385 #define PCI_COMM_MODEM_IF_HAYES_16550 0x2 /* Hayes 16550-compat Modem */ 386 #define PCI_COMM_MODEM_IF_HAYES_16650 0x3 /* Hayes 16650-compat Modem */ 387 #define PCI_COMM_MODEM_IF_HAYES_16750 0x4 /* Hayes 16750-compat Modem */ 388 389 /* 390 * PCI Sub-class codes - base class 0x8 391 */ 392 #define PCI_PERIPH_PIC 0x0 /* Generic PIC */ 393 #define PCI_PERIPH_DMA 0x1 /* Generic DMA Controller */ 394 #define PCI_PERIPH_TIMER 0x2 /* Generic System Timer Controller */ 395 #define PCI_PERIPH_RTC 0x3 /* Generic RTC Controller */ 396 #define PCI_PERIPH_HPC 0x4 /* Generic PCI Hot-Plug Controller */ 397 #define PCI_PERIPH_SD_HC 0x5 /* SD Host Controller */ 398 #define PCI_PERIPH_IOMMU 0x6 /* IOMMU */ 399 #define PCI_PERIPH_OTHER 0x80 /* Other System Peripheral */ 400 401 /* 402 * Programming interfaces for class 0x8 / subclass 0x0 (interrupt controller) 403 */ 404 #define PCI_PERIPH_PIC_IF_GENERIC 0x0 /* Generic 8259 APIC */ 405 #define PCI_PERIPH_PIC_IF_ISA 0x1 /* ISA PIC */ 406 #define PCI_PERIPH_PIC_IF_EISA 0x2 /* EISA PIC */ 407 #define PCI_PERIPH_PIC_IF_IO_APIC 0x10 /* I/O APIC interrupt ctrlr */ 408 #define PCI_PERIPH_PIC_IF_IOX_APIC 0x20 /* I/O(x) APIC intr ctrlr */ 409 410 /* 411 * Programming interfaces for class 0x8 / subclass 0x1 (DMA controller) 412 */ 413 #define PCI_PERIPH_DMA_IF_GENERIC 0x0 /* Generic 8237 DMA ctrlr */ 414 #define PCI_PERIPH_DMA_IF_ISA 0x1 /* ISA DMA ctrlr */ 415 #define PCI_PERIPH_DMA_IF_EISA 0x2 /* EISA DMA ctrlr */ 416 417 /* 418 * Programming interfaces for class 0x8 / subclass 0x2 (timer) 419 */ 420 #define PCI_PERIPH_TIMER_IF_GENERIC 0x0 /* Generic 8254 system timer */ 421 #define PCI_PERIPH_TIMER_IF_ISA 0x1 /* ISA system timers */ 422 #define PCI_PERIPH_TIMER_IF_EISA 0x2 /* EISA system timers (two) */ 423 #define PCI_PERIPH_TIMER_IF_HPET 0x3 /* High Perf Event timer */ 424 425 /* 426 * Programming interfaces for class 0x8 / subclass 0x3 (realtime clock) 427 */ 428 #define PCI_PERIPH_RTC_IF_GENERIC 0x0 /* Generic RTC controller */ 429 #define PCI_PERIPH_RTC_IF_ISA 0x1 /* ISA RTC controller */ 430 431 /* 432 * PCI Sub-class codes - base class 0x9 433 */ 434 #define PCI_INPUT_KEYBOARD 0x0 /* Keyboard Controller */ 435 #define PCI_INPUT_DIGITIZ 0x1 /* Digitizer (Pen) */ 436 #define PCI_INPUT_MOUSE 0x2 /* Mouse Controller */ 437 #define PCI_INPUT_SCANNER 0x3 /* Scanner Controller */ 438 #define PCI_INPUT_GAMEPORT 0x4 /* Gameport Controller */ 439 #define PCI_INPUT_OTHER 0x80 /* Other Input Controller */ 440 441 /* 442 * Programming interfaces for class 0x9 / subclass 0x4 (Gameport controller) 443 */ 444 #define PCI_INPUT_GAMEPORT_IF_GENERIC 0x00 /* Generic controller */ 445 #define PCI_INPUT_GAMEPORT_IF_LEGACY 0x10 /* Legacy controller */ 446 447 /* 448 * PCI Sub-class codes - base class 0xA 449 */ 450 #define PCI_DOCK_GENERIC 0x00 /* Generic Docking Station */ 451 #define PCI_DOCK_OTHER 0x80 /* Other Type of Docking Station */ 452 453 /* 454 * PCI Sub-class codes - base class 0xB 455 */ 456 #define PCI_PROCESSOR_386 0x0 /* 386 */ 457 #define PCI_PROCESSOR_486 0x1 /* 486 */ 458 #define PCI_PROCESSOR_PENT 0x2 /* Pentium */ 459 #define PCI_PROCESSOR_ALPHA 0x10 /* Alpha */ 460 #define PCI_PROCESSOR_POWERPC 0x20 /* PowerPC */ 461 #define PCI_PROCESSOR_MIPS 0x30 /* MIPS */ 462 #define PCI_PROCESSOR_COPROC 0x40 /* Co-processor */ 463 #define PCI_PROCESSOR_OTHER 0x80 /* Other processors */ 464 465 /* 466 * PCI Sub-class codes - base class 0xC (Serial Controllers) 467 */ 468 #define PCI_SERIAL_FIRE 0x0 /* FireWire (IEEE 1394) */ 469 #define PCI_SERIAL_ACCESS 0x1 /* ACCESS.bus */ 470 #define PCI_SERIAL_SSA 0x2 /* SSA */ 471 #define PCI_SERIAL_USB 0x3 /* Universal Serial Bus */ 472 #define PCI_SERIAL_FIBRE 0x4 /* Fibre Channel */ 473 #define PCI_SERIAL_SMBUS 0x5 /* System Management Bus */ 474 #define PCI_SERIAL_IB 0x6 /* InfiniBand */ 475 #define PCI_SERIAL_IPMI 0x7 /* IPMI */ 476 #define PCI_SERIAL_SERCOS 0x8 /* SERCOS Interface Std (IEC 61491) */ 477 #define PCI_SERIAL_CANBUS 0x9 /* CANbus */ 478 #define PCI_SERIAL_OTHER 0x80 /* Other Serial Bus Controllers */ 479 480 /* 481 * Programming interfaces for class 0xC / subclass 0x0 (Firewire) 482 */ 483 #define PCI_SERIAL_FIRE_WIRE 0x00 /* IEEE 1394 (Firewire) */ 484 #define PCI_SERIAL_FIRE_1394_HCI 0x10 /* 1394 OpenHCI Host Cntrlr */ 485 486 /* 487 * Programming interfaces for class 0xC / subclass 0x3 (USB controller) 488 */ 489 #define PCI_SERIAL_USB_IF_UHCI 0x00 /* UHCI Compliant */ 490 #define PCI_SERIAL_USB_IF_OHCI 0x10 /* OHCI Compliant */ 491 #define PCI_SERIAL_USB_IF_EHCI 0x20 /* EHCI Compliant */ 492 #define PCI_SERIAL_USB_IF_GENERIC 0x80 /* no specific HCD */ 493 #define PCI_SERIAL_USB_IF_DEVICE 0xFE /* not a HCD */ 494 495 /* 496 * Programming interfaces for class 0xC / subclass 0x7 (IPMI controller) 497 */ 498 #define PCI_SERIAL_IPMI_IF_SMIC 0x0 /* SMIC Interface */ 499 #define PCI_SERIAL_IPMI_IF_KBD 0x1 /* Keyboard Ctrl Style Intfc */ 500 #define PCI_SERIAL_IPMI_IF_BTI 0x2 /* Block Transfer Interface */ 501 502 /* 503 * PCI Sub-class codes - base class 0xD (Wireless controllers) 504 */ 505 #define PCI_WIRELESS_IRDA 0x0 /* iRDA Compatible Controller */ 506 #define PCI_WIRELESS_IR 0x1 /* Consumer IR Controller */ 507 #define PCI_WIRELESS_RF 0x10 /* RF Controller */ 508 #define PCI_WIRELESS_BLUETOOTH 0x11 /* Bluetooth Controller */ 509 #define PCI_WIRELESS_BROADBAND 0x12 /* Broadband Controller */ 510 #define PCI_WIRELESS_80211A 0x20 /* Ethernet 802.11a 5 GHz */ 511 #define PCI_WIRELESS_80211B 0x21 /* Ethernet 802.11b 2.4 GHz */ 512 #define PCI_WIRELESS_OTHER 0x80 /* Other Wireless Controllers */ 513 514 /* 515 * Programming interfaces for class 0xD / subclass 0x1 (Consumer IR controller) 516 */ 517 #define PCI_WIRELESS_IR_CONSUMER 0x00 /* Consumer IR Controller */ 518 #define PCI_WIRELESS_IR_UWB_RC 0x10 /* UWB Radio Controller */ 519 520 /* 521 * PCI Sub-class codes - base class 0xE (Intelligent I/O controllers) 522 */ 523 #define PCI_INTIO_MSG_FIFO 0x0 /* Message FIFO at off 40h */ 524 #define PCI_INTIO_I20 0x1 /* I20 Arch Spec 1.0 */ 525 526 /* 527 * PCI Sub-class codes - base class 0xF (Satellite Communication controllers) 528 */ 529 #define PCI_SATELLITE_COMM_TV 0x01 /* TV */ 530 #define PCI_SATELLITE_COMM_AUDIO 0x02 /* Audio */ 531 #define PCI_SATELLITE_COMM_VOICE 0x03 /* Voice */ 532 #define PCI_SATELLITE_COMM_DATA 0x04 /* DATA */ 533 #define PCI_SATELLITE_COMM_OTHER 0x80 /* Other Satelite Comm Cntrlr */ 534 535 /* 536 * PCI Sub-class codes - base class 0x10 (Encryption/Decryption controllers) 537 */ 538 #define PCI_CRYPT_NETWORK 0x00 /* Network and Computing */ 539 #define PCI_CRYPT_ENTERTAINMENT 0x10 /* Entertainment en/decrypt */ 540 #define PCI_CRYPT_OTHER 0x80 /* Other en/decryption ctrlrs */ 541 542 /* 543 * PCI Sub-class codes - base class 0x11 (Signal Processing controllers) 544 */ 545 #define PCI_SIGNAL_DPIO 0x00 /* DPIO modules */ 546 #define PCI_SIGNAL_PERF_COUNTERS 0x01 /* Performance counters */ 547 #define PCI_SIGNAL_COMM_SYNC 0x10 /* Comm. synchronization plus */ 548 /* time and freq test ctrlr */ 549 #define PCI_SIGNAL_MANAGEMENT 0x20 /* Management card */ 550 #define PCI_SIGNAL_OTHER 0x80 /* DSP/DAP controller */ 551 552 /* PCI header decode */ 553 #define PCI_HEADER_MULTI 0x80 /* multi-function device */ 554 #define PCI_HEADER_ZERO 0x00 /* type zero PCI header */ 555 #define PCI_HEADER_ONE 0x01 /* type one PCI header */ 556 #define PCI_HEADER_TWO 0x02 /* type two PCI header */ 557 #define PCI_HEADER_PPB PCI_HEADER_ONE /* type one PCI to PCI Bridge */ 558 #define PCI_HEADER_CARDBUS PCI_HEADER_TWO /* type one PCI header */ 559 560 #define PCI_HEADER_TYPE_M 0x7f /* type mask for header */ 561 562 /* 563 * Base register bit definitions. 564 */ 565 #define PCI_BASE_SPACE_M 0x1 /* memory space indicator */ 566 #define PCI_BASE_SPACE_IO 0x1 /* IO space */ 567 #define PCI_BASE_SPACE_MEM 0x0 /* memory space */ 568 569 #define PCI_BASE_TYPE_MEM 0x0 /* 32-bit memory address */ 570 #define PCI_BASE_TYPE_LOW 0x2 /* less than 1Mb address */ 571 #define PCI_BASE_TYPE_ALL 0x4 /* 64-bit memory address */ 572 #define PCI_BASE_TYPE_RES 0x6 /* reserved */ 573 574 #define PCI_BASE_TYPE_M 0x00000006 /* type indicator mask */ 575 #define PCI_BASE_PREF_M 0x00000008 /* prefetch mask */ 576 #define PCI_BASE_M_ADDR_M 0xfffffff0 /* memory address mask */ 577 #define PCI_BASE_IO_ADDR_M 0xfffffffe /* I/O address mask */ 578 579 #define PCI_BASE_ROM_ADDR_M 0xfffff800 /* ROM address mask */ 580 #define PCI_BASE_ROM_ENABLE 0x00000001 /* ROM decoder enable */ 581 582 /* 583 * Capabilities linked list entry offsets 584 */ 585 #define PCI_CAP_ID 0x0 /* capability identifier, 1 byte */ 586 #define PCI_CAP_NEXT_PTR 0x1 /* next entry pointer, 1 byte */ 587 #define PCI_CAP_ID_REGS_OFF 0x2 /* cap id register offset */ 588 #define PCI_CAP_MAX_PTR 0x30 /* maximum number of cap pointers */ 589 #define PCI_CAP_PTR_OFF 0x40 /* minimum cap pointer offset */ 590 #define PCI_CAP_PTR_MASK 0xFC /* mask for capability pointer */ 591 592 /* 593 * Capability identifier values 594 */ 595 #define PCI_CAP_ID_PM 0x1 /* power management entry */ 596 #define PCI_CAP_ID_AGP 0x2 /* AGP supported */ 597 #define PCI_CAP_ID_VPD 0x3 /* VPD supported */ 598 #define PCI_CAP_ID_SLOT_ID 0x4 /* Slot Identification supported */ 599 #define PCI_CAP_ID_MSI 0x5 /* MSI supported */ 600 #define PCI_CAP_ID_cPCI_HS 0x6 /* CompactPCI Host Swap supported */ 601 #define PCI_CAP_ID_PCIX 0x7 /* PCI-X supported */ 602 #define PCI_CAP_ID_HT 0x8 /* HyperTransport supported */ 603 #define PCI_CAP_ID_VS 0x9 /* Vendor Specific */ 604 #define PCI_CAP_ID_DEBUG_PORT 0xA /* Debug Port supported */ 605 #define PCI_CAP_ID_cPCI_CRC 0xB /* CompactPCI central resource ctrl */ 606 #define PCI_CAP_ID_PCI_HOTPLUG 0xC /* PCI Hot Plug supported */ 607 #define PCI_CAP_ID_P2P_SUBSYS 0xD /* PCI bridge Sub-system ID */ 608 #define PCI_CAP_ID_AGP_8X 0xE /* AGP 8X supported */ 609 #define PCI_CAP_ID_SECURE_DEV 0xF /* Secure Device supported */ 610 #define PCI_CAP_ID_PCI_E 0x10 /* PCI Express supported */ 611 #define PCI_CAP_ID_MSI_X 0x11 /* MSI-X supported */ 612 #define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Config supported */ 613 #define PCI_CAP_ID_FLR 0x13 /* Function Level Reset supported */ 614 615 /* 616 * Capability next entry pointer values 617 */ 618 #define PCI_CAP_NEXT_PTR_NULL 0x0 /* no more entries in the list */ 619 620 /* 621 * PCI power management (PM) capability entry offsets 622 */ 623 #define PCI_PMCAP 0x2 /* PM capabilities, 2 bytes */ 624 #define PCI_PMCSR 0x4 /* PM control/status reg, 2 bytes */ 625 #define PCI_PMCSR_BSE 0x6 /* PCI-PCI bridge extensions, 1 byte */ 626 #define PCI_PMDATA 0x7 /* PM data, 1 byte */ 627 628 /* 629 * PM capabilities values - 2 bytes 630 */ 631 #define PCI_PMCAP_VER_1_0 0x1 /* PCI PM spec 1.0 */ 632 #define PCI_PMCAP_VER_1_1 0x2 /* PCI PM spec 1.1 */ 633 #define PCI_PMCAP_VER_MASK 0x7 /* version mask */ 634 #define PCI_PMCAP_PME_CLOCK 0x8 /* needs PCI clock for PME */ 635 #define PCI_PMCAP_DSI 0x20 /* needs device specific init */ 636 #define PCI_PMCAP_AUX_CUR_SELF 0x0 /* 0 aux current - self powered */ 637 #define PCI_PMCAP_AUX_CUR_55mA 0x40 /* 55 mA aux current */ 638 #define PCI_PMCAP_AUX_CUR_100mA 0x80 /* 100 mA aux current */ 639 #define PCI_PMCAP_AUX_CUR_160mA 0xc0 /* 160 mA aux current */ 640 #define PCI_PMCAP_AUX_CUR_220mA 0x100 /* 220 mA aux current */ 641 #define PCI_PMCAP_AUX_CUR_270mA 0x140 /* 270 mA aux current */ 642 #define PCI_PMCAP_AUX_CUR_320mA 0x180 /* 320 mA aux current */ 643 #define PCI_PMCAP_AUX_CUR_375mA 0x1c0 /* 375 mA aux current */ 644 #define PCI_PMCAP_AUX_CUR_MASK 0x1c0 /* 3.3Vaux aux current needs */ 645 #define PCI_PMCAP_D1 0x200 /* D1 state supported */ 646 #define PCI_PMCAP_D2 0x400 /* D2 state supported */ 647 #define PCI_PMCAP_D0_PME 0x800 /* PME from D0 */ 648 #define PCI_PMCAP_D1_PME 0x1000 /* PME from D1 */ 649 #define PCI_PMCAP_D2_PME 0x2000 /* PME from D2 */ 650 #define PCI_PMCAP_D3HOT_PME 0x4000 /* PME from D3hot */ 651 #define PCI_PMCAP_D3COLD_PME 0x8000 /* PME from D3cold */ 652 #define PCI_PMCAP_PME_MASK 0xf800 /* PME support mask */ 653 654 /* 655 * PM control/status values - 2 bytes 656 */ 657 #define PCI_PMCSR_D0 0x0 /* power state D0 */ 658 #define PCI_PMCSR_D1 0x1 /* power state D1 */ 659 #define PCI_PMCSR_D2 0x2 /* power state D2 */ 660 #define PCI_PMCSR_D3HOT 0x3 /* power state D3hot */ 661 #define PCI_PMCSR_STATE_MASK 0x3 /* power state mask */ 662 #define PCI_PMCSR_PME_EN 0x100 /* enable PME assertion */ 663 #define PCI_PMCSR_DSEL_D0_PWR_C 0x0 /* D0 power consumed */ 664 #define PCI_PMCSR_DSEL_D1_PWR_C 0x200 /* D1 power consumed */ 665 #define PCI_PMCSR_DSEL_D2_PWR_C 0x400 /* D2 power consumed */ 666 #define PCI_PMCSR_DSEL_D3_PWR_C 0x600 /* D3 power consumed */ 667 #define PCI_PMCSR_DSEL_D0_PWR_D 0x800 /* D0 power dissipated */ 668 #define PCI_PMCSR_DSEL_D1_PWR_D 0xa00 /* D1 power dissipated */ 669 #define PCI_PMCSR_DSEL_D2_PWR_D 0xc00 /* D2 power dissipated */ 670 #define PCI_PMCSR_DSEL_D3_PWR_D 0xe00 /* D3 power dissipated */ 671 #define PCI_PMCSR_DSEL_COM_C 0x1000 /* common power consumption */ 672 #define PCI_PMCSR_DSEL_MASK 0x1e00 /* data select mask */ 673 #define PCI_PMCSR_DSCL_UNKNOWN 0x0 /* data scale unknown */ 674 #define PCI_PMCSR_DSCL_1_BY_10 0x2000 /* data scale 0.1x */ 675 #define PCI_PMCSR_DSCL_1_BY_100 0x4000 /* data scale 0.01x */ 676 #define PCI_PMCSR_DSCL_1_BY_1000 0x6000 /* data scale 0.001x */ 677 #define PCI_PMCSR_DSCL_MASK 0x6000 /* data scale mask */ 678 #define PCI_PMCSR_PME_STAT 0x8000 /* PME status */ 679 680 /* 681 * PM PMCSR PCI to PCI bridge support extension values - 1 byte 682 */ 683 #define PCI_PMCSR_BSE_B2_B3 0x40 /* bridge D3hot -> secondary B2 */ 684 #define PCI_PMCSR_BSE_BPCC_EN 0x80 /* bus power/clock control enabled */ 685 686 /* 687 * PCI-X capability related definitions 688 */ 689 #define PCI_PCIX_COMMAND 0x2 /* Command register offset */ 690 #define PCI_PCIX_STATUS 0x4 /* Status register offset */ 691 #define PCI_PCIX_ECC_STATUS 0x8 /* ECC Status register offset */ 692 #define PCI_PCIX_ECC_FST_AD 0xC /* ECC First address register offset */ 693 #define PCI_PCIX_ECC_SEC_AD 0x10 /* ECC Second address register offset */ 694 #define PCI_PCIX_ECC_ATTR 0x14 /* ECC Attribute register offset */ 695 696 /* 697 * PCI-X bridge capability related definitions 698 */ 699 #define PCI_PCIX_SEC_STATUS 0x2 /* Secondary Status offset */ 700 #define PCI_PCIX_SEC_STATUS_SCD 0x4 /* Split Completion Discarded */ 701 #define PCI_PCIX_SEC_STATUS_USC 0x8 /* Unexpected Split Complete */ 702 #define PCI_PCIX_SEC_STATUS_SCO 0x10 /* Split Completion Overrun */ 703 #define PCI_PCIX_SEC_STATUS_SRD 0x20 /* Split Completion Delayed */ 704 #define PCI_PCIX_SEC_STATUS_ERR_MASK 0x3C 705 706 #define PCI_PCIX_BDG_STATUS 0x4 /* Bridge Status offset */ 707 #define PCI_PCIX_BDG_STATUS_USC 0x80000 708 #define PCI_PCIX_BDG_STATUS_SCO 0x100000 709 #define PCI_PCIX_BDG_STATUS_SRD 0x200000 710 #define PCI_PCIX_BDG_STATUS_ERR_MASK 0x380000 711 712 #define PCI_PCIX_UP_SPL_CTL 0x8 /* Upstream split ctrl reg offset */ 713 #define PCI_PCIX_DOWN_SPL_CTL 0xC /* Downstream split ctrl reg offset */ 714 #define PCI_PCIX_BDG_ECC_STATUS 0x10 /* ECC Status register offset */ 715 #define PCI_PCIX_BDG_ECC_FST_AD 0x14 /* ECC First address register offset */ 716 #define PCI_PCIX_BDG_ECC_SEC_AD 0x18 /* ECC Second address register offset */ 717 #define PCI_PCIX_BDG_ECC_ATTR 0x1C /* ECC Attribute register offset */ 718 719 /* 720 * PCIX capabilities values 721 */ 722 #define PCI_PCIX_VER_MASK 0x3000 /* Bits 12 and 13 */ 723 #define PCI_PCIX_VER_0 0x0000 /* PCIX cap list item version 0 */ 724 #define PCI_PCIX_VER_1 0x1000 /* PCIX cap list item version 1 */ 725 #define PCI_PCIX_VER_2 0x2000 /* PCIX cap list item version 2 */ 726 727 #define PCI_PCIX_SPL_DSCD 0x40000 /* Split Completion Discarded */ 728 #define PCI_PCIX_UNEX_SPL 0x80000 /* Unexpected Split Completion */ 729 #define PCI_PCIX_RX_SPL_MSG 0x20000000 /* Recieved Spl Comp Error Message */ 730 731 #define PCI_PCIX_ECC_SEL 0x1 /* Secondary ECC register select */ 732 #define PCI_PCIX_ECC_EP 0x2 /* Error Present on other side */ 733 #define PCI_PCIX_ECC_S_CE 0x4 /* Addl Correctable ECC Error */ 734 #define PCI_PCIX_ECC_S_UE 0x8 /* Addl Uncorrectable ECC Error */ 735 #define PCI_PCIX_ECC_PHASE 0x70 /* ECC Error Phase */ 736 #define PCI_PCIX_ECC_CORR 0x80 /* ECC Error Corrected */ 737 #define PCI_PCIX_ECC_SYN 0xff00 /* ECC Error Syndrome */ 738 #define PCI_PCIX_ECC_FST_CMD 0xf0000 /* ECC Error First Command */ 739 #define PCI_PCIX_ECC_SEC_CMD 0xf00000 /* ECC Error Second Command */ 740 #define PCI_PCIX_ECC_UP_ATTR 0xf000000 /* ECC Error Upper Attributes */ 741 742 /* 743 * PCIX ECC Phase Values 744 */ 745 #define PCI_PCIX_ECC_PHASE_NOERR 0x0 746 #define PCI_PCIX_ECC_PHASE_FADDR 0x1 747 #define PCI_PCIX_ECC_PHASE_SADDR 0x2 748 #define PCI_PCIX_ECC_PHASE_ATTR 0x3 749 #define PCI_PCIX_ECC_PHASE_DATA32 0x4 750 #define PCI_PCIX_ECC_PHASE_DATA64 0x5 751 752 /* 753 * PCI-X Command Encoding 754 */ 755 #define PCI_PCIX_CMD_INTR 0x0 756 #define PCI_PCIX_CMD_SPEC 0x1 757 #define PCI_PCIX_CMD_IORD 0x2 758 #define PCI_PCIX_CMD_IOWR 0x3 759 #define PCI_PCIX_CMD_DEVID 0x5 760 #define PCI_PCIX_CMD_MEMRD_DW 0x6 761 #define PCI_PCIX_CMD_MEMWR 0x7 762 #define PCI_PCIX_CMD_MEMRD_BL 0x8 763 #define PCI_PCIX_CMD_MEMWR_BL 0x9 764 #define PCI_PCIX_CMD_CFRD 0xA 765 #define PCI_PCIX_CMD_CFWR 0xB 766 #define PCI_PCIX_CMD_SPL 0xC 767 #define PCI_PCIX_CMD_DADR 0xD 768 #define PCI_PCIX_CMD_MEMRDBL 0xE 769 #define PCI_PCIX_CMD_MEMWRBL 0xF 770 771 #if defined(_BIT_FIELDS_LTOH) 772 typedef struct pcix_attr { 773 uint32_t lbc :8, 774 rid :16, 775 tag :5, 776 ro :1, 777 ns :1, 778 r :1; 779 } pcix_attr_t; 780 #elif defined(_BIT_FIELDS_HTOL) 781 typedef struct pcix_attr { 782 uint32_t r :1, 783 ns :1, 784 ro :1, 785 tag :5, 786 rid :16, 787 lbc :8; 788 } pcix_attr_t; 789 #else 790 #error "bit field not defined" 791 #endif 792 793 #define PCI_PCIX_BSS_SPL_DSCD 0x4 /* Secondary split comp discarded */ 794 #define PCI_PCIX_BSS_UNEX_SPL 0x8 /* Secondary unexpected split comp */ 795 #define PCI_PCIX_BSS_SPL_OR 0x10 /* Secondary split comp overrun */ 796 #define PCI_PCIX_BSS_SPL_DLY 0x20 /* Secondary split comp delayed */ 797 798 /* 799 * PCI Message Signalled Interrupts (MSI) capability entry offsets for 32-bit 800 */ 801 #define PCI_MSI_CTRL 0x02 /* MSI control register, 2 bytes */ 802 #define PCI_MSI_ADDR_OFFSET 0x04 /* MSI 32-bit msg address, 4 bytes */ 803 #define PCI_MSI_32BIT_DATA 0x08 /* MSI 32-bit msg data, 2 bytes */ 804 #define PCI_MSI_32BIT_MASK 0x0C /* MSI 32-bit mask bits, 4 bytes */ 805 #define PCI_MSI_32BIT_PENDING 0x10 /* MSI 32-bit pending bits, 4 bytes */ 806 807 /* 808 * PCI Message Signalled Interrupts (MSI) capability entry offsets for 64-bit 809 */ 810 #define PCI_MSI_64BIT_DATA 0x0C /* MSI 64-bit msg data, 2 bytes */ 811 #define PCI_MSI_64BIT_MASKBITS 0x10 /* MSI 64-bit mask bits, 4 bytes */ 812 #define PCI_MSI_64BIT_PENDING 0x14 /* MSI 64-bit pending bits, 4 bytes */ 813 814 /* 815 * PCI Message Signalled Interrupts (MSI) capability masks and shifts 816 */ 817 #define PCI_MSI_ENABLE_BIT 0x0001 /* MSI enable mask in MSI ctrl reg */ 818 #define PCI_MSI_MMC_MASK 0x000E /* MMC mask in MSI ctrl reg */ 819 #define PCI_MSI_MMC_SHIFT 0x1 /* Shift for MMC bits */ 820 #define PCI_MSI_MME_MASK 0x0070 /* MME mask in MSI ctrl reg */ 821 #define PCI_MSI_MME_SHIFT 0x4 /* Shift for MME bits */ 822 #define PCI_MSI_64BIT_MASK 0x0080 /* 64bit support mask in MSI ctrl reg */ 823 #define PCI_MSI_PVM_MASK 0x0100 /* PVM support mask in MSI ctrl reg */ 824 825 /* 826 * PCI Extended Message Signalled Interrupts (MSI-X) capability entry offsets 827 */ 828 #define PCI_MSIX_CTRL 0x02 /* MSI-X control register, 2 bytes */ 829 #define PCI_MSIX_TBL_OFFSET 0x04 /* MSI-X table offset, 4 bytes */ 830 #define PCI_MSIX_TBL_BIR_MASK 0x0007 /* MSI-X table BIR mask */ 831 #define PCI_MSIX_PBA_OFFSET 0x08 /* MSI-X pending bit array, 4 bytes */ 832 #define PCI_MSIX_PBA_BIR_MASK 0x0007 /* MSI-X PBA BIR mask */ 833 834 #define PCI_MSIX_TBL_SIZE_MASK 0x07FF /* table size mask in MSI-X ctrl reg */ 835 #define PCI_MSIX_FUNCTION_MASK 0x4000 /* function mask in MSI-X ctrl reg */ 836 #define PCI_MSIX_ENABLE_BIT 0x8000 /* MSI-X enable mask in MSI-X ctl reg */ 837 838 #define PCI_MSIX_LOWER_ADDR_OFFSET 0 /* MSI-X lower addr offset */ 839 #define PCI_MSIX_UPPER_ADDR_OFFSET 4 /* MSI-X upper addr offset */ 840 #define PCI_MSIX_DATA_OFFSET 8 /* MSI-X data offset */ 841 #define PCI_MSIX_VECTOR_CTRL_OFFSET 12 /* MSI-X vector ctrl offset */ 842 #define PCI_MSIX_VECTOR_SIZE 16 /* MSI-X size of each vector */ 843 844 /* 845 * PCI Message Signalled Interrupts: other interesting constants 846 */ 847 #define PCI_MSI_MAX_INTRS 32 /* maximum MSI interrupts supported */ 848 #define PCI_MSIX_MAX_INTRS 2048 /* maximum MSI-X interrupts supported */ 849 850 /* 851 * PCI Slot Id Capabilities, 2 bytes 852 */ 853 /* Byte 1: Expansion Slot Register (ESR), Byte 2: Chassis Number Register */ 854 #define PCI_CAPSLOT_ESR_NSLOTS_MASK 0x1F /* Number of slots mask */ 855 #define PCI_CAPSLOT_ESR_FIC 0x20 /* First In Chassis bit */ 856 #define PCI_CAPSLOT_ESR_FIC_MASK 0x01 /* First In Chassis mask */ 857 #define PCI_CAPSLOT_ESR_FIC_SHIFT 5 /* First In Chassis shift */ 858 #define PCI_CAPSLOT_FIC(esr_reg) ((esr_reg) & PCI_CAPSLOT_ESR_FIC) 859 #define PCI_CAPSLOT_NSLOTS(esr_reg) ((esr_reg) & \ 860 PCI_CAPSLOT_ESR_NSLOTS_MASK) 861 862 /* 863 * other interesting PCI constants 864 */ 865 #define PCI_BASE_NUM 6 /* num of base regs in configuration header */ 866 #define PCI_BAR_SZ_32 4 /* size of 32 bit base addr reg in bytes */ 867 #define PCI_BAR_SZ_64 8 /* size of 64 bit base addr reg in bytes */ 868 #define PCI_BASE_SIZE 4 /* size of base reg in bytes */ 869 #define PCI_CONF_HDR_SIZE 256 /* configuration header size */ 870 #define PCI_MAX_BUS_NUM 256 /* Maximum PCI buses allowed */ 871 #define PCI_MAX_DEVICES 32 /* Max PCI devices allowed */ 872 #define PCI_MAX_FUNCTIONS 8 /* Max PCI functions allowed */ 873 #define PCI_MAX_CHILDREN PCI_MAX_DEVICES * PCI_MAX_FUNCTIONS 874 #define PCI_CLK_33MHZ (33 * 1000 * 1000) /* 33MHz clock speed */ 875 #define PCI_CLK_66MHZ (66 * 1000 * 1000) /* 66MHz clock speed */ 876 #define PCI_CLK_133MHZ (133 * 1000 * 1000) /* 133MHz clock speed */ 877 878 /* 879 * pci bus range definition 880 */ 881 typedef struct pci_bus_range { 882 uint32_t lo; 883 uint32_t hi; 884 } pci_bus_range_t; 885 886 /* 887 * The following typedef is used to represent an entry in the "ranges" 888 * property of a pci hostbridge device node. 889 */ 890 typedef struct pci_ranges { 891 uint32_t child_high; 892 uint32_t child_mid; 893 uint32_t child_low; 894 uint32_t parent_high; 895 uint32_t parent_low; 896 uint32_t size_high; 897 uint32_t size_low; 898 } pci_ranges_t; 899 900 /* 901 * The following typedef is used to represent an entry in the "ranges" 902 * property of a pci-pci bridge device node. 903 */ 904 typedef struct { 905 uint32_t child_high; 906 uint32_t child_mid; 907 uint32_t child_low; 908 uint32_t parent_high; 909 uint32_t parent_mid; 910 uint32_t parent_low; 911 uint32_t size_high; 912 uint32_t size_low; 913 } ppb_ranges_t; 914 915 /* 916 * This structure represents one entry of the 1275 "reg" property and 917 * "assigned-addresses" property for a PCI node. For the "reg" property, it 918 * may be one of an arbitrary length array for devices with multiple address 919 * windows. For the "assigned-addresses" property, it denotes an assigned 920 * physical address on the PCI bus. It may be one entry of the six entries 921 * for devices with multiple base registers. 922 * 923 * The physical address format is: 924 * 925 * Bit#: 33222222 22221111 11111100 00000000 926 * 10987654 32109876 54321098 76543210 927 * 928 * pci_phys_hi cell: np0000tt bbbbbbbb dddddfff rrrrrrrr 929 * pci_phys_mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh 930 * pci_phys_low cell: llllllll llllllll llllllll llllllll 931 * 932 * n is 0 if the address is relocatable, 1 otherwise 933 * p is 1 if the addressable region is "prefetchable", 0 otherwise 934 * t is 1 if the address range is aliased 935 * tt is the type code, denoting which address space 936 * bbbbbbbb is the 8-bit bus number 937 * ddddd is the 5-bit device number 938 * fff is the 3-bit function number 939 * rrrrrrrr is the 8-bit register number 940 * hh...hhh is the 32-bit unsigned number 941 * ll...lll is the 32-bit unsigned number 942 * 943 * The physical size format is: 944 * 945 * pci_size_hi cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh 946 * pci_size_low cell: llllllll llllllll llllllll llllllll 947 * 948 * hh...hhh is the 32-bit unsigned number 949 * ll...lll is the 32-bit unsigned number 950 */ 951 struct pci_phys_spec { 952 uint_t pci_phys_hi; /* child's address, hi word */ 953 uint_t pci_phys_mid; /* child's address, middle word */ 954 uint_t pci_phys_low; /* child's address, low word */ 955 uint_t pci_size_hi; /* high word of size field */ 956 uint_t pci_size_low; /* low word of size field */ 957 }; 958 959 typedef struct pci_phys_spec pci_regspec_t; 960 961 /* 962 * PCI masks for pci_phy_hi of PCI 1275 address cell. 963 */ 964 #define PCI_REG_REG_M 0xff /* register mask */ 965 #define PCI_REG_FUNC_M 0x700 /* function mask */ 966 #define PCI_REG_DEV_M 0xf800 /* device mask */ 967 #define PCI_REG_BUS_M 0xff0000 /* bus number mask */ 968 #define PCI_REG_ADDR_M 0x3000000 /* address space mask */ 969 #define PCI_REG_ALIAS_M 0x20000000 /* aliased bit mask */ 970 #define PCI_REG_PF_M 0x40000000 /* prefetch bit mask */ 971 #define PCI_REG_REL_M 0x80000000 /* relocation bit mask */ 972 #define PCI_REG_BDFR_M 0xffffff /* bus, dev, func, reg mask */ 973 #define PCI_REG_EXTREG_M 0xF0000000 /* extended config bits mask */ 974 975 #define PCI_REG_FUNC_SHIFT 8 /* Offset of function bits */ 976 #define PCI_REG_DEV_SHIFT 11 /* Offset of device bits */ 977 #define PCI_REG_BUS_SHIFT 16 /* Offset of bus bits */ 978 #define PCI_REG_ADDR_SHIFT 24 /* Offset of address bits */ 979 #define PCI_REG_EXTREG_SHIFT 28 /* Offset of ext. config bits */ 980 981 #define PCI_REG_REG_G(x) ((x) & PCI_REG_REG_M) 982 #define PCI_REG_FUNC_G(x) (((x) & PCI_REG_FUNC_M) >> PCI_REG_FUNC_SHIFT) 983 #define PCI_REG_DEV_G(x) (((x) & PCI_REG_DEV_M) >> PCI_REG_DEV_SHIFT) 984 #define PCI_REG_BUS_G(x) (((x) & PCI_REG_BUS_M) >> PCI_REG_BUS_SHIFT) 985 #define PCI_REG_ADDR_G(x) (((x) & PCI_REG_ADDR_M) >> PCI_REG_ADDR_SHIFT) 986 #define PCI_REG_BDFR_G(x) ((x) & PCI_REG_BDFR_M) 987 988 /* 989 * PCI bit encodings of pci_phys_hi of PCI 1275 address cell. 990 */ 991 #define PCI_ADDR_MASK PCI_REG_ADDR_M 992 #define PCI_ADDR_CONFIG 0x00000000 /* configuration address */ 993 #define PCI_ADDR_IO 0x01000000 /* I/O address */ 994 #define PCI_ADDR_MEM32 0x02000000 /* 32-bit memory address */ 995 #define PCI_ADDR_MEM64 0x03000000 /* 64-bit memory address */ 996 #define PCI_ALIAS_B PCI_REG_ALIAS_M /* aliased bit */ 997 #define PCI_PREFETCH_B PCI_REG_PF_M /* prefetch bit */ 998 #define PCI_RELOCAT_B PCI_REG_REL_M /* non-relocatable bit */ 999 #define PCI_CONF_ADDR_MASK 0x00ffffff /* mask for config address */ 1000 1001 #define PCI_HARDDEC_8514 2 /* number of reg entries for 8514 hard-decode */ 1002 #define PCI_HARDDEC_VGA 3 /* number of reg entries for VGA hard-decode */ 1003 #define PCI_HARDDEC_IDE 4 /* number of reg entries for IDE hard-decode */ 1004 #define PCI_HARDDEC_IDE_PRI 2 /* number of reg entries for IDE primary */ 1005 #define PCI_HARDDEC_IDE_SEC 2 /* number of reg entries for IDE secondary */ 1006 1007 /* 1008 * PCI Expansion ROM Header Format 1009 */ 1010 #define PCI_ROM_SIGNATURE 0x0 /* ROM Signature 0xaa55 */ 1011 #define PCI_ROM_ARCH_UNIQUE_START 0x2 /* Start of processor unique */ 1012 #define PCI_ROM_PCI_DATA_STRUCT_PTR 0x18 /* Ptr to PCI Data Structure */ 1013 1014 /* 1015 * PCI Data Structure 1016 * 1017 * The PCI Data Structure is located within the first 64KB 1018 * of the ROM image and must be DWORD aligned. 1019 */ 1020 #define PCI_PDS_SIGNATURE 0x0 /* Signature, the string 'PCIR' */ 1021 #define PCI_PDS_VENDOR_ID 0x4 /* Vendor Identification */ 1022 #define PCI_PDS_DEVICE_ID 0x6 /* Device Identification */ 1023 #define PCI_PDS_VPD_PTR 0x8 /* Pointer to Vital Product Data */ 1024 #define PCI_PDS_PDS_LENGTH 0xa /* PCI Data Structure Length */ 1025 #define PCI_PDS_PDS_REVISION 0xc /* PCI Data Structure Revision */ 1026 #define PCI_PDS_CLASS_CODE 0xd /* Class Code */ 1027 #define PCI_PDS_IMAGE_LENGTH 0x10 /* Image Length in 512 byte units */ 1028 #define PCI_PDS_CODE_REVISON 0x12 /* Revision Level of Code/Data */ 1029 #define PCI_PDS_CODE_TYPE 0x14 /* Code Type */ 1030 #define PCI_PDS_INDICATOR 0x15 /* Indicates if image is last in ROM */ 1031 1032 #define PCI_PDS_CODE_TYPE_PCAT 0x0 /* Intel x86/PC-AT Type */ 1033 #define PCI_PDS_CODE_TYPE_OPEN_FW 0x1 /* Open Firmware */ 1034 1035 /* 1036 * we recognize the non transparent bridge child nodes with the 1037 * following property. This is specific to an implementation only. 1038 * This property is specific to AP nodes only. 1039 */ 1040 #define PCI_DEV_CONF_MAP_PROP "pci-parent-indirect" 1041 1042 /* 1043 * If a bridge device provides its own config space access services, 1044 * and supports a hotplug/hotswap bus below at any level, then 1045 * the following property must be defined for the node either by 1046 * the driver or the OBP. 1047 */ 1048 #define PCI_BUS_CONF_MAP_PROP "pci-conf-indirect" 1049 1050 #ifdef __cplusplus 1051 } 1052 #endif 1053 1054 #endif /* _SYS_PCI_H */ 1055