xref: /titanic_50/usr/src/uts/common/sys/pci.h (revision 049fa28a1fa444b1ffffe4e619e7e39fbd617462)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef	_SYS_PCI_H
27 #define	_SYS_PCI_H
28 
29 #pragma ident	"%Z%%M%	%I%	%E% SMI"
30 
31 #ifdef	__cplusplus
32 extern "C" {
33 #endif
34 
35 /*
36  * PCI Configuration Header offsets
37  */
38 #define	PCI_CONF_VENID		0x0	/* vendor id, 2 bytes */
39 #define	PCI_CONF_DEVID		0x2	/* device id, 2 bytes */
40 #define	PCI_CONF_COMM		0x4	/* command register, 2 bytes */
41 #define	PCI_CONF_STAT		0x6	/* status register, 2 bytes */
42 #define	PCI_CONF_REVID		0x8	/* revision id, 1 byte */
43 #define	PCI_CONF_PROGCLASS	0x9	/* programming class code, 1 byte */
44 #define	PCI_CONF_SUBCLASS	0xA	/* sub-class code, 1 byte */
45 #define	PCI_CONF_BASCLASS	0xB	/* basic class code, 1 byte */
46 #define	PCI_CONF_CACHE_LINESZ	0xC	/* cache line size, 1 byte */
47 #define	PCI_CONF_LATENCY_TIMER	0xD	/* latency timer, 1 byte */
48 #define	PCI_CONF_HEADER		0xE	/* header type, 1 byte */
49 #define	PCI_CONF_BIST		0xF	/* builtin self test, 1 byte */
50 
51 /*
52  * Header type 0 offsets
53  */
54 #define	PCI_CONF_BASE0		0x10	/* base register 0, 4 bytes */
55 #define	PCI_CONF_BASE1		0x14	/* base register 1, 4 bytes */
56 #define	PCI_CONF_BASE2		0x18	/* base register 2, 4 bytes */
57 #define	PCI_CONF_BASE3		0x1c	/* base register 3, 4 bytes */
58 #define	PCI_CONF_BASE4		0x20	/* base register 4, 4 bytes */
59 #define	PCI_CONF_BASE5		0x24	/* base register 5, 4 bytes */
60 #define	PCI_CONF_CIS		0x28	/* Cardbus CIS Pointer */
61 #define	PCI_CONF_SUBVENID	0x2c	/* Subsystem Vendor ID */
62 #define	PCI_CONF_SUBSYSID	0x2e	/* Subsystem ID */
63 #define	PCI_CONF_ROM		0x30	/* ROM base register, 4 bytes */
64 #define	PCI_CONF_CAP_PTR	0x34	/* capabilities pointer, 1 byte */
65 #define	PCI_CONF_ILINE		0x3c	/* interrupt line, 1 byte */
66 #define	PCI_CONF_IPIN		0x3d	/* interrupt pin, 1 byte */
67 #define	PCI_CONF_MIN_G		0x3e	/* minimum grant, 1 byte */
68 #define	PCI_CONF_MAX_L		0x3f	/* maximum grant, 1 byte */
69 
70 /*
71  * PCI to PCI bridge configuration space header format
72  */
73 #define	PCI_BCNF_PRIBUS		0x18	/* primary bus number */
74 #define	PCI_BCNF_SECBUS		0x19	/* secondary bus number */
75 #define	PCI_BCNF_SUBBUS		0x1a	/* subordinate bus number */
76 #define	PCI_BCNF_LATENCY_TIMER	0x1b
77 #define	PCI_BCNF_IO_BASE_LOW	0x1c
78 #define	PCI_BCNF_IO_LIMIT_LOW	0x1d
79 #define	PCI_BCNF_SEC_STATUS	0x1e
80 #define	PCI_BCNF_MEM_BASE	0x20
81 #define	PCI_BCNF_MEM_LIMIT	0x22
82 #define	PCI_BCNF_PF_BASE_LOW	0x24
83 #define	PCI_BCNF_PF_LIMIT_LOW	0x26
84 #define	PCI_BCNF_PF_BASE_HIGH	0x28
85 #define	PCI_BCNF_PF_LIMIT_HIGH	0x2c
86 #define	PCI_BCNF_IO_BASE_HI	0x30
87 #define	PCI_BCNF_IO_LIMIT_HI	0x32
88 #define	PCI_BCNF_CAP_PTR	0x34
89 #define	PCI_BCNF_ROM		0x38
90 #define	PCI_BCNF_ILINE		0x3c
91 #define	PCI_BCNF_IPIN		0x3d
92 #define	PCI_BCNF_BCNTRL		0x3e
93 
94 #define	PCI_BCNF_BASE_NUM	0x2
95 
96 /*
97  * PCI to PCI bridge control register (0x3e) format
98  */
99 #define	PCI_BCNF_BCNTRL_PARITY_ENABLE	0x1
100 #define	PCI_BCNF_BCNTRL_SERR_ENABLE	0x2
101 #define	PCI_BCNF_BCNTRL_MAST_AB_MODE	0x20
102 #define	PCI_BCNF_BCNTRL_DTO_STAT	0x400
103 
104 #define	PCI_BCNF_IO_MASK	0xf0
105 #define	PCI_BCNF_MEM_MASK	0xfff0
106 
107 /*
108  * Header type 2 (Cardbus) offsets
109  */
110 #define	PCI_CBUS_SOCK_REG	0x10	/* Cardbus socket regs, 4 bytes */
111 #define	PCI_CBUS_RESERVED1	0x14	/* Reserved, 2 bytes */
112 #define	PCI_CBUS_SEC_STATUS	0x16	/* Secondary status, 2 bytes */
113 #define	PCI_CBUS_PCI_BUS_NO	0x18	/* PCI bus number, 1 byte */
114 #define	PCI_CBUS_CBUS_NO	0x19	/* Cardbus bus number, 1 byte */
115 #define	PCI_CBUS_SUB_BUS_NO	0x1a	/* Subordinate bus number, 1 byte */
116 #define	PCI_CBUS_LATENCY_TIMER	0x1b	/* Cardbus latency timer, 1 byte */
117 #define	PCI_CBUS_MEM_BASE0	0x1c	/* Memory base reg 0, 4 bytes */
118 #define	PCI_CBUS_MEM_LIMIT0	0x20	/* Memory limit reg 0, 4 bytes */
119 #define	PCI_CBUS_MEM_BASE1	0x24	/* Memory base reg 1, 4 bytes */
120 #define	PCI_CBUS_MEM_LIMIT1	0x28	/* Memory limit reg 1, 4 bytes */
121 #define	PCI_CBUS_IO_BASE0	0x2c	/* IO base reg 0, 4 bytes */
122 #define	PCI_CBUS_IO_LIMIT0	0x30	/* IO limit reg 0, 4 bytes */
123 #define	PCI_CBUS_IO_BASE1	0x34	/* IO base reg 1, 4 bytes */
124 #define	PCI_CBUS_IO_LIMIT1	0x38	/* IO limit reg 1, 4 bytes */
125 #define	PCI_CBUS_ILINE		0x3c	/* interrupt line, 1 byte */
126 #define	PCI_CBUS_IPIN		0x3d	/* interrupt pin, 1 byte */
127 #define	PCI_CBUS_BRIDGE_CTRL	0x3e	/* Bridge control, 2 bytes */
128 #define	PCI_CBUS_BRIDGE_CTRL	0x3e	/* Bridge control, 2 bytes */
129 #define	PCI_CBUS_SUBVENID	0x40	/* Subsystem Vendor ID, 2 bytes */
130 #define	PCI_CBUS_SUBSYSID	0x42	/* Subsystem ID, 2 bytes */
131 #define	PCI_CBUS_LEG_MODE_ADDR	0x44	/* PCCard 16bit IF legacy mode addr */
132 
133 #define	PCI_CBUS_BASE_NUM	0x1	/* number of base registers */
134 
135 /*
136  * PCI command register bits
137  */
138 #define	PCI_COMM_IO		0x1	/* I/O access enable */
139 #define	PCI_COMM_MAE		0x2	/* memory access enable */
140 #define	PCI_COMM_ME		0x4	/* master enable */
141 #define	PCI_COMM_SPEC_CYC	0x8
142 #define	PCI_COMM_MEMWR_INVAL	0x10
143 #define	PCI_COMM_PALETTE_SNOOP	0x20
144 #define	PCI_COMM_PARITY_DETECT	0x40
145 #define	PCI_COMM_WAIT_CYC_ENAB	0x80
146 #define	PCI_COMM_SERR_ENABLE	0x100
147 #define	PCI_COMM_BACK2BACK_ENAB	0x200
148 #define	PCI_COMM_INTX_DISABLE	0x400	/* INTx emulation disable */
149 
150 /*
151  * PCI Interrupt pin value
152  */
153 #define	PCI_INTA	1
154 #define	PCI_INTB	2
155 #define	PCI_INTC	3
156 #define	PCI_INTD	4
157 
158 /*
159  * PCI status register bits
160  */
161 #define	PCI_STAT_INTR		0x8	/* Interrupt state */
162 #define	PCI_STAT_CAP		0x10	/* Implements Capabilities */
163 #define	PCI_STAT_66MHZ		0x20	/* 66 MHz capable */
164 #define	PCI_STAT_UDF		0x40	/* UDF supported */
165 #define	PCI_STAT_FBBC		0x80	/* Fast Back-to-Back Capable */
166 #define	PCI_STAT_S_PERROR	0x100	/* Data Parity Reported */
167 #define	PCI_STAT_DEVSELT	0x600	/* Device select timing */
168 #define	PCI_STAT_S_TARG_AB	0x800	/* Signaled Target Abort */
169 #define	PCI_STAT_R_TARG_AB	0x1000	/* Received Target Abort */
170 #define	PCI_STAT_R_MAST_AB	0x2000	/* Received Master Abort */
171 #define	PCI_STAT_S_SYSERR	0x4000	/* Signaled System Error */
172 #define	PCI_STAT_PERROR		0x8000	/* Detected Parity Error */
173 
174 /*
175  * DEVSEL timing values
176  */
177 #define	PCI_STAT_DEVSELT_FAST	0x0000
178 #define	PCI_STAT_DEVSELT_MEDIUM	0x0200
179 #define	PCI_STAT_DEVSELT_SLOW	0x0400
180 
181 /*
182  * BIST values
183  */
184 #define	PCI_BIST_SUPPORTED	0x80
185 #define	PCI_BIST_GO		0x40
186 #define	PCI_BIST_RESULT_M	0x0f
187 #define	PCI_BIST_RESULT_OK	0x00
188 
189 /*
190  * PCI class codes
191  */
192 #define	PCI_CLASS_NONE		0x0	/* class code for pre-2.0 devices */
193 #define	PCI_CLASS_MASS		0x1	/* Mass storage Controller class */
194 #define	PCI_CLASS_NET		0x2	/* Network Controller class */
195 #define	PCI_CLASS_DISPLAY	0x3	/* Display Controller class */
196 #define	PCI_CLASS_MM		0x4	/* Multimedia Controller class */
197 #define	PCI_CLASS_MEM		0x5	/* Memory Controller class */
198 #define	PCI_CLASS_BRIDGE	0x6	/* Bridge Controller class */
199 #define	PCI_CLASS_COMM		0x7	/* Communications Controller class */
200 #define	PCI_CLASS_PERIPH	0x8	/* Peripheral Controller class */
201 #define	PCI_CLASS_INPUT		0x9	/* Input Device class */
202 #define	PCI_CLASS_DOCK		0xa	/* Docking Station class */
203 #define	PCI_CLASS_PROCESSOR	0xb	/* Processor class */
204 #define	PCI_CLASS_SERIALBUS	0xc	/* Serial Bus class */
205 #define	PCI_CLASS_WIRELESS	0xd	/* Wireless Controller class */
206 #define	PCI_CLASS_INTIO		0xe	/* Intelligent IO Controller class */
207 #define	PCI_CLASS_SATELLITE	0xf	/* Satellite Communication class */
208 #define	PCI_CLASS_CRYPT		0x10	/* Encrytion/Decryption class */
209 #define	PCI_CLASS_SIGNAL	0x11	/* Signal Processing class */
210 
211 /*
212  * PCI Sub-class codes - base class 0x0 (no new devices should use this code).
213  */
214 #define	PCI_NONE_NOTVGA		0x0	/* All devices except VGA compatible */
215 #define	PCI_NONE_VGA		0x1	/* VGA compatible */
216 
217 /*
218  * PCI Sub-class codes - base class 0x1 (mass storage controllers)
219  */
220 #define	PCI_MASS_SCSI		0x0	/* SCSI bus Controller */
221 #define	PCI_MASS_IDE		0x1	/* IDE Controller */
222 #define	PCI_MASS_FD		0x2	/* floppy disk Controller */
223 #define	PCI_MASS_IPI		0x3	/* IPI bus Controller */
224 #define	PCI_MASS_RAID		0x4	/* RAID Controller */
225 #define	PCI_MASS_ATA		0x5	/* ATA Controller */
226 #define	PCI_MASS_SATA		0x6	/* Serial ATA */
227 #define	PCI_MASS_OTHER		0x80	/* Other Mass Storage Controller */
228 
229 /*
230  * programming interface for IDE (subclass 1)
231  */
232 #define	PCI_IDE_IF_NATIVE_PRI	0x1	/* primary channel is native */
233 #define	PCI_IDE_IF_PROG_PRI	0x2	/* primary can operate in either mode */
234 #define	PCI_IDE_IF_NATIVE_SEC	0x4	/* secondary channel is native */
235 #define	PCI_IDE_IF_PROG_SEC	0x8	/* sec. can operate in either mode */
236 #define	PCI_IDE_IF_MASK		0xf	/* programming interface mask */
237 
238 
239 /*
240  * programming interface for ATA (subclass 5)
241  */
242 #define	PCI_ATA_IF_SINGLE_DMA	0x20	/* ATA controller with single DMA */
243 #define	PCI_ATA_IF_CHAINED_DMA	0x30	/* ATA controller with chained DMA */
244 
245 /*
246  * PCI Sub-class codes - base class 0x2 (Network controllers)
247  */
248 #define	PCI_NET_ENET		0x0	/* Ethernet Controller */
249 #define	PCI_NET_TOKEN		0x1	/* Token Ring Controller */
250 #define	PCI_NET_FDDI		0x2	/* FDDI Controller */
251 #define	PCI_NET_ATM		0x3	/* ATM Controller */
252 #define	PCI_NET_ISDN		0x4	/* ISDN Controller */
253 #define	PCI_NET_WFIP		0x5	/* WorldFip Controller */
254 #define	PCI_NET_PICMG		0x6	/* PICMG 2.14 Multi Computing */
255 #define	PCI_NET_OTHER		0x80	/* Other Network Controller */
256 
257 /*
258  * PCI Sub-class codes - base class 03 (display controllers)
259  */
260 #define	PCI_DISPLAY_VGA		0x0	/* VGA device */
261 #define	PCI_DISPLAY_XGA		0x1	/* XGA device */
262 #define	PCI_DISPLAY_3D		0x2	/* 3D controller */
263 #define	PCI_DISPLAY_OTHER	0x80	/* Other Display Device */
264 
265 /*
266  * programming interface for display for display class (subclass 0) VGA ctrlrs
267  */
268 #define	PCI_DISPLAY_IF_VGA	0x0	/* VGA compatible */
269 #define	PCI_DISPLAY_IF_8514	0x1	/* 8514 compatible */
270 
271 /*
272  * PCI Sub-class codes - base class 0x4 (multi-media devices)
273  */
274 #define	PCI_MM_VIDEO		0x0	/* Video device */
275 #define	PCI_MM_AUDIO		0x1	/* Audio device */
276 #define	PCI_MM_TELEPHONY	0x2	/* Computer Telephony device */
277 #define	PCI_MM_OTHER		0x80	/* Other Multimedia Device */
278 
279 /*
280  * PCI Sub-class codes - base class 0x5 (memory controllers)
281  */
282 #define	PCI_MEM_RAM		0x0	/* RAM device */
283 #define	PCI_MEM_FLASH		0x1	/* FLASH device */
284 #define	PCI_MEM_OTHER		0x80	/* Other Memory Controller */
285 
286 /*
287  * PCI Sub-class codes - base class 0x6 (Bridge devices)
288  */
289 #define	PCI_BRIDGE_HOST		0x0	/* Host/PCI Bridge */
290 #define	PCI_BRIDGE_ISA		0x1	/* PCI/ISA Bridge */
291 #define	PCI_BRIDGE_EISA		0x2	/* PCI/EISA Bridge */
292 #define	PCI_BRIDGE_MC		0x3	/* PCI/MC Bridge */
293 #define	PCI_BRIDGE_PCI		0x4	/* PCI/PCI Bridge */
294 #define	PCI_BRIDGE_PCMCIA	0x5	/* PCI/PCMCIA Bridge */
295 #define	PCI_BRIDGE_NUBUS	0x6	/* PCI/NUBUS Bridge */
296 #define	PCI_BRIDGE_CARDBUS	0x7	/* PCI/CARDBUS Bridge */
297 #define	PCI_BRIDGE_RACE		0x8	/* RACE-way Bridge */
298 #define	PCI_BRIDGE_STPCI	0x9	/* Semi-transparent PCI/PCI Bridge */
299 #define	PCI_BRIDGE_IB		0xA	/* InfiniBand/PCI host Bridge */
300 #define	PCI_BRIDGE_OTHER	0x80	/* PCI/Other Bridge Device */
301 
302 /*
303  * programming interface for Bridges class 0x6 (subclass 4) PCI-PCI bridge
304  */
305 #define	PCI_BRIDGE_PCI_IF_PCI2PCI	0x0	/* PCI-PCI bridge */
306 #define	PCI_BRIDGE_PCI_IF_SUBDECODE	0x1	/* Subtractive Decode */
307 						/* PCI/PCI bridge */
308 
309 /*
310  * programming interface for Bridges class 0x6 (subclass 08) RACEway bridge
311  */
312 #define	PCI_BRIDGE_RACE_IF_TRANSPARENT	0x0	/* Transport mode */
313 #define	PCI_BRIDGE_RACE_IF_ENDPOINT	0x1	/* Endpoint mode */
314 
315 /*
316  * programming interface for Bridges class 0x6 (subclass 09)
317  * Semi-transparent PCI-to-PCI bridge
318  */
319 #define	PCI_BRIDGE_STPCI_IF_PRIMARY	0x40	/* primary PCI side bus */
320 						/* facing system processor */
321 #define	PCI_BRIDGE_STPCI_IF_SECONDARY	0x80	/* secondary PCI side bus */
322 						/* facing system processor */
323 
324 /*
325  * PCI Sub-class codes - base class 0x7 (communication devices)
326  */
327 #define	PCI_COMM_GENERIC_XT	0x0	/* XT Compatible Serial Controller */
328 #define	PCI_COMM_PARALLEL	0x1	/* Parallel Port Controller */
329 #define	PCI_COMM_MSC		0x2	/* Multiport Serial Controller */
330 #define	PCI_COMM_MODEM		0x3	/* Modem Controller */
331 #define	PCI_COMM_GPIB		0x4	/* GPIB Controller */
332 #define	PCI_COMM_SMARTCARD	0x5	/* Smart Card Controller */
333 #define	PCI_COMM_OTHER		0x80	/* Other Communications Controller */
334 
335 /*
336  * Programming interfaces for class 0x7 / subclass 0x0 (Serial)
337  */
338 #define	PCI_COMM_SERIAL_IF_GENERIC	0x0	/* Generic XT-compat serial */
339 #define	PCI_COMM_SERIAL_IF_16450	0x1	/* 16450-compat serial ctrlr */
340 #define	PCI_COMM_SERIAL_IF_16550	0x2	/* 16550-compat serial ctrlr */
341 #define	PCI_COMM_SERIAL_IF_16650	0x3	/* 16650-compat serial ctrlr */
342 #define	PCI_COMM_SERIAL_IF_16750	0x4	/* 16750-compat serial ctrlr */
343 #define	PCI_COMM_SERIAL_IF_16850	0x5	/* 16850-compat serial ctrlr */
344 #define	PCI_COMM_SERIAL_IF_16950	0x6	/* 16950-compat serial ctrlr */
345 
346 /*
347  * Programming interfaces for class 0x7 / subclass 0x1 (Parallel)
348  */
349 #define	PCI_COMM_PARALLEL_IF_GENERIC	0x0	/* Generic Parallel port */
350 #define	PCI_COMM_PARALLEL_IF_BIDIRECT	0x1	/* Bi-directional Parallel */
351 #define	PCI_COMM_PARALLEL_IF_ECP	0x2	/* ECP 1.X Parallel port */
352 #define	PCI_COMM_PARALLEL_IF_1284	0x3	/* IEEE 1284 Parallel port */
353 #define	PCI_COMM_PARALLEL_IF_1284_TARG	0xFE	/* IEEE 1284 target device */
354 
355 /*
356  * Programming interfaces for class 0x7 / subclass 0x3 (Modem)
357  */
358 #define	PCI_COMM_MODEM_IF_GENERIC	0x0	/* Generic Modem */
359 #define	PCI_COMM_MODEM_IF_HAYES_16450	0x1	/* Hayes 16450-compat Modem */
360 #define	PCI_COMM_MODEM_IF_HAYES_16550	0x2	/* Hayes 16550-compat Modem */
361 #define	PCI_COMM_MODEM_IF_HAYES_16650	0x3	/* Hayes 16650-compat Modem */
362 #define	PCI_COMM_MODEM_IF_HAYES_16750	0x4	/* Hayes 16750-compat Modem */
363 
364 /*
365  * PCI Sub-class codes - base class 0x8
366  */
367 #define	PCI_PERIPH_PIC		0x0	/* Generic PIC */
368 #define	PCI_PERIPH_DMA		0x1	/* Generic DMA Controller */
369 #define	PCI_PERIPH_TIMER	0x2	/* Generic System Timer Controller */
370 #define	PCI_PERIPH_RTC		0x3	/* Generic RTC Controller */
371 #define	PCI_PERIPH_HPC		0x3	/* Generic PCI Hot-Plug Controller */
372 #define	PCI_PERIPH_OTHER	0x80	/* Other System Peripheral */
373 
374 /*
375  * Programming interfaces for class 0x8 / subclass 0x0 (interrupt controller)
376  */
377 #define	PCI_PERIPH_PIC_IF_GENERIC	0x0	/* Generic 8259 APIC */
378 #define	PCI_PERIPH_PIC_IF_ISA		0x1	/* ISA PIC */
379 #define	PCI_PERIPH_PIC_IF_EISA		0x2	/* EISA PIC */
380 #define	PCI_PERIPH_PIC_IF_IO_APIC	0x10	/* I/O APIC interrupt ctrlr */
381 #define	PCI_PERIPH_PIC_IF_IOX_APIC	0x20	/* I/O(x) APIC intr ctrlr */
382 
383 /*
384  * Programming interfaces for class 0x8 / subclass 0x1 (DMA controller)
385  */
386 #define	PCI_PERIPH_DMA_IF_GENERIC	0x0	/* Generic 8237 DMA ctrlr */
387 #define	PCI_PERIPH_DMA_IF_ISA		0x1	/* ISA DMA ctrlr */
388 #define	PCI_PERIPH_DMA_IF_EISA		0x2	/* EISA DMA ctrlr */
389 
390 /*
391  * Programming interfaces for class 0x8 / subclass 0x2 (timer)
392  */
393 #define	PCI_PERIPH_TIMER_IF_GENERIC	0x0	/* Generic 8254 system timer */
394 #define	PCI_PERIPH_TIMER_IF_ISA		0x1	/* ISA system timers */
395 #define	PCI_PERIPH_TIMER_IF_EISA	0x2	/* EISA system timers (two) */
396 
397 /*
398  * Programming interfaces for class 0x8 / subclass 0x3 (realtime clock)
399  */
400 #define	PCI_PERIPH_RTC_IF_GENERIC	0x0	/* Generic RTC controller */
401 #define	PCI_PERIPH_RTC_IF_ISA		0x1	/* ISA RTC controller */
402 
403 /*
404  * PCI Sub-class codes - base class 0x9
405  */
406 #define	PCI_INPUT_KEYBOARD	0x0	/* Keyboard Controller */
407 #define	PCI_INPUT_DIGITIZ	0x1	/* Digitizer (Pen) */
408 #define	PCI_INPUT_MOUSE		0x2	/* Mouse Controller */
409 #define	PCI_INPUT_SCANNER	0x3	/* Scanner Controller */
410 #define	PCI_INPUT_GAMEPORT	0x4	/* Gameport Controller */
411 #define	PCI_INPUT_OTHER		0x80	/* Other Input Controller */
412 
413 /*
414  * Programming interfaces for class 0x9 / subclass 0x4 (Gameport controller)
415  */
416 #define	PCI_INPUT_GAMEPORT_IF_GENERIC	0x00	/* Generic controller */
417 #define	PCI_INPUT_GAMEPORT_IF_LEGACY	0x10	/* Legacy controller */
418 
419 /*
420  * PCI Sub-class codes - base class 0xa
421  */
422 #define	PCI_DOCK_GENERIC	0x00	/* Generic Docking Station */
423 #define	PCI_DOCK_OTHER		0x80	/* Other Type of Docking Station */
424 
425 /*
426  * PCI Sub-class codes - base class 0xb
427  */
428 #define	PCI_PROCESSOR_386	0x0	/* 386 */
429 #define	PCI_PROCESSOR_486	0x1	/* 486 */
430 #define	PCI_PROCESSOR_PENT	0x2	/* Pentium */
431 #define	PCI_PROCESSOR_ALPHA	0x10	/* Alpha */
432 #define	PCI_PROCESSOR_POWERPC	0x20	/* PowerPC */
433 #define	PCI_PROCESSOR_MIPS	0x30	/* MIPS */
434 #define	PCI_PROCESSOR_COPROC	0x40	/* Co-processor */
435 
436 /*
437  * PCI Sub-class codes - base class 0xc (Serial Controllers)
438  */
439 #define	PCI_SERIAL_FIRE		0x0	/* FireWire (IEEE 1394) */
440 #define	PCI_SERIAL_ACCESS	0x1	/* ACCESS.bus */
441 #define	PCI_SERIAL_SSA		0x2	/* SSA */
442 #define	PCI_SERIAL_USB		0x3	/* Universal Serial Bus */
443 #define	PCI_SERIAL_FIBRE	0x4	/* Fibre Channel */
444 #define	PCI_SERIAL_SMBUS	0x5	/* System Management Bus */
445 #define	PCI_SERIAL_IB		0x6	/* InfiniBand */
446 #define	PCI_SERIAL_IPMI		0x7	/* IPMI */
447 #define	PCI_SERIAL_SERCOS	0x8	/* SERCOS Interface Std (IEC 61491) */
448 #define	PCI_SERIAL_CANBUS	0x9	/* CANbus */
449 
450 /*
451  * Programming interfaces for class 0xC / subclass 0x3 (USB controller)
452  */
453 #define	PCI_SERIAL_USB_IF_UHCI 		0x00	/* UHCI Compliant */
454 #define	PCI_SERIAL_USB_IF_OHCI 		0x10	/* OHCI Compliant */
455 #define	PCI_SERIAL_USB_IF_EHCI 		0x20	/* EHCI Compliant */
456 #define	PCI_SERIAL_USB_IF_GENERIC 	0x80	/* no specific HCD */
457 #define	PCI_SERIAL_USB_IF_DEVICE 	0xFE	/* not a HCD */
458 
459 /*
460  * Programming interfaces for class 0xC / subclass 0x7 (IPMI controller)
461  */
462 #define	PCI_SERIAL_IPMI_IF_SMIC 	0x0	/* SMIC Interface */
463 #define	PCI_SERIAL_IPMI_IF_KBD 		0x1	/* Keyboard Ctrl Style Intfc */
464 #define	PCI_SERIAL_IPMI_IF_BTI		0x2	/* Block Transfer Interface */
465 
466 /*
467  * PCI Sub-class codes - base class 0xd (Wireless controllers)
468  */
469 #define	PCI_WIRELESS_IRDA		0x0	/* iRDA Compatible Controller */
470 #define	PCI_WIRELESS_IR			0x1	/* Consumer IR Controller */
471 #define	PCI_WIRELESS_RF			0x10	/* RF Controller */
472 #define	PCI_WIRELESS_BLUETOOTH		0x11	/* Bluetooth Controller */
473 #define	PCI_WIRELESS_BROADBAND		0x12	/* Broadband Controller */
474 #define	PCI_WIRELESS_80211A		0x20	/* Ethernet 802.11a 5 GHz */
475 #define	PCI_WIRELESS_80211B		0x21	/* Ethernet 802.11b 2.4 GHz */
476 #define	PCI_WIRELESS_OTHER		0x80	/* Other Wireless Controllers */
477 
478 /*
479  * PCI Sub-class codes - base class 0xe (Intelligent I/O controllers)
480  */
481 #define	PCI_INTIO_I20			0x1	/* I20 Arch Spec 1.0 */
482 
483 /*
484  * PCI Sub-class codes - base class 0xf (Satellite Communication controllers)
485  */
486 #define	PCI_SATELLITE_COMM_TV		0x01	/* TV */
487 #define	PCI_SATELLITE_COMM_AUDIO	0x02	/* Audio */
488 #define	PCI_SATELLITE_COMM_VOICE	0x03	/* Voice */
489 #define	PCI_SATELLITE_COMM_DATA		0x04	/* DATA */
490 
491 /*
492  * PCI Sub-class codes - base class 0x10 (Encryption/Decryption controllers)
493  */
494 #define	PCI_CRYPT_NETWORK		0x00	/* Network and Computing */
495 #define	PCI_CRYPT_ENTERTAINMENT		0x10	/* Entertainment en/decrypt */
496 #define	PCI_CRYPT_OTHER			0x80	/* Other en/decryption ctrlrs */
497 
498 /*
499  * PCI Sub-class codes - base class 0x11 (Signal Processing controllers)
500  */
501 #define	PCI_SIGNAL_DPIO			0x00	/* DPIO modules */
502 #define	PCI_SIGNAL_PERF_COUNTERS	0x01	/* Performance counters */
503 #define	PCI_SIGNAL_COMM_SYNC		0x10	/* Comm. synchronization plus */
504 						/* time and freq test ctrlr */
505 #define	PCI_SIGNAL_MANAGEMENT		0x20	/* Management card */
506 #define	PCI_SIGNAL_OTHER		0x80	/* DSP/DAP controller */
507 
508 /* PCI header decode */
509 #define	PCI_HEADER_MULTI	0x80	/* multi-function device */
510 #define	PCI_HEADER_ZERO		0x00	/* type zero PCI header */
511 #define	PCI_HEADER_ONE		0x01	/* type one PCI header */
512 #define	PCI_HEADER_TWO		0x02	/* type two PCI header */
513 #define	PCI_HEADER_PPB		PCI_HEADER_ONE  /* type one PCI to PCI Bridge */
514 #define	PCI_HEADER_CARDBUS	PCI_HEADER_TWO	/* type one PCI header */
515 
516 #define	PCI_HEADER_TYPE_M	0x7f  /* type mask for header */
517 
518 /*
519  * Base register bit definitions.
520  */
521 #define	PCI_BASE_SPACE_M    0x1  /* memory space indicator */
522 #define	PCI_BASE_SPACE_IO   0x1   /* IO space */
523 #define	PCI_BASE_SPACE_MEM  0x0   /* memory space */
524 
525 #define	PCI_BASE_TYPE_MEM   0x0   /* 32-bit memory address */
526 #define	PCI_BASE_TYPE_LOW   0x2   /* less than 1Mb address */
527 #define	PCI_BASE_TYPE_ALL   0x4   /* 64-bit memory address */
528 #define	PCI_BASE_TYPE_RES   0x6   /* reserved */
529 
530 #define	PCI_BASE_TYPE_M		0x00000006  /* type indicator mask */
531 #define	PCI_BASE_PREF_M		0x00000008  /* prefetch mask */
532 #define	PCI_BASE_M_ADDR_M	0xfffffff0  /* memory address mask */
533 #define	PCI_BASE_IO_ADDR_M	0xfffffffe  /* I/O address mask */
534 
535 #define	PCI_BASE_ROM_ADDR_M	0xfffff800  /* ROM address mask */
536 #define	PCI_BASE_ROM_ENABLE	0x00000001  /* ROM decoder enable */
537 
538 /*
539  * Capabilities linked list entry offsets
540  */
541 #define	PCI_CAP_ID		0x0	/* capability identifier, 1 byte */
542 #define	PCI_CAP_NEXT_PTR	0x1	/* next entry pointer, 1 byte */
543 #define	PCI_CAP_ID_REGS_OFF	0x2	/* cap id register offset */
544 #define	PCI_CAP_MAX_PTR		0x30	/* maximum number of cap pointers */
545 #define	PCI_CAP_PTR_OFF		0x40	/* minimum cap pointer offset */
546 #define	PCI_CAP_PTR_MASK	0xFC	/* mask for capability pointer */
547 
548 /*
549  * Capability identifier values
550  */
551 #define	PCI_CAP_ID_PM		0x1	/* power management entry */
552 #define	PCI_CAP_ID_AGP		0x2	/* AGP supported */
553 #define	PCI_CAP_ID_VPD		0x3	/* VPD supported */
554 #define	PCI_CAP_ID_SLOT_ID	0x4	/* Slot Identification supported */
555 #define	PCI_CAP_ID_MSI		0x5	/* MSI supported */
556 #define	PCI_CAP_ID_cPCI_HS	0x6	/* CompactPCI Host Swap supported */
557 #define	PCI_CAP_ID_PCIX		0x7	/* PCI-X supported */
558 #define	PCI_CAP_ID_HT		0x8	/* HyperTransport supported */
559 #define	PCI_CAP_ID_VS		0x9	/* Vendor Specific */
560 #define	PCI_CAP_ID_DEBUG_PORT	0xA	/* Debug Port supported */
561 #define	PCI_CAP_ID_cPCI_CRC	0xB	/* CompactPCI central resource ctrl */
562 #define	PCI_CAP_ID_PCI_HOTPLUG	0xC	/* PCI Hot Plug supported */
563 #define	PCI_CAP_ID_AGP_8X	0xE	/* AGP 8X supported */
564 #define	PCI_CAP_ID_SECURE_DEV	0xF	/* Secure Device supported */
565 #define	PCI_CAP_ID_PCI_E	0x10	/* PCI Express supported */
566 #define	PCI_CAP_ID_MSI_X	0x11	/* MSI-X supported */
567 
568 /*
569  * Capability next entry pointer values
570  */
571 #define	PCI_CAP_NEXT_PTR_NULL	0x0	/* no more entries in the list */
572 
573 /*
574  * PCI power management (PM) capability entry offsets
575  */
576 #define	PCI_PMCAP		0x2	/* PM capabilities, 2 bytes */
577 #define	PCI_PMCSR		0x4	/* PM control/status reg, 2 bytes */
578 #define	PCI_PMCSR_BSE		0x6	/* PCI-PCI bridge extensions, 1 byte */
579 #define	PCI_PMDATA		0x7	/* PM data, 1 byte */
580 
581 /*
582  * PM capabilities values - 2 bytes
583  */
584 #define	PCI_PMCAP_VER_1_0	0x1	/* PCI PM spec 1.0 */
585 #define	PCI_PMCAP_VER_1_1	0x2	/* PCI PM spec 1.1 */
586 #define	PCI_PMCAP_VER_MASK	0x7	/* version mask */
587 #define	PCI_PMCAP_PME_CLOCK	0x8	/* needs PCI clock for PME */
588 #define	PCI_PMCAP_DSI		0x20	/* needs device specific init */
589 #define	PCI_PMCAP_AUX_CUR_SELF	0x0	/* 0 aux current - self powered */
590 #define	PCI_PMCAP_AUX_CUR_55mA	0x40	/* 55 mA aux current */
591 #define	PCI_PMCAP_AUX_CUR_100mA	0x80	/* 100 mA aux current */
592 #define	PCI_PMCAP_AUX_CUR_160mA	0xc0	/* 160 mA aux current */
593 #define	PCI_PMCAP_AUX_CUR_220mA	0x100	/* 220 mA aux current */
594 #define	PCI_PMCAP_AUX_CUR_270mA	0x140	/* 270 mA aux current */
595 #define	PCI_PMCAP_AUX_CUR_320mA	0x180	/* 320 mA aux current */
596 #define	PCI_PMCAP_AUX_CUR_375mA	0x1c0	/* 375 mA aux current */
597 #define	PCI_PMCAP_AUX_CUR_MASK	0x1c0	/* 3.3Vaux aux current needs */
598 #define	PCI_PMCAP_D1		0x200	/* D1 state supported */
599 #define	PCI_PMCAP_D2		0x400	/* D2 state supported */
600 #define	PCI_PMCAP_D0_PME	0x800	/* PME from D0 */
601 #define	PCI_PMCAP_D1_PME	0x1000	/* PME from D1 */
602 #define	PCI_PMCAP_D2_PME	0x2000	/* PME from D2 */
603 #define	PCI_PMCAP_D3HOT_PME	0x4000	/* PME from D3hot */
604 #define	PCI_PMCAP_D3COLD_PME	0x8000	/* PME from D3cold */
605 #define	PCI_PMCAP_PME_MASK	0xf800	/* PME support mask */
606 
607 /*
608  * PM control/status values - 2 bytes
609  */
610 #define	PCI_PMCSR_D0			0x0	/* power state D0 */
611 #define	PCI_PMCSR_D1			0x1	/* power state D1 */
612 #define	PCI_PMCSR_D2			0x2	/* power state D2 */
613 #define	PCI_PMCSR_D3HOT			0x3	/* power state D3hot */
614 #define	PCI_PMCSR_STATE_MASK		0x3	/* power state mask */
615 #define	PCI_PMCSR_PME_EN		0x100	/* enable PME assertion */
616 #define	PCI_PMCSR_DSEL_D0_PWR_C		0x0	/* D0 power consumed */
617 #define	PCI_PMCSR_DSEL_D1_PWR_C		0x200	/* D1 power consumed */
618 #define	PCI_PMCSR_DSEL_D2_PWR_C		0x400	/* D2 power consumed */
619 #define	PCI_PMCSR_DSEL_D3_PWR_C		0x600	/* D3 power consumed */
620 #define	PCI_PMCSR_DSEL_D0_PWR_D		0x800	/* D0 power dissipated */
621 #define	PCI_PMCSR_DSEL_D1_PWR_D		0xa00	/* D1 power dissipated */
622 #define	PCI_PMCSR_DSEL_D2_PWR_D		0xc00	/* D2 power dissipated */
623 #define	PCI_PMCSR_DSEL_D3_PWR_D		0xe00	/* D3 power dissipated */
624 #define	PCI_PMCSR_DSEL_COM_C		0x1000	/* common power consumption */
625 #define	PCI_PMCSR_DSEL_MASK		0x1e00	/* data select mask */
626 #define	PCI_PMCSR_DSCL_UNKNOWN		0x0	/* data scale unknown */
627 #define	PCI_PMCSR_DSCL_1_BY_10		0x2000	/* data scale 0.1x */
628 #define	PCI_PMCSR_DSCL_1_BY_100		0x4000	/* data scale 0.01x */
629 #define	PCI_PMCSR_DSCL_1_BY_1000	0x6000	/* data scale 0.001x */
630 #define	PCI_PMCSR_DSCL_MASK		0x6000	/* data scale mask */
631 #define	PCI_PMCSR_PME_STAT		0x8000	/* PME status */
632 
633 /*
634  * PM PMCSR PCI to PCI bridge support extension values - 1 byte
635  */
636 #define	PCI_PMCSR_BSE_B2_B3	0x40	/* bridge D3hot -> secondary B2 */
637 #define	PCI_PMCSR_BSE_BPCC_EN	0x80	/* bus power/clock control enabled */
638 
639 /*
640  * PCI-X capability related definitions
641  */
642 #define	PCI_PCIX_COMMAND	0x2	/* Command register offset */
643 #define	PCI_PCIX_STATUS		0x4	/* Status register offset */
644 #define	PCI_PCIX_ECC_STATUS	0x8	/* ECC Status register offset */
645 #define	PCI_PCIX_ECC_FST_AD	0xC	/* ECC First address register offset */
646 #define	PCI_PCIX_ECC_SEC_AD	0x10	/* ECC Second address register offset */
647 #define	PCI_PCIX_ECC_ATTR	0x14	/* ECC Attribute register offset */
648 
649 /*
650  * PCI-X bridge capability related definitions
651  */
652 #define	PCI_PCIX_SEC_STATUS	0x2	/* Secondary status register offset */
653 #define	PCI_PCIX_BDG_STATUS	0x4	/* Bridge Status register offset */
654 #define	PCI_PCIX_UP_SPL_CTL	0x8	/* Upstream split ctrl reg offset */
655 #define	PCI_PCIX_DOWN_SPL_CTL	0xC	/* Downstream split ctrl reg offset */
656 #define	PCI_PCIX_BDG_ECC_STATUS	0x10	/* ECC Status register offset */
657 #define	PCI_PCIX_BDG_ECC_FST_AD	0x14	/* ECC First address register offset */
658 #define	PCI_PCIX_BDG_ECC_SEC_AD	0x18	/* ECC Second address register offset */
659 #define	PCI_PCIX_BDG_ECC_ATTR	0x1C	/* ECC Attribute register offset */
660 
661 /*
662  * PCIX capabilities values
663  */
664 #define	PCI_PCIX_VER_MASK	0x3000	/* Bits 12 and 13 */
665 #define	PCI_PCIX_VER_0		0x0000	/* PCIX cap list item version 0 */
666 #define	PCI_PCIX_VER_1		0x1000	/* PCIX cap list item version 1 */
667 #define	PCI_PCIX_VER_2		0x2000	/* PCIX cap list item version 2 */
668 
669 #define	PCI_PCIX_SPL_DSCD	0x40000 /* Split Completion Discarded */
670 #define	PCI_PCIX_UNEX_SPL	0x80000	/* Unexpected Split Completion */
671 #define	PCI_PCIX_RX_SPL_MSG	0x20000000 /* Recieved Spl Comp Error Message */
672 
673 #define	PCI_PCIX_ECC_SEL	0x1	/* Secondary ECC register select */
674 #define	PCI_PCIX_ECC_EP		0x2	/* Error Present on other side */
675 #define	PCI_PCIX_ECC_S_CE	0x4	/* Addl Correctable ECC Error */
676 #define	PCI_PCIX_ECC_S_UE	0x8	/* Addl Uncorrectable ECC Error */
677 #define	PCI_PCIX_ECC_PHASE	0x70	/* ECC Error Phase */
678 #define	PCI_PCIX_ECC_CORR	0x80	/* ECC Error Corrected */
679 #define	PCI_PCIX_ECC_SYN	0xff00	/* ECC Error Syndrome */
680 #define	PCI_PCIX_ECC_FST_CMD	0xf0000	 /* ECC Error First Command */
681 #define	PCI_PCIX_ECC_SEC_CMD	0xf00000 /* ECC Error Second Command */
682 #define	PCI_PCIX_ECC_UP_ATTR	0xf000000 /* ECC Error Upper Attributes */
683 
684 /*
685  * PCIX ECC Phase Values
686  */
687 #define	PCI_PCIX_ECC_PHASE_NOERR	0x0
688 #define	PCI_PCIX_ECC_PHASE_FADDR	0x1
689 #define	PCI_PCIX_ECC_PHASE_SADDR	0x2
690 #define	PCI_PCIX_ECC_PHASE_ATTR		0x3
691 #define	PCI_PCIX_ECC_PHASE_DATA32	0x4
692 #define	PCI_PCIX_ECC_PHASE_DATA64	0x5
693 
694 /*
695  * PCI-X Command Encoding
696  */
697 #define	PCI_PCIX_CMD_INTR		0x0
698 #define	PCI_PCIX_CMD_SPEC		0x1
699 #define	PCI_PCIX_CMD_IORD		0x2
700 #define	PCI_PCIX_CMD_IOWR		0x3
701 #define	PCI_PCIX_CMD_DEVID		0x5
702 #define	PCI_PCIX_CMD_MEMRD_DW		0x6
703 #define	PCI_PCIX_CMD_MEMWR		0x7
704 #define	PCI_PCIX_CMD_MEMRD_BL		0x8
705 #define	PCI_PCIX_CMD_MEMWR_BL		0x9
706 #define	PCI_PCIX_CMD_CFRD		0xA
707 #define	PCI_PCIX_CMD_CFWR		0xB
708 #define	PCI_PCIX_CMD_SPL		0xC
709 #define	PCI_PCIX_CMD_DADR		0xD
710 #define	PCI_PCIX_CMD_MEMRDBL		0xE
711 #define	PCI_PCIX_CMD_MEMWRBL		0xF
712 
713 #if defined(_BIT_FIELDS_LTOH)
714 typedef struct pcix_attr {
715 	uint32_t	lbc	:8,
716 			rid	:16,
717 			tag	:5,
718 			ro	:1,
719 			ns	:1,
720 			r	:1;
721 } pcix_attr_t;
722 #elif defined(_BIT_FIELDS_HTOL)
723 typedef struct pcix_attr {
724 	uint32_t	r	:1,
725 			ns	:1,
726 			ro	:1,
727 			tag	:5,
728 			rid	:16,
729 			lbc	:8;
730 } pcix_attr_t;
731 #else
732 #error "bit field not defined"
733 #endif
734 
735 #define	PCI_PCIX_BSS_SPL_DSCD	0x4	/* Secondary split comp discarded */
736 #define	PCI_PCIX_BSS_UNEX_SPL	0x8	/* Secondary unexpected split comp */
737 #define	PCI_PCIX_BSS_SPL_OR	0x10	/* Secondary split comp overrun */
738 #define	PCI_PCIX_BSS_SPL_DLY	0x20	/* Secondary split comp delayed */
739 
740 /*
741  * PCI Message Signalled Interrupts (MSI) capability entry offsets for 32-bit
742  */
743 #define	PCI_MSI_CTRL		0x02	/* MSI control register, 2 bytes */
744 #define	PCI_MSI_ADDR_OFFSET	0x04	/* MSI 32-bit msg address, 4 bytes */
745 #define	PCI_MSI_32BIT_DATA	0x08	/* MSI 32-bit msg data, 2 bytes */
746 #define	PCI_MSI_32BIT_MASK	0x0C	/* MSI 32-bit mask bits, 4 bytes */
747 #define	PCI_MSI_32BIT_PENDING	0x10	/* MSI 32-bit pending bits, 4 bytes */
748 
749 /*
750  * PCI Message Signalled Interrupts (MSI) capability entry offsets for 64-bit
751  */
752 #define	PCI_MSI_64BIT_DATA	0x0C	/* MSI 64-bit msg data, 2 bytes */
753 #define	PCI_MSI_64BIT_MASKBITS	0x10	/* MSI 64-bit mask bits, 4 bytes */
754 #define	PCI_MSI_64BIT_PENDING	0x14	/* MSI 64-bit pending bits, 4 bytes */
755 
756 /*
757  * PCI Message Signalled Interrupts (MSI) capability masks and shifts
758  */
759 #define	PCI_MSI_ENABLE_BIT	0x0001	/* MSI enable mask in MSI ctrl reg */
760 #define	PCI_MSI_MMC_MASK	0x000E	/* MMC mask in MSI ctrl reg */
761 #define	PCI_MSI_MMC_SHIFT	0x1	/* Shift for MMC bits */
762 #define	PCI_MSI_MME_MASK	0x0070	/* MME mask in MSI ctrl reg */
763 #define	PCI_MSI_MME_SHIFT	0x4	/* Shift for MME bits */
764 #define	PCI_MSI_64BIT_MASK	0x0080	/* 64bit support mask in MSI ctrl reg */
765 #define	PCI_MSI_PVM_MASK	0x0100	/* PVM support mask in MSI ctrl reg */
766 
767 /*
768  * PCI Extended Message Signalled Interrupts (MSI-X) capability entry offsets
769  */
770 #define	PCI_MSIX_CTRL		0x02	/* MSI-X control register, 2 bytes */
771 #define	PCI_MSIX_TBL_OFFSET	0x04	/* MSI-X table offset, 4 bytes */
772 #define	PCI_MSIX_TBL_BIR_MASK	0x0007	/* MSI-X table BIR mask */
773 #define	PCI_MSIX_PBA_OFFSET	0x08	/* MSI-X pending bit array, 4 bytes */
774 #define	PCI_MSIX_PBA_BIR_MASK	0x0007	/* MSI-X PBA BIR mask */
775 
776 #define	PCI_MSIX_TBL_SIZE_MASK	0x07FF	/* table size mask in MSI-X ctrl reg */
777 #define	PCI_MSIX_FUNCTION_MASK	0x4000	/* function mask in MSI-X ctrl reg */
778 #define	PCI_MSIX_ENABLE_BIT	0x8000	/* MSI-X enable mask in MSI-X ctl reg */
779 
780 #define	PCI_MSIX_LOWER_ADDR_OFFSET	0	/* MSI-X lower addr offset */
781 #define	PCI_MSIX_UPPER_ADDR_OFFSET	4	/* MSI-X upper addr offset */
782 #define	PCI_MSIX_DATA_OFFSET		8	/* MSI-X data offset */
783 #define	PCI_MSIX_VECTOR_CTRL_OFFSET	12	/* MSI-X vector ctrl offset */
784 #define	PCI_MSIX_VECTOR_SIZE		16	/* MSI-X size of each vector */
785 
786 /*
787  * PCI Message Signalled Interrupts: other interesting constants
788  */
789 #define	PCI_MSI_MAX_INTRS	32	/* maximum MSI interrupts supported */
790 #define	PCI_MSIX_MAX_INTRS	2048	/* maximum MSI-X interrupts supported */
791 
792 /*
793  * PCI Slot Id Capabilities, 2 bytes
794  */
795 /* Byte 1: Expansion Slot Register (ESR), Byte 2: Chassis Number Register */
796 #define	PCI_CAPSLOT_ESR_NSLOTS_MASK	0x1F	/* Number of slots mask */
797 #define	PCI_CAPSLOT_ESR_FIC		0x20	/* First In Chassis bit */
798 #define	PCI_CAPSLOT_ESR_FIC_MASK	0x01	/* First In Chassis mask */
799 #define	PCI_CAPSLOT_ESR_FIC_SHIFT	5	/* First In Chassis shift */
800 #define	PCI_CAPSLOT_FIC(esr_reg)	((esr_reg) & PCI_CAPSLOT_ESR_FIC)
801 #define	PCI_CAPSLOT_NSLOTS(esr_reg)	((esr_reg) & \
802 						PCI_CAPSLOT_ESR_NSLOTS_MASK)
803 
804 /*
805  * other interesting PCI constants
806  */
807 #define	PCI_BASE_NUM	6	/* num of base regs in configuration header */
808 #define	PCI_BAR_SZ_32	4	/* size of 32 bit base addr reg in bytes */
809 #define	PCI_BAR_SZ_64	8	/* size of 64 bit base addr reg in bytes */
810 #define	PCI_BASE_SIZE	4	/* size of base reg in bytes */
811 #define	PCI_CONF_HDR_SIZE	256	/* configuration header size */
812 #define	PCI_MAX_BUS_NUM		256		/* Maximum PCI buses allowed */
813 #define	PCI_CLK_33MHZ	(33 * 1000 * 1000)	/* 33MHz clock speed */
814 #define	PCI_CLK_66MHZ	(66 * 1000 * 1000)	/* 66MHz clock speed */
815 #define	PCI_CLK_133MHZ	(133 * 1000 * 1000)	/* 133MHz clock speed */
816 
817 /*
818  * pci bus range definition
819  */
820 typedef struct pci_bus_range {
821 	uint32_t lo;
822 	uint32_t hi;
823 } pci_bus_range_t;
824 
825 /*
826  * The following typedef is used to represent an entry in the "ranges"
827  * property of a pci hostbridge device node.
828  */
829 typedef struct pci_ranges {
830 	uint32_t child_high;
831 	uint32_t child_mid;
832 	uint32_t child_low;
833 	uint32_t parent_high;
834 	uint32_t parent_low;
835 	uint32_t size_high;
836 	uint32_t size_low;
837 } pci_ranges_t;
838 
839 /*
840  * The following typedef is used to represent an entry in the "ranges"
841  * property of a pci-pci bridge device node.
842  */
843 typedef struct {
844 	uint32_t child_high;
845 	uint32_t child_mid;
846 	uint32_t child_low;
847 	uint32_t parent_high;
848 	uint32_t parent_mid;
849 	uint32_t parent_low;
850 	uint32_t size_high;
851 	uint32_t size_low;
852 } ppb_ranges_t;
853 
854 /*
855  * This structure represents one entry of the 1275 "reg" property and
856  * "assigned-addresses" property for a PCI node.  For the "reg" property, it
857  * may be one of an arbitrary length array for devices with multiple address
858  * windows.  For the "assigned-addresses" property, it denotes an assigned
859  * physical address on the PCI bus.  It may be one entry of the six entries
860  * for devices with multiple base registers.
861  *
862  * The physical address format is:
863  *
864  *             Bit#:  33222222 22221111 11111100 00000000
865  *                    10987654 32109876 54321098 76543210
866  *
867  * pci_phys_hi cell:  np0000tt bbbbbbbb dddddfff rrrrrrrr
868  * pci_phys_mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
869  * pci_phys_low cell: llllllll llllllll llllllll llllllll
870  *
871  * n          is 0 if the address is relocatable, 1 otherwise
872  * p          is 1 if the addressable region is "prefetchable", 0 otherwise
873  * t          is 1 if the address range is aliased
874  * tt         is the type code, denoting which address space
875  * bbbbbbbb   is the 8-bit bus number
876  * ddddd      is the 5-bit device number
877  * fff        is the 3-bit function number
878  * rrrrrrrr   is the 8-bit register number
879  * hh...hhh   is the 32-bit unsigned number
880  * ll...lll   is the 32-bit unsigned number
881  *
882  * The physical size format is:
883  *
884  * pci_size_hi cell:  hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
885  * pci_size_low cell: llllllll llllllll llllllll llllllll
886  *
887  * hh...hhh   is the 32-bit unsigned number
888  * ll...lll   is the 32-bit unsigned number
889  */
890 struct pci_phys_spec {
891 	uint_t pci_phys_hi;		/* child's address, hi word */
892 	uint_t pci_phys_mid;		/* child's address, middle word */
893 	uint_t pci_phys_low;		/* child's address, low word */
894 	uint_t pci_size_hi;		/* high word of size field */
895 	uint_t pci_size_low;		/* low word of size field */
896 };
897 
898 typedef struct pci_phys_spec pci_regspec_t;
899 
900 /*
901  * PCI masks for pci_phy_hi of PCI 1275 address cell.
902  */
903 #define	PCI_REG_REG_M		0xff		/* register mask */
904 #define	PCI_REG_FUNC_M		0x700		/* function mask */
905 #define	PCI_REG_DEV_M		0xf800		/* device mask */
906 #define	PCI_REG_BUS_M		0xff0000	/* bus number mask */
907 #define	PCI_REG_ADDR_M		0x3000000	/* address space mask */
908 #define	PCI_REG_ALIAS_M		0x20000000	/* aliased bit mask */
909 #define	PCI_REG_PF_M		0x40000000	/* prefetch bit mask */
910 #define	PCI_REG_REL_M		0x80000000	/* relocation bit mask */
911 #define	PCI_REG_BDFR_M		0xffffff	/* bus, dev, func, reg mask */
912 
913 #define	PCI_REG_FUNC_SHIFT	8		/* Offset of function bits */
914 #define	PCI_REG_DEV_SHIFT	11		/* Offset of device bits */
915 #define	PCI_REG_BUS_SHIFT	16		/* Offset of bus bits */
916 #define	PCI_REG_ADDR_SHIFT	24		/* Offset of address bits */
917 
918 #define	PCI_REG_REG_G(x)	((x) & PCI_REG_REG_M)
919 #define	PCI_REG_FUNC_G(x)	(((x) & PCI_REG_FUNC_M) >> PCI_REG_FUNC_SHIFT)
920 #define	PCI_REG_DEV_G(x)	(((x) & PCI_REG_DEV_M) >> PCI_REG_DEV_SHIFT)
921 #define	PCI_REG_BUS_G(x)	(((x) & PCI_REG_BUS_M) >> PCI_REG_BUS_SHIFT)
922 #define	PCI_REG_ADDR_G(x)	(((x) & PCI_REG_ADDR_M) >> PCI_REG_ADDR_SHIFT)
923 #define	PCI_REG_BDFR_G(x)	((x) & PCI_REG_BDFR_M)
924 
925 /*
926  * PCI bit encodings of pci_phys_hi of PCI 1275 address cell.
927  */
928 #define	PCI_ADDR_MASK		PCI_REG_ADDR_M
929 #define	PCI_ADDR_CONFIG		0x00000000	/* configuration address */
930 #define	PCI_ADDR_IO		0x01000000	/* I/O address */
931 #define	PCI_ADDR_MEM32		0x02000000	/* 32-bit memory address */
932 #define	PCI_ADDR_MEM64		0x03000000	/* 64-bit memory address */
933 #define	PCI_ALIAS_B		PCI_REG_ALIAS_M	/* aliased bit */
934 #define	PCI_PREFETCH_B		PCI_REG_PF_M	/* prefetch bit */
935 #define	PCI_RELOCAT_B		PCI_REG_REL_M	/* non-relocatable bit */
936 #define	PCI_CONF_ADDR_MASK	0x00ffffff	/* mask for config address */
937 
938 #define	PCI_HARDDEC_8514 2	/* number of reg entries for 8514 hard-decode */
939 #define	PCI_HARDDEC_VGA	3	/* number of reg entries for VGA hard-decode */
940 #define	PCI_HARDDEC_IDE	4	/* number of reg entries for IDE hard-decode */
941 #define	PCI_HARDDEC_IDE_PRI 2	/* number of reg entries for IDE primary */
942 #define	PCI_HARDDEC_IDE_SEC 2	/* number of reg entries for IDE secondary */
943 
944 /*
945  * PCI Expansion ROM Header Format
946  */
947 #define	PCI_ROM_SIGNATURE		0x0	/* ROM Signature 0xaa55 */
948 #define	PCI_ROM_ARCH_UNIQUE_START	0x2	/* Start of processor unique */
949 #define	PCI_ROM_PCI_DATA_STRUCT_PTR	0x18	/* Ptr to PCI Data Structure */
950 
951 /*
952  * PCI Data Structure
953  *
954  * The PCI Data Structure is located within the first 64KB
955  * of the ROM image and must be DWORD aligned.
956  */
957 #define	PCI_PDS_SIGNATURE	0x0	/* Signature, the string 'PCIR' */
958 #define	PCI_PDS_VENDOR_ID	0x4	/* Vendor Identification */
959 #define	PCI_PDS_DEVICE_ID	0x6	/* Device Identification */
960 #define	PCI_PDS_VPD_PTR		0x8	/* Pointer to Vital Product Data */
961 #define	PCI_PDS_PDS_LENGTH	0xa	/* PCI Data Structure Length */
962 #define	PCI_PDS_PDS_REVISION	0xc	/* PCI Data Structure Revision */
963 #define	PCI_PDS_CLASS_CODE	0xd	/* Class Code */
964 #define	PCI_PDS_IMAGE_LENGTH	0x10	/* Image Length in 512 byte units */
965 #define	PCI_PDS_CODE_REVISON	0x12	/* Revision Level of Code/Data */
966 #define	PCI_PDS_CODE_TYPE	0x14	/* Code Type */
967 #define	PCI_PDS_INDICATOR	0x15	/* Indicates if image is last in ROM */
968 
969 #define	PCI_PDS_CODE_TYPE_PCAT		0x0	/* Intel x86/PC-AT Type */
970 #define	PCI_PDS_CODE_TYPE_OPEN_FW	0x1	/* Open Firmware */
971 
972 #ifdef	__cplusplus
973 }
974 #endif
975 
976 #endif	/* _SYS_PCI_H */
977