1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_IMPL_H 27 #define _SYS_NXGE_NXGE_IMPL_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * NIU HV API version definitions. 37 */ 38 #define NIU_MAJOR_VER 1 39 #define NIU_MINOR_VER 1 40 41 /* 42 * NIU HV API v1.0 definitions 43 */ 44 #define N2NIU_RX_LP_CONF 0x142 45 #define N2NIU_RX_LP_INFO 0x143 46 #define N2NIU_TX_LP_CONF 0x144 47 #define N2NIU_TX_LP_INFO 0x145 48 49 #ifndef _ASM 50 51 #include <sys/types.h> 52 #include <sys/byteorder.h> 53 #include <sys/debug.h> 54 #include <sys/stropts.h> 55 #include <sys/stream.h> 56 #include <sys/strlog.h> 57 #ifndef COSIM 58 #include <sys/strsubr.h> 59 #endif 60 #include <sys/cmn_err.h> 61 #include <sys/vtrace.h> 62 #include <sys/kmem.h> 63 #include <sys/ddi.h> 64 #include <sys/sunddi.h> 65 #include <sys/strsun.h> 66 #include <sys/stat.h> 67 #include <sys/cpu.h> 68 #include <sys/kstat.h> 69 #include <inet/common.h> 70 #include <inet/ip.h> 71 #include <sys/dlpi.h> 72 #include <inet/nd.h> 73 #include <netinet/in.h> 74 #include <sys/ethernet.h> 75 #include <sys/vlan.h> 76 #include <sys/pci.h> 77 #include <sys/taskq.h> 78 #include <sys/atomic.h> 79 80 #include <sys/nxge/nxge_defs.h> 81 #include <sys/nxge/nxge_hw.h> 82 #include <sys/nxge/nxge_mac.h> 83 #include <sys/nxge/nxge_mii.h> 84 #include <sys/nxge/nxge_fm.h> 85 #if !defined(IODIAG) 86 #include <sys/netlb.h> 87 #endif 88 89 #include <sys/ddi_intr.h> 90 91 #if defined(_KERNEL) 92 #include <sys/mac.h> 93 #include <sys/mac_impl.h> 94 #include <sys/mac_ether.h> 95 #endif 96 97 #if defined(sun4v) 98 #include <sys/hypervisor_api.h> 99 #include <sys/machsystm.h> 100 #include <sys/hsvc.h> 101 #endif 102 103 /* 104 * Handy macros (taken from bge driver) 105 */ 106 #define RBR_SIZE 4 107 #define DMA_COMMON_CHANNEL(area) ((area.dma_channel)) 108 #define DMA_COMMON_VPTR(area) ((area.kaddrp)) 109 #define DMA_COMMON_VPTR_INDEX(area, index) \ 110 (((char *)(area.kaddrp)) + \ 111 (index * RBR_SIZE)) 112 #define DMA_COMMON_HANDLE(area) ((area.dma_handle)) 113 #define DMA_COMMON_ACC_HANDLE(area) ((area.acc_handle)) 114 #define DMA_COMMON_IOADDR(area) ((area.dma_cookie.dmac_laddress)) 115 #define DMA_COMMON_IOADDR_INDEX(area, index) \ 116 ((area.dma_cookie.dmac_laddress) + \ 117 (index * RBR_SIZE)) 118 119 #define DMA_NPI_HANDLE(area) ((area.npi_handle) 120 121 #define DMA_COMMON_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_handle,\ 122 (area).offset, (area).alength, \ 123 (flag))) 124 #define DMA_COMMON_SYNC_OFFSET(area, bufoffset, len, flag) \ 125 ((void) ddi_dma_sync((area).dma_handle,\ 126 (area.offset + bufoffset), len, \ 127 (flag))) 128 129 #define DMA_COMMON_SYNC_RBR_DESC(area, index, flag) \ 130 ((void) ddi_dma_sync((area).dma_handle,\ 131 (index * RBR_SIZE), RBR_SIZE, \ 132 (flag))) 133 134 #define DMA_COMMON_SYNC_RBR_DESC_MULTI(area, index, count, flag) \ 135 ((void) ddi_dma_sync((area).dma_handle,\ 136 (index * RBR_SIZE), count * RBR_SIZE, \ 137 (flag))) 138 #define DMA_COMMON_SYNC_ENTRY(area, index, flag) \ 139 ((void) ddi_dma_sync((area).dma_handle,\ 140 (index * (area).block_size), \ 141 (area).block_size, \ 142 (flag))) 143 144 #define NEXT_ENTRY(index, wrap) ((index + 1) & wrap) 145 #define NEXT_ENTRY_PTR(ptr, first, last) \ 146 ((ptr == last) ? first : (ptr + 1)) 147 148 /* 149 * NPI related macros 150 */ 151 #define NXGE_DEV_NPI_HANDLE(nxgep) (nxgep->npi_handle) 152 153 #define NPI_PCI_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_pci_handle.regh = ah) 154 #define NPI_PCI_ADD_HANDLE_SET(nxgep, ap) (nxgep->npi_pci_handle.regp = ap) 155 156 #define NPI_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_handle.regh = ah) 157 #define NPI_ADD_HANDLE_SET(nxgep, ap) \ 158 nxgep->npi_handle.is_vraddr = B_FALSE; \ 159 nxgep->npi_handle.function.instance = nxgep->instance; \ 160 nxgep->npi_handle.function.function = nxgep->function_num; \ 161 nxgep->npi_handle.nxgep = (void *) nxgep; \ 162 nxgep->npi_handle.regp = ap; 163 164 #define NPI_REG_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_reg_handle.regh = ah) 165 #define NPI_REG_ADD_HANDLE_SET(nxgep, ap) \ 166 nxgep->npi_reg_handle.is_vraddr = B_FALSE; \ 167 nxgep->npi_handle.function.instance = nxgep->instance; \ 168 nxgep->npi_handle.function.function = nxgep->function_num; \ 169 nxgep->npi_reg_handle.nxgep = (void *) nxgep; \ 170 nxgep->npi_reg_handle.regp = ap; 171 172 #define NPI_MSI_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_msi_handle.regh = ah) 173 #define NPI_MSI_ADD_HANDLE_SET(nxgep, ap) (nxgep->npi_msi_handle.regp = ap) 174 175 #define NPI_VREG_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_vreg_handle.regh = ah) 176 #define NPI_VREG_ADD_HANDLE_SET(nxgep, ap) \ 177 nxgep->npi_vreg_handle.is_vraddr = B_TRUE; \ 178 nxgep->npi_handle.function.instance = nxgep->instance; \ 179 nxgep->npi_handle.function.function = nxgep->function_num; \ 180 nxgep->npi_vreg_handle.nxgep = (void *) nxgep; \ 181 nxgep->npi_vreg_handle.regp = ap; 182 183 #define NPI_V2REG_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_v2reg_handle.regh = ah) 184 #define NPI_V2REG_ADD_HANDLE_SET(nxgep, ap) \ 185 nxgep->npi_v2reg_handle.is_vraddr = B_TRUE; \ 186 nxgep->npi_handle.function.instance = nxgep->instance; \ 187 nxgep->npi_handle.function.function = nxgep->function_num; \ 188 nxgep->npi_v2reg_handle.nxgep = (void *) nxgep; \ 189 nxgep->npi_v2reg_handle.regp = ap; 190 191 #define NPI_PCI_ACC_HANDLE_GET(nxgep) (nxgep->npi_pci_handle.regh) 192 #define NPI_PCI_ADD_HANDLE_GET(nxgep) (nxgep->npi_pci_handle.regp) 193 #define NPI_ACC_HANDLE_GET(nxgep) (nxgep->npi_handle.regh) 194 #define NPI_ADD_HANDLE_GET(nxgep) (nxgep->npi_handle.regp) 195 #define NPI_REG_ACC_HANDLE_GET(nxgep) (nxgep->npi_reg_handle.regh) 196 #define NPI_REG_ADD_HANDLE_GET(nxgep) (nxgep->npi_reg_handle.regp) 197 #define NPI_MSI_ACC_HANDLE_GET(nxgep) (nxgep->npi_msi_handle.regh) 198 #define NPI_MSI_ADD_HANDLE_GET(nxgep) (nxgep->npi_msi_handle.regp) 199 #define NPI_VREG_ACC_HANDLE_GET(nxgep) (nxgep->npi_vreg_handle.regh) 200 #define NPI_VREG_ADD_HANDLE_GET(nxgep) (nxgep->npi_vreg_handle.regp) 201 #define NPI_V2REG_ACC_HANDLE_GET(nxgep) (nxgep->npi_v2reg_handle.regh) 202 #define NPI_V2REG_ADD_HANDLE_GET(nxgep) (nxgep->npi_v2reg_handle.regp) 203 204 #define NPI_DMA_ACC_HANDLE_SET(dmap, ah) (dmap->npi_handle.regh = ah) 205 #define NPI_DMA_ACC_HANDLE_GET(dmap) (dmap->npi_handle.regh) 206 207 /* 208 * DMA handles. 209 */ 210 #define NXGE_DESC_D_HANDLE_GET(desc) (desc.dma_handle) 211 #define NXGE_DESC_D_IOADD_GET(desc) (desc.dma_cookie.dmac_laddress) 212 #define NXGE_DMA_IOADD_GET(dma_cookie) (dma_cookie.dmac_laddress) 213 #define NXGE_DMA_AREA_IOADD_GET(dma_area) (dma_area.dma_cookie.dmac_laddress) 214 215 #define LDV_ON(ldv, vector) ((vector >> ldv) & 0x1) 216 #define LDV2_ON_1(ldv, vector) ((vector >> (ldv - 64)) & 0x1) 217 #define LDV2_ON_2(ldv, vector) (((vector >> 5) >> (ldv - 64)) & 0x1) 218 219 typedef uint32_t nxge_status_t; 220 221 typedef enum { 222 IDLE, 223 PROGRESS, 224 CONFIGURED 225 } dev_func_shared_t; 226 227 typedef enum { 228 DVMA, 229 DMA, 230 SDMA 231 } dma_method_t; 232 233 typedef enum { 234 BKSIZE_4K, 235 BKSIZE_8K, 236 BKSIZE_16K, 237 BKSIZE_32K 238 } nxge_rx_block_size_t; 239 240 #ifdef TX_ONE_BUF 241 #define TX_BCOPY_MAX 1514 242 #else 243 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 244 #define TX_BCOPY_MAX 4096 245 #define TX_BCOPY_SIZE 4096 246 #else 247 #define TX_BCOPY_MAX 2048 248 #define TX_BCOPY_SIZE 2048 249 #endif 250 #endif 251 252 #define TX_STREAM_MIN 512 253 #define TX_FASTDVMA_MIN 1024 254 255 /* 256 * Send repeated FMA ereports or display messages about some non-fatal 257 * hardware errors only the the first NXGE_ERROR_SHOW_MAX -1 times 258 */ 259 #define NXGE_ERROR_SHOW_MAX 2 260 261 262 /* 263 * Defaults 264 */ 265 #define NXGE_RDC_RCR_THRESHOLD 8 266 #define NXGE_RDC_RCR_TIMEOUT 16 267 268 #define NXGE_RDC_RCR_THRESHOLD_MAX 1024 269 #define NXGE_RDC_RCR_TIMEOUT_MAX 64 270 #define NXGE_RDC_RCR_THRESHOLD_MIN 1 271 #define NXGE_RDC_RCR_TIMEOUT_MIN 1 272 #define NXGE_RCR_FULL_HEADER 1 273 274 #define NXGE_IS_VLAN_PACKET(ptr) \ 275 ((((struct ether_vlan_header *)ptr)->ether_tpid) == \ 276 htons(VLAN_ETHERTYPE)) 277 278 typedef enum { 279 NONE, 280 SMALL, 281 MEDIUM, 282 LARGE 283 } dma_size_t; 284 285 typedef enum { 286 USE_NONE, 287 USE_BCOPY, 288 USE_DVMA, 289 USE_DMA, 290 USE_SDMA 291 } dma_type_t; 292 293 typedef enum { 294 NOT_IN_USE, 295 HDR_BUF, 296 MTU_BUF, 297 RE_ASSEMBLY_BUF, 298 FREE_BUF 299 } rx_page_state_t; 300 301 struct _nxge_block_mv_t { 302 uint32_t msg_type; 303 dma_type_t dma_type; 304 }; 305 306 typedef struct _nxge_block_mv_t nxge_block_mv_t, *p_nxge_block_mv_t; 307 308 typedef enum { 309 NIU_TYPE_NONE = 0, 310 311 NEPTUNE_4_1GC = 312 (NXGE_PORT_1G_COPPER | 313 (NXGE_PORT_1G_COPPER << 4) | 314 (NXGE_PORT_1G_COPPER << 8) | 315 (NXGE_PORT_1G_COPPER << 12)), 316 317 NEPTUNE_2_10GF = 318 (NXGE_PORT_10G_FIBRE | 319 (NXGE_PORT_10G_FIBRE << 4) | 320 (NXGE_PORT_NONE << 8) | 321 (NXGE_PORT_NONE << 12)), 322 323 NEPTUNE_2_10GF_2_1GC = 324 (NXGE_PORT_10G_FIBRE | 325 (NXGE_PORT_10G_FIBRE << 4) | 326 (NXGE_PORT_1G_COPPER << 8) | 327 (NXGE_PORT_1G_COPPER << 12)), 328 329 NEPTUNE_1_10GF_3_1GC = 330 (NXGE_PORT_10G_FIBRE | 331 (NXGE_PORT_1G_COPPER << 4) | 332 (NXGE_PORT_1G_COPPER << 8) | 333 (NXGE_PORT_1G_COPPER << 12)), 334 335 NEPTUNE_1_1GC_1_10GF_2_1GC = 336 (NXGE_PORT_1G_COPPER | 337 (NXGE_PORT_10G_FIBRE << 4) | 338 (NXGE_PORT_1G_COPPER << 8) | 339 (NXGE_PORT_1G_COPPER << 12)), 340 341 N2_NIU = 342 (NXGE_PORT_RSVD | 343 (NXGE_PORT_RSVD << 4) | 344 (NXGE_PORT_RSVD << 8) | 345 (NXGE_PORT_RSVD << 12)) 346 347 } niu_type_t; 348 349 typedef enum { 350 P_NEPTUNE_NONE, 351 P_NEPTUNE_GENERIC, 352 P_NEPTUNE_ATLAS_2PORT, 353 P_NEPTUNE_ATLAS_4PORT, 354 P_NEPTUNE_MARAMBA_P0, 355 P_NEPTUNE_MARAMBA_P1, 356 P_NEPTUNE_ALONSO, 357 P_NEPTUNE_NIU 358 } platform_type_t; 359 360 #define NXGE_IS_VALID_NEPTUNE_TYPE(nxgep) \ 361 (((nxgep->platform_type) == P_NEPTUNE_ATLAS_2PORT) || \ 362 ((nxgep->platform_type) == P_NEPTUNE_ATLAS_4PORT) || \ 363 ((nxgep->platform_type) == P_NEPTUNE_MARAMBA_P0) || \ 364 ((nxgep->platform_type) == P_NEPTUNE_MARAMBA_P1) || \ 365 ((nxgep->platform_type) == P_NEPTUNE_GENERIC) || \ 366 ((nxgep->platform_type) == P_NEPTUNE_ALONSO)) 367 368 #define NXGE_IS_XAUI_PLATFORM(nxgep) \ 369 (((nxgep->platform_type) == P_NEPTUNE_NIU) || \ 370 ((nxgep->platform_type) == P_NEPTUNE_MARAMBA_P0) || \ 371 ((nxgep->platform_type) == P_NEPTUNE_MARAMBA_P1)) 372 373 374 typedef enum { 375 CFG_DEFAULT = 0, /* default cfg */ 376 CFG_EQUAL, /* Equal */ 377 CFG_FAIR, /* Equal */ 378 CFG_CLASSIFY, 379 CFG_L2_CLASSIFY, 380 CFG_L3_CLASSIFY, 381 CFG_L3_DISTRIBUTE, 382 CFG_L3_WEB, 383 CFG_L3_TCAM, 384 CFG_NOT_SPECIFIED, 385 CFG_CUSTOM /* Custom */ 386 } cfg_type_t; 387 388 typedef enum { 389 NO_MSG = 0x0, /* No message output or storage. */ 390 CONSOLE = 0x1, /* Messages are go to the console. */ 391 BUFFER = 0x2, /* Messages are go to the system buffer. */ 392 CON_BUF = 0x3, /* Messages are go to the console and */ 393 /* system buffer. */ 394 VERBOSE = 0x4 /* Messages are go out only in VERBOSE node. */ 395 } out_msg_t, *p_out_msg_t; 396 397 typedef enum { 398 DBG_NO_MSG = 0x0, /* No message output or storage. */ 399 DBG_CONSOLE = 0x1, /* Messages are go to the console. */ 400 DBG_BUFFER = 0x2, /* Messages are go to the system buffer. */ 401 DBG_CON_BUF = 0x3, /* Messages are go to the console and */ 402 /* system buffer. */ 403 STR_LOG = 4 /* Sessage sent to streams logging driver. */ 404 } out_dbgmsg_t, *p_out_dbgmsg_t; 405 406 407 408 #if defined(_KERNEL) || defined(COSIM) 409 410 typedef struct ether_addr ether_addr_st, *p_ether_addr_t; 411 typedef struct ether_header ether_header_t, *p_ether_header_t; 412 typedef queue_t *p_queue_t; 413 414 #if !defined(IODIAG) 415 typedef mblk_t *p_mblk_t; 416 #endif 417 418 /* 419 * Generic phy table to support different phy types. 420 */ 421 typedef struct _nxge_xcvr_table { 422 nxge_status_t (*serdes_init) (); /* Serdes init routine */ 423 nxge_status_t (*xcvr_init) (); /* xcvr init routine */ 424 nxge_status_t (*link_intr_stop) (); /* Link intr disable routine */ 425 nxge_status_t (*link_intr_start) (); /* Link intr enable routine */ 426 nxge_status_t (*check_link) (); /* Link check routine */ 427 428 uint32_t xcvr_inuse; 429 } nxge_xcvr_table_t, *p_nxge_xcvr_table_t; 430 431 /* 432 * Common DMA data elements. 433 */ 434 struct _nxge_dma_common_t { 435 uint16_t dma_channel; 436 void *kaddrp; 437 void *first_kaddrp; 438 void *last_kaddrp; 439 void *ioaddr_pp; 440 void *first_ioaddr_pp; 441 void *last_ioaddr_pp; 442 ddi_dma_cookie_t dma_cookie; 443 uint32_t ncookies; 444 445 nxge_block_mv_t msg_dma_flags; 446 ddi_dma_handle_t dma_handle; 447 nxge_os_acc_handle_t acc_handle; 448 npi_handle_t npi_handle; 449 450 size_t block_size; 451 uint32_t nblocks; 452 size_t alength; 453 uint_t offset; 454 uint_t dma_chunk_index; 455 void *orig_ioaddr_pp; 456 uint64_t orig_vatopa; 457 void *orig_kaddrp; 458 size_t orig_alength; 459 boolean_t contig_alloc_type; 460 }; 461 462 typedef struct _nxge_t nxge_t, *p_nxge_t; 463 typedef struct _nxge_dma_common_t nxge_dma_common_t, *p_nxge_dma_common_t; 464 465 typedef struct _nxge_dma_pool_t { 466 p_nxge_dma_common_t *dma_buf_pool_p; 467 uint32_t ndmas; 468 uint32_t *num_chunks; 469 boolean_t buf_allocated; 470 } nxge_dma_pool_t, *p_nxge_dma_pool_t; 471 472 /* 473 * Each logical device (69): 474 * - LDG # 475 * - flag bits 476 * - masks. 477 * - interrupt handler function. 478 * 479 * Generic system interrupt handler with two arguments: 480 * (nxge_sys_intr_t) 481 * Per device instance data structure 482 * Logical group data structure. 483 * 484 * Logical device interrupt handler with two arguments: 485 * (nxge_ldv_intr_t) 486 * Per device instance data structure 487 * Logical device number 488 */ 489 typedef struct _nxge_ldg_t nxge_ldg_t, *p_nxge_ldg_t; 490 typedef struct _nxge_ldv_t nxge_ldv_t, *p_nxge_ldv_t; 491 typedef uint_t (*nxge_sys_intr_t)(void *arg1, void *arg2); 492 typedef uint_t (*nxge_ldv_intr_t)(void *arg1, void *arg2); 493 494 /* 495 * Each logical device Group (64) needs to have the following 496 * configurations: 497 * - timer counter (6 bits) 498 * - timer resolution (20 bits, number of system clocks) 499 * - system data (7 bits) 500 */ 501 struct _nxge_ldg_t { 502 uint8_t ldg; /* logical group number */ 503 uint8_t vldg_index; 504 boolean_t arm; 505 boolean_t interrupted; 506 uint16_t ldg_timer; /* counter */ 507 uint8_t func; 508 uint8_t vector; 509 uint8_t intdata; 510 uint8_t nldvs; 511 p_nxge_ldv_t ldvp; 512 nxge_sys_intr_t sys_intr_handler; 513 uint_t (*ih_cb_func)(caddr_t, caddr_t); 514 p_nxge_t nxgep; 515 }; 516 517 struct _nxge_ldv_t { 518 uint8_t ldg_assigned; 519 uint8_t ldv; 520 boolean_t is_rxdma; 521 boolean_t is_txdma; 522 boolean_t is_mif; 523 boolean_t is_mac; 524 boolean_t is_syserr; 525 boolean_t use_timer; 526 uint8_t channel; 527 uint8_t vdma_index; 528 uint8_t func; 529 p_nxge_ldg_t ldgp; 530 uint8_t ldv_flags; 531 boolean_t is_leve; 532 boolean_t is_edge; 533 uint8_t ldv_ldf_masks; 534 nxge_ldv_intr_t ldv_intr_handler; 535 uint_t (*ih_cb_func)(caddr_t, caddr_t); 536 p_nxge_t nxgep; 537 }; 538 #endif 539 540 typedef struct _nxge_logical_page_t { 541 uint16_t dma; 542 uint16_t page; 543 boolean_t valid; 544 uint64_t mask; 545 uint64_t value; 546 uint64_t reloc; 547 uint32_t handle; 548 } nxge_logical_page_t, *p_nxge_logical_page_t; 549 550 /* 551 * (Internal) return values from ioctl subroutines. 552 */ 553 enum nxge_ioc_reply { 554 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 555 IOC_DONE, /* OK, reply sent */ 556 IOC_ACK, /* OK, just send ACK */ 557 IOC_REPLY, /* OK, just send reply */ 558 IOC_RESTART_ACK, /* OK, restart & ACK */ 559 IOC_RESTART_REPLY /* OK, restart & reply */ 560 }; 561 562 typedef struct _pci_cfg_t { 563 uint16_t vendorid; 564 uint16_t devid; 565 uint16_t command; 566 uint16_t status; 567 uint8_t revid; 568 uint8_t res0; 569 uint16_t junk1; 570 uint8_t cache_line; 571 uint8_t latency; 572 uint8_t header; 573 uint8_t bist; 574 uint32_t base; 575 uint32_t base14; 576 uint32_t base18; 577 uint32_t base1c; 578 uint32_t base20; 579 uint32_t base24; 580 uint32_t base28; 581 uint32_t base2c; 582 uint32_t base30; 583 uint32_t res1[2]; 584 uint8_t int_line; 585 uint8_t int_pin; 586 uint8_t min_gnt; 587 uint8_t max_lat; 588 } pci_cfg_t, *p_pci_cfg_t; 589 590 #if defined(_KERNEL) || defined(COSIM) 591 592 typedef struct _dev_regs_t { 593 nxge_os_acc_handle_t nxge_pciregh; /* PCI config DDI IO handle */ 594 p_pci_cfg_t nxge_pciregp; /* mapped PCI registers */ 595 596 nxge_os_acc_handle_t nxge_regh; /* device DDI IO (BAR 0) */ 597 void *nxge_regp; /* mapped device registers */ 598 599 nxge_os_acc_handle_t nxge_msix_regh; /* MSI/X DDI handle (BAR 2) */ 600 void *nxge_msix_regp; /* MSI/X register */ 601 602 nxge_os_acc_handle_t nxge_vir_regh; /* virtualization (BAR 4) */ 603 unsigned char *nxge_vir_regp; /* virtualization register */ 604 605 nxge_os_acc_handle_t nxge_vir2_regh; /* second virtualization */ 606 unsigned char *nxge_vir2_regp; /* second virtualization */ 607 608 nxge_os_acc_handle_t nxge_romh; /* fcode rom handle */ 609 unsigned char *nxge_romp; /* fcode pointer */ 610 } dev_regs_t, *p_dev_regs_t; 611 612 613 typedef struct _nxge_mac_addr_t { 614 ether_addr_t addr; 615 uint_t flags; 616 } nxge_mac_addr_t; 617 618 /* 619 * The hardware supports 1 unique MAC and 16 alternate MACs (num_mmac) 620 * for each XMAC port and supports 1 unique MAC and 7 alternate MACs 621 * for each BMAC port. The number of MACs assigned by the factory is 622 * different and is as follows, 623 * BMAC port: num_factory_mmac = num_mmac = 7 624 * XMAC port on a 2-port NIC: num_factory_mmac = num_mmac - 1 = 15 625 * XMAC port on a 4-port NIC: num_factory_mmac = 7 626 * So num_factory_mmac is smaller than num_mmac. nxge_m_mmac_add uses 627 * num_mmac and nxge_m_mmac_reserve uses num_factory_mmac. 628 * 629 * total_factory_macs is the total number of factory MACs, including 630 * the unique MAC, assigned to a Neptune based NIC card, it is 32. 631 */ 632 typedef struct _nxge_mmac_t { 633 uint8_t total_factory_macs; 634 uint8_t num_mmac; 635 uint8_t num_factory_mmac; 636 nxge_mac_addr_t mac_pool[XMAC_MAX_ADDR_ENTRY]; 637 ether_addr_t factory_mac_pool[XMAC_MAX_ADDR_ENTRY]; 638 uint8_t naddrfree; /* number of alt mac addr available */ 639 } nxge_mmac_t; 640 641 /* 642 * mmac stats structure 643 */ 644 typedef struct _nxge_mmac_stats_t { 645 uint8_t mmac_max_cnt; 646 uint8_t mmac_avail_cnt; 647 struct ether_addr mmac_avail_pool[16]; 648 } nxge_mmac_stats_t, *p_nxge_mmac_stats_t; 649 650 #define NXGE_MAX_MMAC_ADDRS 32 651 #define NXGE_NUM_MMAC_ADDRS 8 652 #define NXGE_NUM_OF_PORTS_QUAD 4 653 #define NXGE_NUM_OF_PORTS_DUAL 2 654 655 #define NXGE_QGC_LP_BM_STR "501-7606" 656 #define NXGE_2XGF_LP_BM_STR "501-7283" 657 #define NXGE_QGC_PEM_BM_STR "501-7765" 658 #define NXGE_2XGF_PEM_BM_STR "501-7626" 659 #define NXGE_ALONSO_BM_STR "373-0202-01" 660 #define NXGE_ALONSO_MODEL_STR "SUNW,CP3220" 661 #define NXGE_RFEM_BM_STR "501-7961-01" 662 #define NXGE_RFEM_MODEL_STR "SUNW,pcie-rfem" 663 #define NXGE_EROM_LEN 1048576 664 665 #endif 666 667 #include <sys/nxge/nxge_common_impl.h> 668 #include <sys/nxge/nxge_common.h> 669 #include <sys/nxge/nxge_txc.h> 670 #include <sys/nxge/nxge_rxdma.h> 671 #include <sys/nxge/nxge_txdma.h> 672 #include <sys/nxge/nxge_fflp.h> 673 #include <sys/nxge/nxge_ipp.h> 674 #include <sys/nxge/nxge_zcp.h> 675 #include <sys/nxge/nxge_fzc.h> 676 #include <sys/nxge/nxge_flow.h> 677 #include <sys/nxge/nxge_virtual.h> 678 679 #include <npi_espc.h> 680 #include <npi_vir.h> 681 682 #include <sys/nxge/nxge.h> 683 684 #include <sys/modctl.h> 685 #include <sys/pattr.h> 686 687 extern int secpolicy_net_config(const cred_t *, boolean_t); 688 extern void nxge_fm_report_error(p_nxge_t, uint8_t, 689 uint8_t, nxge_fm_ereport_id_t); 690 extern int fm_check_acc_handle(ddi_acc_handle_t); 691 extern int fm_check_dma_handle(ddi_dma_handle_t); 692 693 /* nxge_classify.c */ 694 nxge_status_t nxge_classify_init(p_nxge_t); 695 nxge_status_t nxge_classify_uninit(p_nxge_t); 696 nxge_status_t nxge_set_hw_classify_config(p_nxge_t); 697 nxge_status_t nxge_classify_exit_sw(p_nxge_t); 698 699 /* nxge_fflp.c */ 700 void nxge_put_tcam(p_nxge_t, p_mblk_t); 701 void nxge_get_tcam(p_nxge_t, p_mblk_t); 702 nxge_status_t nxge_classify_init_hw(p_nxge_t); 703 nxge_status_t nxge_classify_init_sw(p_nxge_t); 704 nxge_status_t nxge_fflp_ip_class_config_all(p_nxge_t); 705 nxge_status_t nxge_fflp_ip_class_config(p_nxge_t, tcam_class_t, 706 uint32_t); 707 708 nxge_status_t nxge_fflp_ip_class_config_get(p_nxge_t, 709 tcam_class_t, 710 uint32_t *); 711 712 nxge_status_t nxge_cfg_ip_cls_flow_key(p_nxge_t, tcam_class_t, 713 uint32_t); 714 715 nxge_status_t nxge_fflp_ip_usr_class_config(p_nxge_t, tcam_class_t, 716 uint32_t); 717 718 uint64_t nxge_classify_get_cfg_value(p_nxge_t, uint8_t, uint8_t); 719 nxge_status_t nxge_add_flow(p_nxge_t, flow_resource_t *); 720 nxge_status_t nxge_fflp_config_tcam_enable(p_nxge_t); 721 nxge_status_t nxge_fflp_config_tcam_disable(p_nxge_t); 722 723 nxge_status_t nxge_fflp_config_hash_lookup_enable(p_nxge_t); 724 nxge_status_t nxge_fflp_config_hash_lookup_disable(p_nxge_t); 725 726 nxge_status_t nxge_fflp_config_llc_snap_enable(p_nxge_t); 727 nxge_status_t nxge_fflp_config_llc_snap_disable(p_nxge_t); 728 729 nxge_status_t nxge_logical_mac_assign_rdc_table(p_nxge_t, uint8_t); 730 nxge_status_t nxge_fflp_config_vlan_table(p_nxge_t, uint16_t); 731 732 nxge_status_t nxge_fflp_set_hash1(p_nxge_t, uint32_t); 733 734 nxge_status_t nxge_fflp_set_hash2(p_nxge_t, uint16_t); 735 736 nxge_status_t nxge_fflp_init_hostinfo(p_nxge_t); 737 738 void nxge_handle_tcam_fragment_bug(p_nxge_t); 739 nxge_status_t nxge_fflp_hw_reset(p_nxge_t); 740 nxge_status_t nxge_fflp_handle_sys_errors(p_nxge_t); 741 nxge_status_t nxge_zcp_handle_sys_errors(p_nxge_t); 742 743 /* nxge_kstats.c */ 744 void nxge_init_statsp(p_nxge_t); 745 void nxge_setup_kstats(p_nxge_t); 746 void nxge_destroy_kstats(p_nxge_t); 747 int nxge_port_kstat_update(kstat_t *, int); 748 void nxge_save_cntrs(p_nxge_t); 749 750 int nxge_m_stat(void *arg, uint_t, uint64_t *); 751 752 /* nxge_hw.c */ 753 void 754 nxge_hw_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *); 755 void nxge_loopback_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *); 756 nxge_status_t nxge_global_reset(p_nxge_t); 757 uint_t nxge_intr(void *, void *); 758 void nxge_intr_enable(p_nxge_t); 759 void nxge_intr_disable(p_nxge_t); 760 void nxge_hw_blank(void *arg, time_t, uint_t); 761 void nxge_hw_id_init(p_nxge_t); 762 void nxge_hw_init_niu_common(p_nxge_t); 763 void nxge_intr_hw_enable(p_nxge_t); 764 void nxge_intr_hw_disable(p_nxge_t); 765 void nxge_hw_stop(p_nxge_t); 766 void nxge_check_hw_state(p_nxge_t); 767 768 void nxge_rxdma_channel_put64(nxge_os_acc_handle_t, 769 void *, uint32_t, uint16_t, 770 uint64_t); 771 uint64_t nxge_rxdma_channel_get64(nxge_os_acc_handle_t, void *, 772 uint32_t, uint16_t); 773 774 775 void nxge_get32(p_nxge_t, p_mblk_t); 776 void nxge_put32(p_nxge_t, p_mblk_t); 777 778 void nxge_hw_set_mac_modes(p_nxge_t); 779 780 /* nxge_send.c. */ 781 uint_t nxge_reschedule(caddr_t); 782 783 /* nxge_rxdma.c */ 784 nxge_status_t nxge_rxdma_cfg_rdcgrp_default_rdc(p_nxge_t, 785 uint8_t, uint8_t); 786 787 nxge_status_t nxge_rxdma_cfg_port_default_rdc(p_nxge_t, 788 uint8_t, uint8_t); 789 nxge_status_t nxge_rxdma_cfg_rcr_threshold(p_nxge_t, uint8_t, 790 uint16_t); 791 nxge_status_t nxge_rxdma_cfg_rcr_timeout(p_nxge_t, uint8_t, 792 uint16_t, uint8_t); 793 794 /* nxge_ndd.c */ 795 void nxge_get_param_soft_properties(p_nxge_t); 796 void nxge_copy_hw_default_to_param(p_nxge_t); 797 void nxge_copy_param_hw_to_config(p_nxge_t); 798 void nxge_setup_param(p_nxge_t); 799 void nxge_init_param(p_nxge_t); 800 void nxge_destroy_param(p_nxge_t); 801 boolean_t nxge_check_rxdma_rdcgrp_member(p_nxge_t, uint8_t, uint8_t); 802 boolean_t nxge_check_rxdma_port_member(p_nxge_t, uint8_t); 803 boolean_t nxge_check_rdcgrp_port_member(p_nxge_t, uint8_t); 804 805 boolean_t nxge_check_txdma_port_member(p_nxge_t, uint8_t); 806 807 int nxge_param_get_generic(p_nxge_t, queue_t *, mblk_t *, caddr_t); 808 int nxge_param_set_generic(p_nxge_t, queue_t *, mblk_t *, char *, caddr_t); 809 int nxge_get_default(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 810 int nxge_set_default(p_nxge_t, queue_t *, p_mblk_t, char *, caddr_t); 811 int nxge_nd_get_names(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 812 int nxge_mk_mblk_tail_space(p_mblk_t, p_mblk_t *, size_t); 813 long nxge_strtol(char *, char **, int); 814 boolean_t nxge_param_get_instance(queue_t *, mblk_t *); 815 void nxge_param_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *); 816 boolean_t nxge_nd_load(caddr_t *, char *, pfi_t, pfi_t, caddr_t); 817 void nxge_nd_free(caddr_t *); 818 int nxge_nd_getset(p_nxge_t, queue_t *, caddr_t, p_mblk_t); 819 820 nxge_status_t nxge_set_lb_normal(p_nxge_t); 821 boolean_t nxge_set_lb(p_nxge_t, queue_t *, p_mblk_t); 822 823 /* nxge_virtual.c */ 824 nxge_status_t nxge_cntlops(dev_info_t *, nxge_ctl_enum_t, void *, void *); 825 void nxge_common_lock_get(p_nxge_t); 826 void nxge_common_lock_free(p_nxge_t); 827 828 nxge_status_t nxge_get_config_properties(p_nxge_t); 829 void nxge_get_xcvr_properties(p_nxge_t); 830 void nxge_init_vlan_config(p_nxge_t); 831 void nxge_init_mac_config(p_nxge_t); 832 833 834 void nxge_init_logical_devs(p_nxge_t); 835 int nxge_init_ldg_intrs(p_nxge_t); 836 837 void nxge_set_ldgimgmt(p_nxge_t, uint32_t, boolean_t, 838 uint32_t); 839 840 void nxge_init_fzc_txdma_channels(p_nxge_t); 841 842 nxge_status_t nxge_init_fzc_txdma_channel(p_nxge_t, uint16_t, 843 p_tx_ring_t, p_tx_mbox_t); 844 nxge_status_t nxge_init_fzc_txdma_port(p_nxge_t); 845 846 nxge_status_t nxge_init_fzc_rxdma_channel(p_nxge_t, uint16_t, 847 p_rx_rbr_ring_t, p_rx_rcr_ring_t, p_rx_mbox_t); 848 849 nxge_status_t nxge_init_fzc_rdc_tbl(p_nxge_t); 850 nxge_status_t nxge_init_fzc_rx_common(p_nxge_t); 851 nxge_status_t nxge_init_fzc_rxdma_port(p_nxge_t); 852 853 nxge_status_t nxge_init_fzc_rxdma_channel_pages(p_nxge_t, 854 uint16_t, p_rx_rbr_ring_t); 855 nxge_status_t nxge_init_fzc_rxdma_channel_red(p_nxge_t, 856 uint16_t, p_rx_rcr_ring_t); 857 858 nxge_status_t nxge_init_fzc_rxdma_channel_clrlog(p_nxge_t, 859 uint16_t, p_rx_rbr_ring_t); 860 861 862 nxge_status_t nxge_init_fzc_txdma_channel_pages(p_nxge_t, 863 uint16_t, p_tx_ring_t); 864 865 nxge_status_t nxge_init_fzc_txdma_channel_drr(p_nxge_t, uint16_t, 866 p_tx_ring_t); 867 868 nxge_status_t nxge_init_fzc_txdma_port(p_nxge_t); 869 870 void nxge_init_fzc_ldg_num(p_nxge_t); 871 void nxge_init_fzc_sys_int_data(p_nxge_t); 872 void nxge_init_fzc_ldg_int_timer(p_nxge_t); 873 nxge_status_t nxge_intr_mask_mgmt_set(p_nxge_t, boolean_t on); 874 875 /* MAC functions */ 876 nxge_status_t nxge_mac_init(p_nxge_t); 877 nxge_status_t nxge_link_init(p_nxge_t); 878 nxge_status_t nxge_xif_init(p_nxge_t); 879 nxge_status_t nxge_pcs_init(p_nxge_t); 880 nxge_status_t nxge_mac_ctrl_init(p_nxge_t); 881 nxge_status_t nxge_serdes_init(p_nxge_t); 882 nxge_status_t nxge_serdes_reset(p_nxge_t); 883 nxge_status_t nxge_xcvr_find(p_nxge_t); 884 nxge_status_t nxge_get_xcvr_type(p_nxge_t); 885 nxge_status_t nxge_setup_xcvr_table(p_nxge_t); 886 nxge_status_t nxge_xcvr_init(p_nxge_t); 887 nxge_status_t nxge_tx_mac_init(p_nxge_t); 888 nxge_status_t nxge_rx_mac_init(p_nxge_t); 889 nxge_status_t nxge_tx_mac_enable(p_nxge_t); 890 nxge_status_t nxge_tx_mac_disable(p_nxge_t); 891 nxge_status_t nxge_rx_mac_enable(p_nxge_t); 892 nxge_status_t nxge_rx_mac_disable(p_nxge_t); 893 nxge_status_t nxge_tx_mac_reset(p_nxge_t); 894 nxge_status_t nxge_rx_mac_reset(p_nxge_t); 895 nxge_status_t nxge_link_intr(p_nxge_t, link_intr_enable_t); 896 nxge_status_t nxge_mii_xcvr_init(p_nxge_t); 897 nxge_status_t nxge_mii_xcvr_fiber_init(p_nxge_t); 898 nxge_status_t nxge_mii_read(p_nxge_t, uint8_t, 899 uint8_t, uint16_t *); 900 nxge_status_t nxge_mii_write(p_nxge_t, uint8_t, 901 uint8_t, uint16_t); 902 nxge_status_t nxge_mdio_read(p_nxge_t, uint8_t, uint8_t, 903 uint16_t, uint16_t *); 904 nxge_status_t nxge_mdio_write(p_nxge_t, uint8_t, 905 uint8_t, uint16_t, uint16_t); 906 nxge_status_t nxge_mii_check(p_nxge_t, mii_bmsr_t, 907 mii_bmsr_t, nxge_link_state_t *); 908 nxge_status_t nxge_pcs_check(p_nxge_t, uint8_t portn, nxge_link_state_t *); 909 nxge_status_t nxge_add_mcast_addr(p_nxge_t, struct ether_addr *); 910 nxge_status_t nxge_del_mcast_addr(p_nxge_t, struct ether_addr *); 911 nxge_status_t nxge_set_mac_addr(p_nxge_t, struct ether_addr *); 912 nxge_status_t nxge_check_bcm8704_link(p_nxge_t, boolean_t *); 913 void nxge_link_is_down(p_nxge_t); 914 void nxge_link_is_up(p_nxge_t); 915 nxge_status_t nxge_link_monitor(p_nxge_t, link_mon_enable_t); 916 uint32_t crc32_mchash(p_ether_addr_t); 917 nxge_status_t nxge_set_promisc(p_nxge_t, boolean_t); 918 nxge_status_t nxge_mac_handle_sys_errors(p_nxge_t); 919 nxge_status_t nxge_10g_link_led_on(p_nxge_t); 920 nxge_status_t nxge_10g_link_led_off(p_nxge_t); 921 nxge_status_t nxge_scan_ports_phy(p_nxge_t, p_nxge_hw_list_t); 922 boolean_t nxge_is_valid_local_mac(ether_addr_st); 923 924 /* espc (sprom) prototypes */ 925 nxge_status_t nxge_espc_mac_addrs_get(p_nxge_t); 926 nxge_status_t nxge_espc_num_macs_get(p_nxge_t, uint8_t *); 927 nxge_status_t nxge_espc_num_ports_get(p_nxge_t); 928 nxge_status_t nxge_espc_phy_type_get(p_nxge_t); 929 nxge_status_t nxge_espc_verify_chksum(p_nxge_t); 930 void nxge_espc_get_next_mac_addr(uint8_t *, uint8_t, struct ether_addr *); 931 void nxge_vpd_info_get(p_nxge_t); 932 933 934 void nxge_debug_msg(p_nxge_t, uint64_t, char *, ...); 935 int nxge_get_nports(p_nxge_t); 936 937 uint64_t hv_niu_rx_logical_page_conf(uint64_t, uint64_t, 938 uint64_t, uint64_t); 939 #pragma weak hv_niu_rx_logical_page_conf 940 941 uint64_t hv_niu_rx_logical_page_info(uint64_t, uint64_t, 942 uint64_t *, uint64_t *); 943 #pragma weak hv_niu_rx_logical_page_info 944 945 uint64_t hv_niu_tx_logical_page_conf(uint64_t, uint64_t, 946 uint64_t, uint64_t); 947 #pragma weak hv_niu_tx_logical_page_conf 948 949 uint64_t hv_niu_tx_logical_page_info(uint64_t, uint64_t, 950 uint64_t *, uint64_t *); 951 #pragma weak hv_niu_tx_logical_page_info 952 953 #ifdef NXGE_DEBUG 954 char *nxge_dump_packet(char *, int); 955 #endif 956 957 #endif /* !_ASM */ 958 959 #ifdef __cplusplus 960 } 961 #endif 962 963 #endif /* _SYS_NXGE_NXGE_IMPL_H */ 964