1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_IMPL_H 27 #define _SYS_NXGE_NXGE_IMPL_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 /* 34 * NIU HV API version definitions. 35 */ 36 #define NIU_MAJOR_VER 1 37 #define NIU_MINOR_VER 1 38 39 /* 40 * NIU HV API v1.0 definitions 41 */ 42 #define N2NIU_RX_LP_CONF 0x142 43 #define N2NIU_RX_LP_INFO 0x143 44 #define N2NIU_TX_LP_CONF 0x144 45 #define N2NIU_TX_LP_INFO 0x145 46 47 #ifndef _ASM 48 49 #include <sys/types.h> 50 #include <sys/byteorder.h> 51 #include <sys/debug.h> 52 #include <sys/stropts.h> 53 #include <sys/stream.h> 54 #include <sys/strlog.h> 55 #ifndef COSIM 56 #include <sys/strsubr.h> 57 #endif 58 #include <sys/cmn_err.h> 59 #include <sys/vtrace.h> 60 #include <sys/kmem.h> 61 #include <sys/ddi.h> 62 #include <sys/sunddi.h> 63 #include <sys/strsun.h> 64 #include <sys/stat.h> 65 #include <sys/cpu.h> 66 #include <sys/kstat.h> 67 #include <inet/common.h> 68 #include <inet/ip.h> 69 #include <sys/dlpi.h> 70 #include <inet/nd.h> 71 #include <netinet/in.h> 72 #include <sys/ethernet.h> 73 #include <sys/vlan.h> 74 #include <sys/pci.h> 75 #include <sys/taskq.h> 76 #include <sys/atomic.h> 77 78 #include <sys/nxge/nxge_defs.h> 79 #include <sys/nxge/nxge_hw.h> 80 #include <sys/nxge/nxge_mac.h> 81 #include <sys/nxge/nxge_mii.h> 82 #include <sys/nxge/nxge_fm.h> 83 #if !defined(IODIAG) 84 #include <sys/netlb.h> 85 #endif 86 87 #include <sys/ddi_intr.h> 88 89 #if defined(_KERNEL) 90 #include <sys/mac.h> 91 #include <sys/mac_impl.h> 92 #include <sys/mac_ether.h> 93 #endif 94 95 #if defined(sun4v) 96 #include <sys/hypervisor_api.h> 97 #include <sys/machsystm.h> 98 #include <sys/hsvc.h> 99 #endif 100 101 #include <sys/dld.h> 102 103 /* 104 * Handy macros (taken from bge driver) 105 */ 106 #define RBR_SIZE 4 107 #define DMA_COMMON_CHANNEL(area) ((area.dma_channel)) 108 #define DMA_COMMON_VPTR(area) ((area.kaddrp)) 109 #define DMA_COMMON_VPTR_INDEX(area, index) \ 110 (((char *)(area.kaddrp)) + \ 111 (index * RBR_SIZE)) 112 #define DMA_COMMON_HANDLE(area) ((area.dma_handle)) 113 #define DMA_COMMON_ACC_HANDLE(area) ((area.acc_handle)) 114 #define DMA_COMMON_IOADDR(area) ((area.dma_cookie.dmac_laddress)) 115 #define DMA_COMMON_IOADDR_INDEX(area, index) \ 116 ((area.dma_cookie.dmac_laddress) + \ 117 (index * RBR_SIZE)) 118 119 #define DMA_NPI_HANDLE(area) ((area.npi_handle) 120 121 #define DMA_COMMON_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_handle,\ 122 (area).offset, (area).alength, \ 123 (flag))) 124 #define DMA_COMMON_SYNC_OFFSET(area, bufoffset, len, flag) \ 125 ((void) ddi_dma_sync((area).dma_handle,\ 126 (area.offset + bufoffset), len, \ 127 (flag))) 128 129 #define DMA_COMMON_SYNC_RBR_DESC(area, index, flag) \ 130 ((void) ddi_dma_sync((area).dma_handle,\ 131 (index * RBR_SIZE), RBR_SIZE, \ 132 (flag))) 133 134 #define DMA_COMMON_SYNC_RBR_DESC_MULTI(area, index, count, flag) \ 135 ((void) ddi_dma_sync((area).dma_handle,\ 136 (index * RBR_SIZE), count * RBR_SIZE, \ 137 (flag))) 138 #define DMA_COMMON_SYNC_ENTRY(area, index, flag) \ 139 ((void) ddi_dma_sync((area).dma_handle,\ 140 (index * (area).block_size), \ 141 (area).block_size, \ 142 (flag))) 143 144 #define NEXT_ENTRY(index, wrap) ((index + 1) & wrap) 145 #define NEXT_ENTRY_PTR(ptr, first, last) \ 146 ((ptr == last) ? first : (ptr + 1)) 147 148 /* 149 * NPI related macros 150 */ 151 #define NXGE_DEV_NPI_HANDLE(nxgep) (nxgep->npi_handle) 152 153 #define NPI_PCI_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_pci_handle.regh = ah) 154 #define NPI_PCI_ADD_HANDLE_SET(nxgep, ap) (nxgep->npi_pci_handle.regp = ap) 155 156 #define NPI_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_handle.regh = ah) 157 #define NPI_ADD_HANDLE_SET(nxgep, ap) \ 158 nxgep->npi_handle.is_vraddr = B_FALSE; \ 159 nxgep->npi_handle.function.instance = nxgep->instance; \ 160 nxgep->npi_handle.function.function = nxgep->function_num; \ 161 nxgep->npi_handle.nxgep = (void *) nxgep; \ 162 nxgep->npi_handle.regp = ap; 163 164 #define NPI_REG_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_reg_handle.regh = ah) 165 #define NPI_REG_ADD_HANDLE_SET(nxgep, ap) \ 166 nxgep->npi_reg_handle.is_vraddr = B_FALSE; \ 167 nxgep->npi_handle.function.instance = nxgep->instance; \ 168 nxgep->npi_handle.function.function = nxgep->function_num; \ 169 nxgep->npi_reg_handle.nxgep = (void *) nxgep; \ 170 nxgep->npi_reg_handle.regp = ap; 171 172 #define NPI_MSI_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_msi_handle.regh = ah) 173 #define NPI_MSI_ADD_HANDLE_SET(nxgep, ap) (nxgep->npi_msi_handle.regp = ap) 174 175 #define NPI_VREG_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_vreg_handle.regh = ah) 176 #define NPI_VREG_ADD_HANDLE_SET(nxgep, ap) \ 177 nxgep->npi_vreg_handle.is_vraddr = B_TRUE; \ 178 nxgep->npi_handle.function.instance = nxgep->instance; \ 179 nxgep->npi_handle.function.function = nxgep->function_num; \ 180 nxgep->npi_vreg_handle.nxgep = (void *) nxgep; \ 181 nxgep->npi_vreg_handle.regp = ap; 182 183 #define NPI_V2REG_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_v2reg_handle.regh = ah) 184 #define NPI_V2REG_ADD_HANDLE_SET(nxgep, ap) \ 185 nxgep->npi_v2reg_handle.is_vraddr = B_TRUE; \ 186 nxgep->npi_handle.function.instance = nxgep->instance; \ 187 nxgep->npi_handle.function.function = nxgep->function_num; \ 188 nxgep->npi_v2reg_handle.nxgep = (void *) nxgep; \ 189 nxgep->npi_v2reg_handle.regp = ap; 190 191 #define NPI_PCI_ACC_HANDLE_GET(nxgep) (nxgep->npi_pci_handle.regh) 192 #define NPI_PCI_ADD_HANDLE_GET(nxgep) (nxgep->npi_pci_handle.regp) 193 #define NPI_ACC_HANDLE_GET(nxgep) (nxgep->npi_handle.regh) 194 #define NPI_ADD_HANDLE_GET(nxgep) (nxgep->npi_handle.regp) 195 #define NPI_REG_ACC_HANDLE_GET(nxgep) (nxgep->npi_reg_handle.regh) 196 #define NPI_REG_ADD_HANDLE_GET(nxgep) (nxgep->npi_reg_handle.regp) 197 #define NPI_MSI_ACC_HANDLE_GET(nxgep) (nxgep->npi_msi_handle.regh) 198 #define NPI_MSI_ADD_HANDLE_GET(nxgep) (nxgep->npi_msi_handle.regp) 199 #define NPI_VREG_ACC_HANDLE_GET(nxgep) (nxgep->npi_vreg_handle.regh) 200 #define NPI_VREG_ADD_HANDLE_GET(nxgep) (nxgep->npi_vreg_handle.regp) 201 #define NPI_V2REG_ACC_HANDLE_GET(nxgep) (nxgep->npi_v2reg_handle.regh) 202 #define NPI_V2REG_ADD_HANDLE_GET(nxgep) (nxgep->npi_v2reg_handle.regp) 203 204 #define NPI_DMA_ACC_HANDLE_SET(dmap, ah) (dmap->npi_handle.regh = ah) 205 #define NPI_DMA_ACC_HANDLE_GET(dmap) (dmap->npi_handle.regh) 206 207 /* 208 * DMA handles. 209 */ 210 #define NXGE_DESC_D_HANDLE_GET(desc) (desc.dma_handle) 211 #define NXGE_DESC_D_IOADD_GET(desc) (desc.dma_cookie.dmac_laddress) 212 #define NXGE_DMA_IOADD_GET(dma_cookie) (dma_cookie.dmac_laddress) 213 #define NXGE_DMA_AREA_IOADD_GET(dma_area) (dma_area.dma_cookie.dmac_laddress) 214 215 #define LDV_ON(ldv, vector) ((vector >> ldv) & 0x1) 216 #define LDV2_ON_1(ldv, vector) ((vector >> (ldv - 64)) & 0x1) 217 #define LDV2_ON_2(ldv, vector) (((vector >> 5) >> (ldv - 64)) & 0x1) 218 219 typedef uint32_t nxge_status_t; 220 221 typedef enum { 222 IDLE, 223 PROGRESS, 224 CONFIGURED 225 } dev_func_shared_t; 226 227 typedef enum { 228 DVMA, 229 DMA, 230 SDMA 231 } dma_method_t; 232 233 typedef enum { 234 BKSIZE_4K, 235 BKSIZE_8K, 236 BKSIZE_16K, 237 BKSIZE_32K 238 } nxge_rx_block_size_t; 239 240 #ifdef TX_ONE_BUF 241 #define TX_BCOPY_MAX 1514 242 #else 243 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 244 #define TX_BCOPY_MAX 4096 245 #define TX_BCOPY_SIZE 4096 246 #else 247 #define TX_BCOPY_MAX 2048 248 #define TX_BCOPY_SIZE 2048 249 #endif 250 #endif 251 252 #define TX_STREAM_MIN 512 253 #define TX_FASTDVMA_MIN 1024 254 255 /* 256 * Send repeated FMA ereports or display messages about some non-fatal 257 * hardware errors only the the first NXGE_ERROR_SHOW_MAX -1 times 258 */ 259 #define NXGE_ERROR_SHOW_MAX 2 260 261 262 /* 263 * Defaults 264 */ 265 #define NXGE_RDC_RCR_THRESHOLD 8 266 #define NXGE_RDC_RCR_TIMEOUT 16 267 268 #define NXGE_RDC_RCR_THRESHOLD_MAX 1024 269 #define NXGE_RDC_RCR_TIMEOUT_MAX 64 270 #define NXGE_RDC_RCR_THRESHOLD_MIN 1 271 #define NXGE_RDC_RCR_TIMEOUT_MIN 1 272 #define NXGE_RCR_FULL_HEADER 1 273 274 #define NXGE_IS_VLAN_PACKET(ptr) \ 275 ((((struct ether_vlan_header *)ptr)->ether_tpid) == \ 276 htons(VLAN_ETHERTYPE)) 277 278 typedef enum { 279 NONE, 280 SMALL, 281 MEDIUM, 282 LARGE 283 } dma_size_t; 284 285 typedef enum { 286 USE_NONE, 287 USE_BCOPY, 288 USE_DVMA, 289 USE_DMA, 290 USE_SDMA 291 } dma_type_t; 292 293 typedef enum { 294 NOT_IN_USE, 295 HDR_BUF, 296 MTU_BUF, 297 RE_ASSEMBLY_BUF, 298 FREE_BUF 299 } rx_page_state_t; 300 301 struct _nxge_block_mv_t { 302 uint32_t msg_type; 303 dma_type_t dma_type; 304 }; 305 306 typedef struct _nxge_block_mv_t nxge_block_mv_t, *p_nxge_block_mv_t; 307 308 typedef enum { 309 NIU_TYPE_NONE = 0, 310 311 /* QGC NIC */ 312 NEPTUNE_4_1GC = 313 (NXGE_PORT_1G_COPPER | 314 (NXGE_PORT_1G_COPPER << 4) | 315 (NXGE_PORT_1G_COPPER << 8) | 316 (NXGE_PORT_1G_COPPER << 12)), 317 318 /* Huron: 2 fiber XAUI cards */ 319 NEPTUNE_2_10GF = 320 (NXGE_PORT_10G_FIBRE | 321 (NXGE_PORT_10G_FIBRE << 4) | 322 (NXGE_PORT_NONE << 8) | 323 (NXGE_PORT_NONE << 12)), 324 325 /* Huron: port0 is a TN1010 copper XAUI */ 326 NEPTUNE_1_TN1010 = 327 (NXGE_PORT_TN1010 | 328 (NXGE_PORT_NONE << 4) | 329 (NXGE_PORT_NONE << 8) | 330 (NXGE_PORT_NONE << 12)), 331 332 /* Huron: port1 is a TN1010 copper XAUI */ 333 NEPTUNE_1_NONE_1_TN1010 = 334 (NXGE_PORT_NONE | 335 (NXGE_PORT_TN1010 << 4) | 336 (NXGE_PORT_NONE << 8) | 337 (NXGE_PORT_NONE << 12)), 338 339 /* Huron: 2 TN1010 copper XAUI cards */ 340 NEPTUNE_2_TN1010 = 341 (NXGE_PORT_TN1010 | 342 (NXGE_PORT_TN1010 << 4) | 343 (NXGE_PORT_NONE << 8) | 344 (NXGE_PORT_NONE << 12)), 345 346 /* Huron: port0 is fiber XAUI, port1 is copper XAUI */ 347 NEPTUNE_1_10GF_1_TN1010 = 348 (NXGE_PORT_10G_FIBRE | 349 (NXGE_PORT_TN1010 << 4) | 350 (NXGE_PORT_NONE << 8) | 351 (NXGE_PORT_NONE << 12)), 352 353 /* Huron: port0 is copper XAUI, port1 is fiber XAUI */ 354 NEPTUNE_1_TN1010_1_10GF = 355 (NXGE_PORT_TN1010 | 356 (NXGE_PORT_10G_FIBRE << 4) | 357 (NXGE_PORT_NONE << 8) | 358 (NXGE_PORT_NONE << 12)), 359 360 /* Maramba: port0 and port1 are fiber XAUIs */ 361 NEPTUNE_2_10GF_2_1GC = 362 (NXGE_PORT_10G_FIBRE | 363 (NXGE_PORT_10G_FIBRE << 4) | 364 (NXGE_PORT_1G_COPPER << 8) | 365 (NXGE_PORT_1G_COPPER << 12)), 366 367 /* Maramba: port0 and port1 are copper TN1010 XAUIs */ 368 NEPTUNE_2_TN1010_2_1GC = 369 (NXGE_PORT_TN1010 | 370 (NXGE_PORT_TN1010 << 4) | 371 (NXGE_PORT_1G_COPPER << 8) | 372 (NXGE_PORT_1G_COPPER << 12)), 373 374 /* Maramba: port0 is copper XAUI, port1 is Fiber XAUI */ 375 NEPTUNE_1_TN1010_1_10GF_2_1GC = 376 (NXGE_PORT_TN1010 | 377 (NXGE_PORT_10G_FIBRE << 4) | 378 (NXGE_PORT_1G_COPPER << 8) | 379 (NXGE_PORT_1G_COPPER << 12)), 380 381 /* Maramba: port0 is fiber XAUI, port1 is copper XAUI */ 382 NEPTUNE_1_10GF_1_TN1010_2_1GC = 383 (NXGE_PORT_10G_FIBRE | 384 (NXGE_PORT_TN1010 << 4) | 385 (NXGE_PORT_1G_COPPER << 8) | 386 (NXGE_PORT_1G_COPPER << 12)), 387 388 /* Maramba: port0 is fiber XAUI */ 389 NEPTUNE_1_10GF_3_1GC = 390 (NXGE_PORT_10G_FIBRE | 391 (NXGE_PORT_1G_COPPER << 4) | 392 (NXGE_PORT_1G_COPPER << 8) | 393 (NXGE_PORT_1G_COPPER << 12)), 394 395 /* Maramba: port0 is TN1010 copper XAUI */ 396 NEPTUNE_1_TN1010_3_1GC = 397 (NXGE_PORT_TN1010 | 398 (NXGE_PORT_1G_COPPER << 4) | 399 (NXGE_PORT_1G_COPPER << 8) | 400 (NXGE_PORT_1G_COPPER << 12)), 401 402 /* Maramba: port1 is fiber XAUI */ 403 NEPTUNE_1_1GC_1_10GF_2_1GC = 404 (NXGE_PORT_1G_COPPER | 405 (NXGE_PORT_10G_FIBRE << 4) | 406 (NXGE_PORT_1G_COPPER << 8) | 407 (NXGE_PORT_1G_COPPER << 12)), 408 409 /* Maramba: port1 is TN1010 copper XAUI */ 410 NEPTUNE_1_1GC_1_TN1010_2_1GC = 411 (NXGE_PORT_1G_COPPER | 412 (NXGE_PORT_TN1010 << 4) | 413 (NXGE_PORT_1G_COPPER << 8) | 414 (NXGE_PORT_1G_COPPER << 12)), 415 416 NEPTUNE_2_1GRF = 417 (NXGE_PORT_NONE | 418 (NXGE_PORT_NONE << 4) | 419 (NXGE_PORT_1G_RGMII_FIBER << 8) | 420 (NXGE_PORT_1G_RGMII_FIBER << 12)), 421 422 NEPTUNE_2_10GF_2_1GRF = 423 (NXGE_PORT_10G_FIBRE | 424 (NXGE_PORT_10G_FIBRE << 4) | 425 (NXGE_PORT_1G_RGMII_FIBER << 8) | 426 (NXGE_PORT_1G_RGMII_FIBER << 12)), 427 428 N2_NIU = 429 (NXGE_PORT_RSVD | 430 (NXGE_PORT_RSVD << 4) | 431 (NXGE_PORT_RSVD << 8) | 432 (NXGE_PORT_RSVD << 12)) 433 434 } niu_type_t; 435 436 /* 437 * P_NEPTUNE_GENERIC: 438 * The cover-all case for Neptune (as opposed to NIU) where we do not 439 * care the exact platform as we do not do anything that is platform 440 * specific. 441 * P_NEPTUNE_ATLAS_2PORT: 442 * Dual Port Fiber Neptune based NIC (2XGF) 443 * P_NEPTUNE_ATLAS_4PORT: 444 * Quad Port Copper Neptune based NIC (QGC) 445 * P_NEPTUNE_NIU: 446 * This is NIU. Could be Huron, Glendale, Monza or any other NIU based 447 * platform. 448 */ 449 typedef enum { 450 P_NEPTUNE_NONE, 451 P_NEPTUNE_GENERIC, 452 P_NEPTUNE_ATLAS_2PORT, 453 P_NEPTUNE_ATLAS_4PORT, 454 P_NEPTUNE_MARAMBA_P0, 455 P_NEPTUNE_MARAMBA_P1, 456 P_NEPTUNE_ALONSO, 457 P_NEPTUNE_ROCK, 458 P_NEPTUNE_NIU 459 } platform_type_t; 460 461 #define NXGE_IS_VALID_NEPTUNE_TYPE(nxgep) \ 462 (((nxgep->platform_type) == P_NEPTUNE_ATLAS_2PORT) || \ 463 ((nxgep->platform_type) == P_NEPTUNE_ATLAS_4PORT) || \ 464 ((nxgep->platform_type) == P_NEPTUNE_MARAMBA_P0) || \ 465 ((nxgep->platform_type) == P_NEPTUNE_MARAMBA_P1) || \ 466 ((nxgep->platform_type) == P_NEPTUNE_GENERIC) || \ 467 ((nxgep->platform_type) == P_NEPTUNE_ALONSO) || \ 468 ((nxgep->platform_type) == P_NEPTUNE_ROCK)) 469 470 #define NXGE_IS_XAUI_PLATFORM(nxgep) \ 471 (((nxgep->platform_type) == P_NEPTUNE_NIU) || \ 472 ((nxgep->platform_type) == P_NEPTUNE_MARAMBA_P0) || \ 473 ((nxgep->platform_type) == P_NEPTUNE_MARAMBA_P1)) 474 475 476 typedef enum { 477 CFG_DEFAULT = 0, /* default cfg */ 478 CFG_EQUAL, /* Equal */ 479 CFG_FAIR, /* Equal */ 480 CFG_CLASSIFY, 481 CFG_L2_CLASSIFY, 482 CFG_L3_CLASSIFY, 483 CFG_L3_DISTRIBUTE, 484 CFG_L3_WEB, 485 CFG_L3_TCAM, 486 CFG_NOT_SPECIFIED, 487 CFG_CUSTOM /* Custom */ 488 } cfg_type_t; 489 490 typedef enum { 491 NO_MSG = 0x0, /* No message output or storage. */ 492 CONSOLE = 0x1, /* Messages are go to the console. */ 493 BUFFER = 0x2, /* Messages are go to the system buffer. */ 494 CON_BUF = 0x3, /* Messages are go to the console and */ 495 /* system buffer. */ 496 VERBOSE = 0x4 /* Messages are go out only in VERBOSE node. */ 497 } out_msg_t, *p_out_msg_t; 498 499 typedef enum { 500 DBG_NO_MSG = 0x0, /* No message output or storage. */ 501 DBG_CONSOLE = 0x1, /* Messages are go to the console. */ 502 DBG_BUFFER = 0x2, /* Messages are go to the system buffer. */ 503 DBG_CON_BUF = 0x3, /* Messages are go to the console and */ 504 /* system buffer. */ 505 STR_LOG = 4 /* Sessage sent to streams logging driver. */ 506 } out_dbgmsg_t, *p_out_dbgmsg_t; 507 508 typedef enum { 509 DDI_MEM_ALLOC, /* default (use ddi_dma_mem_alloc) */ 510 KMEM_ALLOC, /* use kmem_alloc(). */ 511 CONTIG_MEM_ALLOC /* use contig_mem_alloc() (N2/NIU only) */ 512 } buf_alloc_type_t; 513 514 #define BUF_ALLOCATED 0x00000001 515 #define BUF_ALLOCATED_WAIT_FREE 0x00000002 516 517 #if defined(_KERNEL) || defined(COSIM) 518 519 typedef struct ether_addr ether_addr_st, *p_ether_addr_t; 520 typedef struct ether_header ether_header_t, *p_ether_header_t; 521 typedef queue_t *p_queue_t; 522 523 #if !defined(IODIAG) 524 typedef mblk_t *p_mblk_t; 525 #endif 526 527 /* 528 * Generic phy table to support different phy types. 529 * 530 * The argument for check_link is nxgep, which is passed to check_link 531 * as an argument to the timer routine. 532 */ 533 typedef struct _nxge_xcvr_table { 534 nxge_status_t (*serdes_init) (); /* Serdes init routine */ 535 nxge_status_t (*xcvr_init) (); /* xcvr init routine */ 536 nxge_status_t (*link_intr_stop) (); /* Link intr disable routine */ 537 nxge_status_t (*link_intr_start) (); /* Link intr enable routine */ 538 nxge_status_t (*check_link) (); /* Link check routine */ 539 540 uint32_t xcvr_inuse; 541 } nxge_xcvr_table_t, *p_nxge_xcvr_table_t; 542 543 /* 544 * Common DMA data elements. 545 */ 546 typedef struct _nxge_dma_pool_t nxge_dma_pool_t, *p_nxge_dma_pool_t; 547 548 struct _nxge_dma_common_t { 549 uint16_t dma_channel; 550 void *kaddrp; 551 void *last_kaddrp; 552 void *ioaddr_pp; 553 void *first_ioaddr_pp; 554 void *last_ioaddr_pp; 555 ddi_dma_cookie_t dma_cookie; 556 uint32_t ncookies; 557 558 ddi_dma_handle_t dma_handle; 559 nxge_os_acc_handle_t acc_handle; 560 npi_handle_t npi_handle; 561 562 size_t block_size; 563 uint32_t nblocks; 564 size_t alength; 565 uint_t offset; 566 uint_t dma_chunk_index; 567 void *orig_ioaddr_pp; 568 uint64_t orig_vatopa; 569 void *orig_kaddrp; 570 size_t orig_alength; 571 boolean_t contig_alloc_type; 572 /* 573 * Receive buffers may be allocated using 574 * kmem_alloc(). The buffer free function 575 * depends on its allocation function. 576 */ 577 boolean_t kmem_alloc_type; 578 uint32_t buf_alloc_state; 579 buf_alloc_type_t buf_alloc_type; 580 p_nxge_dma_pool_t rx_buf_pool_p; 581 }; 582 583 typedef struct _nxge_t nxge_t, *p_nxge_t; 584 typedef struct _nxge_dma_common_t nxge_dma_common_t, *p_nxge_dma_common_t; 585 586 struct _nxge_dma_pool_t { 587 p_nxge_dma_common_t *dma_buf_pool_p; 588 uint32_t ndmas; 589 uint32_t *num_chunks; 590 boolean_t buf_allocated; 591 }; 592 593 /* 594 * Each logical device (69): 595 * - LDG # 596 * - flag bits 597 * - masks. 598 * - interrupt handler function. 599 * 600 * Generic system interrupt handler with two arguments: 601 * (nxge_sys_intr_t) 602 * Per device instance data structure 603 * Logical group data structure. 604 * 605 * Logical device interrupt handler with two arguments: 606 * (nxge_ldv_intr_t) 607 * Per device instance data structure 608 * Logical device number 609 */ 610 typedef struct _nxge_ldg_t nxge_ldg_t, *p_nxge_ldg_t; 611 typedef struct _nxge_ldv_t nxge_ldv_t, *p_nxge_ldv_t; 612 typedef uint_t (*nxge_sys_intr_t)(void *arg1, void *arg2); 613 typedef uint_t (*nxge_ldv_intr_t)(void *arg1, void *arg2); 614 615 /* 616 * Each logical device Group (64) needs to have the following 617 * configurations: 618 * - timer counter (6 bits) 619 * - timer resolution (20 bits, number of system clocks) 620 * - system data (7 bits) 621 */ 622 struct _nxge_ldg_t { 623 uint8_t ldg; /* logical group number */ 624 uint8_t vldg_index; 625 boolean_t arm; 626 boolean_t interrupted; 627 uint16_t ldg_timer; /* counter */ 628 uint8_t func; 629 uint8_t vector; 630 uint8_t intdata; 631 uint8_t nldvs; 632 p_nxge_ldv_t ldvp; 633 nxge_sys_intr_t sys_intr_handler; 634 p_nxge_t nxgep; 635 }; 636 637 struct _nxge_ldv_t { 638 uint8_t ldg_assigned; 639 uint8_t ldv; 640 boolean_t is_rxdma; 641 boolean_t is_txdma; 642 boolean_t is_mif; 643 boolean_t is_mac; 644 boolean_t is_syserr; 645 boolean_t use_timer; 646 uint8_t channel; 647 uint8_t vdma_index; 648 uint8_t func; 649 p_nxge_ldg_t ldgp; 650 uint8_t ldv_flags; 651 uint8_t ldv_ldf_masks; 652 nxge_ldv_intr_t ldv_intr_handler; 653 p_nxge_t nxgep; 654 }; 655 #endif 656 657 typedef struct _nxge_logical_page_t { 658 uint16_t dma; 659 uint16_t page; 660 boolean_t valid; 661 uint64_t mask; 662 uint64_t value; 663 uint64_t reloc; 664 uint32_t handle; 665 } nxge_logical_page_t, *p_nxge_logical_page_t; 666 667 /* 668 * (Internal) return values from ioctl subroutines. 669 */ 670 enum nxge_ioc_reply { 671 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 672 IOC_DONE, /* OK, reply sent */ 673 IOC_ACK, /* OK, just send ACK */ 674 IOC_REPLY, /* OK, just send reply */ 675 IOC_RESTART_ACK, /* OK, restart & ACK */ 676 IOC_RESTART_REPLY /* OK, restart & reply */ 677 }; 678 679 typedef struct _pci_cfg_t { 680 uint16_t vendorid; 681 uint16_t devid; 682 uint16_t command; 683 uint16_t status; 684 uint8_t revid; 685 uint8_t res0; 686 uint16_t junk1; 687 uint8_t cache_line; 688 uint8_t latency; 689 uint8_t header; 690 uint8_t bist; 691 uint32_t base; 692 uint32_t base14; 693 uint32_t base18; 694 uint32_t base1c; 695 uint32_t base20; 696 uint32_t base24; 697 uint32_t base28; 698 uint32_t base2c; 699 uint32_t base30; 700 uint32_t res1[2]; 701 uint8_t int_line; 702 uint8_t int_pin; 703 uint8_t min_gnt; 704 uint8_t max_lat; 705 } pci_cfg_t, *p_pci_cfg_t; 706 707 #if defined(_KERNEL) || defined(COSIM) 708 709 typedef struct _dev_regs_t { 710 nxge_os_acc_handle_t nxge_pciregh; /* PCI config DDI IO handle */ 711 p_pci_cfg_t nxge_pciregp; /* mapped PCI registers */ 712 713 nxge_os_acc_handle_t nxge_regh; /* device DDI IO (BAR 0) */ 714 void *nxge_regp; /* mapped device registers */ 715 716 nxge_os_acc_handle_t nxge_msix_regh; /* MSI/X DDI handle (BAR 2) */ 717 void *nxge_msix_regp; /* MSI/X register */ 718 719 nxge_os_acc_handle_t nxge_vir_regh; /* virtualization (BAR 4) */ 720 unsigned char *nxge_vir_regp; /* virtualization register */ 721 722 nxge_os_acc_handle_t nxge_vir2_regh; /* second virtualization */ 723 unsigned char *nxge_vir2_regp; /* second virtualization */ 724 725 nxge_os_acc_handle_t nxge_romh; /* fcode rom handle */ 726 unsigned char *nxge_romp; /* fcode pointer */ 727 } dev_regs_t, *p_dev_regs_t; 728 729 730 typedef struct _nxge_mac_addr_t { 731 ether_addr_t addr; 732 uint_t flags; 733 } nxge_mac_addr_t; 734 735 /* 736 * The hardware supports 1 unique MAC and 16 alternate MACs (num_mmac) 737 * for each XMAC port and supports 1 unique MAC and 7 alternate MACs 738 * for each BMAC port. The number of MACs assigned by the factory is 739 * different and is as follows, 740 * BMAC port: num_factory_mmac = num_mmac = 7 741 * XMAC port on a 2-port NIC: num_factory_mmac = num_mmac - 1 = 15 742 * XMAC port on a 4-port NIC: num_factory_mmac = 7 743 * So num_factory_mmac is smaller than num_mmac. nxge_m_mmac_add uses 744 * num_mmac and nxge_m_mmac_reserve uses num_factory_mmac. 745 * 746 * total_factory_macs is the total number of factory MACs, including 747 * the unique MAC, assigned to a Neptune based NIC card, it is 32. 748 */ 749 typedef struct _nxge_mmac_t { 750 uint8_t total_factory_macs; 751 uint8_t num_mmac; 752 uint8_t num_factory_mmac; 753 nxge_mac_addr_t mac_pool[XMAC_MAX_ADDR_ENTRY]; 754 ether_addr_t factory_mac_pool[XMAC_MAX_ADDR_ENTRY]; 755 uint8_t naddrfree; /* number of alt mac addr available */ 756 } nxge_mmac_t; 757 758 /* 759 * mmac stats structure 760 */ 761 typedef struct _nxge_mmac_stats_t { 762 uint8_t mmac_max_cnt; 763 uint8_t mmac_avail_cnt; 764 struct ether_addr mmac_avail_pool[16]; 765 } nxge_mmac_stats_t, *p_nxge_mmac_stats_t; 766 767 #define NXGE_MAX_MMAC_ADDRS 32 768 #define NXGE_NUM_MMAC_ADDRS 8 769 #define NXGE_NUM_OF_PORTS_QUAD 4 770 #define NXGE_NUM_OF_PORTS_DUAL 2 771 772 #define NXGE_QGC_LP_BM_STR "501-7606" 773 #define NXGE_2XGF_LP_BM_STR "501-7283" 774 #define NXGE_QGC_PEM_BM_STR "501-7765" 775 #define NXGE_2XGF_PEM_BM_STR "501-7626" 776 #define NXGE_ALONSO_BM_STR "373-0202-01" 777 #define NXGE_ALONSO_MODEL_STR "SUNW,CP3220" 778 #define NXGE_RFEM_BM_STR "501-7961-01" 779 #define NXGE_RFEM_MODEL_STR "SUNW,pcie-rfem" 780 #define NXGE_ARTM_BM_STR "375-3544-01" 781 #define NXGE_ARTM_MODEL_STR "SUNW,pcie-artm" 782 /* ROCK OBP creates a compatible property for ROCK */ 783 #define NXGE_ROCK_COMPATIBLE "SUNW,rock-pciex108e,abcd" 784 #define NXGE_EROM_LEN 1048576 785 786 #endif 787 788 #include <sys/nxge/nxge_common_impl.h> 789 #include <sys/nxge/nxge_common.h> 790 #include <sys/nxge/nxge_txc.h> 791 #include <sys/nxge/nxge_rxdma.h> 792 #include <sys/nxge/nxge_txdma.h> 793 #include <sys/nxge/nxge_fflp.h> 794 #include <sys/nxge/nxge_ipp.h> 795 #include <sys/nxge/nxge_zcp.h> 796 #include <sys/nxge/nxge_fzc.h> 797 #include <sys/nxge/nxge_flow.h> 798 #include <sys/nxge/nxge_virtual.h> 799 800 #include <npi_espc.h> 801 #include <npi_vir.h> 802 803 #include <sys/nxge/nxge.h> 804 805 #include <sys/modctl.h> 806 #include <sys/pattr.h> 807 808 extern int secpolicy_net_config(const cred_t *, boolean_t); 809 extern void nxge_fm_report_error(p_nxge_t, uint8_t, 810 uint8_t, nxge_fm_ereport_id_t); 811 extern int fm_check_acc_handle(ddi_acc_handle_t); 812 extern int fm_check_dma_handle(ddi_dma_handle_t); 813 814 /* nxge_classify.c */ 815 nxge_status_t nxge_classify_init(p_nxge_t); 816 nxge_status_t nxge_classify_uninit(p_nxge_t); 817 nxge_status_t nxge_set_hw_classify_config(p_nxge_t); 818 nxge_status_t nxge_classify_exit_sw(p_nxge_t); 819 820 /* nxge_fflp.c */ 821 void nxge_put_tcam(p_nxge_t, p_mblk_t); 822 void nxge_get_tcam(p_nxge_t, p_mblk_t); 823 nxge_status_t nxge_classify_init_hw(p_nxge_t); 824 nxge_status_t nxge_classify_init_sw(p_nxge_t); 825 nxge_status_t nxge_fflp_ip_class_config_all(p_nxge_t); 826 nxge_status_t nxge_fflp_ip_class_config(p_nxge_t, tcam_class_t, 827 uint32_t); 828 829 nxge_status_t nxge_fflp_ip_class_config_get(p_nxge_t, 830 tcam_class_t, 831 uint32_t *); 832 833 nxge_status_t nxge_cfg_ip_cls_flow_key(p_nxge_t, tcam_class_t, 834 uint32_t); 835 836 nxge_status_t nxge_fflp_ip_usr_class_config(p_nxge_t, tcam_class_t, 837 uint32_t); 838 839 uint64_t nxge_classify_get_cfg_value(p_nxge_t, uint8_t, uint8_t); 840 nxge_status_t nxge_add_flow(p_nxge_t, flow_resource_t *); 841 nxge_status_t nxge_fflp_config_tcam_enable(p_nxge_t); 842 nxge_status_t nxge_fflp_config_tcam_disable(p_nxge_t); 843 844 nxge_status_t nxge_fflp_config_hash_lookup_enable(p_nxge_t); 845 nxge_status_t nxge_fflp_config_hash_lookup_disable(p_nxge_t); 846 847 nxge_status_t nxge_fflp_config_llc_snap_enable(p_nxge_t); 848 nxge_status_t nxge_fflp_config_llc_snap_disable(p_nxge_t); 849 850 nxge_status_t nxge_logical_mac_assign_rdc_table(p_nxge_t, uint8_t); 851 nxge_status_t nxge_fflp_config_vlan_table(p_nxge_t, uint16_t); 852 853 nxge_status_t nxge_fflp_set_hash1(p_nxge_t, uint32_t); 854 855 nxge_status_t nxge_fflp_set_hash2(p_nxge_t, uint16_t); 856 857 nxge_status_t nxge_fflp_init_hostinfo(p_nxge_t); 858 859 void nxge_handle_tcam_fragment_bug(p_nxge_t); 860 nxge_status_t nxge_fflp_hw_reset(p_nxge_t); 861 nxge_status_t nxge_fflp_handle_sys_errors(p_nxge_t); 862 nxge_status_t nxge_zcp_handle_sys_errors(p_nxge_t); 863 864 /* nxge_kstats.c */ 865 void nxge_init_statsp(p_nxge_t); 866 void nxge_setup_kstats(p_nxge_t); 867 void nxge_setup_rdc_kstats(p_nxge_t, int); 868 void nxge_setup_tdc_kstats(p_nxge_t, int); 869 void nxge_destroy_kstats(p_nxge_t); 870 int nxge_port_kstat_update(kstat_t *, int); 871 void nxge_save_cntrs(p_nxge_t); 872 873 int nxge_m_stat(void *arg, uint_t, uint64_t *); 874 875 /* nxge_hw.c */ 876 void 877 nxge_hw_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *); 878 void nxge_loopback_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *); 879 nxge_status_t nxge_global_reset(p_nxge_t); 880 uint_t nxge_intr(void *, void *); 881 void nxge_intr_enable(p_nxge_t); 882 void nxge_intr_disable(p_nxge_t); 883 void nxge_hw_blank(void *arg, time_t, uint_t); 884 void nxge_hw_id_init(p_nxge_t); 885 void nxge_hw_init_niu_common(p_nxge_t); 886 void nxge_intr_hw_enable(p_nxge_t); 887 void nxge_intr_hw_disable(p_nxge_t); 888 void nxge_hw_stop(p_nxge_t); 889 void nxge_check_hw_state(p_nxge_t); 890 891 void nxge_rxdma_channel_put64(nxge_os_acc_handle_t, 892 void *, uint32_t, uint16_t, 893 uint64_t); 894 uint64_t nxge_rxdma_channel_get64(nxge_os_acc_handle_t, void *, 895 uint32_t, uint16_t); 896 897 898 void nxge_get32(p_nxge_t, p_mblk_t); 899 void nxge_put32(p_nxge_t, p_mblk_t); 900 901 void nxge_hw_set_mac_modes(p_nxge_t); 902 903 /* nxge_send.c. */ 904 uint_t nxge_reschedule(caddr_t); 905 906 /* nxge_rxdma.c */ 907 nxge_status_t nxge_rxdma_cfg_rdcgrp_default_rdc(p_nxge_t, 908 uint8_t, uint8_t); 909 910 nxge_status_t nxge_rxdma_cfg_port_default_rdc(p_nxge_t, 911 uint8_t, uint8_t); 912 nxge_status_t nxge_rxdma_cfg_rcr_threshold(p_nxge_t, uint8_t, 913 uint16_t); 914 nxge_status_t nxge_rxdma_cfg_rcr_timeout(p_nxge_t, uint8_t, 915 uint16_t, uint8_t); 916 917 /* nxge_ndd.c */ 918 void nxge_get_param_soft_properties(p_nxge_t); 919 void nxge_copy_hw_default_to_param(p_nxge_t); 920 void nxge_copy_param_hw_to_config(p_nxge_t); 921 void nxge_setup_param(p_nxge_t); 922 void nxge_init_param(p_nxge_t); 923 void nxge_destroy_param(p_nxge_t); 924 boolean_t nxge_check_rxdma_rdcgrp_member(p_nxge_t, uint8_t, uint8_t); 925 boolean_t nxge_check_rxdma_port_member(p_nxge_t, uint8_t); 926 boolean_t nxge_check_rdcgrp_port_member(p_nxge_t, uint8_t); 927 928 boolean_t nxge_check_txdma_port_member(p_nxge_t, uint8_t); 929 930 int nxge_param_get_generic(p_nxge_t, queue_t *, mblk_t *, caddr_t); 931 int nxge_param_set_generic(p_nxge_t, queue_t *, mblk_t *, char *, caddr_t); 932 int nxge_get_default(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 933 int nxge_set_default(p_nxge_t, queue_t *, p_mblk_t, char *, caddr_t); 934 int nxge_nd_get_names(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 935 int nxge_mk_mblk_tail_space(p_mblk_t, p_mblk_t *, size_t); 936 long nxge_strtol(char *, char **, int); 937 boolean_t nxge_param_get_instance(queue_t *, mblk_t *); 938 void nxge_param_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *); 939 boolean_t nxge_nd_load(caddr_t *, char *, pfi_t, pfi_t, caddr_t); 940 void nxge_nd_free(caddr_t *); 941 int nxge_nd_getset(p_nxge_t, queue_t *, caddr_t, p_mblk_t); 942 943 nxge_status_t nxge_set_lb_normal(p_nxge_t); 944 boolean_t nxge_set_lb(p_nxge_t, queue_t *, p_mblk_t); 945 boolean_t nxge_param_link_update(p_nxge_t); 946 int nxge_param_set_ip_opt(p_nxge_t, queue_t *, mblk_t *, char *, caddr_t); 947 int nxge_dld_get_ip_opt(p_nxge_t, caddr_t); 948 int nxge_param_rx_intr_pkts(p_nxge_t, queue_t *, 949 mblk_t *, char *, caddr_t); 950 int nxge_param_rx_intr_time(p_nxge_t, queue_t *, 951 mblk_t *, char *, caddr_t); 952 953 954 /* nxge_virtual.c */ 955 nxge_status_t nxge_cntlops(dev_info_t *, nxge_ctl_enum_t, void *, void *); 956 void nxge_common_lock_get(p_nxge_t); 957 void nxge_common_lock_free(p_nxge_t); 958 959 nxge_status_t nxge_get_config_properties(p_nxge_t); 960 void nxge_get_xcvr_properties(p_nxge_t); 961 void nxge_init_vlan_config(p_nxge_t); 962 void nxge_init_mac_config(p_nxge_t); 963 964 965 void nxge_init_logical_devs(p_nxge_t); 966 int nxge_init_ldg_intrs(p_nxge_t); 967 968 void nxge_set_ldgimgmt(p_nxge_t, uint32_t, boolean_t, 969 uint32_t); 970 971 void nxge_init_fzc_txdma_channels(p_nxge_t); 972 973 nxge_status_t nxge_init_fzc_txdma_channel(p_nxge_t, uint16_t, 974 p_tx_ring_t, p_tx_mbox_t); 975 nxge_status_t nxge_init_fzc_txdma_port(p_nxge_t); 976 977 nxge_status_t nxge_init_fzc_rxdma_channel(p_nxge_t, uint16_t); 978 979 nxge_status_t nxge_init_fzc_rx_common(p_nxge_t); 980 nxge_status_t nxge_init_fzc_rxdma_port(p_nxge_t); 981 982 nxge_status_t nxge_init_fzc_rxdma_channel_pages(p_nxge_t, 983 uint16_t, p_rx_rbr_ring_t); 984 nxge_status_t nxge_init_fzc_rxdma_channel_red(p_nxge_t, 985 uint16_t, p_rx_rcr_ring_t); 986 987 nxge_status_t nxge_init_fzc_rxdma_channel_clrlog(p_nxge_t, 988 uint16_t, p_rx_rbr_ring_t); 989 990 991 nxge_status_t nxge_init_fzc_txdma_channel_pages(p_nxge_t, 992 uint16_t, p_tx_ring_t); 993 994 nxge_status_t nxge_init_fzc_txdma_channel_drr(p_nxge_t, uint16_t, 995 p_tx_ring_t); 996 997 nxge_status_t nxge_init_fzc_txdma_port(p_nxge_t); 998 999 void nxge_init_fzc_ldg_num(p_nxge_t); 1000 void nxge_init_fzc_sys_int_data(p_nxge_t); 1001 void nxge_init_fzc_ldg_int_timer(p_nxge_t); 1002 nxge_status_t nxge_intr_mask_mgmt_set(p_nxge_t, boolean_t on); 1003 1004 /* MAC functions */ 1005 nxge_status_t nxge_mac_init(p_nxge_t); 1006 nxge_status_t nxge_link_init(p_nxge_t); 1007 nxge_status_t nxge_xif_init(p_nxge_t); 1008 nxge_status_t nxge_pcs_init(p_nxge_t); 1009 nxge_status_t nxge_mac_ctrl_init(p_nxge_t); 1010 nxge_status_t nxge_serdes_init(p_nxge_t); 1011 nxge_status_t nxge_serdes_reset(p_nxge_t); 1012 nxge_status_t nxge_xcvr_find(p_nxge_t); 1013 nxge_status_t nxge_get_xcvr_type(p_nxge_t); 1014 nxge_status_t nxge_setup_xcvr_table(p_nxge_t); 1015 nxge_status_t nxge_xcvr_init(p_nxge_t); 1016 nxge_status_t nxge_tx_mac_init(p_nxge_t); 1017 nxge_status_t nxge_rx_mac_init(p_nxge_t); 1018 nxge_status_t nxge_tx_mac_enable(p_nxge_t); 1019 nxge_status_t nxge_tx_mac_disable(p_nxge_t); 1020 nxge_status_t nxge_rx_mac_enable(p_nxge_t); 1021 nxge_status_t nxge_rx_mac_disable(p_nxge_t); 1022 nxge_status_t nxge_tx_mac_reset(p_nxge_t); 1023 nxge_status_t nxge_rx_mac_reset(p_nxge_t); 1024 nxge_status_t nxge_link_intr(p_nxge_t, link_intr_enable_t); 1025 nxge_status_t nxge_mii_xcvr_init(p_nxge_t); 1026 nxge_status_t nxge_mii_xcvr_fiber_init(p_nxge_t); 1027 nxge_status_t nxge_mii_read(p_nxge_t, uint8_t, 1028 uint8_t, uint16_t *); 1029 nxge_status_t nxge_mii_write(p_nxge_t, uint8_t, 1030 uint8_t, uint16_t); 1031 nxge_status_t nxge_mdio_read(p_nxge_t, uint8_t, uint8_t, 1032 uint16_t, uint16_t *); 1033 nxge_status_t nxge_mdio_write(p_nxge_t, uint8_t, 1034 uint8_t, uint16_t, uint16_t); 1035 nxge_status_t nxge_mii_check(p_nxge_t, mii_bmsr_t, 1036 mii_bmsr_t, nxge_link_state_t *); 1037 void nxge_pcs_check(p_nxge_t, uint8_t portn, nxge_link_state_t *); 1038 nxge_status_t nxge_add_mcast_addr(p_nxge_t, struct ether_addr *); 1039 nxge_status_t nxge_del_mcast_addr(p_nxge_t, struct ether_addr *); 1040 nxge_status_t nxge_set_mac_addr(p_nxge_t, struct ether_addr *); 1041 nxge_status_t nxge_check_bcm8704_link(p_nxge_t, boolean_t *); 1042 nxge_status_t nxge_check_tn1010_link(p_nxge_t); 1043 void nxge_link_is_down(p_nxge_t); 1044 void nxge_link_is_up(p_nxge_t); 1045 nxge_status_t nxge_link_monitor(p_nxge_t, link_mon_enable_t); 1046 uint32_t crc32_mchash(p_ether_addr_t); 1047 nxge_status_t nxge_set_promisc(p_nxge_t, boolean_t); 1048 nxge_status_t nxge_mac_handle_sys_errors(p_nxge_t); 1049 nxge_status_t nxge_10g_link_led_on(p_nxge_t); 1050 nxge_status_t nxge_10g_link_led_off(p_nxge_t); 1051 nxge_status_t nxge_scan_ports_phy(p_nxge_t, p_nxge_hw_list_t); 1052 boolean_t nxge_is_valid_local_mac(ether_addr_st); 1053 nxge_status_t nxge_mac_set_framesize(p_nxge_t); 1054 1055 /* espc (sprom) prototypes */ 1056 nxge_status_t nxge_espc_mac_addrs_get(p_nxge_t); 1057 nxge_status_t nxge_espc_num_macs_get(p_nxge_t, uint8_t *); 1058 nxge_status_t nxge_espc_num_ports_get(p_nxge_t); 1059 nxge_status_t nxge_espc_phy_type_get(p_nxge_t); 1060 nxge_status_t nxge_espc_verify_chksum(p_nxge_t); 1061 void nxge_espc_get_next_mac_addr(uint8_t *, uint8_t, struct ether_addr *); 1062 void nxge_vpd_info_get(p_nxge_t); 1063 1064 1065 void nxge_debug_msg(p_nxge_t, uint64_t, char *, ...); 1066 int nxge_get_nports(p_nxge_t); 1067 1068 void nxge_free_buf(buf_alloc_type_t, uint64_t, uint32_t); 1069 1070 uint64_t hv_niu_rx_logical_page_conf(uint64_t, uint64_t, 1071 uint64_t, uint64_t); 1072 #pragma weak hv_niu_rx_logical_page_conf 1073 1074 uint64_t hv_niu_rx_logical_page_info(uint64_t, uint64_t, 1075 uint64_t *, uint64_t *); 1076 #pragma weak hv_niu_rx_logical_page_info 1077 1078 uint64_t hv_niu_tx_logical_page_conf(uint64_t, uint64_t, 1079 uint64_t, uint64_t); 1080 #pragma weak hv_niu_tx_logical_page_conf 1081 1082 uint64_t hv_niu_tx_logical_page_info(uint64_t, uint64_t, 1083 uint64_t *, uint64_t *); 1084 #pragma weak hv_niu_tx_logical_page_info 1085 1086 uint64_t hv_niu_vr_assign(uint64_t vridx, uint64_t ldc_id, uint32_t *cookie); 1087 #pragma weak hv_niu_vr_assign 1088 1089 uint64_t hv_niu_vr_unassign(uint32_t cookie); 1090 #pragma weak hv_niu_vr_unassign 1091 1092 uint64_t hv_niu_vr_getinfo(uint32_t cookie, uint64_t *real_start, 1093 uint64_t *size); 1094 #pragma weak hv_niu_vr_getinfo 1095 1096 uint64_t hv_niu_vr_get_rxmap(uint32_t cookie, uint64_t *dma_map); 1097 #pragma weak hv_niu_vr_get_rxmap 1098 1099 uint64_t hv_niu_vr_get_txmap(uint32_t cookie, uint64_t *dma_map); 1100 #pragma weak hv_niu_vr_get_txmap 1101 1102 uint64_t hv_niu_rx_dma_assign(uint32_t cookie, uint64_t chidx, 1103 uint64_t *vchidx); 1104 #pragma weak hv_niu_rx_dma_assign 1105 1106 uint64_t hv_niu_rx_dma_unassign(uint32_t cookie, uint64_t chidx); 1107 #pragma weak hv_niu_rx_dma_unassign 1108 1109 uint64_t hv_niu_tx_dma_assign(uint32_t cookie, uint64_t chidx, 1110 uint64_t *vchidx); 1111 #pragma weak hv_niu_tx_dma_assign 1112 1113 uint64_t hv_niu_tx_dma_unassign(uint32_t cookie, uint64_t chidx); 1114 #pragma weak hv_niu_tx_dma_unassign 1115 1116 uint64_t hv_niu_vrrx_logical_page_conf(uint32_t cookie, uint64_t chidx, 1117 uint64_t pgidx, uint64_t raddr, uint64_t size); 1118 #pragma weak hv_niu_vrrx_logical_page_conf 1119 1120 uint64_t hv_niu_vrrx_logical_page_info(uint32_t cookie, uint64_t chidx, 1121 uint64_t pgidx, uint64_t *raddr, uint64_t *size); 1122 #pragma weak hv_niu_vrrx_logical_page_info 1123 1124 uint64_t hv_niu_vrtx_logical_page_conf(uint32_t cookie, uint64_t chidx, 1125 uint64_t pgidx, uint64_t raddr, uint64_t size); 1126 #pragma weak hv_niu_vrtx_logical_page_conf 1127 1128 uint64_t hv_niu_vrtx_logical_page_info(uint32_t cookie, uint64_t chidx, 1129 uint64_t pgidx, uint64_t *raddr, uint64_t *size); 1130 #pragma weak hv_niu_vrtx_logical_page_info 1131 1132 // 1133 // NIU-specific interrupt API 1134 // 1135 uint64_t hv_niu_vrrx_getinfo(uint32_t cookie, uint64_t v_chidx, 1136 uint64_t *group, uint64_t *logdev); 1137 #pragma weak hv_niu_vrrx_getinfo 1138 1139 uint64_t hv_niu_vrtx_getinfo(uint32_t cookie, uint64_t v_chidx, 1140 uint64_t *group, uint64_t *logdev); 1141 #pragma weak hv_niu_vrtx_getinfo 1142 1143 uint64_t hv_niu_vrrx_to_logical_dev(uint32_t cookie, uint64_t v_chidx, 1144 uint64_t *ldn); 1145 #pragma weak hv_niu_vrrx_to_logical_dev 1146 1147 uint64_t hv_niu_vrtx_to_logical_dev(uint32_t cookie, uint64_t v_chidx, 1148 uint64_t *ldn); 1149 #pragma weak hv_niu_vrtx_to_logical_dev 1150 1151 #ifdef NXGE_DEBUG 1152 char *nxge_dump_packet(char *, int); 1153 #endif 1154 1155 #endif /* !_ASM */ 1156 1157 #ifdef __cplusplus 1158 } 1159 #endif 1160 1161 #endif /* _SYS_NXGE_NXGE_IMPL_H */ 1162