1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_IMPL_H 27 #define _SYS_NXGE_NXGE_IMPL_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * NIU HV API version definitions. 37 */ 38 #define NIU_MAJOR_VER 1 39 #define NIU_MINOR_VER 1 40 41 /* 42 * NIU HV API v1.0 definitions 43 */ 44 #define N2NIU_RX_LP_CONF 0x142 45 #define N2NIU_RX_LP_INFO 0x143 46 #define N2NIU_TX_LP_CONF 0x144 47 #define N2NIU_TX_LP_INFO 0x145 48 49 #ifndef _ASM 50 51 #include <sys/types.h> 52 #include <sys/byteorder.h> 53 #include <sys/debug.h> 54 #include <sys/stropts.h> 55 #include <sys/stream.h> 56 #include <sys/strlog.h> 57 #ifndef COSIM 58 #include <sys/strsubr.h> 59 #endif 60 #include <sys/cmn_err.h> 61 #include <sys/vtrace.h> 62 #include <sys/kmem.h> 63 #include <sys/ddi.h> 64 #include <sys/sunddi.h> 65 #include <sys/strsun.h> 66 #include <sys/stat.h> 67 #include <sys/cpu.h> 68 #include <sys/kstat.h> 69 #include <inet/common.h> 70 #include <inet/ip.h> 71 #include <sys/dlpi.h> 72 #include <inet/nd.h> 73 #include <netinet/in.h> 74 #include <sys/ethernet.h> 75 #include <sys/vlan.h> 76 #include <sys/pci.h> 77 #include <sys/taskq.h> 78 #include <sys/atomic.h> 79 80 #include <sys/nxge/nxge_defs.h> 81 #include <sys/nxge/nxge_hw.h> 82 #include <sys/nxge/nxge_mac.h> 83 #include <sys/nxge/nxge_mii.h> 84 #include <sys/nxge/nxge_fm.h> 85 #if !defined(IODIAG) 86 #include <sys/netlb.h> 87 #endif 88 89 #include <sys/ddi_intr.h> 90 91 #if defined(_KERNEL) 92 #include <sys/mac.h> 93 #include <sys/mac_impl.h> 94 #include <sys/mac_ether.h> 95 #endif 96 97 #if defined(sun4v) 98 #include <sys/hypervisor_api.h> 99 #include <sys/machsystm.h> 100 #include <sys/hsvc.h> 101 #endif 102 103 #include <sys/dld.h> 104 105 /* 106 * Handy macros (taken from bge driver) 107 */ 108 #define RBR_SIZE 4 109 #define DMA_COMMON_CHANNEL(area) ((area.dma_channel)) 110 #define DMA_COMMON_VPTR(area) ((area.kaddrp)) 111 #define DMA_COMMON_VPTR_INDEX(area, index) \ 112 (((char *)(area.kaddrp)) + \ 113 (index * RBR_SIZE)) 114 #define DMA_COMMON_HANDLE(area) ((area.dma_handle)) 115 #define DMA_COMMON_ACC_HANDLE(area) ((area.acc_handle)) 116 #define DMA_COMMON_IOADDR(area) ((area.dma_cookie.dmac_laddress)) 117 #define DMA_COMMON_IOADDR_INDEX(area, index) \ 118 ((area.dma_cookie.dmac_laddress) + \ 119 (index * RBR_SIZE)) 120 121 #define DMA_NPI_HANDLE(area) ((area.npi_handle) 122 123 #define DMA_COMMON_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_handle,\ 124 (area).offset, (area).alength, \ 125 (flag))) 126 #define DMA_COMMON_SYNC_OFFSET(area, bufoffset, len, flag) \ 127 ((void) ddi_dma_sync((area).dma_handle,\ 128 (area.offset + bufoffset), len, \ 129 (flag))) 130 131 #define DMA_COMMON_SYNC_RBR_DESC(area, index, flag) \ 132 ((void) ddi_dma_sync((area).dma_handle,\ 133 (index * RBR_SIZE), RBR_SIZE, \ 134 (flag))) 135 136 #define DMA_COMMON_SYNC_RBR_DESC_MULTI(area, index, count, flag) \ 137 ((void) ddi_dma_sync((area).dma_handle,\ 138 (index * RBR_SIZE), count * RBR_SIZE, \ 139 (flag))) 140 #define DMA_COMMON_SYNC_ENTRY(area, index, flag) \ 141 ((void) ddi_dma_sync((area).dma_handle,\ 142 (index * (area).block_size), \ 143 (area).block_size, \ 144 (flag))) 145 146 #define NEXT_ENTRY(index, wrap) ((index + 1) & wrap) 147 #define NEXT_ENTRY_PTR(ptr, first, last) \ 148 ((ptr == last) ? first : (ptr + 1)) 149 150 /* 151 * NPI related macros 152 */ 153 #define NXGE_DEV_NPI_HANDLE(nxgep) (nxgep->npi_handle) 154 155 #define NPI_PCI_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_pci_handle.regh = ah) 156 #define NPI_PCI_ADD_HANDLE_SET(nxgep, ap) (nxgep->npi_pci_handle.regp = ap) 157 158 #define NPI_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_handle.regh = ah) 159 #define NPI_ADD_HANDLE_SET(nxgep, ap) \ 160 nxgep->npi_handle.is_vraddr = B_FALSE; \ 161 nxgep->npi_handle.function.instance = nxgep->instance; \ 162 nxgep->npi_handle.function.function = nxgep->function_num; \ 163 nxgep->npi_handle.nxgep = (void *) nxgep; \ 164 nxgep->npi_handle.regp = ap; 165 166 #define NPI_REG_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_reg_handle.regh = ah) 167 #define NPI_REG_ADD_HANDLE_SET(nxgep, ap) \ 168 nxgep->npi_reg_handle.is_vraddr = B_FALSE; \ 169 nxgep->npi_handle.function.instance = nxgep->instance; \ 170 nxgep->npi_handle.function.function = nxgep->function_num; \ 171 nxgep->npi_reg_handle.nxgep = (void *) nxgep; \ 172 nxgep->npi_reg_handle.regp = ap; 173 174 #define NPI_MSI_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_msi_handle.regh = ah) 175 #define NPI_MSI_ADD_HANDLE_SET(nxgep, ap) (nxgep->npi_msi_handle.regp = ap) 176 177 #define NPI_VREG_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_vreg_handle.regh = ah) 178 #define NPI_VREG_ADD_HANDLE_SET(nxgep, ap) \ 179 nxgep->npi_vreg_handle.is_vraddr = B_TRUE; \ 180 nxgep->npi_handle.function.instance = nxgep->instance; \ 181 nxgep->npi_handle.function.function = nxgep->function_num; \ 182 nxgep->npi_vreg_handle.nxgep = (void *) nxgep; \ 183 nxgep->npi_vreg_handle.regp = ap; 184 185 #define NPI_V2REG_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_v2reg_handle.regh = ah) 186 #define NPI_V2REG_ADD_HANDLE_SET(nxgep, ap) \ 187 nxgep->npi_v2reg_handle.is_vraddr = B_TRUE; \ 188 nxgep->npi_handle.function.instance = nxgep->instance; \ 189 nxgep->npi_handle.function.function = nxgep->function_num; \ 190 nxgep->npi_v2reg_handle.nxgep = (void *) nxgep; \ 191 nxgep->npi_v2reg_handle.regp = ap; 192 193 #define NPI_PCI_ACC_HANDLE_GET(nxgep) (nxgep->npi_pci_handle.regh) 194 #define NPI_PCI_ADD_HANDLE_GET(nxgep) (nxgep->npi_pci_handle.regp) 195 #define NPI_ACC_HANDLE_GET(nxgep) (nxgep->npi_handle.regh) 196 #define NPI_ADD_HANDLE_GET(nxgep) (nxgep->npi_handle.regp) 197 #define NPI_REG_ACC_HANDLE_GET(nxgep) (nxgep->npi_reg_handle.regh) 198 #define NPI_REG_ADD_HANDLE_GET(nxgep) (nxgep->npi_reg_handle.regp) 199 #define NPI_MSI_ACC_HANDLE_GET(nxgep) (nxgep->npi_msi_handle.regh) 200 #define NPI_MSI_ADD_HANDLE_GET(nxgep) (nxgep->npi_msi_handle.regp) 201 #define NPI_VREG_ACC_HANDLE_GET(nxgep) (nxgep->npi_vreg_handle.regh) 202 #define NPI_VREG_ADD_HANDLE_GET(nxgep) (nxgep->npi_vreg_handle.regp) 203 #define NPI_V2REG_ACC_HANDLE_GET(nxgep) (nxgep->npi_v2reg_handle.regh) 204 #define NPI_V2REG_ADD_HANDLE_GET(nxgep) (nxgep->npi_v2reg_handle.regp) 205 206 #define NPI_DMA_ACC_HANDLE_SET(dmap, ah) (dmap->npi_handle.regh = ah) 207 #define NPI_DMA_ACC_HANDLE_GET(dmap) (dmap->npi_handle.regh) 208 209 /* 210 * DMA handles. 211 */ 212 #define NXGE_DESC_D_HANDLE_GET(desc) (desc.dma_handle) 213 #define NXGE_DESC_D_IOADD_GET(desc) (desc.dma_cookie.dmac_laddress) 214 #define NXGE_DMA_IOADD_GET(dma_cookie) (dma_cookie.dmac_laddress) 215 #define NXGE_DMA_AREA_IOADD_GET(dma_area) (dma_area.dma_cookie.dmac_laddress) 216 217 #define LDV_ON(ldv, vector) ((vector >> ldv) & 0x1) 218 #define LDV2_ON_1(ldv, vector) ((vector >> (ldv - 64)) & 0x1) 219 #define LDV2_ON_2(ldv, vector) (((vector >> 5) >> (ldv - 64)) & 0x1) 220 221 typedef uint32_t nxge_status_t; 222 223 typedef enum { 224 IDLE, 225 PROGRESS, 226 CONFIGURED 227 } dev_func_shared_t; 228 229 typedef enum { 230 DVMA, 231 DMA, 232 SDMA 233 } dma_method_t; 234 235 typedef enum { 236 BKSIZE_4K, 237 BKSIZE_8K, 238 BKSIZE_16K, 239 BKSIZE_32K 240 } nxge_rx_block_size_t; 241 242 #ifdef TX_ONE_BUF 243 #define TX_BCOPY_MAX 1514 244 #else 245 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 246 #define TX_BCOPY_MAX 4096 247 #define TX_BCOPY_SIZE 4096 248 #else 249 #define TX_BCOPY_MAX 2048 250 #define TX_BCOPY_SIZE 2048 251 #endif 252 #endif 253 254 #define TX_STREAM_MIN 512 255 #define TX_FASTDVMA_MIN 1024 256 257 /* 258 * Send repeated FMA ereports or display messages about some non-fatal 259 * hardware errors only the the first NXGE_ERROR_SHOW_MAX -1 times 260 */ 261 #define NXGE_ERROR_SHOW_MAX 2 262 263 264 /* 265 * Defaults 266 */ 267 #define NXGE_RDC_RCR_THRESHOLD 8 268 #define NXGE_RDC_RCR_TIMEOUT 16 269 270 #define NXGE_RDC_RCR_THRESHOLD_MAX 1024 271 #define NXGE_RDC_RCR_TIMEOUT_MAX 64 272 #define NXGE_RDC_RCR_THRESHOLD_MIN 1 273 #define NXGE_RDC_RCR_TIMEOUT_MIN 1 274 #define NXGE_RCR_FULL_HEADER 1 275 276 #define NXGE_IS_VLAN_PACKET(ptr) \ 277 ((((struct ether_vlan_header *)ptr)->ether_tpid) == \ 278 htons(VLAN_ETHERTYPE)) 279 280 typedef enum { 281 NONE, 282 SMALL, 283 MEDIUM, 284 LARGE 285 } dma_size_t; 286 287 typedef enum { 288 USE_NONE, 289 USE_BCOPY, 290 USE_DVMA, 291 USE_DMA, 292 USE_SDMA 293 } dma_type_t; 294 295 typedef enum { 296 NOT_IN_USE, 297 HDR_BUF, 298 MTU_BUF, 299 RE_ASSEMBLY_BUF, 300 FREE_BUF 301 } rx_page_state_t; 302 303 struct _nxge_block_mv_t { 304 uint32_t msg_type; 305 dma_type_t dma_type; 306 }; 307 308 typedef struct _nxge_block_mv_t nxge_block_mv_t, *p_nxge_block_mv_t; 309 310 typedef enum { 311 NIU_TYPE_NONE = 0, 312 313 NEPTUNE_4_1GC = 314 (NXGE_PORT_1G_COPPER | 315 (NXGE_PORT_1G_COPPER << 4) | 316 (NXGE_PORT_1G_COPPER << 8) | 317 (NXGE_PORT_1G_COPPER << 12)), 318 319 NEPTUNE_2_10GF = 320 (NXGE_PORT_10G_FIBRE | 321 (NXGE_PORT_10G_FIBRE << 4) | 322 (NXGE_PORT_NONE << 8) | 323 (NXGE_PORT_NONE << 12)), 324 325 NEPTUNE_2_10GF_2_1GC = 326 (NXGE_PORT_10G_FIBRE | 327 (NXGE_PORT_10G_FIBRE << 4) | 328 (NXGE_PORT_1G_COPPER << 8) | 329 (NXGE_PORT_1G_COPPER << 12)), 330 331 NEPTUNE_1_10GF_3_1GC = 332 (NXGE_PORT_10G_FIBRE | 333 (NXGE_PORT_1G_COPPER << 4) | 334 (NXGE_PORT_1G_COPPER << 8) | 335 (NXGE_PORT_1G_COPPER << 12)), 336 337 NEPTUNE_1_1GC_1_10GF_2_1GC = 338 (NXGE_PORT_1G_COPPER | 339 (NXGE_PORT_10G_FIBRE << 4) | 340 (NXGE_PORT_1G_COPPER << 8) | 341 (NXGE_PORT_1G_COPPER << 12)), 342 343 NEPTUNE_2_1GRF = 344 (NXGE_PORT_NONE | 345 (NXGE_PORT_NONE << 4) | 346 (NXGE_PORT_1G_RGMII_FIBER << 8) | 347 (NXGE_PORT_1G_RGMII_FIBER << 12)), 348 349 NEPTUNE_2_10GF_2_1GRF = 350 (NXGE_PORT_10G_FIBRE | 351 (NXGE_PORT_10G_FIBRE << 4) | 352 (NXGE_PORT_1G_RGMII_FIBER << 8) | 353 (NXGE_PORT_1G_RGMII_FIBER << 12)), 354 355 N2_NIU = 356 (NXGE_PORT_RSVD | 357 (NXGE_PORT_RSVD << 4) | 358 (NXGE_PORT_RSVD << 8) | 359 (NXGE_PORT_RSVD << 12)) 360 361 } niu_type_t; 362 363 typedef enum { 364 P_NEPTUNE_NONE, 365 P_NEPTUNE_GENERIC, 366 P_NEPTUNE_ATLAS_2PORT, 367 P_NEPTUNE_ATLAS_4PORT, 368 P_NEPTUNE_MARAMBA_P0, 369 P_NEPTUNE_MARAMBA_P1, 370 P_NEPTUNE_ALONSO, 371 P_NEPTUNE_NIU 372 } platform_type_t; 373 374 #define NXGE_IS_VALID_NEPTUNE_TYPE(nxgep) \ 375 (((nxgep->platform_type) == P_NEPTUNE_ATLAS_2PORT) || \ 376 ((nxgep->platform_type) == P_NEPTUNE_ATLAS_4PORT) || \ 377 ((nxgep->platform_type) == P_NEPTUNE_MARAMBA_P0) || \ 378 ((nxgep->platform_type) == P_NEPTUNE_MARAMBA_P1) || \ 379 ((nxgep->platform_type) == P_NEPTUNE_GENERIC) || \ 380 ((nxgep->platform_type) == P_NEPTUNE_ALONSO)) 381 382 #define NXGE_IS_XAUI_PLATFORM(nxgep) \ 383 (((nxgep->platform_type) == P_NEPTUNE_NIU) || \ 384 ((nxgep->platform_type) == P_NEPTUNE_MARAMBA_P0) || \ 385 ((nxgep->platform_type) == P_NEPTUNE_MARAMBA_P1)) 386 387 388 typedef enum { 389 CFG_DEFAULT = 0, /* default cfg */ 390 CFG_EQUAL, /* Equal */ 391 CFG_FAIR, /* Equal */ 392 CFG_CLASSIFY, 393 CFG_L2_CLASSIFY, 394 CFG_L3_CLASSIFY, 395 CFG_L3_DISTRIBUTE, 396 CFG_L3_WEB, 397 CFG_L3_TCAM, 398 CFG_NOT_SPECIFIED, 399 CFG_CUSTOM /* Custom */ 400 } cfg_type_t; 401 402 typedef enum { 403 NO_MSG = 0x0, /* No message output or storage. */ 404 CONSOLE = 0x1, /* Messages are go to the console. */ 405 BUFFER = 0x2, /* Messages are go to the system buffer. */ 406 CON_BUF = 0x3, /* Messages are go to the console and */ 407 /* system buffer. */ 408 VERBOSE = 0x4 /* Messages are go out only in VERBOSE node. */ 409 } out_msg_t, *p_out_msg_t; 410 411 typedef enum { 412 DBG_NO_MSG = 0x0, /* No message output or storage. */ 413 DBG_CONSOLE = 0x1, /* Messages are go to the console. */ 414 DBG_BUFFER = 0x2, /* Messages are go to the system buffer. */ 415 DBG_CON_BUF = 0x3, /* Messages are go to the console and */ 416 /* system buffer. */ 417 STR_LOG = 4 /* Sessage sent to streams logging driver. */ 418 } out_dbgmsg_t, *p_out_dbgmsg_t; 419 420 typedef enum { 421 DDI_MEM_ALLOC, /* default (use ddi_dma_mem_alloc) */ 422 KMEM_ALLOC, /* use kmem_alloc(). */ 423 CONTIG_MEM_ALLOC /* use contig_mem_alloc() (N2/NIU only) */ 424 } buf_alloc_type_t; 425 426 #define BUF_ALLOCATED 0x00000001 427 #define BUF_ALLOCATED_WAIT_FREE 0x00000002 428 429 #if defined(_KERNEL) || defined(COSIM) 430 431 typedef struct ether_addr ether_addr_st, *p_ether_addr_t; 432 typedef struct ether_header ether_header_t, *p_ether_header_t; 433 typedef queue_t *p_queue_t; 434 435 #if !defined(IODIAG) 436 typedef mblk_t *p_mblk_t; 437 #endif 438 439 /* 440 * Generic phy table to support different phy types. 441 */ 442 typedef struct _nxge_xcvr_table { 443 nxge_status_t (*serdes_init) (); /* Serdes init routine */ 444 nxge_status_t (*xcvr_init) (); /* xcvr init routine */ 445 nxge_status_t (*link_intr_stop) (); /* Link intr disable routine */ 446 nxge_status_t (*link_intr_start) (); /* Link intr enable routine */ 447 nxge_status_t (*check_link) (); /* Link check routine */ 448 449 uint32_t xcvr_inuse; 450 } nxge_xcvr_table_t, *p_nxge_xcvr_table_t; 451 452 /* 453 * Common DMA data elements. 454 */ 455 typedef struct _nxge_dma_pool_t nxge_dma_pool_t, *p_nxge_dma_pool_t; 456 457 struct _nxge_dma_common_t { 458 uint16_t dma_channel; 459 void *kaddrp; 460 void *first_kaddrp; 461 void *last_kaddrp; 462 void *ioaddr_pp; 463 void *first_ioaddr_pp; 464 void *last_ioaddr_pp; 465 ddi_dma_cookie_t dma_cookie; 466 uint32_t ncookies; 467 468 nxge_block_mv_t msg_dma_flags; 469 ddi_dma_handle_t dma_handle; 470 nxge_os_acc_handle_t acc_handle; 471 npi_handle_t npi_handle; 472 473 size_t block_size; 474 uint32_t nblocks; 475 size_t alength; 476 uint_t offset; 477 uint_t dma_chunk_index; 478 void *orig_ioaddr_pp; 479 uint64_t orig_vatopa; 480 void *orig_kaddrp; 481 size_t orig_alength; 482 boolean_t contig_alloc_type; 483 /* 484 * Receive buffers may be allocated using 485 * kmem_alloc(). The buffer free function 486 * depends on its allocation function. 487 */ 488 boolean_t kmem_alloc_type; 489 uint32_t buf_alloc_state; 490 buf_alloc_type_t buf_alloc_type; 491 p_nxge_dma_pool_t rx_buf_pool_p; 492 }; 493 494 typedef struct _nxge_t nxge_t, *p_nxge_t; 495 typedef struct _nxge_dma_common_t nxge_dma_common_t, *p_nxge_dma_common_t; 496 497 struct _nxge_dma_pool_t { 498 p_nxge_dma_common_t *dma_buf_pool_p; 499 uint32_t ndmas; 500 uint32_t *num_chunks; 501 boolean_t buf_allocated; 502 }; 503 504 /* 505 * Each logical device (69): 506 * - LDG # 507 * - flag bits 508 * - masks. 509 * - interrupt handler function. 510 * 511 * Generic system interrupt handler with two arguments: 512 * (nxge_sys_intr_t) 513 * Per device instance data structure 514 * Logical group data structure. 515 * 516 * Logical device interrupt handler with two arguments: 517 * (nxge_ldv_intr_t) 518 * Per device instance data structure 519 * Logical device number 520 */ 521 typedef struct _nxge_ldg_t nxge_ldg_t, *p_nxge_ldg_t; 522 typedef struct _nxge_ldv_t nxge_ldv_t, *p_nxge_ldv_t; 523 typedef uint_t (*nxge_sys_intr_t)(void *arg1, void *arg2); 524 typedef uint_t (*nxge_ldv_intr_t)(void *arg1, void *arg2); 525 526 /* 527 * Each logical device Group (64) needs to have the following 528 * configurations: 529 * - timer counter (6 bits) 530 * - timer resolution (20 bits, number of system clocks) 531 * - system data (7 bits) 532 */ 533 struct _nxge_ldg_t { 534 uint8_t ldg; /* logical group number */ 535 uint8_t vldg_index; 536 boolean_t arm; 537 boolean_t interrupted; 538 uint16_t ldg_timer; /* counter */ 539 uint8_t func; 540 uint8_t vector; 541 uint8_t intdata; 542 uint8_t nldvs; 543 p_nxge_ldv_t ldvp; 544 nxge_sys_intr_t sys_intr_handler; 545 uint_t (*ih_cb_func)(caddr_t, caddr_t); 546 p_nxge_t nxgep; 547 }; 548 549 struct _nxge_ldv_t { 550 uint8_t ldg_assigned; 551 uint8_t ldv; 552 boolean_t is_rxdma; 553 boolean_t is_txdma; 554 boolean_t is_mif; 555 boolean_t is_mac; 556 boolean_t is_syserr; 557 boolean_t use_timer; 558 uint8_t channel; 559 uint8_t vdma_index; 560 uint8_t func; 561 p_nxge_ldg_t ldgp; 562 uint8_t ldv_flags; 563 boolean_t is_leve; 564 boolean_t is_edge; 565 uint8_t ldv_ldf_masks; 566 nxge_ldv_intr_t ldv_intr_handler; 567 uint_t (*ih_cb_func)(caddr_t, caddr_t); 568 p_nxge_t nxgep; 569 }; 570 #endif 571 572 typedef struct _nxge_logical_page_t { 573 uint16_t dma; 574 uint16_t page; 575 boolean_t valid; 576 uint64_t mask; 577 uint64_t value; 578 uint64_t reloc; 579 uint32_t handle; 580 } nxge_logical_page_t, *p_nxge_logical_page_t; 581 582 /* 583 * (Internal) return values from ioctl subroutines. 584 */ 585 enum nxge_ioc_reply { 586 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 587 IOC_DONE, /* OK, reply sent */ 588 IOC_ACK, /* OK, just send ACK */ 589 IOC_REPLY, /* OK, just send reply */ 590 IOC_RESTART_ACK, /* OK, restart & ACK */ 591 IOC_RESTART_REPLY /* OK, restart & reply */ 592 }; 593 594 typedef struct _pci_cfg_t { 595 uint16_t vendorid; 596 uint16_t devid; 597 uint16_t command; 598 uint16_t status; 599 uint8_t revid; 600 uint8_t res0; 601 uint16_t junk1; 602 uint8_t cache_line; 603 uint8_t latency; 604 uint8_t header; 605 uint8_t bist; 606 uint32_t base; 607 uint32_t base14; 608 uint32_t base18; 609 uint32_t base1c; 610 uint32_t base20; 611 uint32_t base24; 612 uint32_t base28; 613 uint32_t base2c; 614 uint32_t base30; 615 uint32_t res1[2]; 616 uint8_t int_line; 617 uint8_t int_pin; 618 uint8_t min_gnt; 619 uint8_t max_lat; 620 } pci_cfg_t, *p_pci_cfg_t; 621 622 #if defined(_KERNEL) || defined(COSIM) 623 624 typedef struct _dev_regs_t { 625 nxge_os_acc_handle_t nxge_pciregh; /* PCI config DDI IO handle */ 626 p_pci_cfg_t nxge_pciregp; /* mapped PCI registers */ 627 628 nxge_os_acc_handle_t nxge_regh; /* device DDI IO (BAR 0) */ 629 void *nxge_regp; /* mapped device registers */ 630 631 nxge_os_acc_handle_t nxge_msix_regh; /* MSI/X DDI handle (BAR 2) */ 632 void *nxge_msix_regp; /* MSI/X register */ 633 634 nxge_os_acc_handle_t nxge_vir_regh; /* virtualization (BAR 4) */ 635 unsigned char *nxge_vir_regp; /* virtualization register */ 636 637 nxge_os_acc_handle_t nxge_vir2_regh; /* second virtualization */ 638 unsigned char *nxge_vir2_regp; /* second virtualization */ 639 640 nxge_os_acc_handle_t nxge_romh; /* fcode rom handle */ 641 unsigned char *nxge_romp; /* fcode pointer */ 642 } dev_regs_t, *p_dev_regs_t; 643 644 645 typedef struct _nxge_mac_addr_t { 646 ether_addr_t addr; 647 uint_t flags; 648 } nxge_mac_addr_t; 649 650 /* 651 * The hardware supports 1 unique MAC and 16 alternate MACs (num_mmac) 652 * for each XMAC port and supports 1 unique MAC and 7 alternate MACs 653 * for each BMAC port. The number of MACs assigned by the factory is 654 * different and is as follows, 655 * BMAC port: num_factory_mmac = num_mmac = 7 656 * XMAC port on a 2-port NIC: num_factory_mmac = num_mmac - 1 = 15 657 * XMAC port on a 4-port NIC: num_factory_mmac = 7 658 * So num_factory_mmac is smaller than num_mmac. nxge_m_mmac_add uses 659 * num_mmac and nxge_m_mmac_reserve uses num_factory_mmac. 660 * 661 * total_factory_macs is the total number of factory MACs, including 662 * the unique MAC, assigned to a Neptune based NIC card, it is 32. 663 */ 664 typedef struct _nxge_mmac_t { 665 uint8_t total_factory_macs; 666 uint8_t num_mmac; 667 uint8_t num_factory_mmac; 668 nxge_mac_addr_t mac_pool[XMAC_MAX_ADDR_ENTRY]; 669 ether_addr_t factory_mac_pool[XMAC_MAX_ADDR_ENTRY]; 670 uint8_t naddrfree; /* number of alt mac addr available */ 671 } nxge_mmac_t; 672 673 /* 674 * mmac stats structure 675 */ 676 typedef struct _nxge_mmac_stats_t { 677 uint8_t mmac_max_cnt; 678 uint8_t mmac_avail_cnt; 679 struct ether_addr mmac_avail_pool[16]; 680 } nxge_mmac_stats_t, *p_nxge_mmac_stats_t; 681 682 #define NXGE_MAX_MMAC_ADDRS 32 683 #define NXGE_NUM_MMAC_ADDRS 8 684 #define NXGE_NUM_OF_PORTS_QUAD 4 685 #define NXGE_NUM_OF_PORTS_DUAL 2 686 687 #define NXGE_QGC_LP_BM_STR "501-7606" 688 #define NXGE_2XGF_LP_BM_STR "501-7283" 689 #define NXGE_QGC_PEM_BM_STR "501-7765" 690 #define NXGE_2XGF_PEM_BM_STR "501-7626" 691 #define NXGE_ALONSO_BM_STR "373-0202-01" 692 #define NXGE_ALONSO_MODEL_STR "SUNW,CP3220" 693 #define NXGE_RFEM_BM_STR "501-7961-01" 694 #define NXGE_RFEM_MODEL_STR "SUNW,pcie-rfem" 695 #define NXGE_ARTM_BM_STR "375-3544-01" 696 #define NXGE_ARTM_MODEL_STR "SUNW,pcie-artm" 697 #define NXGE_EROM_LEN 1048576 698 699 #endif 700 701 #include <sys/nxge/nxge_common_impl.h> 702 #include <sys/nxge/nxge_common.h> 703 #include <sys/nxge/nxge_txc.h> 704 #include <sys/nxge/nxge_rxdma.h> 705 #include <sys/nxge/nxge_txdma.h> 706 #include <sys/nxge/nxge_fflp.h> 707 #include <sys/nxge/nxge_ipp.h> 708 #include <sys/nxge/nxge_zcp.h> 709 #include <sys/nxge/nxge_fzc.h> 710 #include <sys/nxge/nxge_flow.h> 711 #include <sys/nxge/nxge_virtual.h> 712 713 #include <npi_espc.h> 714 #include <npi_vir.h> 715 716 #include <sys/nxge/nxge.h> 717 718 #include <sys/modctl.h> 719 #include <sys/pattr.h> 720 721 extern int secpolicy_net_config(const cred_t *, boolean_t); 722 extern void nxge_fm_report_error(p_nxge_t, uint8_t, 723 uint8_t, nxge_fm_ereport_id_t); 724 extern int fm_check_acc_handle(ddi_acc_handle_t); 725 extern int fm_check_dma_handle(ddi_dma_handle_t); 726 727 /* nxge_classify.c */ 728 nxge_status_t nxge_classify_init(p_nxge_t); 729 nxge_status_t nxge_classify_uninit(p_nxge_t); 730 nxge_status_t nxge_set_hw_classify_config(p_nxge_t); 731 nxge_status_t nxge_classify_exit_sw(p_nxge_t); 732 733 /* nxge_fflp.c */ 734 void nxge_put_tcam(p_nxge_t, p_mblk_t); 735 void nxge_get_tcam(p_nxge_t, p_mblk_t); 736 nxge_status_t nxge_classify_init_hw(p_nxge_t); 737 nxge_status_t nxge_classify_init_sw(p_nxge_t); 738 nxge_status_t nxge_fflp_ip_class_config_all(p_nxge_t); 739 nxge_status_t nxge_fflp_ip_class_config(p_nxge_t, tcam_class_t, 740 uint32_t); 741 742 nxge_status_t nxge_fflp_ip_class_config_get(p_nxge_t, 743 tcam_class_t, 744 uint32_t *); 745 746 nxge_status_t nxge_cfg_ip_cls_flow_key(p_nxge_t, tcam_class_t, 747 uint32_t); 748 749 nxge_status_t nxge_fflp_ip_usr_class_config(p_nxge_t, tcam_class_t, 750 uint32_t); 751 752 uint64_t nxge_classify_get_cfg_value(p_nxge_t, uint8_t, uint8_t); 753 nxge_status_t nxge_add_flow(p_nxge_t, flow_resource_t *); 754 nxge_status_t nxge_fflp_config_tcam_enable(p_nxge_t); 755 nxge_status_t nxge_fflp_config_tcam_disable(p_nxge_t); 756 757 nxge_status_t nxge_fflp_config_hash_lookup_enable(p_nxge_t); 758 nxge_status_t nxge_fflp_config_hash_lookup_disable(p_nxge_t); 759 760 nxge_status_t nxge_fflp_config_llc_snap_enable(p_nxge_t); 761 nxge_status_t nxge_fflp_config_llc_snap_disable(p_nxge_t); 762 763 nxge_status_t nxge_logical_mac_assign_rdc_table(p_nxge_t, uint8_t); 764 nxge_status_t nxge_fflp_config_vlan_table(p_nxge_t, uint16_t); 765 766 nxge_status_t nxge_fflp_set_hash1(p_nxge_t, uint32_t); 767 768 nxge_status_t nxge_fflp_set_hash2(p_nxge_t, uint16_t); 769 770 nxge_status_t nxge_fflp_init_hostinfo(p_nxge_t); 771 772 void nxge_handle_tcam_fragment_bug(p_nxge_t); 773 nxge_status_t nxge_fflp_hw_reset(p_nxge_t); 774 nxge_status_t nxge_fflp_handle_sys_errors(p_nxge_t); 775 nxge_status_t nxge_zcp_handle_sys_errors(p_nxge_t); 776 777 /* nxge_kstats.c */ 778 void nxge_init_statsp(p_nxge_t); 779 void nxge_setup_kstats(p_nxge_t); 780 void nxge_setup_rdc_kstats(p_nxge_t, int); 781 void nxge_setup_tdc_kstats(p_nxge_t, int); 782 void nxge_destroy_kstats(p_nxge_t); 783 int nxge_port_kstat_update(kstat_t *, int); 784 void nxge_save_cntrs(p_nxge_t); 785 786 int nxge_m_stat(void *arg, uint_t, uint64_t *); 787 788 /* nxge_hw.c */ 789 void 790 nxge_hw_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *); 791 void nxge_loopback_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *); 792 nxge_status_t nxge_global_reset(p_nxge_t); 793 uint_t nxge_intr(void *, void *); 794 void nxge_intr_enable(p_nxge_t); 795 void nxge_intr_disable(p_nxge_t); 796 void nxge_hw_blank(void *arg, time_t, uint_t); 797 void nxge_hw_id_init(p_nxge_t); 798 void nxge_hw_init_niu_common(p_nxge_t); 799 void nxge_intr_hw_enable(p_nxge_t); 800 void nxge_intr_hw_disable(p_nxge_t); 801 void nxge_hw_stop(p_nxge_t); 802 void nxge_check_hw_state(p_nxge_t); 803 804 void nxge_rxdma_channel_put64(nxge_os_acc_handle_t, 805 void *, uint32_t, uint16_t, 806 uint64_t); 807 uint64_t nxge_rxdma_channel_get64(nxge_os_acc_handle_t, void *, 808 uint32_t, uint16_t); 809 810 811 void nxge_get32(p_nxge_t, p_mblk_t); 812 void nxge_put32(p_nxge_t, p_mblk_t); 813 814 void nxge_hw_set_mac_modes(p_nxge_t); 815 816 /* nxge_send.c. */ 817 uint_t nxge_reschedule(caddr_t); 818 819 /* nxge_rxdma.c */ 820 nxge_status_t nxge_rxdma_cfg_rdcgrp_default_rdc(p_nxge_t, 821 uint8_t, uint8_t); 822 823 nxge_status_t nxge_rxdma_cfg_port_default_rdc(p_nxge_t, 824 uint8_t, uint8_t); 825 nxge_status_t nxge_rxdma_cfg_rcr_threshold(p_nxge_t, uint8_t, 826 uint16_t); 827 nxge_status_t nxge_rxdma_cfg_rcr_timeout(p_nxge_t, uint8_t, 828 uint16_t, uint8_t); 829 830 /* nxge_ndd.c */ 831 void nxge_get_param_soft_properties(p_nxge_t); 832 void nxge_copy_hw_default_to_param(p_nxge_t); 833 void nxge_copy_param_hw_to_config(p_nxge_t); 834 void nxge_setup_param(p_nxge_t); 835 void nxge_init_param(p_nxge_t); 836 void nxge_destroy_param(p_nxge_t); 837 boolean_t nxge_check_rxdma_rdcgrp_member(p_nxge_t, uint8_t, uint8_t); 838 boolean_t nxge_check_rxdma_port_member(p_nxge_t, uint8_t); 839 boolean_t nxge_check_rdcgrp_port_member(p_nxge_t, uint8_t); 840 841 boolean_t nxge_check_txdma_port_member(p_nxge_t, uint8_t); 842 843 int nxge_param_get_generic(p_nxge_t, queue_t *, mblk_t *, caddr_t); 844 int nxge_param_set_generic(p_nxge_t, queue_t *, mblk_t *, char *, caddr_t); 845 int nxge_get_default(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 846 int nxge_set_default(p_nxge_t, queue_t *, p_mblk_t, char *, caddr_t); 847 int nxge_nd_get_names(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 848 int nxge_mk_mblk_tail_space(p_mblk_t, p_mblk_t *, size_t); 849 long nxge_strtol(char *, char **, int); 850 boolean_t nxge_param_get_instance(queue_t *, mblk_t *); 851 void nxge_param_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *); 852 boolean_t nxge_nd_load(caddr_t *, char *, pfi_t, pfi_t, caddr_t); 853 void nxge_nd_free(caddr_t *); 854 int nxge_nd_getset(p_nxge_t, queue_t *, caddr_t, p_mblk_t); 855 856 nxge_status_t nxge_set_lb_normal(p_nxge_t); 857 boolean_t nxge_set_lb(p_nxge_t, queue_t *, p_mblk_t); 858 boolean_t nxge_param_link_update(p_nxge_t); 859 int nxge_param_set_ip_opt(p_nxge_t, queue_t *, mblk_t *, char *, caddr_t); 860 int nxge_dld_get_ip_opt(p_nxge_t, caddr_t); 861 int nxge_param_rx_intr_pkts(p_nxge_t, queue_t *, 862 mblk_t *, char *, caddr_t); 863 int nxge_param_rx_intr_time(p_nxge_t, queue_t *, 864 mblk_t *, char *, caddr_t); 865 866 867 /* nxge_virtual.c */ 868 nxge_status_t nxge_cntlops(dev_info_t *, nxge_ctl_enum_t, void *, void *); 869 void nxge_common_lock_get(p_nxge_t); 870 void nxge_common_lock_free(p_nxge_t); 871 872 nxge_status_t nxge_get_config_properties(p_nxge_t); 873 void nxge_get_xcvr_properties(p_nxge_t); 874 void nxge_init_vlan_config(p_nxge_t); 875 void nxge_init_mac_config(p_nxge_t); 876 877 878 void nxge_init_logical_devs(p_nxge_t); 879 int nxge_init_ldg_intrs(p_nxge_t); 880 881 void nxge_set_ldgimgmt(p_nxge_t, uint32_t, boolean_t, 882 uint32_t); 883 884 void nxge_init_fzc_txdma_channels(p_nxge_t); 885 886 nxge_status_t nxge_init_fzc_txdma_channel(p_nxge_t, uint16_t, 887 p_tx_ring_t, p_tx_mbox_t); 888 nxge_status_t nxge_init_fzc_txdma_port(p_nxge_t); 889 890 nxge_status_t nxge_init_fzc_rxdma_channel(p_nxge_t, uint16_t); 891 892 nxge_status_t nxge_init_fzc_rx_common(p_nxge_t); 893 nxge_status_t nxge_init_fzc_rxdma_port(p_nxge_t); 894 895 nxge_status_t nxge_init_fzc_rxdma_channel_pages(p_nxge_t, 896 uint16_t, p_rx_rbr_ring_t); 897 nxge_status_t nxge_init_fzc_rxdma_channel_red(p_nxge_t, 898 uint16_t, p_rx_rcr_ring_t); 899 900 nxge_status_t nxge_init_fzc_rxdma_channel_clrlog(p_nxge_t, 901 uint16_t, p_rx_rbr_ring_t); 902 903 904 nxge_status_t nxge_init_fzc_txdma_channel_pages(p_nxge_t, 905 uint16_t, p_tx_ring_t); 906 907 nxge_status_t nxge_init_fzc_txdma_channel_drr(p_nxge_t, uint16_t, 908 p_tx_ring_t); 909 910 nxge_status_t nxge_init_fzc_txdma_port(p_nxge_t); 911 912 void nxge_init_fzc_ldg_num(p_nxge_t); 913 void nxge_init_fzc_sys_int_data(p_nxge_t); 914 void nxge_init_fzc_ldg_int_timer(p_nxge_t); 915 nxge_status_t nxge_intr_mask_mgmt_set(p_nxge_t, boolean_t on); 916 917 /* MAC functions */ 918 nxge_status_t nxge_mac_init(p_nxge_t); 919 nxge_status_t nxge_link_init(p_nxge_t); 920 nxge_status_t nxge_xif_init(p_nxge_t); 921 nxge_status_t nxge_pcs_init(p_nxge_t); 922 nxge_status_t nxge_mac_ctrl_init(p_nxge_t); 923 nxge_status_t nxge_serdes_init(p_nxge_t); 924 nxge_status_t nxge_serdes_reset(p_nxge_t); 925 nxge_status_t nxge_xcvr_find(p_nxge_t); 926 nxge_status_t nxge_get_xcvr_type(p_nxge_t); 927 nxge_status_t nxge_setup_xcvr_table(p_nxge_t); 928 nxge_status_t nxge_xcvr_init(p_nxge_t); 929 nxge_status_t nxge_tx_mac_init(p_nxge_t); 930 nxge_status_t nxge_rx_mac_init(p_nxge_t); 931 nxge_status_t nxge_tx_mac_enable(p_nxge_t); 932 nxge_status_t nxge_tx_mac_disable(p_nxge_t); 933 nxge_status_t nxge_rx_mac_enable(p_nxge_t); 934 nxge_status_t nxge_rx_mac_disable(p_nxge_t); 935 nxge_status_t nxge_tx_mac_reset(p_nxge_t); 936 nxge_status_t nxge_rx_mac_reset(p_nxge_t); 937 nxge_status_t nxge_link_intr(p_nxge_t, link_intr_enable_t); 938 nxge_status_t nxge_mii_xcvr_init(p_nxge_t); 939 nxge_status_t nxge_mii_xcvr_fiber_init(p_nxge_t); 940 nxge_status_t nxge_mii_read(p_nxge_t, uint8_t, 941 uint8_t, uint16_t *); 942 nxge_status_t nxge_mii_write(p_nxge_t, uint8_t, 943 uint8_t, uint16_t); 944 nxge_status_t nxge_mdio_read(p_nxge_t, uint8_t, uint8_t, 945 uint16_t, uint16_t *); 946 nxge_status_t nxge_mdio_write(p_nxge_t, uint8_t, 947 uint8_t, uint16_t, uint16_t); 948 nxge_status_t nxge_mii_check(p_nxge_t, mii_bmsr_t, 949 mii_bmsr_t, nxge_link_state_t *); 950 nxge_status_t nxge_pcs_check(p_nxge_t, uint8_t portn, nxge_link_state_t *); 951 nxge_status_t nxge_add_mcast_addr(p_nxge_t, struct ether_addr *); 952 nxge_status_t nxge_del_mcast_addr(p_nxge_t, struct ether_addr *); 953 nxge_status_t nxge_set_mac_addr(p_nxge_t, struct ether_addr *); 954 nxge_status_t nxge_check_bcm8704_link(p_nxge_t, boolean_t *); 955 void nxge_link_is_down(p_nxge_t); 956 void nxge_link_is_up(p_nxge_t); 957 nxge_status_t nxge_link_monitor(p_nxge_t, link_mon_enable_t); 958 uint32_t crc32_mchash(p_ether_addr_t); 959 nxge_status_t nxge_set_promisc(p_nxge_t, boolean_t); 960 nxge_status_t nxge_mac_handle_sys_errors(p_nxge_t); 961 nxge_status_t nxge_10g_link_led_on(p_nxge_t); 962 nxge_status_t nxge_10g_link_led_off(p_nxge_t); 963 nxge_status_t nxge_scan_ports_phy(p_nxge_t, p_nxge_hw_list_t); 964 boolean_t nxge_is_valid_local_mac(ether_addr_st); 965 nxge_status_t nxge_mac_set_framesize(p_nxge_t); 966 967 /* espc (sprom) prototypes */ 968 nxge_status_t nxge_espc_mac_addrs_get(p_nxge_t); 969 nxge_status_t nxge_espc_num_macs_get(p_nxge_t, uint8_t *); 970 nxge_status_t nxge_espc_num_ports_get(p_nxge_t); 971 nxge_status_t nxge_espc_phy_type_get(p_nxge_t); 972 nxge_status_t nxge_espc_verify_chksum(p_nxge_t); 973 void nxge_espc_get_next_mac_addr(uint8_t *, uint8_t, struct ether_addr *); 974 void nxge_vpd_info_get(p_nxge_t); 975 976 977 void nxge_debug_msg(p_nxge_t, uint64_t, char *, ...); 978 int nxge_get_nports(p_nxge_t); 979 980 void nxge_free_buf(buf_alloc_type_t, uint64_t, uint32_t); 981 982 uint64_t hv_niu_rx_logical_page_conf(uint64_t, uint64_t, 983 uint64_t, uint64_t); 984 #pragma weak hv_niu_rx_logical_page_conf 985 986 uint64_t hv_niu_rx_logical_page_info(uint64_t, uint64_t, 987 uint64_t *, uint64_t *); 988 #pragma weak hv_niu_rx_logical_page_info 989 990 uint64_t hv_niu_tx_logical_page_conf(uint64_t, uint64_t, 991 uint64_t, uint64_t); 992 #pragma weak hv_niu_tx_logical_page_conf 993 994 uint64_t hv_niu_tx_logical_page_info(uint64_t, uint64_t, 995 uint64_t *, uint64_t *); 996 #pragma weak hv_niu_tx_logical_page_info 997 998 uint64_t hv_niu_vr_assign(uint64_t vridx, uint64_t ldc_id, uint32_t *cookie); 999 #pragma weak hv_niu_vr_assign 1000 1001 uint64_t hv_niu_vr_unassign(uint32_t cookie); 1002 #pragma weak hv_niu_vr_unassign 1003 1004 uint64_t hv_niu_vr_getinfo(uint32_t cookie, uint64_t *real_start, 1005 uint64_t *size); 1006 #pragma weak hv_niu_vr_getinfo 1007 1008 uint64_t hv_niu_vr_get_rxmap(uint32_t cookie, uint64_t *dma_map); 1009 #pragma weak hv_niu_vr_get_rxmap 1010 1011 uint64_t hv_niu_vr_get_txmap(uint32_t cookie, uint64_t *dma_map); 1012 #pragma weak hv_niu_vr_get_txmap 1013 1014 uint64_t hv_niu_rx_dma_assign(uint32_t cookie, uint64_t chidx, 1015 uint64_t *vchidx); 1016 #pragma weak hv_niu_rx_dma_assign 1017 1018 uint64_t hv_niu_rx_dma_unassign(uint32_t cookie, uint64_t chidx); 1019 #pragma weak hv_niu_rx_dma_unassign 1020 1021 uint64_t hv_niu_tx_dma_assign(uint32_t cookie, uint64_t chidx, 1022 uint64_t *vchidx); 1023 #pragma weak hv_niu_tx_dma_assign 1024 1025 uint64_t hv_niu_tx_dma_unassign(uint32_t cookie, uint64_t chidx); 1026 #pragma weak hv_niu_tx_dma_unassign 1027 1028 uint64_t hv_niu_vrrx_logical_page_conf(uint32_t cookie, uint64_t chidx, 1029 uint64_t pgidx, uint64_t raddr, uint64_t size); 1030 #pragma weak hv_niu_vrrx_logical_page_conf 1031 1032 uint64_t hv_niu_vrrx_logical_page_info(uint32_t cookie, uint64_t chidx, 1033 uint64_t pgidx, uint64_t *raddr, uint64_t *size); 1034 #pragma weak hv_niu_vrrx_logical_page_info 1035 1036 uint64_t hv_niu_vrtx_logical_page_conf(uint32_t cookie, uint64_t chidx, 1037 uint64_t pgidx, uint64_t raddr, uint64_t size); 1038 #pragma weak hv_niu_vrtx_logical_page_conf 1039 1040 uint64_t hv_niu_vrtx_logical_page_info(uint32_t cookie, uint64_t chidx, 1041 uint64_t pgidx, uint64_t *raddr, uint64_t *size); 1042 #pragma weak hv_niu_vrtx_logical_page_info 1043 1044 // 1045 // NIU-specific interrupt API 1046 // 1047 uint64_t hv_niu_vrrx_getinfo(uint32_t cookie, uint64_t v_chidx, 1048 uint64_t *group, uint64_t *logdev); 1049 #pragma weak hv_niu_vrrx_getinfo 1050 1051 uint64_t hv_niu_vrtx_getinfo(uint32_t cookie, uint64_t v_chidx, 1052 uint64_t *group, uint64_t *logdev); 1053 #pragma weak hv_niu_vrtx_getinfo 1054 1055 uint64_t hv_niu_vrrx_to_logical_dev(uint32_t cookie, uint64_t v_chidx, 1056 uint64_t *ldn); 1057 #pragma weak hv_niu_vrrx_to_logical_dev 1058 1059 uint64_t hv_niu_vrtx_to_logical_dev(uint32_t cookie, uint64_t v_chidx, 1060 uint64_t *ldn); 1061 #pragma weak hv_niu_vrtx_to_logical_dev 1062 1063 #ifdef NXGE_DEBUG 1064 char *nxge_dump_packet(char *, int); 1065 #endif 1066 1067 #endif /* !_ASM */ 1068 1069 #ifdef __cplusplus 1070 } 1071 #endif 1072 1073 #endif /* _SYS_NXGE_NXGE_IMPL_H */ 1074