1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_DEFS_H 27 #define _SYS_NXGE_NXGE_DEFS_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * Block Address Assignment (24-bit base address) 37 * (bits [23:20]: block [19]: set to 1 for FZC ) 38 */ 39 #define PIO 0x000000 40 #define FZC_PIO 0x080000 41 #define RESERVED_1 0x100000 42 #define FZC_MAC 0x180000 43 #define RESERVED_2 0x200000 44 #define FZC_IPP 0x280000 45 #define FFLP 0x300000 46 #define FZC_FFLP 0x380000 47 #define PIO_VADDR 0x400000 48 #define RESERVED_3 0x480000 49 #define ZCP 0x500000 50 #define FZC_ZCP 0x580000 51 #define DMC 0x600000 52 #define FZC_DMC 0x680000 53 #define TXC 0x700000 54 #define FZC_TXC 0x780000 55 #define PIO_LDSV 0x800000 56 #define RESERVED_4 0x880000 57 #define PIO_LDGIM 0x900000 58 #define RESERVED_5 0x980000 59 #define PIO_IMASK0 0xa00000 60 #define RESERVED_6 0xa80000 61 #define PIO_IMASK1 0xb00000 62 #define RESERVED_7_START 0xb80000 63 #define RESERVED_7_END 0xc00000 64 #define FZC_PROM 0xc80000 65 #define RESERVED_8 0xd00000 66 #define FZC_PIM 0xd80000 67 #define RESERVED_9_START 0xe00000 68 #define RESERVED_9_END 0xf80000 69 70 /* PIO (0x000000) */ 71 72 73 /* FZC_PIO (0x080000) */ 74 #define LDGITMRES (FZC_PIO + 0x00008) /* timer resolution */ 75 #define SID (FZC_PIO + 0x10200) /* 64 LDG, INT data */ 76 #define LDG_NUM (FZC_PIO + 0x20000) /* 69 LDs */ 77 78 79 80 /* FZC_IPP (0x280000) */ 81 82 83 /* FFLP (0x300000), Header Parser */ 84 85 /* PIO_VADDR (0x400000), PIO Virtaul DMA Address */ 86 /* ?? how to access DMA via PIO_VADDR? */ 87 #define VADDR (PIO_VADDR + 0x00000) /* ?? not for driver */ 88 89 90 /* ZCP (0x500000), Neptune Only */ 91 92 93 /* FZC_ZCP (0x580000), Neptune Only */ 94 95 96 /* DMC (0x600000), register offset (32 DMA channels) */ 97 98 /* Transmit Ring Register Offset (32 Channels) */ 99 #define TX_RNG_CFIG (DMC + 0x40000) 100 #define TX_RING_HDH (DMC + 0x40008) 101 #define TX_RING_HDL (DMC + 0x40010) 102 #define TX_RING_KICK (DMC + 0x40018) 103 /* Transmit Operations (32 Channels) */ 104 #define TX_ENT_MSK (DMC + 0x40020) 105 #define TX_CS (DMC + 0x40028) 106 #define TXDMA_MBH (DMC + 0x40030) 107 #define TXDMA_MBL (DMC + 0x40038) 108 #define TX_DMA_PRE_ST (DMC + 0x40040) 109 #define TX_RNG_ERR_LOGH (DMC + 0x40048) 110 #define TX_RNG_ERR_LOGL (DMC + 0x40050) 111 #if OLD 112 #define SH_TX_RNG_ERR_LOGH (DMC + 0x40058) 113 #define SH_TX_RNG_ERR_LOGL (DMC + 0x40060) 114 #endif 115 116 /* FZC_DMC RED Initial Random Value register offset (global) */ 117 #define RED_RAN_INIT (FZC_DMC + 0x00068) 118 119 #define RX_ADDR_MD (FZC_DMC + 0x00070) 120 121 /* FZC_DMC Ethernet Timeout Countue register offset (global) */ 122 #define EING_TIMEOUT (FZC_DMC + 0x00078) 123 124 /* RDC Table */ 125 #define RDC_TBL (FZC_DMC + 0x10000) /* 256 * 8 */ 126 127 /* FZC_DMC partitioning support register offset (32 channels) */ 128 129 #define TX_LOG_PAGE_VLD (FZC_DMC + 0x40000) 130 #define TX_LOG_MASK1 (FZC_DMC + 0x40008) 131 #define TX_LOG_VAL1 (FZC_DMC + 0x40010) 132 #define TX_LOG_MASK2 (FZC_DMC + 0x40018) 133 #define TX_LOG_VAL2 (FZC_DMC + 0x40020) 134 #define TX_LOG_PAGE_RELO1 (FZC_DMC + 0x40028) 135 #define TX_LOG_PAGE_RELO2 (FZC_DMC + 0x40030) 136 #define TX_LOG_PAGE_HDL (FZC_DMC + 0x40038) 137 138 #define TX_ADDR_MOD (FZC_DMC + 0x41000) /* only one? */ 139 140 141 /* FZC_DMC RED Parameters register offset (32 channels) */ 142 #define RDC_RED_PARA1 (FZC_DMC + 0x30000) 143 #define RDC_RED_PARA2 (FZC_DMC + 0x30008) 144 /* FZC_DMC RED Discard Cound Register offset (32 channels) */ 145 #define RED_DIS_CNT (FZC_DMC + 0x30010) 146 147 #if OLD /* This has been moved to TXC */ 148 /* Transmit Ring Scheduler (per port) */ 149 #define TX_DMA_MAP0 (FZC_DMC + 0x50000) 150 #define TX_DMA_MAP1 (FZC_DMC + 0x50008) 151 #define TX_DMA_MAP2 (FZC_DMC + 0x50010) 152 #define TX_DMA_MAP3 (FZC_DMC + 0x50018) 153 #endif 154 155 /* Transmit Ring Scheduler: DRR Weight (32 Channels) */ 156 #define DRR_WT (FZC_DMC + 0x51000) 157 #if OLD 158 #define TXRNG_USE (FZC_DMC + 0x51008) 159 #endif 160 161 /* TXC (0x700000)?? */ 162 163 164 /* FZC_TXC (0x780000)?? */ 165 166 167 /* 168 * PIO_LDSV (0x800000) 169 * Logical Device State Vector 0, 1, 2. 170 * (69 logical devices, 8192 apart, partitioning control) 171 */ 172 #define LDSV0 (PIO_LDSV + 0x00000) /* RO (64 - 69) */ 173 #define LDSV1 (PIO_LDSV + 0x00008) /* RO (32 - 63) */ 174 #define LDSV2 (PIO_LDSV + 0x00010) /* RO ( 0 - 31) */ 175 176 /* 177 * PIO_LDGIM (0x900000) 178 * Logical Device Group Interrupt Management (64 groups). 179 * (count 64, step 8192) 180 */ 181 #define LDGIMGN (PIO_LDGIMGN + 0x00000) /* RW */ 182 183 /* 184 * PIO_IMASK0 (0xA000000) 185 * 186 * Logical Device Masks 0, 1. 187 * (64 logical devices, 8192 apart, partitioning control) 188 */ 189 #define LD_IM0 (PIO_IMASK0 + 0x00000) /* RW ( 0 - 63) */ 190 191 /* 192 * PIO_IMASK0 (0xB000000) 193 * 194 * Logical Device Masks 0, 1. 195 * (5 logical devices, 8192 apart, partitioning control) 196 */ 197 #define LD_IM1 (PIO_IMASK1 + 0x00000) /* RW (64 - 69) */ 198 199 200 /* DMC/TMC CSR size */ 201 #define DMA_CSR_SIZE 512 202 #define DMA_CSR_MIN_PAGE_SIZE 1024 203 204 /* 205 * Define the Default RBR, RCR 206 */ 207 #define RBR_DEFAULT_MAX_BLKS 4096 /* each entry (16 blockaddr/64B) */ 208 #define RBR_NBLK_PER_LINE 16 /* 16 block addresses per 64 B line */ 209 #define RBR_DEFAULT_MAX_LEN (RBR_DEFAULT_MAX_BLKS) 210 #define RBR_DEFAULT_MIN_LEN 1 211 212 #define SW_OFFSET_NO_OFFSET 0 213 #define SW_OFFSET_64 1 /* 64 bytes */ 214 #define SW_OFFSET_128 2 /* 128 bytes */ 215 #define SW_OFFSET_INVALID 3 216 217 /* 218 * RBR block descriptor is 32 bits (bits [43:12] 219 */ 220 #define RBR_BKADDR_SHIFT 12 221 222 223 #define RCR_DEFAULT_MAX_BLKS 4096 /* each entry (8 blockaddr/64B) */ 224 #define RCR_NBLK_PER_LINE 8 /* 8 block addresses per 64 B line */ 225 #define RCR_DEFAULT_MAX_LEN (RCR_DEFAULT_MAX_BLKS) 226 #define RCR_DEFAULT_MIN_LEN 1 227 228 /* DMA Channels. */ 229 #define NXGE_MAX_DMCS (NXGE_MAX_RDCS + NXGE_MAX_TDCS) 230 #define NXGE_MAX_RDCS 16 231 #define NXGE_MAX_TDCS 24 232 #define NXGE_MAX_TDCS_NIU 16 233 /* 234 * original mapping from Hypervisor 235 */ 236 #ifdef ORIGINAL 237 #define NXGE_N2_RXDMA_START_LDG 0 238 #define NXGE_N2_TXDMA_START_LDG 16 239 #define NXGE_N2_MIF_LDG 32 240 #define NXGE_N2_MAC_0_LDG 33 241 #define NXGE_N2_MAC_1_LDG 34 242 #define NXGE_N2_SYS_ERROR_LDG 35 243 #endif 244 245 #define NXGE_N2_RXDMA_START_LDG 19 246 #define NXGE_N2_TXDMA_START_LDG 27 247 #define NXGE_N2_MIF_LDG 17 248 #define NXGE_N2_MAC_0_LDG 16 249 #define NXGE_N2_MAC_1_LDG 35 250 #define NXGE_N2_SYS_ERROR_LDG 18 251 #define NXGE_N2_LDG_GAP 17 252 253 #define NXGE_MAX_RDC_GRPS 8 254 255 /* 256 * Max. ports per Neptune and NIU 257 */ 258 #define NXGE_MAX_PORTS 4 259 #define NXGE_PORTS_NEPTUNE 4 260 #define NXGE_PORTS_NIU 2 261 262 /* Max. RDC table groups */ 263 #define NXGE_MAX_RDC_GROUPS 8 264 #define NXGE_MAX_RDCS 16 265 #define NXGE_MAX_DMAS 32 266 267 268 #define NXGE_MAX_MACS_XMACS 16 269 #define NXGE_MAX_MACS_BMACS 8 270 #define NXGE_MAX_MACS (NXGE_MAX_PORTS * NXGE_MAX_MACS_XMACS) 271 272 #define NXGE_MAX_VLANS 4096 273 #define VLAN_ETHERTYPE (0x8100) 274 275 276 /* Scaling factor for RBR (receive block ring) */ 277 #define RBR_SCALE_1 0 278 #define RBR_SCALE_2 1 279 #define RBR_SCALE_3 2 280 #define RBR_SCALE_4 3 281 #define RBR_SCALE_5 4 282 #define RBR_SCALE_6 5 283 #define RBR_SCALE_7 6 284 #define RBR_SCALE_8 7 285 286 287 #define MAX_PORTS_PER_NXGE 4 288 #define MAX_MACS 32 289 290 #define TX_GATHER_POINTER_SZ 8 291 #define TX_GP_PER_BLOCK 8 292 #define TX_DEFAULT_MAX_GPS 1024 /* Max. # of gather pointers */ 293 #define TX_DEFAULT_JUMBO_MAX_GPS 4096 /* Max. # of gather pointers */ 294 #define TX_DEFAULT_MAX_LEN (TX_DEFAULT_MAX_GPS/TX_GP_PER_BLOCK) 295 #define TX_DEFAULT_JUMBO_MAX_LEN (TX_DEFAULT_JUMBO_MAX_GPS/TX_GP_PER_BLOCK) 296 297 #define TX_RING_THRESHOLD (TX_DEFAULT_MAX_GPS/4) 298 #define TX_RING_JUMBO_THRESHOLD (TX_DEFAULT_JUMBO_MAX_GPS/4) 299 300 #define TRANSMIT_HEADER_SIZE 16 /* 16 B frame header */ 301 302 #define TX_DESC_SAD_SHIFT 0 303 #define TX_DESC_SAD_MASK 0x00000FFFFFFFFFFFULL /* start address */ 304 #define TX_DESC_TR_LEN_SHIFT 44 305 #define TX_DESC_TR_LEN_MASK 0x00FFF00000000000ULL /* Transfer Length */ 306 #define TX_DESC_NUM_PTR_SHIFT 58 307 #define TX_DESC_NUM_PTR_MASK 0x2C00000000000000ULL /* gather pointers */ 308 #define TX_DESC_MASK_SHIFT 62 309 #define TX_DESC_MASK_MASK 0x4000000000000000ULL /* Mark bit */ 310 #define TX_DESC_SOP_SHIF 63 311 #define TX_DESC_NUM_MASK 0x8000000000000000ULL /* Start of packet */ 312 313 #define TCAM_FLOW_KEY_MAX_CLASS 12 314 #define TCAM_L3_MAX_USER_CLASS 4 315 #define TCAM_NIU_TCAM_MAX_ENTRY 128 316 #define TCAM_NXGE_TCAM_MAX_ENTRY 256 317 318 319 320 /* TCAM entry formats */ 321 #define TCAM_IPV4_5TUPLE_FORMAT 0x00 322 #define TCAM_IPV6_5TUPLE_FORMAT 0x01 323 #define TCAM_ETHERTYPE_FORMAT 0x02 324 325 326 /* TCAM */ 327 #define TCAM_SELECT_IPV6 0x01 328 #define TCAM_LOOKUP 0x04 329 #define TCAM_DISCARD 0x08 330 331 /* FLOW Key */ 332 #define FLOW_L4_1_34_BYTES 0x10 333 #define FLOW_L4_1_78_BYTES 0x11 334 #define FLOW_L4_0_12_BYTES (0x10 << 2) 335 #define FLOW_L4_0_56_BYTES (0x11 << 2) 336 #define FLOW_PROTO_NEXT 0x10 337 #define FLOW_IPDA 0x20 338 #define FLOW_IPSA 0x40 339 #define FLOW_VLAN 0x80 340 #define FLOW_L2DA 0x100 341 #define FLOW_PORT 0x200 342 343 /* TCAM */ 344 #define MAX_EFRAME 11 345 346 #define TCAM_USE_L2RDC_FLOW_LOOKUP 0x00 347 #define TCAM_USE_OFFSET_DONE 0x01 348 #define TCAM_OVERRIDE_L2_FLOW_LOOKUP 0x02 349 #define TCAM_OVERRIDE_L2_USE_OFFSET 0x03 350 351 /* 352 * FCRAM (Hashing): 353 * 1. IPv4 exact match 354 * 2. IPv6 exact match 355 * 3. IPv4 Optimistic match 356 * 4. IPv6 Optimistic match 357 * 358 */ 359 #define FCRAM_IPV4_EXT_MATCH 0x00 360 #define FCRAM_IPV6_EXT_MATCH 0x01 361 #define FCRAM_IPV4_OPTI_MATCH 0x02 362 #define FCRAM_IPV6_OPTI_MATCH 0x03 363 364 365 #define NXGE_HASH_MAX_ENTRY 256 366 367 368 #define MAC_ADDR_LENGTH 6 369 370 /* convert values */ 371 #define NXGE_BASE(x, y) (((y) << (x ## _SHIFT)) & (x ## _MASK)) 372 #define NXGE_VAL(x, y) (((y) & (x ## _MASK)) >> (x ## _SHIFT)) 373 374 /* 375 * Locate the DMA channel start offset (PIO_VADDR) 376 * (DMA virtual address space of the PIO block) 377 */ 378 #define TDMC_PIOVADDR_OFFSET(channel) (2 * DMA_CSR_SIZE * channel) 379 #define RDMC_PIOVADDR_OFFSET(channel) (TDMC_OFFSET(channel) + DMA_CSR_SIZE) 380 381 /* 382 * PIO access using the DMC block directly (DMC) 383 */ 384 #define DMC_OFFSET(channel) (DMA_CSR_SIZE * channel) 385 #define TDMC_OFFSET(channel) (TX_RNG_CFIG + DMA_CSR_SIZE * channel) 386 387 /* 388 * Number of logical pages. 389 */ 390 #define NXGE_MAX_LOGICAL_PAGES 2 391 392 #ifdef SOLARIS 393 #ifndef i386 394 #define _BIT_FIELDS_BIG_ENDIAN _BIT_FIELDS_HTOL 395 #else 396 #define _BIT_FIELDS_LITTLE_ENDIAN _BIT_FIELDS_LTOH 397 #endif 398 #else 399 #define _BIT_FIELDS_LITTLE_ENDIAN _LITTLE_ENDIAN_BITFIELD 400 #endif 401 402 #ifdef COSIM 403 #define MAX_PIO_RETRIES 3200 404 #else 405 #define MAX_PIO_RETRIES 32 406 #endif 407 408 #define IS_PORT_NUM_VALID(portn)\ 409 (portn < 4) 410 411 /* 412 * The following macros expect unsigned input values. 413 */ 414 #define TXDMA_CHANNEL_VALID(cn) (cn < NXGE_MAX_TDCS) 415 #define TXDMA_PAGE_VALID(pn) (pn < NXGE_MAX_LOGICAL_PAGES) 416 #define TXDMA_FUNC_VALID(fn) (fn < MAX_PORTS_PER_NXGE) 417 #define FUNC_VALID(n) (n < MAX_PORTS_PER_NXGE) 418 419 /* 420 * DMA channel binding definitions. 421 */ 422 #define VIR_PAGE_INDEX_MAX 8 423 #define VIR_SUB_REGIONS 2 424 #define VIR_DMA_BIND 1 425 426 #define SUBREGION_VALID(n) (n < VIR_SUB_REGIONS) 427 #define VIR_PAGE_INDEX_VALID(n) (n < VIR_PAGE_INDEX_MAX) 428 #define VRXDMA_CHANNEL_VALID(n) (n < NXGE_MAX_RDCS) 429 430 /* 431 * Logical device definitions. 432 */ 433 #define NXGE_INT_MAX_LD 69 434 #define NXGE_INT_MAX_LDG 64 435 436 #define NXGE_RDMA_LD_START 0 437 #define NXGE_TDMA_LD_START 32 438 #define NXGE_MIF_LD 63 439 #define NXGE_MAC_LD_PORT0 64 440 #define NXGE_MAC_LD_PORT1 65 441 #define NXGE_MAC_LD_PORT2 66 442 #define NXGE_MAC_LD_PORT3 67 443 #define NXGE_SYS_ERROR_LD 68 444 445 #define LDG_VALID(n) (n < NXGE_INT_MAX_LDG) 446 #define LD_VALID(n) (n < NXGE_INT_MAX_LD) 447 #define LD_RXDMA_LD_VALID(n) (n < NXGE_MAX_RDCS) 448 #define LD_TXDMA_LD_VALID(n) (n >= NXGE_MAX_RDCS && \ 449 ((n - NXGE_MAX_RDCS) < NXGE_MAX_TDCS))) 450 #define LD_MAC_VALID(n) (IS_PORT_NUM_VALID(n)) 451 452 #define LD_TIMER_MAX 0x3f 453 #define LD_INTTIMER_VALID(n) (n <= LD_TIMER_MAX) 454 455 /* System Interrupt Data */ 456 #define SID_VECTOR_MAX 0x1f 457 #define SID_VECTOR_VALID(n) (n <= SID_VECTOR_MAX) 458 459 #define NXGE_COMPILE_32 460 461 #ifdef __cplusplus 462 } 463 #endif 464 465 #endif /* _SYS_NXGE_NXGE_DEFS_H */ 466