1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_COMMON_H 27 #define _SYS_NXGE_NXGE_COMMON_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #define NXGE_DMA_START B_TRUE 36 #define NXGE_DMA_STOP B_FALSE 37 38 /* 39 * Default DMA configurations. 40 */ 41 #define NXGE_RDMA_PER_NIU_PORT (NXGE_MAX_RDCS/NXGE_PORTS_NIU) 42 #define NXGE_TDMA_PER_NIU_PORT (NXGE_MAX_TDCS_NIU/NXGE_PORTS_NIU) 43 #define NXGE_RDMA_PER_NEP_PORT (NXGE_MAX_RDCS/NXGE_PORTS_NEPTUNE) 44 #define NXGE_TDMA_PER_NEP_PORT (NXGE_MAX_TDCS/NXGE_PORTS_NEPTUNE) 45 #define NXGE_RDCGRP_PER_NIU_PORT (NXGE_MAX_RDC_GROUPS/NXGE_PORTS_NIU) 46 #define NXGE_RDCGRP_PER_NEP_PORT (NXGE_MAX_RDC_GROUPS/NXGE_PORTS_NEPTUNE) 47 48 #define NXGE_TIMER_RESO 2 49 50 #define NXGE_TIMER_LDG 2 51 52 /* 53 * Receive and Transmit DMA definitions 54 */ 55 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 56 /* 57 * N2/NIU: Maximum descriptors if we need to call 58 * Hypervisor to set up the logical pages 59 * and the driver must use contiguous memory. 60 */ 61 #define NXGE_NIU_MAX_ENTRY (1 << 9) /* 512 */ 62 #define NXGE_NIU_CONTIG_RBR_MAX (NXGE_NIU_MAX_ENTRY) 63 #define NXGE_NIU_CONTIG_RCR_MAX (NXGE_NIU_MAX_ENTRY) 64 #define NXGE_NIU_CONTIG_TX_MAX (NXGE_NIU_MAX_ENTRY) 65 #endif 66 67 #ifdef _DMA_USES_VIRTADDR 68 #ifdef NIU_PA_WORKAROUND 69 #define NXGE_DMA_BLOCK (16 * 64 * 4) 70 #else 71 #define NXGE_DMA_BLOCK 1 72 #endif 73 #else 74 #define NXGE_DMA_BLOCK (64 * 64) 75 #endif 76 77 #define NXGE_RBR_RBB_MIN (128) 78 #define NXGE_RBR_RBB_MAX (64 * 128 -1) 79 80 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 81 #define NXGE_RBR_RBB_DEFAULT 512 82 #define NXGE_RBR_SPARE 0 83 #else 84 #define NXGE_RBR_RBB_DEFAULT (64 * 16) /* x86 hello */ 85 #define NXGE_RBR_SPARE 0 86 #endif 87 88 89 #define NXGE_RCR_MIN (NXGE_RBR_RBB_MIN * 2) 90 91 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 92 #define NXGE_RCR_MAX (NXGE_NIU_CONTIG_RCR_MAX) 93 #define NXGE_RCR_DEFAULT (512) 94 #define NXGE_TX_RING_DEFAULT (512) 95 #else 96 #ifndef NIU_PA_WORKAROUND 97 #define NXGE_RCR_MAX (65355) /* MAX hardware supported */ 98 #if defined(_BIG_ENDIAN) 99 #define NXGE_RCR_DEFAULT (NXGE_RBR_RBB_DEFAULT * 8) 100 #else 101 #ifdef USE_RX_BIG_BUF 102 #define NXGE_RCR_DEFAULT (NXGE_RBR_RBB_DEFAULT * 8) 103 #else 104 #define NXGE_RCR_DEFAULT (NXGE_RBR_RBB_DEFAULT * 4) 105 #endif 106 #endif 107 #define NXGE_TX_RING_DEFAULT (1024) 108 #define NXGE_TX_RING_MAX (64 * 128 - 1) 109 #else 110 #define NXGE_RCR_DEFAULT (512) 111 #define NXGE_TX_RING_DEFAULT (512) 112 #define NXGE_RCR_MAX (1024) 113 #define NXGE_TX_RING_MAX (1024) 114 #endif 115 #endif 116 117 #define NXGE_TX_RECLAIM 32 118 119 /* per receive DMA channel configuration data structure */ 120 typedef struct nxge_rdc_cfg { 121 uint32_t flag; /* 0: not configured, 1: configured */ 122 struct nxge_hw_list *nxge_hw_p; 123 uint32_t partition_id; 124 uint32_t port; /* function number */ 125 uint32_t rx_group_id; 126 127 /* Partitioning, DMC function zero. */ 128 uint32_t rx_log_page_vld_page0; /* TRUE or FALSE */ 129 uint32_t rx_log_page_vld_page1; /* TRUE or FALSE */ 130 uint64_t rx_log_mask1; 131 uint64_t rx_log_value1; 132 uint64_t rx_log_mask2; 133 uint64_t rx_log_value2; 134 uint64_t rx_log_page_relo1; 135 uint64_t rx_log_page_relo2; 136 uint64_t rx_log_page_hdl; 137 138 /* WRED parameters, DMC function zero */ 139 uint32_t red_enable; 140 141 uint32_t thre_syn; 142 uint32_t win_syn; 143 uint32_t threshold; 144 uint32_t win_non_syn; 145 146 /* RXDMA configuration, DMC */ 147 char *rdc_mbaddr_p; /* mailbox address */ 148 uint32_t min_flag; /* TRUE for 18 bytes header */ 149 150 /* Software Reserved Packet Buffer Offset, DMC */ 151 uint32_t sw_offset; 152 153 /* RBR Configuration A */ 154 uint64_t rbr_staddr; /* starting address of RBR */ 155 uint32_t rbr_nblks; /* # of RBR entries */ 156 uint32_t rbr_len; /* # of RBR entries in 64B lines */ 157 158 /* RBR Configuration B */ 159 uint32_t bksize; /* Block size is fixed. */ 160 #define RBR_BKSIZE_4K 0 161 #define RBR_BKSIZE_4K_BYTES (4 * 1024) 162 #define RBR_BKSIZE_8K 1 163 #define RBR_BKSIZE_8K_BYTES (8 * 1024) 164 #define RBR_BKSIZE_16K 2 165 #define RBR_BKSIZE_16K_BYTES (16 * 1024) 166 #define RBR_BKSIZE_32K 3 167 #define RBR_BKSIZE_32K_BYTES (32 * 1024) 168 169 uint32_t bufsz2; 170 #define RBR_BUFSZ2_2K 0 171 #define RBR_BUFSZ2_2K_BYTES (2 * 1024) 172 #define RBR_BUFSZ2_4K 1 173 #define RBR_BUFSZ2_4K_BYTES (4 * 1024) 174 #define RBR_BUFSZ2_8K 2 175 #define RBR_BUFSZ2_8K_BYTES (8 * 1024) 176 #define RBR_BUFSZ2_16K 3 177 #define RBR_BUFSZ2_16K_BYTES (16 * 1024) 178 179 uint32_t bufsz1; 180 #define RBR_BUFSZ1_1K 0 181 #define RBR_BUFSZ1_1K_BYTES 1024 182 #define RBR_BUFSZ1_2K 1 183 #define RBR_BUFSZ1_2K_BYTES (2 * 1024) 184 #define RBR_BUFSZ1_4K 2 185 #define RBR_BUFSZ1_4K_BYTES (4 * 1024) 186 #define RBR_BUFSZ1_8K 3 187 #define RBR_BUFSZ1_8K_BYTES (8 * 1024) 188 189 uint32_t bufsz0; 190 #define RBR_BUFSZ0_256B 0 191 #define RBR_BUFSZ0_256_BYTES 256 192 #define RBR_BUFSZ0_512B 1 193 #define RBR_BUFSZ0_512B_BYTES 512 194 #define RBR_BUFSZ0_1K 2 195 #define RBR_BUFSZ0_1K_BYTES (1024) 196 #define RBR_BUFSZ0_2K 3 197 #define RBR_BUFSZ0_2K_BYTES (2 * 1024) 198 199 /* Receive buffers added by the software */ 200 uint32_t bkadd; /* maximum size is 1 million */ 201 202 /* Receive Completion Ring Configuration A */ 203 uint32_t rcr_len; /* # of 64B blocks, each RCR is 8B */ 204 uint64_t rcr_staddr; 205 206 /* Receive Completion Ring Configuration B */ 207 uint32_t pthres; /* packet threshold */ 208 uint32_t entout; /* enable timeout */ 209 uint32_t timeout; /* timeout value */ 210 211 /* Logical Device Group Number */ 212 uint16_t rx_ldg; 213 uint16_t rx_ld_state_flags; 214 215 /* Receive DMA Channel Event Mask */ 216 uint64_t rx_dma_ent_mask; 217 218 /* 32 bit (set to 1) or 64 bit (set to 0) addressing mode */ 219 uint32_t rx_addr_md; 220 } nxge_rdc_cfg_t, *p_nxge_rdc_cfg_t; 221 222 /* 223 * Per Transmit DMA Channel Configuration Data Structure (32 TDC) 224 */ 225 typedef struct nxge_tdc_cfg { 226 uint32_t flag; /* 0: not configured 1: configured */ 227 struct nxge_hw_list *nxge_hw_p; 228 uint32_t partition_id; 229 uint32_t port; /* function number */ 230 /* partitioning, DMC function zero (All 0s for non-partitioning) */ 231 uint32_t tx_log_page_vld_page0; /* TRUE or FALSE */ 232 uint32_t tx_log_page_vld_page1; /* TRUE or FALSE */ 233 uint64_t tx_log_mask1; 234 uint64_t tx_log_value1; 235 uint64_t tx_log_mask2; 236 uint64_t tx_log_value2; 237 uint64_t tx_log_page_relo1; 238 uint64_t tx_log_page_relo2; 239 uint64_t tx_log_page_hdl; 240 241 /* Transmit Ring Configuration */ 242 uint64_t tx_staddr; 243 uint64_t tx_rng_len; /* in 64 B Blocks */ 244 #define TX_MAX_BUF_SIZE 4096 245 246 /* TXDMA configuration, DMC */ 247 char *tdc_mbaddr_p; /* mailbox address */ 248 249 /* Logical Device Group Number */ 250 uint16_t tx_ldg; 251 uint16_t tx_ld_state_flags; 252 253 /* TXDMA event flags */ 254 uint64_t tx_event_mask; 255 256 /* Transmit threshold before reclamation */ 257 uint32_t tx_rng_threshold; 258 #define TX_RING_THRESHOLD (TX_DEFAULT_MAX_GPS/4) 259 #define TX_RING_JUMBO_THRESHOLD (TX_DEFAULT_JUMBO_MAX_GPS/4) 260 261 /* For reclaim: a wrap-around counter (packets transmitted) */ 262 uint32_t tx_pkt_cnt; 263 /* last packet with the mark bit set */ 264 uint32_t tx_lastmark; 265 } nxge_tdc_cfg_t, *p_nxge_tdc_cfg_t; 266 267 #define RDC_TABLE_ENTRY_METHOD_SEQ 0 268 #define RDC_TABLE_ENTRY_METHOD_REP 1 269 270 /* per receive DMA channel table group data structure */ 271 typedef struct nxge_rdc_grp { 272 uint32_t flag; /* 0:not configured 1: configured */ 273 uint8_t port; 274 uint8_t partition_id; 275 uint8_t rx_group_id; 276 uint8_t start_rdc; /* assume assigned in sequence */ 277 uint8_t max_rdcs; 278 uint8_t def_rdc; 279 uint8_t rdc[NXGE_MAX_RDCS]; 280 uint16_t config_method; 281 } nxge_rdc_grp_t, *p_nxge_rdc_grp_t; 282 283 /* Common RDC and TDC configuration of DMC */ 284 typedef struct _nxge_dma_common_cfg_t { 285 uint16_t rdc_red_ran_init; /* RED initial seed value */ 286 287 /* Transmit Ring */ 288 } nxge_dma_common_cfg_t, *p_nxge_dma_common_cfg_t; 289 290 /* 291 * VLAN and MAC table configurations: 292 * Each VLAN ID should belong to at most one RDC group. 293 * Each port could own multiple RDC groups. 294 * Each MAC should belong to one RDC group. 295 */ 296 typedef struct nxge_mv_cfg { 297 uint8_t flag; /* 0:unconfigure 1:configured */ 298 uint8_t rdctbl; /* RDC channel table group */ 299 uint8_t mpr_npr; /* MAC and VLAN preference */ 300 uint8_t odd_parity; 301 } nxge_mv_cfg_t, *p_nxge_mv_cfg_t; 302 303 typedef struct nxge_param_map { 304 #if defined(_BIG_ENDIAN) 305 uint32_t rsrvd2:2; /* [30:31] rsrvd */ 306 uint32_t remove:1; /* [29] Remove */ 307 uint32_t pref:1; /* [28] preference */ 308 uint32_t rsrv:4; /* [27:24] preference */ 309 uint32_t map_to:8; /* [23:16] map to resource */ 310 uint32_t param_id:16; /* [15:0] Param ID */ 311 #else 312 uint32_t param_id:16; /* [15:0] Param ID */ 313 uint32_t map_to:8; /* [23:16] map to resource */ 314 uint32_t rsrv:4; /* [27:24] preference */ 315 uint32_t pref:1; /* [28] preference */ 316 uint32_t remove:1; /* [29] Remove */ 317 uint32_t rsrvd2:2; /* [30:31] rsrvd */ 318 #endif 319 } nxge_param_map_t, *p_nxge_param_map_t; 320 321 typedef struct nxge_rcr_param { 322 #if defined(_BIG_ENDIAN) 323 uint32_t rsrvd2:2; /* [30:31] rsrvd */ 324 uint32_t remove:1; /* [29] Remove */ 325 uint32_t rsrv:5; /* [28:24] preference */ 326 uint32_t rdc:8; /* [23:16] rdc # */ 327 uint32_t cfg_val:16; /* [15:0] interrupt parameter */ 328 #else 329 uint32_t cfg_val:16; /* [15:0] interrupt parameter */ 330 uint32_t rdc:8; /* [23:16] rdc # */ 331 uint32_t rsrv:5; /* [28:24] preference */ 332 uint32_t remove:1; /* [29] Remove */ 333 uint32_t rsrvd2:2; /* [30:31] rsrvd */ 334 #endif 335 } nxge_rcr_param_t, *p_nxge_rcr_param_t; 336 337 /* Needs to have entries in the ndd table */ 338 /* 339 * Hardware properties created by fcode. 340 * In order for those properties visible to the user 341 * command ndd, we need to add the following properties 342 * to the ndd defined parameter array and data structures. 343 * 344 * Use default static configuration for x86. 345 */ 346 typedef struct nxge_hw_pt_cfg { 347 uint32_t partition_id; /* partition Id */ 348 uint32_t read_write_mode; /* read write permission mode */ 349 uint32_t function_number; /* function number */ 350 uint32_t start_tdc; /* start TDC (0 - 31) */ 351 uint32_t max_tdcs; /* max TDC in sequence */ 352 uint32_t start_rdc; /* start RDC (0 - 31) */ 353 uint32_t max_rdcs; /* max rdc in sequence */ 354 uint32_t ninterrupts; /* obp interrupts(mac/mif/syserr) */ 355 uint32_t mac_ldvid; 356 uint32_t mif_ldvid; 357 uint32_t ser_ldvid; 358 uint32_t def_rdc; /* default RDC */ 359 uint32_t drr_wt; /* port DRR weight */ 360 uint32_t rx_full_header; /* select the header flag */ 361 uint32_t start_grpid; /* starting group ID */ 362 uint32_t max_grpids; /* max group ID */ 363 uint32_t start_rdc_grpid; /* starting RDC group ID */ 364 uint32_t max_rdc_grpids; /* max RDC group ID */ 365 uint32_t start_ldg; /* starting logical group # */ 366 uint32_t max_ldgs; /* max logical device group */ 367 uint32_t max_ldvs; /* max logical devices */ 368 uint32_t start_mac_entry; /* where to put the first mac */ 369 uint32_t max_macs; /* the max mac entry allowed */ 370 uint32_t mac_pref; /* preference over VLAN */ 371 uint32_t def_mac_rxdma_grpid; /* default RDC group ID */ 372 uint32_t start_vlan; /* starting VLAN ID */ 373 uint32_t max_vlans; /* max VLAN ID */ 374 uint32_t vlan_pref; /* preference over MAC */ 375 uint32_t def_vlan_rxdma_grpid; /* default RDC group Id */ 376 377 /* Expand if we have more hardware or default configurations */ 378 uint16_t ldg[NXGE_INT_MAX_LDG]; 379 uint16_t ldg_chn_start; 380 } nxge_hw_pt_cfg_t, *p_nxge_hw_pt_cfg_t; 381 382 383 /* per port configuration */ 384 typedef struct nxge_dma_pt_cfg { 385 uint8_t mac_port; /* MAC port (function) */ 386 nxge_hw_pt_cfg_t hw_config; /* hardware configuration */ 387 388 uint32_t alloc_buf_size; 389 uint32_t rbr_size; 390 uint32_t rcr_size; 391 392 /* 393 * Configuration for hardware initialization based on the 394 * hardware properties or the default properties. 395 */ 396 uint32_t tx_dma_map; /* Transmit DMA channel bit map */ 397 398 /* Receive DMA channel */ 399 nxge_rdc_grp_t rdc_grps[NXGE_MAX_RDC_GROUPS]; 400 401 uint16_t rcr_timeout[NXGE_MAX_RDCS]; 402 uint16_t rcr_threshold[NXGE_MAX_RDCS]; 403 uint8_t rcr_full_header; 404 uint16_t rx_drr_weight; 405 406 /* Add more stuff later */ 407 } nxge_dma_pt_cfg_t, *p_nxge_dma_pt_cfg_t; 408 409 /* classification configuration */ 410 typedef struct nxge_class_pt_cfg { 411 412 /* MAC table */ 413 nxge_mv_cfg_t mac_host_info[NXGE_MAX_MACS]; 414 415 /* VLAN table */ 416 nxge_mv_cfg_t vlan_tbl[NXGE_MAX_VLANS]; 417 /* class config value */ 418 uint32_t init_h1; 419 uint16_t init_h2; 420 uint8_t mcast_rdcgrp; 421 uint8_t mac_rdcgrp; 422 uint32_t class_cfg[TCAM_CLASS_MAX]; 423 } nxge_class_pt_cfg_t, *p_nxge_class_pt_cfg_t; 424 425 /* per Neptune sharable resources among ports */ 426 typedef struct nxge_common { 427 uint32_t partition_id; 428 boolean_t mode32; 429 /* DMA Channels: RDC and TDC */ 430 nxge_rdc_cfg_t rdc_config[NXGE_MAX_RDCS]; 431 nxge_tdc_cfg_t tdc_config[NXGE_MAX_TDCS]; 432 nxge_dma_common_cfg_t dma_common_config; 433 434 uint32_t timer_res; 435 boolean_t ld_sys_error_set; 436 uint8_t sys_error_owner; 437 438 /* Layer 2/3/4 */ 439 uint16_t class2_etype; 440 uint16_t class3_etype; 441 442 /* FCRAM (hashing) */ 443 uint32_t hash1_initval; 444 uint32_t hash2_initval; 445 } nxge_common_t, *p_nxge_common_t; 446 447 /* 448 * Partition (logical domain) configuration per Neptune/NIU. 449 */ 450 typedef struct nxge_part_cfg { 451 uint32_t rdc_grpbits; /* RDC group bit masks */ 452 uint32_t tdc_bitmap; /* bounded TDC */ 453 nxge_dma_pt_cfg_t pt_config[NXGE_MAX_PORTS]; 454 455 /* Flow Classification Partition (flow partition select register) */ 456 uint8_t hash_lookup; /* external lookup is available */ 457 uint8_t base_mask; /* select bits in base_h1 to replace */ 458 /* bits [19:15} in Hash 1. */ 459 uint8_t base_h1; /* value to replace Hash 1 [19:15]. */ 460 461 /* Add more here */ 462 uint32_t attributes; /* permission and attribute bits */ 463 #define FZC_SERVICE_ENTITY 0x01 464 #define FZC_READ_WRITE 0x02 465 #define FZC_READ_ONLY 0x04 466 } nxge_part_cfg_t, *p_nxge_part_cfg_t; 467 468 typedef struct nxge_hw_list { 469 struct nxge_hw_list *next; 470 nxge_os_mutex_t nxge_cfg_lock; 471 nxge_os_mutex_t nxge_tcam_lock; 472 nxge_os_mutex_t nxge_vlan_lock; 473 nxge_os_mutex_t nxge_mdio_lock; 474 nxge_os_mutex_t nxge_mii_lock; 475 476 nxge_dev_info_t *parent_devp; 477 struct _nxge_t *nxge_p[NXGE_MAX_PORTS]; 478 uint32_t ndevs; 479 uint32_t flags; 480 uint32_t magic; 481 uint32_t niu_type; 482 uint32_t platform_type; 483 uint8_t xcvr_addr[NXGE_MAX_PORTS]; 484 } nxge_hw_list_t, *p_nxge_hw_list_t; 485 486 #ifdef __cplusplus 487 } 488 #endif 489 490 #endif /* _SYS_NXGE_NXGE_COMMON_H */ 491