1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_H 27 #define _SYS_NXGE_NXGE_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #if defined(_KERNEL) || defined(COSIM) 36 #include <nxge_mac.h> 37 #include <nxge_ipp.h> 38 #include <nxge_fflp.h> 39 #endif 40 41 /* 42 * NXGE diagnostics IOCTLS. 43 */ 44 #define NXGE_IOC ((((('N' << 8) + 'X') << 8) + 'G') << 8) 45 46 #define NXGE_GET64 (NXGE_IOC|1) 47 #define NXGE_PUT64 (NXGE_IOC|2) 48 #define NXGE_GET_TX_RING_SZ (NXGE_IOC|3) 49 #define NXGE_GET_TX_DESC (NXGE_IOC|4) 50 #define NXGE_GLOBAL_RESET (NXGE_IOC|5) 51 #define NXGE_TX_SIDE_RESET (NXGE_IOC|6) 52 #define NXGE_RX_SIDE_RESET (NXGE_IOC|7) 53 #define NXGE_RESET_MAC (NXGE_IOC|8) 54 55 #define NXGE_GET_MII (NXGE_IOC|11) 56 #define NXGE_PUT_MII (NXGE_IOC|12) 57 #define NXGE_RTRACE (NXGE_IOC|13) 58 #define NXGE_RTRACE_TEST (NXGE_IOC|20) 59 #define NXGE_TX_REGS_DUMP (NXGE_IOC|21) 60 #define NXGE_RX_REGS_DUMP (NXGE_IOC|22) 61 #define NXGE_INT_REGS_DUMP (NXGE_IOC|23) 62 #define NXGE_VIR_REGS_DUMP (NXGE_IOC|24) 63 #define NXGE_VIR_INT_REGS_DUMP (NXGE_IOC|25) 64 #define NXGE_RDUMP (NXGE_IOC|26) 65 #define NXGE_RDC_GRPS_DUMP (NXGE_IOC|27) 66 #define NXGE_PIO_TEST (NXGE_IOC|28) 67 68 #define NXGE_GET_TCAM (NXGE_IOC|29) 69 #define NXGE_PUT_TCAM (NXGE_IOC|30) 70 #define NXGE_INJECT_ERR (NXGE_IOC|40) 71 72 #if (defined(SOLARIS) && defined(_KERNEL)) || defined(COSIM) 73 #define NXGE_OK 0 74 #define NXGE_ERROR 0x40000000 75 #define NXGE_DDI_FAILED 0x20000000 76 #define NXGE_GET_PORT_NUM(n) n 77 78 /* 79 * Definitions for module_info. 80 */ 81 #define NXGE_IDNUM (0) /* module ID number */ 82 #define NXGE_DRIVER_NAME "nxge" /* module name */ 83 84 #define NXGE_MINPSZ (0) /* min packet size */ 85 #define NXGE_MAXPSZ (ETHERMTU) /* max packet size */ 86 #define NXGE_HIWAT (2048 * NXGE_MAXPSZ) /* hi-water mark */ 87 #define NXGE_LOWAT (1) /* lo-water mark */ 88 #define NXGE_HIWAT_MAX (192000 * NXGE_MAXPSZ) 89 #define NXGE_HIWAT_MIN (2 * NXGE_MAXPSZ) 90 #define NXGE_LOWAT_MAX (192000 * NXGE_MAXPSZ) 91 #define NXGE_LOWAT_MIN (1) 92 93 #ifndef D_HOTPLUG 94 #define D_HOTPLUG 0x00 95 #endif 96 97 #define INIT_BUCKET_SIZE 16 /* Initial Hash Bucket Size */ 98 99 #define NXGE_CHECK_TIMER (5000) 100 101 typedef enum { 102 param_instance, 103 param_main_instance, 104 param_function_number, 105 param_partition_id, 106 param_read_write_mode, 107 param_niu_cfg_type, 108 param_tx_quick_cfg, 109 param_rx_quick_cfg, 110 param_master_cfg_enable, 111 param_master_cfg_value, 112 113 param_autoneg, 114 param_anar_10gfdx, 115 param_anar_10ghdx, 116 param_anar_1000fdx, 117 param_anar_1000hdx, 118 param_anar_100T4, 119 param_anar_100fdx, 120 param_anar_100hdx, 121 param_anar_10fdx, 122 param_anar_10hdx, 123 124 param_anar_asmpause, 125 param_anar_pause, 126 param_use_int_xcvr, 127 param_enable_ipg0, 128 param_ipg0, 129 param_ipg1, 130 param_ipg2, 131 param_accept_jumbo, 132 param_txdma_weight, 133 param_txdma_channels_begin, 134 135 param_txdma_channels, 136 param_txdma_info, 137 param_rxdma_channels_begin, 138 param_rxdma_channels, 139 param_rxdma_drr_weight, 140 param_rxdma_full_header, 141 param_rxdma_info, 142 param_rxdma_rbr_size, 143 param_rxdma_rcr_size, 144 param_default_port_rdc, 145 param_rxdma_intr_time, 146 param_rxdma_intr_pkts, 147 148 param_rdc_grps_start, 149 param_rx_rdc_grps, 150 param_default_grp0_rdc, 151 param_default_grp1_rdc, 152 param_default_grp2_rdc, 153 param_default_grp3_rdc, 154 param_default_grp4_rdc, 155 param_default_grp5_rdc, 156 param_default_grp6_rdc, 157 param_default_grp7_rdc, 158 159 param_info_rdc_groups, 160 param_start_ldg, 161 param_max_ldg, 162 param_mac_2rdc_grp, 163 param_vlan_2rdc_grp, 164 param_fcram_part_cfg, 165 param_fcram_access_ratio, 166 param_tcam_access_ratio, 167 param_tcam_enable, 168 param_hash_lookup_enable, 169 param_llc_snap_enable, 170 171 param_h1_init_value, 172 param_h2_init_value, 173 param_class_cfg_ether_usr1, 174 param_class_cfg_ether_usr2, 175 param_class_cfg_ip_usr4, 176 param_class_cfg_ip_usr5, 177 param_class_cfg_ip_usr6, 178 param_class_cfg_ip_usr7, 179 param_class_opt_ip_usr4, 180 param_class_opt_ip_usr5, 181 param_class_opt_ip_usr6, 182 param_class_opt_ip_usr7, 183 param_class_opt_ipv4_tcp, 184 param_class_opt_ipv4_udp, 185 param_class_opt_ipv4_ah, 186 param_class_opt_ipv4_sctp, 187 param_class_opt_ipv6_tcp, 188 param_class_opt_ipv6_udp, 189 param_class_opt_ipv6_ah, 190 param_class_opt_ipv6_sctp, 191 param_nxge_debug_flag, 192 param_npi_debug_flag, 193 param_dump_rdc, 194 param_dump_tdc, 195 param_dump_mac_regs, 196 param_dump_ipp_regs, 197 param_dump_fflp_regs, 198 param_dump_vlan_table, 199 param_dump_rdc_table, 200 param_dump_ptrs, 201 param_end 202 } nxge_param_index_t; 203 204 205 /* 206 * Named Dispatch Parameter Management Structure 207 */ 208 typedef int (*nxge_ndgetf_t)(p_nxge_t, queue_t *, MBLKP, caddr_t, cred_t *); 209 typedef int (*nxge_ndsetf_t)(p_nxge_t, queue_t *, 210 MBLKP, char *, caddr_t, cred_t *); 211 212 #define NXGE_PARAM_READ 0x00000001ULL 213 #define NXGE_PARAM_WRITE 0x00000002ULL 214 #define NXGE_PARAM_SHARED 0x00000004ULL 215 #define NXGE_PARAM_PRIV 0x00000008ULL 216 #define NXGE_PARAM_RW NXGE_PARAM_READ | NXGE_PARAM_WRITE 217 #define NXGE_PARAM_RWS NXGE_PARAM_RW | NXGE_PARAM_SHARED 218 #define NXGE_PARAM_RWP NXGE_PARAM_RW | NXGE_PARAM_PRIV 219 220 #define NXGE_PARAM_RXDMA 0x00000010ULL 221 #define NXGE_PARAM_TXDMA 0x00000020ULL 222 #define NXGE_PARAM_CLASS_GEN 0x00000040ULL 223 #define NXGE_PARAM_MAC 0x00000080ULL 224 #define NXGE_PARAM_CLASS_BIN NXGE_PARAM_CLASS_GEN | NXGE_PARAM_BASE_BIN 225 #define NXGE_PARAM_CLASS_HEX NXGE_PARAM_CLASS_GEN | NXGE_PARAM_BASE_HEX 226 #define NXGE_PARAM_CLASS NXGE_PARAM_CLASS_HEX 227 228 #define NXGE_PARAM_CMPLX 0x00010000ULL 229 #define NXGE_PARAM_NDD_WR_OK 0x00020000ULL 230 #define NXGE_PARAM_INIT_ONLY 0x00040000ULL 231 #define NXGE_PARAM_INIT_CONFIG 0x00080000ULL 232 233 #define NXGE_PARAM_READ_PROP 0x00100000ULL 234 #define NXGE_PARAM_PROP_ARR32 0x00200000ULL 235 #define NXGE_PARAM_PROP_ARR64 0x00400000ULL 236 #define NXGE_PARAM_PROP_STR 0x00800000ULL 237 238 #define NXGE_PARAM_BASE_DEC 0x00000000ULL 239 #define NXGE_PARAM_BASE_BIN 0x10000000ULL 240 #define NXGE_PARAM_BASE_HEX 0x20000000ULL 241 #define NXGE_PARAM_BASE_STR 0x40000000ULL 242 #define NXGE_PARAM_DONT_SHOW 0x80000000ULL 243 244 #define NXGE_PARAM_ARRAY_CNT_MASK 0x0000ffff00000000ULL 245 #define NXGE_PARAM_ARRAY_CNT_SHIFT 32ULL 246 #define NXGE_PARAM_ARRAY_ALLOC_MASK 0xffff000000000000ULL 247 #define NXGE_PARAM_ARRAY_ALLOC_SHIFT 48ULL 248 249 typedef struct _nxge_param_t { 250 int (*getf)(); 251 int (*setf)(); /* null for read only */ 252 uint64_t type; /* R/W/ Common/Port/ .... */ 253 uint64_t minimum; 254 uint64_t maximum; 255 uint64_t value; /* for array params, pointer to value array */ 256 uint64_t old_value; /* for array params, pointer to old_value array */ 257 char *fcode_name; 258 char *name; 259 } nxge_param_t, *p_nxge_param_t; 260 261 262 263 typedef enum { 264 nxge_lb_normal, 265 nxge_lb_ext10g, 266 nxge_lb_ext1000, 267 nxge_lb_ext100, 268 nxge_lb_ext10, 269 nxge_lb_phy10g, 270 nxge_lb_phy1000, 271 nxge_lb_phy, 272 nxge_lb_serdes10g, 273 nxge_lb_serdes1000, 274 nxge_lb_serdes, 275 nxge_lb_mac10g, 276 nxge_lb_mac1000, 277 nxge_lb_mac 278 } nxge_lb_t; 279 280 enum nxge_mac_state { 281 NXGE_MAC_STOPPED = 0, 282 NXGE_MAC_STARTED 283 }; 284 285 /* 286 * Private DLPI full dlsap address format. 287 */ 288 typedef struct _nxge_dladdr_t { 289 ether_addr_st dl_phys; 290 uint16_t dl_sap; 291 } nxge_dladdr_t, *p_nxge_dladdr_t; 292 293 typedef struct _mc_addr_t { 294 ether_addr_st multcast_addr; 295 uint_t mc_addr_cnt; 296 } mc_addr_t, *p_mc_addr_t; 297 298 typedef struct _mc_bucket_t { 299 p_mc_addr_t addr_list; 300 uint_t list_size; 301 } mc_bucket_t, *p_mc_bucket_t; 302 303 typedef struct _mc_table_t { 304 p_mc_bucket_t bucket_list; 305 uint_t buckets_used; 306 } mc_table_t, *p_mc_table_t; 307 308 typedef struct _filter_t { 309 uint32_t all_phys_cnt; 310 uint32_t all_multicast_cnt; 311 uint32_t all_sap_cnt; 312 } filter_t, *p_filter_t; 313 314 #if defined(_KERNEL) || defined(COSIM) 315 316 317 typedef struct _nxge_port_stats_t { 318 /* 319 * Overall structure size 320 */ 321 size_t stats_size; 322 323 /* 324 * Link Input/Output stats 325 */ 326 uint64_t ipackets; 327 uint64_t ierrors; 328 uint64_t opackets; 329 uint64_t oerrors; 330 uint64_t collisions; 331 332 /* 333 * MIB II variables 334 */ 335 uint64_t rbytes; /* # bytes received */ 336 uint64_t obytes; /* # bytes transmitted */ 337 uint32_t multircv; /* # multicast packets received */ 338 uint32_t multixmt; /* # multicast packets for xmit */ 339 uint32_t brdcstrcv; /* # broadcast packets received */ 340 uint32_t brdcstxmt; /* # broadcast packets for xmit */ 341 uint32_t norcvbuf; /* # rcv packets discarded */ 342 uint32_t noxmtbuf; /* # xmit packets discarded */ 343 344 /* 345 * Lets the user know the MTU currently in use by 346 * the physical MAC port. 347 */ 348 nxge_lb_t lb_mode; 349 uint32_t qos_mode; 350 uint32_t trunk_mode; 351 uint32_t poll_mode; 352 353 /* 354 * Tx Statistics. 355 */ 356 uint32_t tx_inits; 357 uint32_t tx_starts; 358 uint32_t tx_nocanput; 359 uint32_t tx_msgdup_fail; 360 uint32_t tx_allocb_fail; 361 uint32_t tx_no_desc; 362 uint32_t tx_dma_bind_fail; 363 uint32_t tx_uflo; 364 uint32_t tx_hdr_pkts; 365 uint32_t tx_ddi_pkts; 366 uint32_t tx_dvma_pkts; 367 368 uint32_t tx_max_pend; 369 370 /* 371 * Rx Statistics. 372 */ 373 uint32_t rx_inits; 374 uint32_t rx_hdr_pkts; 375 uint32_t rx_mtu_pkts; 376 uint32_t rx_split_pkts; 377 uint32_t rx_no_buf; 378 uint32_t rx_no_comp_wb; 379 uint32_t rx_ov_flow; 380 uint32_t rx_len_mm; 381 uint32_t rx_tag_err; 382 uint32_t rx_nocanput; 383 uint32_t rx_msgdup_fail; 384 uint32_t rx_allocb_fail; 385 386 /* 387 * Receive buffer management statistics. 388 */ 389 uint32_t rx_new_pages; 390 uint32_t rx_new_hdr_pgs; 391 uint32_t rx_new_mtu_pgs; 392 uint32_t rx_new_nxt_pgs; 393 uint32_t rx_reused_pgs; 394 uint32_t rx_hdr_drops; 395 uint32_t rx_mtu_drops; 396 uint32_t rx_nxt_drops; 397 398 /* 399 * Receive flow statistics 400 */ 401 uint32_t rx_rel_flow; 402 uint32_t rx_rel_bit; 403 404 uint32_t rx_pkts_dropped; 405 406 /* 407 * PCI-E Bus Statistics. 408 */ 409 uint32_t pci_bus_speed; 410 uint32_t pci_err; 411 uint32_t pci_rta_err; 412 uint32_t pci_rma_err; 413 uint32_t pci_parity_err; 414 uint32_t pci_bad_ack_err; 415 uint32_t pci_drto_err; 416 uint32_t pci_dmawz_err; 417 uint32_t pci_dmarz_err; 418 419 uint32_t rx_taskq_waits; 420 421 uint32_t tx_jumbo_pkts; 422 423 /* 424 * Some statistics added to support bringup, these 425 * should be removed. 426 */ 427 uint32_t user_defined; 428 } nxge_port_stats_t, *p_nxge_port_stats_t; 429 430 431 typedef struct _nxge_stats_t { 432 /* 433 * Overall structure size 434 */ 435 size_t stats_size; 436 437 kstat_t *ksp; 438 kstat_t *rdc_ksp[NXGE_MAX_RDCS]; 439 kstat_t *tdc_ksp[NXGE_MAX_TDCS]; 440 kstat_t *rdc_sys_ksp; 441 kstat_t *fflp_ksp[1]; 442 kstat_t *ipp_ksp; 443 kstat_t *txc_ksp; 444 kstat_t *mac_ksp; 445 kstat_t *zcp_ksp; 446 kstat_t *port_ksp; 447 kstat_t *mmac_ksp; 448 449 nxge_mac_stats_t mac_stats; /* Common MAC Statistics */ 450 nxge_xmac_stats_t xmac_stats; /* XMAC Statistics */ 451 nxge_bmac_stats_t bmac_stats; /* BMAC Statistics */ 452 453 nxge_rx_ring_stats_t rx_stats; /* per port RX stats */ 454 nxge_ipp_stats_t ipp_stats; /* per port IPP stats */ 455 nxge_zcp_stats_t zcp_stats; /* per port IPP stats */ 456 nxge_rx_ring_stats_t rdc_stats[NXGE_MAX_RDCS]; /* per rdc stats */ 457 nxge_rdc_sys_stats_t rdc_sys_stats; /* per port RDC stats */ 458 459 nxge_tx_ring_stats_t tx_stats; /* per port TX stats */ 460 nxge_txc_stats_t txc_stats; /* per port TX stats */ 461 nxge_tx_ring_stats_t tdc_stats[NXGE_MAX_TDCS]; /* per tdc stats */ 462 nxge_fflp_stats_t fflp_stats; /* fflp stats */ 463 nxge_port_stats_t port_stats; /* fflp stats */ 464 nxge_mmac_stats_t mmac_stats; /* Multi mac. stats */ 465 466 } nxge_stats_t, *p_nxge_stats_t; 467 468 469 470 typedef struct _nxge_intr_t { 471 boolean_t intr_registered; /* interrupts are registered */ 472 boolean_t intr_enabled; /* interrupts are enabled */ 473 boolean_t niu_msi_enable; /* debug or configurable? */ 474 uint8_t nldevs; /* # of logical devices */ 475 int intr_types; /* interrupt types supported */ 476 int intr_type; /* interrupt type to add */ 477 int max_int_cnt; /* max MSIX/INT HW supports */ 478 int start_inum; /* start inum (in sequence?) */ 479 int msi_intx_cnt; /* # msi/intx ints returned */ 480 int intr_added; /* # ints actually needed */ 481 int intr_cap; /* interrupt capabilities */ 482 size_t intr_size; /* size of array to allocate */ 483 ddi_intr_handle_t *htable; /* For array of interrupts */ 484 /* Add interrupt number for each interrupt vector */ 485 int pri; 486 } nxge_intr_t, *p_nxge_intr_t; 487 488 typedef struct _nxge_ldgv_t { 489 uint8_t ndma_ldvs; 490 uint8_t nldvs; 491 uint8_t start_ldg; 492 uint8_t start_ldg_tx; 493 uint8_t start_ldg_rx; 494 uint8_t maxldgs; 495 uint8_t maxldvs; 496 uint8_t ldg_intrs; 497 boolean_t own_sys_err; 498 boolean_t own_max_ldv; 499 uint32_t tmres; 500 p_nxge_ldg_t ldgp; 501 p_nxge_ldv_t ldvp; 502 p_nxge_ldv_t ldvp_syserr; 503 } nxge_ldgv_t, *p_nxge_ldgv_t; 504 505 /* 506 * Neptune Device instance state information. 507 * 508 * Each instance is dynamically allocated on first attach. 509 */ 510 struct _nxge_t { 511 dev_info_t *dip; /* device instance */ 512 dev_info_t *p_dip; /* Parent's device instance */ 513 int instance; /* instance number */ 514 int function_num; /* device function number */ 515 int nports; /* # of ports on this device */ 516 int board_ver; /* Board Version */ 517 int partition_id; /* partition ID */ 518 int use_partition; /* partition is enabled */ 519 uint32_t drv_state; /* driver state bit flags */ 520 uint64_t nxge_debug_level; /* driver state bit flags */ 521 kmutex_t genlock[1]; 522 enum nxge_mac_state nxge_mac_state; 523 ddi_softintr_t resched_id; /* reschedule callback */ 524 boolean_t resched_needed; 525 boolean_t resched_running; 526 527 p_dev_regs_t dev_regs; 528 npi_handle_t npi_handle; 529 npi_handle_t npi_pci_handle; 530 npi_handle_t npi_reg_handle; 531 npi_handle_t npi_msi_handle; 532 npi_handle_t npi_vreg_handle; 533 npi_handle_t npi_v2reg_handle; 534 535 nxge_mac_t mac; 536 nxge_ipp_t ipp; 537 nxge_txc_t txc; 538 nxge_classify_t classifier; 539 540 mac_handle_t mach; /* mac module handle */ 541 p_nxge_stats_t statsp; 542 uint32_t param_count; 543 p_nxge_param_t param_arr; 544 nxge_hw_list_t *nxge_hw_p; /* pointer to per Neptune */ 545 niu_type_t niu_type; 546 boolean_t os_addr_mode32; /* set to 1 for 32 bit mode */ 547 uint8_t nrdc; 548 uint8_t def_rdc; 549 uint8_t rdc[NXGE_MAX_RDCS]; 550 uint8_t ntdc; 551 uint8_t tdc[NXGE_MAX_TDCS]; 552 553 nxge_intr_t nxge_intr_type; 554 nxge_dma_pt_cfg_t pt_config; 555 nxge_class_pt_cfg_t class_config; 556 557 /* Logical device and group data structures. */ 558 p_nxge_ldgv_t ldgvp; 559 560 caddr_t param_list; /* Parameter list */ 561 562 ether_addr_st factaddr; /* factory mac address */ 563 ether_addr_st ouraddr; /* individual address */ 564 kmutex_t ouraddr_lock; /* lock to protect to uradd */ 565 566 ddi_iblock_cookie_t interrupt_cookie; 567 568 /* 569 * Blocks of memory may be pre-allocated by the 570 * partition manager or the driver. They may include 571 * blocks for configuration and buffers. The idea is 572 * to preallocate big blocks of contiguous areas in 573 * system memory (i.e. with IOMMU). These blocks then 574 * will be broken up to a fixed number of blocks with 575 * each block having the same block size (4K, 8K, 16K or 576 * 32K) in the case of buffer blocks. For systems that 577 * do not support DVMA, more than one big block will be 578 * allocated. 579 */ 580 uint32_t rx_default_block_size; 581 nxge_rx_block_size_t rx_bksize_code; 582 583 p_nxge_dma_pool_t rx_buf_pool_p; 584 p_nxge_dma_pool_t rx_cntl_pool_p; 585 586 p_nxge_dma_pool_t tx_buf_pool_p; 587 p_nxge_dma_pool_t tx_cntl_pool_p; 588 589 /* Receive buffer block ring and completion ring. */ 590 p_rx_rbr_rings_t rx_rbr_rings; 591 p_rx_rcr_rings_t rx_rcr_rings; 592 p_rx_mbox_areas_t rx_mbox_areas_p; 593 594 p_rx_tx_params_t rx_params; 595 uint32_t start_rdc; 596 uint32_t max_rdcs; 597 uint32_t rdc_mask; 598 599 /* Transmit descriptors rings */ 600 p_tx_rings_t tx_rings; 601 p_tx_mbox_areas_t tx_mbox_areas_p; 602 603 uint32_t start_tdc; 604 uint32_t max_tdcs; 605 uint32_t tdc_mask; 606 607 p_rx_tx_params_t tx_params; 608 609 ddi_dma_handle_t dmasparehandle; 610 611 ulong_t sys_page_sz; 612 ulong_t sys_page_mask; 613 int suspended; 614 615 mii_bmsr_t bmsr; /* xcvr status at last poll. */ 616 mii_bmsr_t soft_bmsr; /* xcvr status kept by SW. */ 617 618 kmutex_t mif_lock; /* Lock to protect the list. */ 619 620 void (*mii_read)(); 621 void (*mii_write)(); 622 void (*mii_poll)(); 623 filter_t filter; /* Current instance filter */ 624 p_hash_filter_t hash_filter; /* Multicast hash filter. */ 625 krwlock_t filter_lock; /* Lock to protect filters. */ 626 627 ulong_t sys_burst_sz; 628 629 uint8_t cache_line; 630 631 timeout_id_t nxge_link_poll_timerid; 632 timeout_id_t nxge_timerid; 633 634 uint_t need_periodic_reclaim; 635 timeout_id_t reclaim_timer; 636 637 uint8_t msg_min; 638 uint8_t crc_size; 639 640 boolean_t hard_props_read; 641 642 boolean_t nxge_htraffic; 643 uint32_t nxge_ncpus; 644 uint32_t nxge_cpumask; 645 uint16_t intr_timeout; 646 uint16_t intr_threshold; 647 uchar_t nxge_rxmode; 648 uint32_t active_threads; 649 650 rtrace_t rtrace; 651 int fm_capabilities; /* FMA capabilities */ 652 653 uint32_t nxge_port_rbr_size; 654 uint32_t nxge_port_rcr_size; 655 uint32_t nxge_port_tx_ring_size; 656 nxge_mmac_t nxge_mmac_info; 657 #if defined(sun4v) 658 boolean_t niu_hsvc_available; 659 hsvc_info_t niu_hsvc; 660 uint64_t niu_min_ver; 661 #endif 662 boolean_t link_notify; 663 }; 664 665 /* 666 * Driver state flags. 667 */ 668 #define STATE_REGS_MAPPED 0x000000001 /* device registers mapped */ 669 #define STATE_KSTATS_SETUP 0x000000002 /* kstats allocated */ 670 #define STATE_NODE_CREATED 0x000000004 /* device node created */ 671 #define STATE_HW_CONFIG_CREATED 0x000000008 /* hardware properties */ 672 #define STATE_HW_INITIALIZED 0x000000010 /* hardware initialized */ 673 #define STATE_MDIO_LOCK_INIT 0x000000020 /* mdio lock initialized */ 674 #define STATE_MII_LOCK_INIT 0x000000040 /* mii lock initialized */ 675 676 #define STOP_POLL_THRESH 9 677 #define START_POLL_THRESH 2 678 679 typedef struct _nxge_port_kstat_t { 680 /* 681 * Transciever state informations. 682 */ 683 kstat_named_t xcvr_inits; 684 kstat_named_t xcvr_inuse; 685 kstat_named_t xcvr_addr; 686 kstat_named_t xcvr_id; 687 kstat_named_t cap_autoneg; 688 kstat_named_t cap_10gfdx; 689 kstat_named_t cap_10ghdx; 690 kstat_named_t cap_1000fdx; 691 kstat_named_t cap_1000hdx; 692 kstat_named_t cap_100T4; 693 kstat_named_t cap_100fdx; 694 kstat_named_t cap_100hdx; 695 kstat_named_t cap_10fdx; 696 kstat_named_t cap_10hdx; 697 kstat_named_t cap_asmpause; 698 kstat_named_t cap_pause; 699 700 /* 701 * Link partner capabilities. 702 */ 703 kstat_named_t lp_cap_autoneg; 704 kstat_named_t lp_cap_10gfdx; 705 kstat_named_t lp_cap_10ghdx; 706 kstat_named_t lp_cap_1000fdx; 707 kstat_named_t lp_cap_1000hdx; 708 kstat_named_t lp_cap_100T4; 709 kstat_named_t lp_cap_100fdx; 710 kstat_named_t lp_cap_100hdx; 711 kstat_named_t lp_cap_10fdx; 712 kstat_named_t lp_cap_10hdx; 713 kstat_named_t lp_cap_asmpause; 714 kstat_named_t lp_cap_pause; 715 716 /* 717 * Shared link setup. 718 */ 719 kstat_named_t link_T4; 720 kstat_named_t link_speed; 721 kstat_named_t link_duplex; 722 kstat_named_t link_asmpause; 723 kstat_named_t link_pause; 724 kstat_named_t link_up; 725 726 /* 727 * Lets the user know the MTU currently in use by 728 * the physical MAC port. 729 */ 730 kstat_named_t mac_mtu; 731 kstat_named_t lb_mode; 732 kstat_named_t qos_mode; 733 kstat_named_t trunk_mode; 734 735 /* 736 * Misc MAC statistics. 737 */ 738 kstat_named_t ifspeed; 739 kstat_named_t promisc; 740 kstat_named_t rev_id; 741 742 /* 743 * Some statistics added to support bringup, these 744 * should be removed. 745 */ 746 kstat_named_t user_defined; 747 } nxge_port_kstat_t, *p_nxge_port_kstat_t; 748 749 typedef struct _nxge_rdc_kstat { 750 /* 751 * Receive DMA channel statistics. 752 */ 753 kstat_named_t ipackets; 754 kstat_named_t rbytes; 755 kstat_named_t errors; 756 kstat_named_t dcf_err; 757 kstat_named_t rcr_ack_err; 758 759 kstat_named_t dc_fifoflow_err; 760 kstat_named_t rcr_sha_par_err; 761 kstat_named_t rbr_pre_par_err; 762 kstat_named_t wred_drop; 763 kstat_named_t rbr_pre_emty; 764 765 kstat_named_t rcr_shadow_full; 766 kstat_named_t rbr_tmout; 767 kstat_named_t rsp_cnt_err; 768 kstat_named_t byte_en_bus; 769 kstat_named_t rsp_dat_err; 770 771 kstat_named_t compl_l2_err; 772 kstat_named_t compl_l4_cksum_err; 773 kstat_named_t compl_zcp_soft_err; 774 kstat_named_t compl_fflp_soft_err; 775 kstat_named_t config_err; 776 777 kstat_named_t rcrincon; 778 kstat_named_t rcrfull; 779 kstat_named_t rbr_empty; 780 kstat_named_t rbrfull; 781 kstat_named_t rbrlogpage; 782 783 kstat_named_t cfiglogpage; 784 kstat_named_t port_drop_pkt; 785 kstat_named_t rcr_to; 786 kstat_named_t rcr_thresh; 787 kstat_named_t rcr_mex; 788 kstat_named_t id_mismatch; 789 kstat_named_t zcp_eop_err; 790 kstat_named_t ipp_eop_err; 791 } nxge_rdc_kstat_t, *p_nxge_rdc_kstat_t; 792 793 typedef struct _nxge_rdc_sys_kstat { 794 /* 795 * Receive DMA system statistics. 796 */ 797 kstat_named_t pre_par; 798 kstat_named_t sha_par; 799 kstat_named_t id_mismatch; 800 kstat_named_t ipp_eop_err; 801 kstat_named_t zcp_eop_err; 802 } nxge_rdc_sys_kstat_t, *p_nxge_rdc_sys_kstat_t; 803 804 typedef struct _nxge_tdc_kstat { 805 /* 806 * Transmit DMA channel statistics. 807 */ 808 kstat_named_t opackets; 809 kstat_named_t obytes; 810 kstat_named_t oerrors; 811 kstat_named_t tx_inits; 812 kstat_named_t tx_no_buf; 813 814 kstat_named_t mbox_err; 815 kstat_named_t pkt_size_err; 816 kstat_named_t tx_ring_oflow; 817 kstat_named_t pref_buf_ecc_err; 818 kstat_named_t nack_pref; 819 kstat_named_t nack_pkt_rd; 820 kstat_named_t conf_part_err; 821 kstat_named_t pkt_prt_err; 822 kstat_named_t reset_fail; 823 /* used to in the common (per port) counter */ 824 825 kstat_named_t tx_starts; 826 kstat_named_t tx_nocanput; 827 kstat_named_t tx_msgdup_fail; 828 kstat_named_t tx_allocb_fail; 829 kstat_named_t tx_no_desc; 830 kstat_named_t tx_dma_bind_fail; 831 kstat_named_t tx_uflo; 832 kstat_named_t tx_hdr_pkts; 833 kstat_named_t tx_ddi_pkts; 834 kstat_named_t tx_dvma_pkts; 835 kstat_named_t tx_max_pend; 836 } nxge_tdc_kstat_t, *p_nxge_tdc_kstat_t; 837 838 typedef struct _nxge_txc_kstat { 839 /* 840 * Transmit port TXC block statistics. 841 */ 842 kstat_named_t pkt_stuffed; 843 kstat_named_t pkt_xmit; 844 kstat_named_t ro_correct_err; 845 kstat_named_t ro_uncorrect_err; 846 kstat_named_t sf_correct_err; 847 kstat_named_t sf_uncorrect_err; 848 kstat_named_t address_failed; 849 kstat_named_t dma_failed; 850 kstat_named_t length_failed; 851 kstat_named_t pkt_assy_dead; 852 kstat_named_t reorder_err; 853 } nxge_txc_kstat_t, *p_nxge_txc_kstat_t; 854 855 typedef struct _nxge_ipp_kstat { 856 /* 857 * Receive port IPP block statistics. 858 */ 859 kstat_named_t eop_miss; 860 kstat_named_t sop_miss; 861 kstat_named_t dfifo_ue; 862 kstat_named_t ecc_err_cnt; 863 kstat_named_t dfifo_perr; 864 kstat_named_t pfifo_over; 865 kstat_named_t pfifo_und; 866 kstat_named_t bad_cs_cnt; 867 kstat_named_t pkt_dis_cnt; 868 kstat_named_t cs_fail; 869 } nxge_ipp_kstat_t, *p_nxge_ipp_kstat_t; 870 871 typedef struct _nxge_zcp_kstat { 872 /* 873 * ZCP statistics. 874 */ 875 kstat_named_t errors; 876 kstat_named_t inits; 877 kstat_named_t rrfifo_underrun; 878 kstat_named_t rrfifo_overrun; 879 kstat_named_t rspfifo_uncorr_err; 880 kstat_named_t buffer_overflow; 881 kstat_named_t stat_tbl_perr; 882 kstat_named_t dyn_tbl_perr; 883 kstat_named_t buf_tbl_perr; 884 kstat_named_t tt_program_err; 885 kstat_named_t rsp_tt_index_err; 886 kstat_named_t slv_tt_index_err; 887 kstat_named_t zcp_tt_index_err; 888 kstat_named_t access_fail; 889 kstat_named_t cfifo_ecc; 890 } nxge_zcp_kstat_t, *p_nxge_zcp_kstat_t; 891 892 typedef struct _nxge_mac_kstat { 893 /* 894 * Transmit MAC statistics. 895 */ 896 kstat_named_t tx_frame_cnt; 897 kstat_named_t tx_underflow_err; 898 kstat_named_t tx_overflow_err; 899 kstat_named_t tx_maxpktsize_err; 900 kstat_named_t tx_fifo_xfr_err; 901 kstat_named_t tx_byte_cnt; 902 903 /* 904 * Receive MAC statistics. 905 */ 906 kstat_named_t rx_frame_cnt; 907 kstat_named_t rx_underflow_err; 908 kstat_named_t rx_overflow_err; 909 kstat_named_t rx_len_err_cnt; 910 kstat_named_t rx_crc_err_cnt; 911 kstat_named_t rx_viol_err_cnt; 912 kstat_named_t rx_byte_cnt; 913 kstat_named_t rx_hist1_cnt; 914 kstat_named_t rx_hist2_cnt; 915 kstat_named_t rx_hist3_cnt; 916 kstat_named_t rx_hist4_cnt; 917 kstat_named_t rx_hist5_cnt; 918 kstat_named_t rx_hist6_cnt; 919 kstat_named_t rx_broadcast_cnt; 920 kstat_named_t rx_mult_cnt; 921 kstat_named_t rx_frag_cnt; 922 kstat_named_t rx_frame_align_err_cnt; 923 kstat_named_t rx_linkfault_err_cnt; 924 kstat_named_t rx_local_fault_err_cnt; 925 kstat_named_t rx_remote_fault_err_cnt; 926 } nxge_mac_kstat_t, *p_nxge_mac_kstat_t; 927 928 typedef struct _nxge_xmac_kstat { 929 /* 930 * XMAC statistics. 931 */ 932 kstat_named_t tx_frame_cnt; 933 kstat_named_t tx_underflow_err; 934 kstat_named_t tx_maxpktsize_err; 935 kstat_named_t tx_overflow_err; 936 kstat_named_t tx_fifo_xfr_err; 937 kstat_named_t tx_byte_cnt; 938 kstat_named_t rx_frame_cnt; 939 kstat_named_t rx_underflow_err; 940 kstat_named_t rx_overflow_err; 941 kstat_named_t rx_crc_err_cnt; 942 kstat_named_t rx_len_err_cnt; 943 kstat_named_t rx_viol_err_cnt; 944 kstat_named_t rx_byte_cnt; 945 kstat_named_t rx_hist1_cnt; 946 kstat_named_t rx_hist2_cnt; 947 kstat_named_t rx_hist3_cnt; 948 kstat_named_t rx_hist4_cnt; 949 kstat_named_t rx_hist5_cnt; 950 kstat_named_t rx_hist6_cnt; 951 kstat_named_t rx_hist7_cnt; 952 kstat_named_t rx_broadcast_cnt; 953 kstat_named_t rx_mult_cnt; 954 kstat_named_t rx_frag_cnt; 955 kstat_named_t rx_frame_align_err_cnt; 956 kstat_named_t rx_linkfault_err_cnt; 957 kstat_named_t rx_remote_fault_err_cnt; 958 kstat_named_t rx_local_fault_err_cnt; 959 kstat_named_t rx_pause_cnt; 960 kstat_named_t xpcs_deskew_err_cnt; 961 kstat_named_t xpcs_ln0_symbol_err_cnt; 962 kstat_named_t xpcs_ln1_symbol_err_cnt; 963 kstat_named_t xpcs_ln2_symbol_err_cnt; 964 kstat_named_t xpcs_ln3_symbol_err_cnt; 965 } nxge_xmac_kstat_t, *p_nxge_xmac_kstat_t; 966 967 typedef struct _nxge_bmac_kstat { 968 /* 969 * BMAC statistics. 970 */ 971 kstat_named_t tx_frame_cnt; 972 kstat_named_t tx_underrun_err; 973 kstat_named_t tx_max_pkt_err; 974 kstat_named_t tx_byte_cnt; 975 kstat_named_t rx_frame_cnt; 976 kstat_named_t rx_byte_cnt; 977 kstat_named_t rx_overflow_err; 978 kstat_named_t rx_align_err_cnt; 979 kstat_named_t rx_crc_err_cnt; 980 kstat_named_t rx_len_err_cnt; 981 kstat_named_t rx_viol_err_cnt; 982 kstat_named_t rx_pause_cnt; 983 kstat_named_t tx_pause_state; 984 kstat_named_t tx_nopause_state; 985 } nxge_bmac_kstat_t, *p_nxge_bmac_kstat_t; 986 987 988 typedef struct _nxge_fflp_kstat { 989 /* 990 * FFLP statistics. 991 */ 992 993 kstat_named_t fflp_tcam_ecc_err; 994 kstat_named_t fflp_tcam_perr; 995 kstat_named_t fflp_vlan_perr; 996 kstat_named_t fflp_hasht_lookup_err; 997 kstat_named_t fflp_access_fail; 998 kstat_named_t fflp_hasht_data_err[MAX_PARTITION]; 999 } nxge_fflp_kstat_t, *p_nxge_fflp_kstat_t; 1000 1001 typedef struct _nxge_mmac_kstat { 1002 kstat_named_t mmac_max_addr_cnt; 1003 kstat_named_t mmac_avail_addr_cnt; 1004 kstat_named_t mmac_addr1; 1005 kstat_named_t mmac_addr2; 1006 kstat_named_t mmac_addr3; 1007 kstat_named_t mmac_addr4; 1008 kstat_named_t mmac_addr5; 1009 kstat_named_t mmac_addr6; 1010 kstat_named_t mmac_addr7; 1011 kstat_named_t mmac_addr8; 1012 kstat_named_t mmac_addr9; 1013 kstat_named_t mmac_addr10; 1014 kstat_named_t mmac_addr11; 1015 kstat_named_t mmac_addr12; 1016 kstat_named_t mmac_addr13; 1017 kstat_named_t mmac_addr14; 1018 kstat_named_t mmac_addr15; 1019 kstat_named_t mmac_addr16; 1020 } nxge_mmac_kstat_t, *p_nxge_mmac_kstat_t; 1021 1022 #endif /* _KERNEL */ 1023 1024 /* 1025 * Prototype definitions. 1026 */ 1027 nxge_status_t nxge_init(p_nxge_t); 1028 void nxge_uninit(p_nxge_t); 1029 void nxge_get64(p_nxge_t, p_mblk_t); 1030 void nxge_put64(p_nxge_t, p_mblk_t); 1031 void nxge_pio_loop(p_nxge_t, p_mblk_t); 1032 1033 #ifndef COSIM 1034 typedef void (*fptrv_t)(); 1035 timeout_id_t nxge_start_timer(p_nxge_t, fptrv_t, int); 1036 void nxge_stop_timer(p_nxge_t, timeout_id_t); 1037 #endif 1038 #endif 1039 1040 #ifdef __cplusplus 1041 } 1042 #endif 1043 1044 #endif /* _SYS_NXGE_NXGE_H */ 1045