1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_H 27 #define _SYS_NXGE_NXGE_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #if defined(_KERNEL) || defined(COSIM) 36 #include <nxge_mac.h> 37 #include <nxge_ipp.h> 38 #include <nxge_fflp.h> 39 #endif 40 41 /* 42 * NXGE diagnostics IOCTLS. 43 */ 44 #define NXGE_IOC ((((('N' << 8) + 'X') << 8) + 'G') << 8) 45 46 #define NXGE_GET64 (NXGE_IOC|1) 47 #define NXGE_PUT64 (NXGE_IOC|2) 48 #define NXGE_GET_TX_RING_SZ (NXGE_IOC|3) 49 #define NXGE_GET_TX_DESC (NXGE_IOC|4) 50 #define NXGE_GLOBAL_RESET (NXGE_IOC|5) 51 #define NXGE_TX_SIDE_RESET (NXGE_IOC|6) 52 #define NXGE_RX_SIDE_RESET (NXGE_IOC|7) 53 #define NXGE_RESET_MAC (NXGE_IOC|8) 54 55 #define NXGE_GET_MII (NXGE_IOC|11) 56 #define NXGE_PUT_MII (NXGE_IOC|12) 57 #define NXGE_RTRACE (NXGE_IOC|13) 58 #define NXGE_RTRACE_TEST (NXGE_IOC|20) 59 #define NXGE_TX_REGS_DUMP (NXGE_IOC|21) 60 #define NXGE_RX_REGS_DUMP (NXGE_IOC|22) 61 #define NXGE_INT_REGS_DUMP (NXGE_IOC|23) 62 #define NXGE_VIR_REGS_DUMP (NXGE_IOC|24) 63 #define NXGE_VIR_INT_REGS_DUMP (NXGE_IOC|25) 64 #define NXGE_RDUMP (NXGE_IOC|26) 65 #define NXGE_RDC_GRPS_DUMP (NXGE_IOC|27) 66 #define NXGE_PIO_TEST (NXGE_IOC|28) 67 68 #define NXGE_GET_TCAM (NXGE_IOC|29) 69 #define NXGE_PUT_TCAM (NXGE_IOC|30) 70 #define NXGE_INJECT_ERR (NXGE_IOC|40) 71 72 #if (defined(SOLARIS) && defined(_KERNEL)) || defined(COSIM) 73 #define NXGE_OK 0 74 #define NXGE_ERROR 0x40000000 75 #define NXGE_DDI_FAILED 0x20000000 76 #define NXGE_GET_PORT_NUM(n) n 77 78 /* 79 * Definitions for module_info. 80 */ 81 #define NXGE_IDNUM (0) /* module ID number */ 82 #define NXGE_DRIVER_NAME "nxge" /* module name */ 83 84 #define NXGE_MINPSZ (0) /* min packet size */ 85 #define NXGE_MAXPSZ (ETHERMTU) /* max packet size */ 86 #define NXGE_HIWAT (2048 * NXGE_MAXPSZ) /* hi-water mark */ 87 #define NXGE_LOWAT (1) /* lo-water mark */ 88 #define NXGE_HIWAT_MAX (192000 * NXGE_MAXPSZ) 89 #define NXGE_HIWAT_MIN (2 * NXGE_MAXPSZ) 90 #define NXGE_LOWAT_MAX (192000 * NXGE_MAXPSZ) 91 #define NXGE_LOWAT_MIN (1) 92 93 #ifndef D_HOTPLUG 94 #define D_HOTPLUG 0x00 95 #endif 96 97 #define INIT_BUCKET_SIZE 16 /* Initial Hash Bucket Size */ 98 99 #define NXGE_CHECK_TIMER (5000) 100 101 typedef enum { 102 param_instance, 103 param_main_instance, 104 param_function_number, 105 param_partition_id, 106 param_read_write_mode, 107 param_fw_version, 108 param_port_mode, 109 param_niu_cfg_type, 110 param_tx_quick_cfg, 111 param_rx_quick_cfg, 112 param_master_cfg_enable, 113 param_master_cfg_value, 114 115 param_autoneg, 116 param_anar_10gfdx, 117 param_anar_10ghdx, 118 param_anar_1000fdx, 119 param_anar_1000hdx, 120 param_anar_100T4, 121 param_anar_100fdx, 122 param_anar_100hdx, 123 param_anar_10fdx, 124 param_anar_10hdx, 125 126 param_anar_asmpause, 127 param_anar_pause, 128 param_use_int_xcvr, 129 param_enable_ipg0, 130 param_ipg0, 131 param_ipg1, 132 param_ipg2, 133 param_accept_jumbo, 134 param_txdma_weight, 135 param_txdma_channels_begin, 136 137 param_txdma_channels, 138 param_txdma_info, 139 param_rxdma_channels_begin, 140 param_rxdma_channels, 141 param_rxdma_drr_weight, 142 param_rxdma_full_header, 143 param_rxdma_info, 144 param_rxdma_rbr_size, 145 param_rxdma_rcr_size, 146 param_default_port_rdc, 147 param_rxdma_intr_time, 148 param_rxdma_intr_pkts, 149 150 param_rdc_grps_start, 151 param_rx_rdc_grps, 152 param_default_grp0_rdc, 153 param_default_grp1_rdc, 154 param_default_grp2_rdc, 155 param_default_grp3_rdc, 156 param_default_grp4_rdc, 157 param_default_grp5_rdc, 158 param_default_grp6_rdc, 159 param_default_grp7_rdc, 160 161 param_info_rdc_groups, 162 param_start_ldg, 163 param_max_ldg, 164 param_mac_2rdc_grp, 165 param_vlan_2rdc_grp, 166 param_fcram_part_cfg, 167 param_fcram_access_ratio, 168 param_tcam_access_ratio, 169 param_tcam_enable, 170 param_hash_lookup_enable, 171 param_llc_snap_enable, 172 173 param_h1_init_value, 174 param_h2_init_value, 175 param_class_cfg_ether_usr1, 176 param_class_cfg_ether_usr2, 177 param_class_cfg_ip_usr4, 178 param_class_cfg_ip_usr5, 179 param_class_cfg_ip_usr6, 180 param_class_cfg_ip_usr7, 181 param_class_opt_ip_usr4, 182 param_class_opt_ip_usr5, 183 param_class_opt_ip_usr6, 184 param_class_opt_ip_usr7, 185 param_class_opt_ipv4_tcp, 186 param_class_opt_ipv4_udp, 187 param_class_opt_ipv4_ah, 188 param_class_opt_ipv4_sctp, 189 param_class_opt_ipv6_tcp, 190 param_class_opt_ipv6_udp, 191 param_class_opt_ipv6_ah, 192 param_class_opt_ipv6_sctp, 193 param_nxge_debug_flag, 194 param_npi_debug_flag, 195 param_dump_rdc, 196 param_dump_tdc, 197 param_dump_mac_regs, 198 param_dump_ipp_regs, 199 param_dump_fflp_regs, 200 param_dump_vlan_table, 201 param_dump_rdc_table, 202 param_dump_ptrs, 203 param_end 204 } nxge_param_index_t; 205 206 207 /* 208 * Named Dispatch Parameter Management Structure 209 */ 210 typedef int (*nxge_ndgetf_t)(p_nxge_t, queue_t *, MBLKP, caddr_t, cred_t *); 211 typedef int (*nxge_ndsetf_t)(p_nxge_t, queue_t *, 212 MBLKP, char *, caddr_t, cred_t *); 213 214 #define NXGE_PARAM_READ 0x00000001ULL 215 #define NXGE_PARAM_WRITE 0x00000002ULL 216 #define NXGE_PARAM_SHARED 0x00000004ULL 217 #define NXGE_PARAM_PRIV 0x00000008ULL 218 #define NXGE_PARAM_RW NXGE_PARAM_READ | NXGE_PARAM_WRITE 219 #define NXGE_PARAM_RWS NXGE_PARAM_RW | NXGE_PARAM_SHARED 220 #define NXGE_PARAM_RWP NXGE_PARAM_RW | NXGE_PARAM_PRIV 221 222 #define NXGE_PARAM_RXDMA 0x00000010ULL 223 #define NXGE_PARAM_TXDMA 0x00000020ULL 224 #define NXGE_PARAM_CLASS_GEN 0x00000040ULL 225 #define NXGE_PARAM_MAC 0x00000080ULL 226 #define NXGE_PARAM_CLASS_BIN NXGE_PARAM_CLASS_GEN | NXGE_PARAM_BASE_BIN 227 #define NXGE_PARAM_CLASS_HEX NXGE_PARAM_CLASS_GEN | NXGE_PARAM_BASE_HEX 228 #define NXGE_PARAM_CLASS NXGE_PARAM_CLASS_HEX 229 230 #define NXGE_PARAM_CMPLX 0x00010000ULL 231 #define NXGE_PARAM_NDD_WR_OK 0x00020000ULL 232 #define NXGE_PARAM_INIT_ONLY 0x00040000ULL 233 #define NXGE_PARAM_INIT_CONFIG 0x00080000ULL 234 235 #define NXGE_PARAM_READ_PROP 0x00100000ULL 236 #define NXGE_PARAM_PROP_ARR32 0x00200000ULL 237 #define NXGE_PARAM_PROP_ARR64 0x00400000ULL 238 #define NXGE_PARAM_PROP_STR 0x00800000ULL 239 240 #define NXGE_PARAM_BASE_DEC 0x00000000ULL 241 #define NXGE_PARAM_BASE_BIN 0x10000000ULL 242 #define NXGE_PARAM_BASE_HEX 0x20000000ULL 243 #define NXGE_PARAM_BASE_STR 0x40000000ULL 244 #define NXGE_PARAM_DONT_SHOW 0x80000000ULL 245 246 #define NXGE_PARAM_ARRAY_CNT_MASK 0x0000ffff00000000ULL 247 #define NXGE_PARAM_ARRAY_CNT_SHIFT 32ULL 248 #define NXGE_PARAM_ARRAY_ALLOC_MASK 0xffff000000000000ULL 249 #define NXGE_PARAM_ARRAY_ALLOC_SHIFT 48ULL 250 251 typedef struct _nxge_param_t { 252 int (*getf)(); 253 int (*setf)(); /* null for read only */ 254 uint64_t type; /* R/W/ Common/Port/ .... */ 255 uint64_t minimum; 256 uint64_t maximum; 257 uint64_t value; /* for array params, pointer to value array */ 258 uint64_t old_value; /* for array params, pointer to old_value array */ 259 char *fcode_name; 260 char *name; 261 } nxge_param_t, *p_nxge_param_t; 262 263 264 /* 265 * Do not change the order of the elements of this enum as that will 266 * break the driver code. 267 */ 268 typedef enum { 269 nxge_lb_normal, 270 nxge_lb_ext10g, 271 nxge_lb_ext1000, 272 nxge_lb_ext100, 273 nxge_lb_ext10, 274 nxge_lb_phy10g, 275 nxge_lb_phy1000, 276 nxge_lb_phy, 277 nxge_lb_serdes10g, 278 nxge_lb_serdes1000, 279 nxge_lb_serdes, 280 nxge_lb_mac10g, 281 nxge_lb_mac1000, 282 nxge_lb_mac 283 } nxge_lb_t; 284 285 enum nxge_mac_state { 286 NXGE_MAC_STOPPED = 0, 287 NXGE_MAC_STARTED 288 }; 289 290 /* 291 * Private DLPI full dlsap address format. 292 */ 293 typedef struct _nxge_dladdr_t { 294 ether_addr_st dl_phys; 295 uint16_t dl_sap; 296 } nxge_dladdr_t, *p_nxge_dladdr_t; 297 298 typedef struct _mc_addr_t { 299 ether_addr_st multcast_addr; 300 uint_t mc_addr_cnt; 301 } mc_addr_t, *p_mc_addr_t; 302 303 typedef struct _mc_bucket_t { 304 p_mc_addr_t addr_list; 305 uint_t list_size; 306 } mc_bucket_t, *p_mc_bucket_t; 307 308 typedef struct _mc_table_t { 309 p_mc_bucket_t bucket_list; 310 uint_t buckets_used; 311 } mc_table_t, *p_mc_table_t; 312 313 typedef struct _filter_t { 314 uint32_t all_phys_cnt; 315 uint32_t all_multicast_cnt; 316 uint32_t all_sap_cnt; 317 } filter_t, *p_filter_t; 318 319 #if defined(_KERNEL) || defined(COSIM) 320 321 322 typedef struct _nxge_port_stats_t { 323 /* 324 * Overall structure size 325 */ 326 size_t stats_size; 327 328 /* 329 * Link Input/Output stats 330 */ 331 uint64_t ipackets; 332 uint64_t ierrors; 333 uint64_t opackets; 334 uint64_t oerrors; 335 uint64_t collisions; 336 337 /* 338 * MIB II variables 339 */ 340 uint64_t rbytes; /* # bytes received */ 341 uint64_t obytes; /* # bytes transmitted */ 342 uint32_t multircv; /* # multicast packets received */ 343 uint32_t multixmt; /* # multicast packets for xmit */ 344 uint32_t brdcstrcv; /* # broadcast packets received */ 345 uint32_t brdcstxmt; /* # broadcast packets for xmit */ 346 uint32_t norcvbuf; /* # rcv packets discarded */ 347 uint32_t noxmtbuf; /* # xmit packets discarded */ 348 349 /* 350 * Lets the user know the MTU currently in use by 351 * the physical MAC port. 352 */ 353 nxge_lb_t lb_mode; 354 uint32_t qos_mode; 355 uint32_t trunk_mode; 356 uint32_t poll_mode; 357 358 /* 359 * Tx Statistics. 360 */ 361 uint32_t tx_inits; 362 uint32_t tx_starts; 363 uint32_t tx_nocanput; 364 uint32_t tx_msgdup_fail; 365 uint32_t tx_allocb_fail; 366 uint32_t tx_no_desc; 367 uint32_t tx_dma_bind_fail; 368 uint32_t tx_uflo; 369 uint32_t tx_hdr_pkts; 370 uint32_t tx_ddi_pkts; 371 uint32_t tx_dvma_pkts; 372 373 uint32_t tx_max_pend; 374 375 /* 376 * Rx Statistics. 377 */ 378 uint32_t rx_inits; 379 uint32_t rx_hdr_pkts; 380 uint32_t rx_mtu_pkts; 381 uint32_t rx_split_pkts; 382 uint32_t rx_no_buf; 383 uint32_t rx_no_comp_wb; 384 uint32_t rx_ov_flow; 385 uint32_t rx_len_mm; 386 uint32_t rx_tag_err; 387 uint32_t rx_nocanput; 388 uint32_t rx_msgdup_fail; 389 uint32_t rx_allocb_fail; 390 391 /* 392 * Receive buffer management statistics. 393 */ 394 uint32_t rx_new_pages; 395 uint32_t rx_new_hdr_pgs; 396 uint32_t rx_new_mtu_pgs; 397 uint32_t rx_new_nxt_pgs; 398 uint32_t rx_reused_pgs; 399 uint32_t rx_hdr_drops; 400 uint32_t rx_mtu_drops; 401 uint32_t rx_nxt_drops; 402 403 /* 404 * Receive flow statistics 405 */ 406 uint32_t rx_rel_flow; 407 uint32_t rx_rel_bit; 408 409 uint32_t rx_pkts_dropped; 410 411 /* 412 * PCI-E Bus Statistics. 413 */ 414 uint32_t pci_bus_speed; 415 uint32_t pci_err; 416 uint32_t pci_rta_err; 417 uint32_t pci_rma_err; 418 uint32_t pci_parity_err; 419 uint32_t pci_bad_ack_err; 420 uint32_t pci_drto_err; 421 uint32_t pci_dmawz_err; 422 uint32_t pci_dmarz_err; 423 424 uint32_t rx_taskq_waits; 425 426 uint32_t tx_jumbo_pkts; 427 428 /* 429 * Some statistics added to support bringup, these 430 * should be removed. 431 */ 432 uint32_t user_defined; 433 } nxge_port_stats_t, *p_nxge_port_stats_t; 434 435 436 typedef struct _nxge_stats_t { 437 /* 438 * Overall structure size 439 */ 440 size_t stats_size; 441 442 kstat_t *ksp; 443 kstat_t *rdc_ksp[NXGE_MAX_RDCS]; 444 kstat_t *tdc_ksp[NXGE_MAX_TDCS]; 445 kstat_t *rdc_sys_ksp; 446 kstat_t *fflp_ksp[1]; 447 kstat_t *ipp_ksp; 448 kstat_t *txc_ksp; 449 kstat_t *mac_ksp; 450 kstat_t *zcp_ksp; 451 kstat_t *port_ksp; 452 kstat_t *mmac_ksp; 453 454 nxge_mac_stats_t mac_stats; /* Common MAC Statistics */ 455 nxge_xmac_stats_t xmac_stats; /* XMAC Statistics */ 456 nxge_bmac_stats_t bmac_stats; /* BMAC Statistics */ 457 458 nxge_rx_ring_stats_t rx_stats; /* per port RX stats */ 459 nxge_ipp_stats_t ipp_stats; /* per port IPP stats */ 460 nxge_zcp_stats_t zcp_stats; /* per port IPP stats */ 461 nxge_rx_ring_stats_t rdc_stats[NXGE_MAX_RDCS]; /* per rdc stats */ 462 nxge_rdc_sys_stats_t rdc_sys_stats; /* per port RDC stats */ 463 464 nxge_tx_ring_stats_t tx_stats; /* per port TX stats */ 465 nxge_txc_stats_t txc_stats; /* per port TX stats */ 466 nxge_tx_ring_stats_t tdc_stats[NXGE_MAX_TDCS]; /* per tdc stats */ 467 nxge_fflp_stats_t fflp_stats; /* fflp stats */ 468 nxge_port_stats_t port_stats; /* fflp stats */ 469 nxge_mmac_stats_t mmac_stats; /* Multi mac. stats */ 470 471 } nxge_stats_t, *p_nxge_stats_t; 472 473 474 475 typedef struct _nxge_intr_t { 476 boolean_t intr_registered; /* interrupts are registered */ 477 boolean_t intr_enabled; /* interrupts are enabled */ 478 boolean_t niu_msi_enable; /* debug or configurable? */ 479 uint8_t nldevs; /* # of logical devices */ 480 int intr_types; /* interrupt types supported */ 481 int intr_type; /* interrupt type to add */ 482 int max_int_cnt; /* max MSIX/INT HW supports */ 483 int start_inum; /* start inum (in sequence?) */ 484 int msi_intx_cnt; /* # msi/intx ints returned */ 485 int intr_added; /* # ints actually needed */ 486 int intr_cap; /* interrupt capabilities */ 487 size_t intr_size; /* size of array to allocate */ 488 ddi_intr_handle_t *htable; /* For array of interrupts */ 489 /* Add interrupt number for each interrupt vector */ 490 int pri; 491 } nxge_intr_t, *p_nxge_intr_t; 492 493 typedef struct _nxge_ldgv_t { 494 uint8_t ndma_ldvs; 495 uint8_t nldvs; 496 uint8_t start_ldg; 497 uint8_t start_ldg_tx; 498 uint8_t start_ldg_rx; 499 uint8_t maxldgs; 500 uint8_t maxldvs; 501 uint8_t ldg_intrs; 502 boolean_t own_sys_err; 503 boolean_t own_max_ldv; 504 uint32_t tmres; 505 p_nxge_ldg_t ldgp; 506 p_nxge_ldv_t ldvp; 507 p_nxge_ldv_t ldvp_syserr; 508 } nxge_ldgv_t, *p_nxge_ldgv_t; 509 510 /* 511 * Neptune Device instance state information. 512 * 513 * Each instance is dynamically allocated on first attach. 514 */ 515 struct _nxge_t { 516 dev_info_t *dip; /* device instance */ 517 dev_info_t *p_dip; /* Parent's device instance */ 518 int instance; /* instance number */ 519 int function_num; /* device function number */ 520 int nports; /* # of ports on this device */ 521 int board_ver; /* Board Version */ 522 int partition_id; /* partition ID */ 523 int use_partition; /* partition is enabled */ 524 uint32_t drv_state; /* driver state bit flags */ 525 uint64_t nxge_debug_level; /* driver state bit flags */ 526 kmutex_t genlock[1]; 527 enum nxge_mac_state nxge_mac_state; 528 ddi_softintr_t resched_id; /* reschedule callback */ 529 boolean_t resched_needed; 530 boolean_t resched_running; 531 532 p_dev_regs_t dev_regs; 533 npi_handle_t npi_handle; 534 npi_handle_t npi_pci_handle; 535 npi_handle_t npi_reg_handle; 536 npi_handle_t npi_msi_handle; 537 npi_handle_t npi_vreg_handle; 538 npi_handle_t npi_v2reg_handle; 539 540 nxge_xcvr_table_t xcvr; 541 boolean_t hot_swappable_phy; 542 boolean_t phy_absent; 543 uint32_t xcvr_addr; 544 uint16_t chip_id; 545 nxge_mac_t mac; 546 nxge_ipp_t ipp; 547 nxge_txc_t txc; 548 nxge_classify_t classifier; 549 550 mac_handle_t mach; /* mac module handle */ 551 p_nxge_stats_t statsp; 552 uint32_t param_count; 553 p_nxge_param_t param_arr; 554 nxge_hw_list_t *nxge_hw_p; /* pointer to per Neptune */ 555 niu_type_t niu_type; 556 platform_type_t platform_type; 557 boolean_t os_addr_mode32; /* set to 1 for 32 bit mode */ 558 uint8_t nrdc; 559 uint8_t def_rdc; 560 uint8_t rdc[NXGE_MAX_RDCS]; 561 uint8_t ntdc; 562 uint8_t tdc[NXGE_MAX_TDCS]; 563 564 nxge_intr_t nxge_intr_type; 565 nxge_dma_pt_cfg_t pt_config; 566 nxge_class_pt_cfg_t class_config; 567 568 /* Logical device and group data structures. */ 569 p_nxge_ldgv_t ldgvp; 570 571 npi_vpd_info_t vpd_info; 572 caddr_t param_list; /* Parameter list */ 573 574 ether_addr_st factaddr; /* factory mac address */ 575 ether_addr_st ouraddr; /* individual address */ 576 kmutex_t ouraddr_lock; /* lock to protect to uradd */ 577 578 ddi_iblock_cookie_t interrupt_cookie; 579 580 /* 581 * Blocks of memory may be pre-allocated by the 582 * partition manager or the driver. They may include 583 * blocks for configuration and buffers. The idea is 584 * to preallocate big blocks of contiguous areas in 585 * system memory (i.e. with IOMMU). These blocks then 586 * will be broken up to a fixed number of blocks with 587 * each block having the same block size (4K, 8K, 16K or 588 * 32K) in the case of buffer blocks. For systems that 589 * do not support DVMA, more than one big block will be 590 * allocated. 591 */ 592 uint32_t rx_default_block_size; 593 nxge_rx_block_size_t rx_bksize_code; 594 595 p_nxge_dma_pool_t rx_buf_pool_p; 596 p_nxge_dma_pool_t rx_cntl_pool_p; 597 598 p_nxge_dma_pool_t tx_buf_pool_p; 599 p_nxge_dma_pool_t tx_cntl_pool_p; 600 601 /* Receive buffer block ring and completion ring. */ 602 p_rx_rbr_rings_t rx_rbr_rings; 603 p_rx_rcr_rings_t rx_rcr_rings; 604 p_rx_mbox_areas_t rx_mbox_areas_p; 605 606 p_rx_tx_params_t rx_params; 607 uint32_t start_rdc; 608 uint32_t max_rdcs; 609 uint32_t rdc_mask; 610 611 /* Transmit descriptors rings */ 612 p_tx_rings_t tx_rings; 613 p_tx_mbox_areas_t tx_mbox_areas_p; 614 615 uint32_t start_tdc; 616 uint32_t max_tdcs; 617 uint32_t tdc_mask; 618 619 p_rx_tx_params_t tx_params; 620 621 ddi_dma_handle_t dmasparehandle; 622 623 ulong_t sys_page_sz; 624 ulong_t sys_page_mask; 625 int suspended; 626 627 mii_bmsr_t bmsr; /* xcvr status at last poll. */ 628 mii_bmsr_t soft_bmsr; /* xcvr status kept by SW. */ 629 630 kmutex_t mif_lock; /* Lock to protect the list. */ 631 632 void (*mii_read)(); 633 void (*mii_write)(); 634 void (*mii_poll)(); 635 filter_t filter; /* Current instance filter */ 636 p_hash_filter_t hash_filter; /* Multicast hash filter. */ 637 krwlock_t filter_lock; /* Lock to protect filters. */ 638 639 ulong_t sys_burst_sz; 640 641 uint8_t cache_line; 642 643 timeout_id_t nxge_link_poll_timerid; 644 timeout_id_t nxge_timerid; 645 646 uint_t need_periodic_reclaim; 647 timeout_id_t reclaim_timer; 648 649 uint8_t msg_min; 650 uint8_t crc_size; 651 652 boolean_t hard_props_read; 653 654 boolean_t nxge_htraffic; 655 uint32_t nxge_ncpus; 656 uint32_t nxge_cpumask; 657 uint16_t intr_timeout; 658 uint16_t intr_threshold; 659 uchar_t nxge_rxmode; 660 uint32_t active_threads; 661 662 rtrace_t rtrace; 663 int fm_capabilities; /* FMA capabilities */ 664 665 uint32_t nxge_port_rbr_size; 666 uint32_t nxge_port_rcr_size; 667 uint32_t nxge_port_tx_ring_size; 668 nxge_mmac_t nxge_mmac_info; 669 #if defined(sun4v) 670 boolean_t niu_hsvc_available; 671 hsvc_info_t niu_hsvc; 672 uint64_t niu_min_ver; 673 #endif 674 boolean_t link_notify; 675 676 kmutex_t poll_lock; 677 kcondvar_t poll_cv; 678 link_mon_enable_t poll_state; 679 #define NXGE_MAGIC 0x3ab434e3 680 uint32_t nxge_magic; 681 682 int soft_lso_enable; 683 }; 684 685 /* 686 * Driver state flags. 687 */ 688 #define STATE_REGS_MAPPED 0x000000001 /* device registers mapped */ 689 #define STATE_KSTATS_SETUP 0x000000002 /* kstats allocated */ 690 #define STATE_NODE_CREATED 0x000000004 /* device node created */ 691 #define STATE_HW_CONFIG_CREATED 0x000000008 /* hardware properties */ 692 #define STATE_HW_INITIALIZED 0x000000010 /* hardware initialized */ 693 #define STATE_MDIO_LOCK_INIT 0x000000020 /* mdio lock initialized */ 694 #define STATE_MII_LOCK_INIT 0x000000040 /* mii lock initialized */ 695 696 #define STOP_POLL_THRESH 9 697 #define START_POLL_THRESH 2 698 699 typedef struct _nxge_port_kstat_t { 700 /* 701 * Transciever state informations. 702 */ 703 kstat_named_t xcvr_inits; 704 kstat_named_t xcvr_inuse; 705 kstat_named_t xcvr_addr; 706 kstat_named_t xcvr_id; 707 kstat_named_t cap_autoneg; 708 kstat_named_t cap_10gfdx; 709 kstat_named_t cap_10ghdx; 710 kstat_named_t cap_1000fdx; 711 kstat_named_t cap_1000hdx; 712 kstat_named_t cap_100T4; 713 kstat_named_t cap_100fdx; 714 kstat_named_t cap_100hdx; 715 kstat_named_t cap_10fdx; 716 kstat_named_t cap_10hdx; 717 kstat_named_t cap_asmpause; 718 kstat_named_t cap_pause; 719 720 /* 721 * Link partner capabilities. 722 */ 723 kstat_named_t lp_cap_autoneg; 724 kstat_named_t lp_cap_10gfdx; 725 kstat_named_t lp_cap_10ghdx; 726 kstat_named_t lp_cap_1000fdx; 727 kstat_named_t lp_cap_1000hdx; 728 kstat_named_t lp_cap_100T4; 729 kstat_named_t lp_cap_100fdx; 730 kstat_named_t lp_cap_100hdx; 731 kstat_named_t lp_cap_10fdx; 732 kstat_named_t lp_cap_10hdx; 733 kstat_named_t lp_cap_asmpause; 734 kstat_named_t lp_cap_pause; 735 736 /* 737 * Shared link setup. 738 */ 739 kstat_named_t link_T4; 740 kstat_named_t link_speed; 741 kstat_named_t link_duplex; 742 kstat_named_t link_asmpause; 743 kstat_named_t link_pause; 744 kstat_named_t link_up; 745 746 /* 747 * Lets the user know the MTU currently in use by 748 * the physical MAC port. 749 */ 750 kstat_named_t mac_mtu; 751 kstat_named_t lb_mode; 752 kstat_named_t qos_mode; 753 kstat_named_t trunk_mode; 754 755 /* 756 * Misc MAC statistics. 757 */ 758 kstat_named_t ifspeed; 759 kstat_named_t promisc; 760 kstat_named_t rev_id; 761 762 /* 763 * Some statistics added to support bringup, these 764 * should be removed. 765 */ 766 kstat_named_t user_defined; 767 } nxge_port_kstat_t, *p_nxge_port_kstat_t; 768 769 typedef struct _nxge_rdc_kstat { 770 /* 771 * Receive DMA channel statistics. 772 */ 773 kstat_named_t ipackets; 774 kstat_named_t rbytes; 775 kstat_named_t errors; 776 kstat_named_t dcf_err; 777 kstat_named_t rcr_ack_err; 778 779 kstat_named_t dc_fifoflow_err; 780 kstat_named_t rcr_sha_par_err; 781 kstat_named_t rbr_pre_par_err; 782 kstat_named_t wred_drop; 783 kstat_named_t rbr_pre_emty; 784 785 kstat_named_t rcr_shadow_full; 786 kstat_named_t rbr_tmout; 787 kstat_named_t rsp_cnt_err; 788 kstat_named_t byte_en_bus; 789 kstat_named_t rsp_dat_err; 790 791 kstat_named_t pkt_too_long_err; 792 kstat_named_t compl_l2_err; 793 kstat_named_t compl_l4_cksum_err; 794 kstat_named_t compl_zcp_soft_err; 795 kstat_named_t compl_fflp_soft_err; 796 kstat_named_t config_err; 797 798 kstat_named_t rcrincon; 799 kstat_named_t rcrfull; 800 kstat_named_t rbr_empty; 801 kstat_named_t rbrfull; 802 kstat_named_t rbrlogpage; 803 804 kstat_named_t cfiglogpage; 805 kstat_named_t port_drop_pkt; 806 kstat_named_t rcr_to; 807 kstat_named_t rcr_thresh; 808 kstat_named_t rcr_mex; 809 kstat_named_t id_mismatch; 810 kstat_named_t zcp_eop_err; 811 kstat_named_t ipp_eop_err; 812 } nxge_rdc_kstat_t, *p_nxge_rdc_kstat_t; 813 814 typedef struct _nxge_rdc_sys_kstat { 815 /* 816 * Receive DMA system statistics. 817 */ 818 kstat_named_t pre_par; 819 kstat_named_t sha_par; 820 kstat_named_t id_mismatch; 821 kstat_named_t ipp_eop_err; 822 kstat_named_t zcp_eop_err; 823 } nxge_rdc_sys_kstat_t, *p_nxge_rdc_sys_kstat_t; 824 825 typedef struct _nxge_tdc_kstat { 826 /* 827 * Transmit DMA channel statistics. 828 */ 829 kstat_named_t opackets; 830 kstat_named_t obytes; 831 kstat_named_t oerrors; 832 kstat_named_t tx_inits; 833 kstat_named_t tx_no_buf; 834 835 kstat_named_t mbox_err; 836 kstat_named_t pkt_size_err; 837 kstat_named_t tx_ring_oflow; 838 kstat_named_t pref_buf_ecc_err; 839 kstat_named_t nack_pref; 840 kstat_named_t nack_pkt_rd; 841 kstat_named_t conf_part_err; 842 kstat_named_t pkt_prt_err; 843 kstat_named_t reset_fail; 844 /* used to in the common (per port) counter */ 845 846 kstat_named_t tx_starts; 847 kstat_named_t tx_nocanput; 848 kstat_named_t tx_msgdup_fail; 849 kstat_named_t tx_allocb_fail; 850 kstat_named_t tx_no_desc; 851 kstat_named_t tx_dma_bind_fail; 852 kstat_named_t tx_uflo; 853 kstat_named_t tx_hdr_pkts; 854 kstat_named_t tx_ddi_pkts; 855 kstat_named_t tx_dvma_pkts; 856 kstat_named_t tx_max_pend; 857 } nxge_tdc_kstat_t, *p_nxge_tdc_kstat_t; 858 859 typedef struct _nxge_txc_kstat { 860 /* 861 * Transmit port TXC block statistics. 862 */ 863 kstat_named_t pkt_stuffed; 864 kstat_named_t pkt_xmit; 865 kstat_named_t ro_correct_err; 866 kstat_named_t ro_uncorrect_err; 867 kstat_named_t sf_correct_err; 868 kstat_named_t sf_uncorrect_err; 869 kstat_named_t address_failed; 870 kstat_named_t dma_failed; 871 kstat_named_t length_failed; 872 kstat_named_t pkt_assy_dead; 873 kstat_named_t reorder_err; 874 } nxge_txc_kstat_t, *p_nxge_txc_kstat_t; 875 876 typedef struct _nxge_ipp_kstat { 877 /* 878 * Receive port IPP block statistics. 879 */ 880 kstat_named_t eop_miss; 881 kstat_named_t sop_miss; 882 kstat_named_t dfifo_ue; 883 kstat_named_t ecc_err_cnt; 884 kstat_named_t pfifo_perr; 885 kstat_named_t pfifo_over; 886 kstat_named_t pfifo_und; 887 kstat_named_t bad_cs_cnt; 888 kstat_named_t pkt_dis_cnt; 889 } nxge_ipp_kstat_t, *p_nxge_ipp_kstat_t; 890 891 typedef struct _nxge_zcp_kstat { 892 /* 893 * ZCP statistics. 894 */ 895 kstat_named_t errors; 896 kstat_named_t inits; 897 kstat_named_t rrfifo_underrun; 898 kstat_named_t rrfifo_overrun; 899 kstat_named_t rspfifo_uncorr_err; 900 kstat_named_t buffer_overflow; 901 kstat_named_t stat_tbl_perr; 902 kstat_named_t dyn_tbl_perr; 903 kstat_named_t buf_tbl_perr; 904 kstat_named_t tt_program_err; 905 kstat_named_t rsp_tt_index_err; 906 kstat_named_t slv_tt_index_err; 907 kstat_named_t zcp_tt_index_err; 908 kstat_named_t access_fail; 909 kstat_named_t cfifo_ecc; 910 } nxge_zcp_kstat_t, *p_nxge_zcp_kstat_t; 911 912 typedef struct _nxge_mac_kstat { 913 /* 914 * Transmit MAC statistics. 915 */ 916 kstat_named_t tx_frame_cnt; 917 kstat_named_t tx_underflow_err; 918 kstat_named_t tx_overflow_err; 919 kstat_named_t tx_maxpktsize_err; 920 kstat_named_t tx_fifo_xfr_err; 921 kstat_named_t tx_byte_cnt; 922 923 /* 924 * Receive MAC statistics. 925 */ 926 kstat_named_t rx_frame_cnt; 927 kstat_named_t rx_underflow_err; 928 kstat_named_t rx_overflow_err; 929 kstat_named_t rx_len_err_cnt; 930 kstat_named_t rx_crc_err_cnt; 931 kstat_named_t rx_viol_err_cnt; 932 kstat_named_t rx_byte_cnt; 933 kstat_named_t rx_hist1_cnt; 934 kstat_named_t rx_hist2_cnt; 935 kstat_named_t rx_hist3_cnt; 936 kstat_named_t rx_hist4_cnt; 937 kstat_named_t rx_hist5_cnt; 938 kstat_named_t rx_hist6_cnt; 939 kstat_named_t rx_hist7_cnt; 940 kstat_named_t rx_broadcast_cnt; 941 kstat_named_t rx_mult_cnt; 942 kstat_named_t rx_frag_cnt; 943 kstat_named_t rx_frame_align_err_cnt; 944 kstat_named_t rx_linkfault_err_cnt; 945 kstat_named_t rx_local_fault_err_cnt; 946 kstat_named_t rx_remote_fault_err_cnt; 947 } nxge_mac_kstat_t, *p_nxge_mac_kstat_t; 948 949 typedef struct _nxge_xmac_kstat { 950 /* 951 * XMAC statistics. 952 */ 953 kstat_named_t tx_frame_cnt; 954 kstat_named_t tx_underflow_err; 955 kstat_named_t tx_maxpktsize_err; 956 kstat_named_t tx_overflow_err; 957 kstat_named_t tx_fifo_xfr_err; 958 kstat_named_t tx_byte_cnt; 959 kstat_named_t rx_frame_cnt; 960 kstat_named_t rx_underflow_err; 961 kstat_named_t rx_overflow_err; 962 kstat_named_t rx_crc_err_cnt; 963 kstat_named_t rx_len_err_cnt; 964 kstat_named_t rx_viol_err_cnt; 965 kstat_named_t rx_byte_cnt; 966 kstat_named_t rx_hist1_cnt; 967 kstat_named_t rx_hist2_cnt; 968 kstat_named_t rx_hist3_cnt; 969 kstat_named_t rx_hist4_cnt; 970 kstat_named_t rx_hist5_cnt; 971 kstat_named_t rx_hist6_cnt; 972 kstat_named_t rx_hist7_cnt; 973 kstat_named_t rx_broadcast_cnt; 974 kstat_named_t rx_mult_cnt; 975 kstat_named_t rx_frag_cnt; 976 kstat_named_t rx_frame_align_err_cnt; 977 kstat_named_t rx_linkfault_err_cnt; 978 kstat_named_t rx_remote_fault_err_cnt; 979 kstat_named_t rx_local_fault_err_cnt; 980 kstat_named_t rx_pause_cnt; 981 kstat_named_t xpcs_deskew_err_cnt; 982 kstat_named_t xpcs_ln0_symbol_err_cnt; 983 kstat_named_t xpcs_ln1_symbol_err_cnt; 984 kstat_named_t xpcs_ln2_symbol_err_cnt; 985 kstat_named_t xpcs_ln3_symbol_err_cnt; 986 } nxge_xmac_kstat_t, *p_nxge_xmac_kstat_t; 987 988 typedef struct _nxge_bmac_kstat { 989 /* 990 * BMAC statistics. 991 */ 992 kstat_named_t tx_frame_cnt; 993 kstat_named_t tx_underrun_err; 994 kstat_named_t tx_max_pkt_err; 995 kstat_named_t tx_byte_cnt; 996 kstat_named_t rx_frame_cnt; 997 kstat_named_t rx_byte_cnt; 998 kstat_named_t rx_overflow_err; 999 kstat_named_t rx_align_err_cnt; 1000 kstat_named_t rx_crc_err_cnt; 1001 kstat_named_t rx_len_err_cnt; 1002 kstat_named_t rx_viol_err_cnt; 1003 kstat_named_t rx_pause_cnt; 1004 kstat_named_t tx_pause_state; 1005 kstat_named_t tx_nopause_state; 1006 } nxge_bmac_kstat_t, *p_nxge_bmac_kstat_t; 1007 1008 1009 typedef struct _nxge_fflp_kstat { 1010 /* 1011 * FFLP statistics. 1012 */ 1013 1014 kstat_named_t fflp_tcam_perr; 1015 kstat_named_t fflp_tcam_ecc_err; 1016 kstat_named_t fflp_vlan_perr; 1017 kstat_named_t fflp_hasht_lookup_err; 1018 kstat_named_t fflp_hasht_data_err[MAX_PARTITION]; 1019 } nxge_fflp_kstat_t, *p_nxge_fflp_kstat_t; 1020 1021 typedef struct _nxge_mmac_kstat { 1022 kstat_named_t mmac_max_addr_cnt; 1023 kstat_named_t mmac_avail_addr_cnt; 1024 kstat_named_t mmac_addr1; 1025 kstat_named_t mmac_addr2; 1026 kstat_named_t mmac_addr3; 1027 kstat_named_t mmac_addr4; 1028 kstat_named_t mmac_addr5; 1029 kstat_named_t mmac_addr6; 1030 kstat_named_t mmac_addr7; 1031 kstat_named_t mmac_addr8; 1032 kstat_named_t mmac_addr9; 1033 kstat_named_t mmac_addr10; 1034 kstat_named_t mmac_addr11; 1035 kstat_named_t mmac_addr12; 1036 kstat_named_t mmac_addr13; 1037 kstat_named_t mmac_addr14; 1038 kstat_named_t mmac_addr15; 1039 kstat_named_t mmac_addr16; 1040 } nxge_mmac_kstat_t, *p_nxge_mmac_kstat_t; 1041 1042 #endif /* _KERNEL */ 1043 1044 /* 1045 * Prototype definitions. 1046 */ 1047 nxge_status_t nxge_init(p_nxge_t); 1048 void nxge_uninit(p_nxge_t); 1049 void nxge_get64(p_nxge_t, p_mblk_t); 1050 void nxge_put64(p_nxge_t, p_mblk_t); 1051 void nxge_pio_loop(p_nxge_t, p_mblk_t); 1052 1053 #ifndef COSIM 1054 typedef void (*fptrv_t)(); 1055 timeout_id_t nxge_start_timer(p_nxge_t, fptrv_t, int); 1056 void nxge_stop_timer(p_nxge_t, timeout_id_t); 1057 #endif 1058 #endif 1059 1060 #ifdef __cplusplus 1061 } 1062 #endif 1063 1064 #endif /* _SYS_NXGE_NXGE_H */ 1065