1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 1998 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* Copyright (c) 1990, 1991 UNIX System Laboratories, Inc. */ 28 /* Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T */ 29 /* All Rights Reserved */ 30 31 /* Copyright (c) 1988, 1989 Intel Corp. */ 32 /* All Rights Reserved */ 33 34 #ifndef _SYS_DMAENGINE_H 35 #define _SYS_DMAENGINE_H 36 37 #pragma ident "%Z%%M% %I% %E% SMI" 38 39 #include <sys/types.h> 40 #include <sys/dditypes.h> 41 42 #ifdef __cplusplus 43 extern "C" { 44 #endif 45 46 #define NCHANS 8 47 48 /* 49 * the DMA Engine Request structure 50 */ 51 struct ddi_dmae_req { 52 dev_info_t *der_rdip; /* original requester's dev_info_t */ 53 uchar_t der_command; /* Read/Write/Translate/Verify */ 54 uchar_t der_bufprocess; /* NoAuto_init/Chain/Auto_init */ 55 uchar_t der_step; /* Inc / Dec / Hold */ 56 uchar_t der_trans; /* Single/Demand/Block/Cascade */ 57 uchar_t der_path; /* 8/16/32 */ 58 uchar_t der_cycles; /* 1 or 2 */ 59 uchar_t der_dest; /* Memory / IO */ 60 uchar_t der_arbus; /* MicroChannel arbitration reg */ 61 ushort_t der_ioadr; /* MicroChannel i/o address reg */ 62 ddi_dma_cookie_t *(*proc)(); /* address of application call routine */ 63 void *procparms; /* parameter buffer for appl call */ 64 }; 65 66 #define DMAE_CMD_VRFY 0 67 #define DMAE_CMD_WRITE 1 /* from memory to device */ 68 #define DMAE_CMD_READ 2 /* from device to memory */ 69 #define DMAE_CMD_TRAN 3 70 71 #define DMAE_BUF_NOAUTO 0 /* default */ 72 #define DMAE_BUF_CHAIN 0x1 73 #define DMAE_BUF_AUTO 0x2 74 75 #define DMAE_STEP_INC 0 /* default */ 76 #define DMAE_STEP_DEC 1 77 #define DMAE_STEP_HOLD 2 78 79 #define DMAE_TRANS_SNGL 0 /* default */ 80 #define DMAE_TRANS_BLCK 1 81 #define DMAE_TRANS_DMND 2 82 #define DMAE_TRANS_CSCD 3 83 84 85 /* 86 * For the EISA bus 87 */ 88 #define DMAE_PATH_DEF 0 /* default to ISA xfer width */ 89 #define DMAE_PATH_8 1 /* ISA default for chnl 0..3 */ 90 #define DMAE_PATH_16 2 /* ISA default for chnl 5..7 */ 91 #define DMAE_PATH_32 3 92 #define DMAE_PATH_64 4 93 #define DMAE_PATH_16B 5 /* 16-bit path but byte count */ 94 95 #define DMAE_CYCLES_1 0 /* Compatible timing */ 96 #define DMAE_CYCLES_2 1 /* Type "A" timing */ 97 #define DMAE_CYCLES_3 2 /* Type "B" timing */ 98 #define DMAE_CYCLES_4 3 /* Burst timing */ 99 100 #define DMAE_DEST_IO 0 /* default */ 101 #define DMAE_DEST_MEM 1 102 103 104 105 /* public function routines */ 106 extern int i_dmae_init(dev_info_t *); 107 extern ddi_dma_cookie_t *_dmae_nxcookie(int); 108 extern int i_dmae_acquire(dev_info_t *, int, int (*)(), caddr_t); 109 extern int i_dmae_free(dev_info_t *, int); 110 extern int i_dmae_prog(dev_info_t *, struct ddi_dmae_req *, 111 ddi_dma_cookie_t *, int); 112 extern int i_dmae_swsetup(dev_info_t *, struct ddi_dmae_req *, 113 ddi_dma_cookie_t *, int); 114 extern void i_dmae_swstart(dev_info_t *, int); 115 extern void i_dmae_stop(dev_info_t *, int); 116 extern void i_dmae_enable(dev_info_t *, int); 117 extern void i_dmae_disable(dev_info_t *, int); 118 extern void i_dmae_get_chan_stat(dev_info_t *dip, int chnl, 119 ulong_t *addressp, int *countp); 120 121 /* 122 * the DMA Channel Block structure 123 */ 124 struct dmae_chnl { 125 ksema_t dch_lock; /* semaphore for this channel */ 126 ddi_dma_cookie_t *dch_cookiep; /* current dma mapping cookie */ 127 ddi_dma_cookie_t *(*proc)(); /* address of application call */ 128 /* routine */ 129 void *procparms; /* parameter buffer for appl call */ 130 }; 131 132 133 /* 134 * DMA Engine DDI functions 135 */ 136 137 /* 138 * Get DMA engine limits 139 * 140 * The limits of the DMA engine of the parent bus-nexus are copied into the 141 * provided structure. This should be called at driver attach time, 142 * rather than for each dma setup (breakup). 143 */ 144 145 int ddi_dmae_getlim(dev_info_t *dip, ddi_dma_lim_t *limitsp); 146 147 /* 148 * Get DMA engine attributes 149 * 150 * The attributes of the DMA engine of the parent bus-nexus are copied into 151 * the provided structure. This should be called at driver attach time, 152 * rather than for each DMA bind. 153 */ 154 155 int ddi_dmae_getattr(dev_info_t *dip, ddi_dma_attr_t *attrp); 156 157 /* 158 * DMA channel allocation 159 * 160 * The allocation function must be called prior to any other DMA engine 161 * function on a channel. The channel should be freed after completion of the 162 * DMA / device operation if the channel is to be shared. 163 * 164 * Specifics of arguments to ddi_dmae_alloc: 165 * 166 * dip - dev_info pointer, which identifies the base device that wishes 167 * to use the DMA channel. 168 * 169 * chnl - a DMA channel number. 170 * 171 * dmae_waitfp - wait/callback_function pointer, which operates in the same 172 * manner as in ddi_dma_setup(). The value DDI_DMA_DONTWAIT will cause an 173 * immediate return if the channel cannot be acquired. The value 174 * DDI_DMA_SLEEP will will cause the thread to sleep and not return until 175 * the channel has been acquired. Any other value is assumed to be a 176 * callback function address. 177 * 178 * When resources might be available, the callback function is called 179 * (with the argument specified in arg) from interrupt context. 180 * 181 * When the callback function dmae_waitfp() is called, it should attempt to 182 * allocate the DMA channel again. If it succeeds or does not need the 183 * channel any more, it must return the value DDI_DMA_CALLBACK_DONE. 184 * If it does not want to allocate the channel, but instead wishes to be 185 * called back again later, it must return the value DDI_DMA_CALLBACK_LATER. 186 * If it tries to allocate the channel, but fails to do so, it must return the 187 * value DDI_DMA_CALLBACK_RUNOUT. 188 * 189 * Failure to observe this protocol will have unpredictable results. 190 * 191 * The callback function must provide its own data structure integrity 192 * when it is invoked. 193 */ 194 195 int ddi_dmae_alloc(dev_info_t *dip, int chnl, int (*dmae_waitfp)(), 196 caddr_t arg); 197 198 /* 199 * DMA channel deallocation 200 * 201 * The deallocation function should be called after completion of the 202 * DMA / device operation if the channel is to be shared. 203 */ 204 205 int ddi_dmae_release(dev_info_t *dip, int chnl); 206 207 /* 208 * DMA channel used in 1st party DMA scheme 209 * 210 * The specified channel will be configured to operate in a "slave" mode 211 * to a first_party DMA engine that also uses the channel. 212 */ 213 214 int ddi_dmae_1stparty(dev_info_t *dip, int chnl); 215 216 /* 217 * Program DMA channel 218 * 219 * The DMA channel is setup for an operation using ddi_dmae_prog(). 220 * This function is implemented to access all capabilities of the DMA engine 221 * hardware. This function disables the channel prior to setup, and enables 222 * the channel before returning. 223 * 224 * Specifics of arguments to ddi_dmae_prog: 225 * 226 * dmaereqp - pointer to a DMA engine request structure. This structure 227 * is implementation specific and contains all the info necessary to 228 * setup the channel, except for the memory address and count. 229 * This structure is implemented with default values equal to zero, 230 * so that normally only der_command has to be set with a read or write 231 * command value. Once the channel has been setup, subsequent calls to 232 * ddi_dmae_prog() can have dmaereqp set to NULL if only the address and 233 * count have to be updated. 234 * 235 * cookiep - pointer to a ddi_dma_cookie object obtained from 236 * ddi_dma_segtocookie(), which contains address, count and intermediate 237 * memory mapping information. 238 */ 239 240 int ddi_dmae_prog(dev_info_t *dip, struct ddi_dmae_req *dmaereqp, 241 ddi_dma_cookie_t *cookiep, int chnl); 242 243 int ddi_dmae_swsetup(dev_info_t *dip, struct ddi_dmae_req *dmaereqp, 244 ddi_dma_cookie_t *cookiep, int chnl); 245 246 int ddi_dmae_swstart(dev_info_t *dip, int chnl); 247 248 /* 249 * Stop DMA channel 250 * 251 * The DMA channel is disabled and any active operation is terminated. 252 */ 253 254 int ddi_dmae_stop(dev_info_t *dip, int chnl); 255 256 /* 257 * Enable DMA channel 258 * 259 * The DMA channel is enabled for operation. The channel is also enabled 260 * after successful setup in ddi_dmae_prog(). 261 */ 262 263 int ddi_dmae_enable(dev_info_t *dip, int chnl); 264 265 /* 266 * Disable DMA channel 267 * 268 * The DMA channel is disabled so that transfers cannot continue. 269 */ 270 271 int ddi_dmae_disable(dev_info_t *dip, int chnl); 272 273 /* 274 * Get remaining xfer count 275 * 276 * The count register of the DMA channel is read. The channel is assumed 277 * to be stopped. 278 */ 279 280 int ddi_dmae_getcnt(dev_info_t *dip, int chnl, int *count); 281 282 #ifdef __cplusplus 283 } 284 #endif 285 286 #endif /* !_SYS_DMAENGINE_H */ 287