1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_DDI_INTR_IMPL_H 28 #define _SYS_DDI_INTR_IMPL_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 /* 33 * Sun DDI interrupt implementation specific definitions 34 */ 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 #ifdef _KERNEL 41 42 /* 43 * Typedef for interrupt ops 44 */ 45 typedef enum { 46 DDI_INTROP_SUPPORTED_TYPES = 1, /* 1 get supported interrupts types */ 47 DDI_INTROP_NINTRS, /* 2 get num of interrupts supported */ 48 DDI_INTROP_ALLOC, /* 3 allocate interrupt handle */ 49 DDI_INTROP_GETPRI, /* 4 get priority */ 50 DDI_INTROP_SETPRI, /* 5 set priority */ 51 DDI_INTROP_ADDISR, /* 6 add interrupt handler */ 52 DDI_INTROP_DUPVEC, /* 7 duplicate interrupt handler */ 53 DDI_INTROP_ENABLE, /* 8 enable interrupt */ 54 DDI_INTROP_BLOCKENABLE, /* 9 block enable interrupts */ 55 DDI_INTROP_BLOCKDISABLE, /* 10 block disable interrupts */ 56 DDI_INTROP_DISABLE, /* 11 disable interrupt */ 57 DDI_INTROP_REMISR, /* 12 remove interrupt handler */ 58 DDI_INTROP_FREE, /* 13 free interrupt handle */ 59 DDI_INTROP_GETCAP, /* 14 get capacity */ 60 DDI_INTROP_SETCAP, /* 15 set capacity */ 61 DDI_INTROP_SETMASK, /* 16 set mask */ 62 DDI_INTROP_CLRMASK, /* 17 clear mask */ 63 DDI_INTROP_GETPENDING, /* 18 get pending interrupt */ 64 DDI_INTROP_NAVAIL /* 19 get num of available interrupts */ 65 } ddi_intr_op_t; 66 67 /* Version number used in the handles */ 68 #define DDI_INTR_VERSION_1 1 69 #define DDI_INTR_VERSION DDI_INTR_VERSION_1 70 71 /* 72 * One such data structure is allocated per ddi_intr_handle_t 73 * This is the incore copy of the regular interrupt info. 74 */ 75 typedef struct ddi_intr_handle_impl { 76 dev_info_t *ih_dip; /* dip associated with handle */ 77 uint16_t ih_type; /* interrupt type being used */ 78 ushort_t ih_inum; /* interrupt number */ 79 uint32_t ih_vector; /* vector number */ 80 uint16_t ih_ver; /* Version */ 81 uint_t ih_state; /* interrupt handle state */ 82 uint_t ih_cap; /* interrupt capabilities */ 83 uint_t ih_pri; /* priority - bus dependent */ 84 krwlock_t ih_rwlock; /* read/write lock per handle */ 85 86 uint_t (*ih_cb_func)(caddr_t, caddr_t); 87 void *ih_cb_arg1; 88 void *ih_cb_arg2; 89 90 /* 91 * The next set of members are for 'scratch' purpose only. 92 * The DDI interrupt framework uses them internally and their 93 * interpretation is left to the framework. For now, 94 * scratch1 - used to send NINTRs information 95 * to various nexus drivers. 96 * scratch2 - used to send 'behavior' flag 97 * information to the nexus drivers 98 * from ddi_intr_alloc() 99 * private - On X86 it usually carries a pointer to 100 * ihdl_plat_t. Not used on SPARC platforms. 101 */ 102 void *ih_private; /* Platform specific data */ 103 uint_t ih_scratch1; /* Scratch1: #interrupts */ 104 uint_t ih_scratch2; /* Scratch2: flag */ 105 } ddi_intr_handle_impl_t; 106 107 /* values for ih_state (strictly for interrupt handle) */ 108 #define DDI_IHDL_STATE_ALLOC 0x01 /* Allocated. ddi_intr_alloc() called */ 109 #define DDI_IHDL_STATE_ADDED 0x02 /* Added interrupt handler */ 110 /* ddi_intr_add_handler() called */ 111 #define DDI_IHDL_STATE_ENABLE 0x04 /* Enabled. ddi_intr_enable() called */ 112 113 #define DDI_INTR_IS_MSI_OR_MSIX(type) \ 114 ((type) == DDI_INTR_TYPE_MSI || (type) == DDI_INTR_TYPE_MSIX) 115 116 #define DDI_INTR_SUP_TYPES DDI_INTR_TYPE_FIXED|DDI_INTR_TYPE_MSI|\ 117 DDI_INTR_TYPE_MSIX 118 119 struct av_softinfo; 120 121 /* 122 * One such data structure is allocated per ddi_soft_intr_handle 123 * This is the incore copy of the softint info. 124 */ 125 typedef struct ddi_softint_hdl_impl { 126 dev_info_t *ih_dip; /* dip associated with handle */ 127 uint_t ih_pri; /* priority - bus dependent */ 128 krwlock_t ih_rwlock; /* read/write lock per handle */ 129 struct av_softinfo *ih_pending; /* whether softint is pending */ 130 131 uint_t (*ih_cb_func)(caddr_t, caddr_t); 132 /* cb function for soft ints */ 133 void *ih_cb_arg1; /* arg1 of callback function */ 134 void *ih_cb_arg2; /* arg2 passed to "trigger" */ 135 136 /* 137 * The next member is for 'scratch' purpose only. 138 * The DDI interrupt framework uses it internally and its 139 * interpretation is left to the framework. 140 * private - used by the DDI framework to pass back 141 * and forth 'softid' information on SPARC 142 * side only. Not used on X86 platform. 143 */ 144 void *ih_private; /* Platform specific data */ 145 } ddi_softint_hdl_impl_t; 146 147 /* Softint internal implementation defines */ 148 #define DDI_SOFT_INTR_PRI_M 4 149 #define DDI_SOFT_INTR_PRI_H 6 150 151 /* 152 * One such data structure is allocated for MSI-X enabled 153 * device. If no MSI-X is enabled then it is NULL 154 */ 155 typedef struct ddi_intr_msix { 156 uint_t msix_intrs_in_use; /* MSI-X intrs in use */ 157 158 /* MSI-X Table related information */ 159 ddi_acc_handle_t msix_tbl_hdl; /* MSI-X table handle */ 160 uint32_t *msix_tbl_addr; /* MSI-X table addr */ 161 uint32_t msix_tbl_offset; /* MSI-X table offset */ 162 163 /* MSI-X PBA Table related information */ 164 ddi_acc_handle_t msix_pba_hdl; /* MSI-X PBA handle */ 165 uint32_t *msix_pba_addr; /* MSI-X PBA addr */ 166 uint32_t msix_pba_offset; /* MSI-X PBA offset */ 167 168 ddi_device_acc_attr_t msix_dev_attr; /* MSI-X device attr */ 169 } ddi_intr_msix_t; 170 171 172 /* 173 * One such data structure is allocated for each dip. 174 * It has interrupt related information that can be 175 * stored/retrieved for convenience. 176 */ 177 typedef struct devinfo_intr { 178 /* These three fields show what the device is capable of */ 179 uint_t devi_intr_sup_types; /* Intrs supported by device */ 180 181 ddi_intr_msix_t *devi_msix_p; /* MSI-X info, if supported */ 182 183 /* Next three fields show current status for the device */ 184 uint_t devi_intr_curr_type; /* Interrupt type being used */ 185 uint_t devi_intr_sup_nintrs; /* #intr supported */ 186 uint_t devi_intr_curr_nintrs; /* #intr currently being used */ 187 188 ddi_intr_handle_t **devi_intr_handle_p; /* Hdl for legacy intr APIs */ 189 } devinfo_intr_t; 190 191 #define NEXUS_HAS_INTR_OP(dip) \ 192 ((DEVI(dip)->devi_ops->devo_bus_ops) && \ 193 (DEVI(dip)->devi_ops->devo_bus_ops->busops_rev >= BUSO_REV_9) && \ 194 (DEVI(dip)->devi_ops->devo_bus_ops->bus_intr_op)) 195 196 int i_ddi_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t op, 197 ddi_intr_handle_impl_t *hdlp, void *result); 198 199 int i_ddi_add_softint(ddi_softint_hdl_impl_t *); 200 void i_ddi_remove_softint(ddi_softint_hdl_impl_t *); 201 int i_ddi_trigger_softint(ddi_softint_hdl_impl_t *, void *); 202 int i_ddi_set_softint_pri(ddi_softint_hdl_impl_t *, uint_t); 203 204 void i_ddi_intr_devi_init(dev_info_t *dip); 205 void i_ddi_intr_devi_fini(dev_info_t *dip); 206 207 uint_t i_ddi_intr_get_supported_types(dev_info_t *dip); 208 void i_ddi_intr_set_supported_types(dev_info_t *dip, int sup_type); 209 uint_t i_ddi_intr_get_current_type(dev_info_t *dip); 210 void i_ddi_intr_set_current_type(dev_info_t *dip, int intr_type); 211 uint_t i_ddi_intr_get_supported_nintrs(dev_info_t *dip, int intr_type); 212 void i_ddi_intr_set_supported_nintrs(dev_info_t *dip, int nintrs); 213 uint_t i_ddi_intr_get_current_nintrs(dev_info_t *dip); 214 void i_ddi_intr_set_current_nintrs(dev_info_t *dip, int nintrs); 215 216 ddi_intr_handle_t *i_ddi_get_intr_handle(dev_info_t *dip, int inum); 217 void i_ddi_set_intr_handle(dev_info_t *dip, int inum, 218 ddi_intr_handle_t *hdlp); 219 220 ddi_intr_msix_t *i_ddi_get_msix(dev_info_t *dip); 221 void i_ddi_set_msix(dev_info_t *dip, ddi_intr_msix_t *msix_p); 222 223 int32_t i_ddi_get_intr_weight(dev_info_t *); 224 int32_t i_ddi_set_intr_weight(dev_info_t *, int32_t); 225 226 void i_ddi_alloc_intr_phdl(ddi_intr_handle_impl_t *); 227 void i_ddi_free_intr_phdl(ddi_intr_handle_impl_t *); 228 229 #define DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, func, arg1, arg2) \ 230 hdlp->ih_cb_func = func; \ 231 hdlp->ih_cb_arg1 = arg1; \ 232 hdlp->ih_cb_arg2 = arg2; 233 234 #else /* _KERNEL */ 235 236 typedef struct devinfo_intr devinfo_intr_t; 237 238 #endif /* _KERNEL */ 239 240 /* 241 * Used only by old DDI interrupt interfaces. 242 */ 243 244 /* 245 * This structure represents one interrupt possible from the given 246 * device. It is used in an array for devices with multiple interrupts. 247 */ 248 struct intrspec { 249 uint_t intrspec_pri; /* interrupt priority */ 250 uint_t intrspec_vec; /* vector # (0 if none) */ 251 uint_t (*intrspec_func)(); /* function to call for interrupt, */ 252 /* If (uint_t (*)()) 0, none. */ 253 /* If (uint_t (*)()) 1, then */ 254 }; 255 256 #ifdef _KERNEL 257 258 /* 259 * NOTE: 260 * The following 4 busops entry points are obsoleted with version 261 * 9 or greater. Use i_ddi_intr_op interface in place of these 262 * obsolete interfaces. 263 * 264 * Remove these busops entry points and all related data structures 265 * in future minor/major solaris release. 266 */ 267 typedef enum {DDI_INTR_CTLOPS_NONE} ddi_intr_ctlop_t; 268 269 /* The following are the obsolete interfaces */ 270 ddi_intrspec_t i_ddi_get_intrspec(dev_info_t *dip, dev_info_t *rdip, 271 uint_t inumber); 272 273 int i_ddi_add_intrspec(dev_info_t *dip, dev_info_t *rdip, 274 ddi_intrspec_t intrspec, ddi_iblock_cookie_t *iblock_cookiep, 275 ddi_idevice_cookie_t *idevice_cookiep, 276 uint_t (*int_handler)(caddr_t int_handler_arg), 277 caddr_t int_handler_arg, int kind); 278 279 void i_ddi_remove_intrspec(dev_info_t *dip, dev_info_t *rdip, 280 ddi_intrspec_t intrspec, ddi_iblock_cookie_t iblock_cookie); 281 282 int i_ddi_intr_ctlops(dev_info_t *dip, dev_info_t *rdip, 283 ddi_intr_ctlop_t op, void *arg, void *val); 284 285 #endif /* _KERNEL */ 286 287 #ifdef __cplusplus 288 } 289 #endif 290 291 #endif /* _SYS_DDI_INTR_IMPL_H */ 292