1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_DDI_INTR_IMPL_H 27 #define _SYS_DDI_INTR_IMPL_H 28 29 /* 30 * Sun DDI interrupt implementation specific definitions 31 */ 32 33 #include <sys/list.h> 34 #include <sys/ksynch.h> 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 #ifdef _KERNEL 41 42 /* 43 * Typedef for interrupt ops 44 */ 45 typedef enum { 46 DDI_INTROP_SUPPORTED_TYPES = 1, /* 1 get supported interrupts types */ 47 DDI_INTROP_NINTRS, /* 2 get num of interrupts supported */ 48 DDI_INTROP_ALLOC, /* 3 allocate interrupt handle */ 49 DDI_INTROP_GETPRI, /* 4 get priority */ 50 DDI_INTROP_SETPRI, /* 5 set priority */ 51 DDI_INTROP_ADDISR, /* 6 add interrupt handler */ 52 DDI_INTROP_DUPVEC, /* 7 duplicate interrupt handler */ 53 DDI_INTROP_ENABLE, /* 8 enable interrupt */ 54 DDI_INTROP_BLOCKENABLE, /* 9 block enable interrupts */ 55 DDI_INTROP_BLOCKDISABLE, /* 10 block disable interrupts */ 56 DDI_INTROP_DISABLE, /* 11 disable interrupt */ 57 DDI_INTROP_REMISR, /* 12 remove interrupt handler */ 58 DDI_INTROP_FREE, /* 13 free interrupt handle */ 59 DDI_INTROP_GETCAP, /* 14 get capacity */ 60 DDI_INTROP_SETCAP, /* 15 set capacity */ 61 DDI_INTROP_SETMASK, /* 16 set mask */ 62 DDI_INTROP_CLRMASK, /* 17 clear mask */ 63 DDI_INTROP_GETPENDING, /* 18 get pending interrupt */ 64 DDI_INTROP_NAVAIL, /* 19 get num of available interrupts */ 65 DDI_INTROP_GETPOOL /* 20 get resource management pool */ 66 } ddi_intr_op_t; 67 68 /* Version number used in the handles */ 69 #define DDI_INTR_VERSION_1 1 70 #define DDI_INTR_VERSION DDI_INTR_VERSION_1 71 72 /* 73 * One such data structure is allocated per ddi_intr_handle_t 74 * This is the incore copy of the regular interrupt info. 75 */ 76 typedef struct ddi_intr_handle_impl { 77 dev_info_t *ih_dip; /* dip associated with handle */ 78 uint16_t ih_type; /* interrupt type being used */ 79 ushort_t ih_inum; /* interrupt number */ 80 uint32_t ih_vector; /* vector number */ 81 uint16_t ih_ver; /* Version */ 82 uint_t ih_state; /* interrupt handle state */ 83 uint_t ih_cap; /* interrupt capabilities */ 84 uint_t ih_pri; /* priority - bus dependent */ 85 krwlock_t ih_rwlock; /* read/write lock per handle */ 86 87 uint_t (*ih_cb_func)(caddr_t, caddr_t); 88 void *ih_cb_arg1; 89 void *ih_cb_arg2; 90 91 /* 92 * The following 3 members are used to support MSI-X specific features 93 */ 94 uint_t ih_flags; /* Misc flags */ 95 uint_t ih_dup_cnt; /* # of dupped msi-x vectors */ 96 struct ddi_intr_handle_impl *ih_main; 97 /* pntr to the main vector */ 98 /* 99 * The next set of members are for 'scratch' purpose only. 100 * The DDI interrupt framework uses them internally and their 101 * interpretation is left to the framework. For now, 102 * scratch1 - used to send NINTRs information 103 * to various nexus drivers. 104 * scratch2 - used to send 'behavior' flag 105 * information to the nexus drivers 106 * from ddi_intr_alloc(). It is also 107 * used to send 'h_array' to the nexus drivers 108 * for ddi_intr_block_enable/disable() on x86. 109 * private - On X86 it usually carries a pointer to 110 * ihdl_plat_t. Not used on SPARC platforms. 111 */ 112 void *ih_private; /* Platform specific data */ 113 uint_t ih_scratch1; /* Scratch1: #interrupts */ 114 void *ih_scratch2; /* Scratch2: flag/h_array */ 115 } ddi_intr_handle_impl_t; 116 117 /* values for ih_state (strictly for interrupt handle) */ 118 #define DDI_IHDL_STATE_ALLOC 0x01 /* Allocated. ddi_intr_alloc() called */ 119 #define DDI_IHDL_STATE_ADDED 0x02 /* Added interrupt handler */ 120 /* ddi_intr_add_handler() called */ 121 #define DDI_IHDL_STATE_ENABLE 0x04 /* Enabled. ddi_intr_enable() called */ 122 123 #define DDI_INTR_IS_MSI_OR_MSIX(type) \ 124 ((type) == DDI_INTR_TYPE_MSI || (type) == DDI_INTR_TYPE_MSIX) 125 126 #define DDI_INTR_BEHAVIOR_FLAG_VALID(f) \ 127 (((f) == DDI_INTR_ALLOC_NORMAL) || ((f) == DDI_INTR_ALLOC_STRICT)) 128 129 #define DDI_INTR_TYPE_FLAG_VALID(t) \ 130 (((t) == DDI_INTR_TYPE_FIXED) || \ 131 ((t) == DDI_INTR_TYPE_MSI) || \ 132 ((t) == DDI_INTR_TYPE_MSIX)) 133 134 /* values for ih_flags */ 135 #define DDI_INTR_MSIX_DUP 0x01 /* MSI-X vector which has been dupped */ 136 137 /* Maximum number of MSI resources to allocate */ 138 #define DDI_MAX_MSI_ALLOC 2 139 140 /* Default number of MSI-X resources to allocate */ 141 #define DDI_DEFAULT_MSIX_ALLOC 2 142 143 #define DDI_MSIX_ALLOC_DIVIDER 32 144 #define DDI_MIN_MSIX_ALLOC 8 145 #define DDI_MAX_MSIX_ALLOC 2048 146 147 struct av_softinfo; 148 149 /* 150 * One such data structure is allocated per ddi_soft_intr_handle 151 * This is the incore copy of the softint info. 152 */ 153 typedef struct ddi_softint_hdl_impl { 154 dev_info_t *ih_dip; /* dip associated with handle */ 155 uint_t ih_pri; /* priority - bus dependent */ 156 krwlock_t ih_rwlock; /* read/write lock per handle */ 157 struct av_softinfo *ih_pending; /* whether softint is pending */ 158 159 uint_t (*ih_cb_func)(caddr_t, caddr_t); 160 /* cb function for soft ints */ 161 void *ih_cb_arg1; /* arg1 of callback function */ 162 void *ih_cb_arg2; /* arg2 passed to "trigger" */ 163 164 /* 165 * The next member is for 'scratch' purpose only. 166 * The DDI interrupt framework uses it internally and its 167 * interpretation is left to the framework. 168 * private - used by the DDI framework to pass back 169 * and forth 'softid' information on SPARC 170 * side only. Not used on X86 platform. 171 */ 172 void *ih_private; /* Platform specific data */ 173 } ddi_softint_hdl_impl_t; 174 175 /* Softint internal implementation defines */ 176 #define DDI_SOFT_INTR_PRI_M 4 177 #define DDI_SOFT_INTR_PRI_H 6 178 179 /* 180 * One such data structure is allocated for MSI-X enabled 181 * device. If no MSI-X is enabled then it is NULL 182 */ 183 typedef struct ddi_intr_msix { 184 /* MSI-X Table related information */ 185 ddi_acc_handle_t msix_tbl_hdl; /* MSI-X table handle */ 186 uint32_t *msix_tbl_addr; /* MSI-X table addr */ 187 uint32_t msix_tbl_offset; /* MSI-X table offset */ 188 189 /* MSI-X PBA Table related information */ 190 ddi_acc_handle_t msix_pba_hdl; /* MSI-X PBA handle */ 191 uint32_t *msix_pba_addr; /* MSI-X PBA addr */ 192 uint32_t msix_pba_offset; /* MSI-X PBA offset */ 193 194 ddi_device_acc_attr_t msix_dev_attr; /* MSI-X device attr */ 195 } ddi_intr_msix_t; 196 197 /* 198 * Interrupt Resource Management (IRM). 199 */ 200 201 #define DDI_IRM_POLICY_LARGE 1 202 #define DDI_IRM_POLICY_EVEN 2 203 204 #define DDI_IRM_POLICY_VALID(p) (((p) == DDI_IRM_POLICY_LARGE) || \ 205 ((p) == DDI_IRM_POLICY_EVEN)) 206 207 #define DDI_IRM_FLAG_ACTIVE 0x1 /* Pool is active */ 208 #define DDI_IRM_FLAG_QUEUED 0x2 /* Pool is queued */ 209 #define DDI_IRM_FLAG_WAITERS 0x4 /* Pool has waiters */ 210 #define DDI_IRM_FLAG_EXIT 0x8 /* Balance thread must exit */ 211 #define DDI_IRM_FLAG_NEW 0x10 /* Request is new */ 212 #define DDI_IRM_FLAG_CALLBACK 0x20 /* Request has callback */ 213 214 /* 215 * One such data structure for each supply of interrupt vectors. 216 * Contains information about the size and policies defining the 217 * supply, and a list of associated device-specific requests. 218 */ 219 typedef struct ddi_irm_pool { 220 int ipool_flags; /* Status flags of the pool */ 221 int ipool_types; /* Types of interrupts */ 222 int ipool_policy; /* Rebalancing policy */ 223 uint_t ipool_totsz; /* Total size of the pool */ 224 uint_t ipool_defsz; /* Default allocation size */ 225 uint_t ipool_minno; /* Minimum number consumed */ 226 uint_t ipool_reqno; /* Total number requested */ 227 uint_t ipool_resno; /* Total number reserved */ 228 kmutex_t ipool_lock; /* Protects all pool usage */ 229 kmutex_t ipool_navail_lock; /* Protects 'navail' of reqs */ 230 kcondvar_t ipool_cv; /* Condition variable */ 231 kthread_t *ipool_thread; /* Balancing thread */ 232 dev_info_t *ipool_owner; /* Device that created pool */ 233 list_t ipool_req_list; /* All requests in pool */ 234 list_t ipool_scratch_list; /* Requests being reduced */ 235 list_node_t ipool_link; /* Links in global pool list */ 236 } ddi_irm_pool_t; 237 238 /* 239 * One such data structure for each dip's devinfo_intr_t. 240 * Contains information about vectors requested from IRM. 241 */ 242 typedef struct ddi_irm_req { 243 int ireq_flags; /* Flags for request */ 244 int ireq_type; /* Type requested */ 245 uint_t ireq_nreq; /* Number requested */ 246 uint_t ireq_navail; /* Number available */ 247 uint_t ireq_scratch; /* Scratch value */ 248 dev_info_t *ireq_dip; /* Requesting device */ 249 ddi_irm_pool_t *ireq_pool_p; /* Supplying pool */ 250 list_node_t ireq_link; /* Request list link */ 251 list_node_t ireq_scratch_link; /* Scratch list link */ 252 } ddi_irm_req_t; 253 254 /* 255 * This structure is used to pass parameters to ndi_create_irm(), 256 * and describes the operating parameters of an IRM pool. 257 */ 258 typedef struct ddi_irm_params { 259 int iparams_types; /* Types of interrupts in pool */ 260 uint_t iparams_total; /* Total size of the pool */ 261 } ddi_irm_params_t; 262 263 /* 264 * One such data structure is allocated for each dip. 265 * It has interrupt related information that can be 266 * stored/retrieved for convenience. 267 */ 268 typedef struct devinfo_intr { 269 /* These three fields show what the device is capable of */ 270 uint_t devi_intr_sup_types; /* Intrs supported by device */ 271 272 ddi_intr_msix_t *devi_msix_p; /* MSI-X info, if supported */ 273 274 /* Next three fields show current status for the device */ 275 uint_t devi_intr_curr_type; /* Interrupt type being used */ 276 uint_t devi_intr_sup_nintrs; /* #intr supported */ 277 uint_t devi_intr_curr_nintrs; /* #intr currently being used */ 278 /* 279 * #intr currently being enabled 280 * (for MSI block enable, the valuse is either 1 or 0.) 281 */ 282 uint_t devi_intr_curr_nenables; 283 284 ddi_intr_handle_t *devi_intr_handle_p; /* Hdl for legacy intr APIs */ 285 286 #if defined(__i386) || defined(__amd64) 287 /* Save the PCI config space handle */ 288 ddi_acc_handle_t devi_cfg_handle; 289 int devi_cap_ptr; /* MSI or MSI-X cap pointer */ 290 #endif 291 292 ddi_irm_req_t *devi_irm_req_p; /* IRM request information */ 293 } devinfo_intr_t; 294 295 #define NEXUS_HAS_INTR_OP(dip) \ 296 ((DEVI(dip)->devi_ops->devo_bus_ops) && \ 297 (DEVI(dip)->devi_ops->devo_bus_ops->busops_rev >= BUSO_REV_9) && \ 298 (DEVI(dip)->devi_ops->devo_bus_ops->bus_intr_op)) 299 300 int i_ddi_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t op, 301 ddi_intr_handle_impl_t *hdlp, void *result); 302 303 int i_ddi_add_softint(ddi_softint_hdl_impl_t *); 304 void i_ddi_remove_softint(ddi_softint_hdl_impl_t *); 305 int i_ddi_trigger_softint(ddi_softint_hdl_impl_t *, void *); 306 int i_ddi_set_softint_pri(ddi_softint_hdl_impl_t *, uint_t); 307 308 void i_ddi_intr_devi_init(dev_info_t *dip); 309 void i_ddi_intr_devi_fini(dev_info_t *dip); 310 311 uint_t i_ddi_intr_get_supported_types(dev_info_t *dip); 312 void i_ddi_intr_set_supported_types(dev_info_t *dip, int sup_type); 313 uint_t i_ddi_intr_get_current_type(dev_info_t *dip); 314 void i_ddi_intr_set_current_type(dev_info_t *dip, int intr_type); 315 uint_t i_ddi_intr_get_supported_nintrs(dev_info_t *dip, int intr_type); 316 void i_ddi_intr_set_supported_nintrs(dev_info_t *dip, int nintrs); 317 uint_t i_ddi_intr_get_current_nintrs(dev_info_t *dip); 318 void i_ddi_intr_set_current_nintrs(dev_info_t *dip, int nintrs); 319 uint_t i_ddi_intr_get_current_nenables(dev_info_t *dip); 320 void i_ddi_intr_set_current_nenables(dev_info_t *dip, int nintrs); 321 uint_t i_ddi_intr_get_current_navail(dev_info_t *dip, int intr_type); 322 323 ddi_irm_pool_t *i_ddi_intr_get_pool(dev_info_t *dip, int intr_type); 324 325 void irm_init(void); 326 int i_ddi_irm_insert(dev_info_t *dip, int intr_type, int count); 327 int i_ddi_irm_modify(dev_info_t *dip, int nreq); 328 int i_ddi_irm_remove(dev_info_t *dip); 329 void i_ddi_irm_set_cb(dev_info_t *dip, boolean_t cb_flag); 330 331 ddi_intr_handle_t i_ddi_get_intr_handle(dev_info_t *dip, int inum); 332 void i_ddi_set_intr_handle(dev_info_t *dip, int inum, ddi_intr_handle_t hdl); 333 334 ddi_intr_msix_t *i_ddi_get_msix(dev_info_t *dip); 335 void i_ddi_set_msix(dev_info_t *dip, ddi_intr_msix_t *msix_p); 336 337 #if defined(__i386) || defined(__amd64) 338 ddi_acc_handle_t i_ddi_get_pci_config_handle(dev_info_t *dip); 339 void i_ddi_set_pci_config_handle(dev_info_t *dip, ddi_acc_handle_t handle); 340 int i_ddi_get_msi_msix_cap_ptr(dev_info_t *dip); 341 void i_ddi_set_msi_msix_cap_ptr(dev_info_t *dip, int cap_ptr); 342 #endif 343 344 int32_t i_ddi_get_intr_weight(dev_info_t *); 345 int32_t i_ddi_set_intr_weight(dev_info_t *, int32_t); 346 347 void i_ddi_alloc_intr_phdl(ddi_intr_handle_impl_t *); 348 void i_ddi_free_intr_phdl(ddi_intr_handle_impl_t *); 349 350 #define DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, func, arg1, arg2) \ 351 hdlp->ih_cb_func = func; \ 352 hdlp->ih_cb_arg1 = arg1; \ 353 hdlp->ih_cb_arg2 = arg2; 354 355 #ifdef DEBUG 356 #define I_DDI_VERIFY_MSIX_HANDLE(hdlp) \ 357 if ((hdlp->ih_type == DDI_INTR_TYPE_MSIX) && \ 358 (hdlp->ih_flags & DDI_INTR_MSIX_DUP)) { \ 359 ASSERT(hdlp->ih_dip == hdlp->ih_main->ih_dip); \ 360 ASSERT(hdlp->ih_type == hdlp->ih_main->ih_type); \ 361 ASSERT(hdlp->ih_vector == hdlp->ih_main->ih_vector); \ 362 ASSERT(hdlp->ih_ver == hdlp->ih_main->ih_ver); \ 363 ASSERT(hdlp->ih_cap == hdlp->ih_main->ih_cap); \ 364 ASSERT(hdlp->ih_pri == hdlp->ih_main->ih_pri); \ 365 } 366 #else 367 #define I_DDI_VERIFY_MSIX_HANDLE(hdlp) 368 #endif 369 370 #else /* _KERNEL */ 371 372 typedef struct devinfo_intr devinfo_intr_t; 373 374 #endif /* _KERNEL */ 375 376 /* 377 * Used only by old DDI interrupt interfaces. 378 */ 379 380 /* 381 * This structure represents one interrupt possible from the given 382 * device. It is used in an array for devices with multiple interrupts. 383 */ 384 struct intrspec { 385 uint_t intrspec_pri; /* interrupt priority */ 386 uint_t intrspec_vec; /* vector # (0 if none) */ 387 uint_t (*intrspec_func)(); /* function to call for interrupt, */ 388 /* If (uint_t (*)()) 0, none. */ 389 /* If (uint_t (*)()) 1, then */ 390 }; 391 392 #ifdef _KERNEL 393 394 /* 395 * Figure out how many FIXED nintrs are supported 396 */ 397 int i_ddi_get_intx_nintrs(dev_info_t *dip); 398 399 /* 400 * NOTE: 401 * The following 4 busops entry points are obsoleted with version 402 * 9 or greater. Use i_ddi_intr_op interface in place of these 403 * obsolete interfaces. 404 * 405 * Remove these busops entry points and all related data structures 406 * in future minor/major solaris release. 407 */ 408 typedef enum {DDI_INTR_CTLOPS_NONE} ddi_intr_ctlop_t; 409 410 /* The following are obsolete interfaces */ 411 ddi_intrspec_t i_ddi_get_intrspec(dev_info_t *dip, dev_info_t *rdip, 412 uint_t inumber); 413 414 int i_ddi_add_intrspec(dev_info_t *dip, dev_info_t *rdip, 415 ddi_intrspec_t intrspec, ddi_iblock_cookie_t *iblock_cookiep, 416 ddi_idevice_cookie_t *idevice_cookiep, 417 uint_t (*int_handler)(caddr_t int_handler_arg), 418 caddr_t int_handler_arg, int kind); 419 420 void i_ddi_remove_intrspec(dev_info_t *dip, dev_info_t *rdip, 421 ddi_intrspec_t intrspec, ddi_iblock_cookie_t iblock_cookie); 422 423 int i_ddi_intr_ctlops(dev_info_t *dip, dev_info_t *rdip, 424 ddi_intr_ctlop_t op, void *arg, void *val); 425 426 #endif /* _KERNEL */ 427 428 #ifdef __cplusplus 429 } 430 #endif 431 432 #endif /* _SYS_DDI_INTR_IMPL_H */ 433