1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_DDI_INTR_IMPL_H 27 #define _SYS_DDI_INTR_IMPL_H 28 29 /* 30 * Sun DDI interrupt implementation specific definitions 31 */ 32 33 #include <sys/list.h> 34 #include <sys/ksynch.h> 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 #ifdef _KERNEL 41 42 /* 43 * Typedef for interrupt ops 44 */ 45 typedef enum { 46 DDI_INTROP_SUPPORTED_TYPES = 1, /* 1 get supported interrupts types */ 47 DDI_INTROP_NINTRS, /* 2 get num of interrupts supported */ 48 DDI_INTROP_ALLOC, /* 3 allocate interrupt handle */ 49 DDI_INTROP_GETPRI, /* 4 get priority */ 50 DDI_INTROP_SETPRI, /* 5 set priority */ 51 DDI_INTROP_ADDISR, /* 6 add interrupt handler */ 52 DDI_INTROP_DUPVEC, /* 7 duplicate interrupt handler */ 53 DDI_INTROP_ENABLE, /* 8 enable interrupt */ 54 DDI_INTROP_BLOCKENABLE, /* 9 block enable interrupts */ 55 DDI_INTROP_BLOCKDISABLE, /* 10 block disable interrupts */ 56 DDI_INTROP_DISABLE, /* 11 disable interrupt */ 57 DDI_INTROP_REMISR, /* 12 remove interrupt handler */ 58 DDI_INTROP_FREE, /* 13 free interrupt handle */ 59 DDI_INTROP_GETCAP, /* 14 get capacity */ 60 DDI_INTROP_SETCAP, /* 15 set capacity */ 61 DDI_INTROP_SETMASK, /* 16 set mask */ 62 DDI_INTROP_CLRMASK, /* 17 clear mask */ 63 DDI_INTROP_GETPENDING, /* 18 get pending interrupt */ 64 DDI_INTROP_NAVAIL, /* 19 get num of available interrupts */ 65 DDI_INTROP_GETPOOL /* 20 get resource management pool */ 66 } ddi_intr_op_t; 67 68 /* Version number used in the handles */ 69 #define DDI_INTR_VERSION_1 1 70 #define DDI_INTR_VERSION DDI_INTR_VERSION_1 71 72 /* 73 * One such data structure is allocated per ddi_intr_handle_t 74 * This is the incore copy of the regular interrupt info. 75 */ 76 typedef struct ddi_intr_handle_impl { 77 dev_info_t *ih_dip; /* dip associated with handle */ 78 uint16_t ih_type; /* interrupt type being used */ 79 ushort_t ih_inum; /* interrupt number */ 80 uint32_t ih_vector; /* vector number */ 81 uint16_t ih_ver; /* Version */ 82 uint_t ih_state; /* interrupt handle state */ 83 uint_t ih_cap; /* interrupt capabilities */ 84 uint_t ih_pri; /* priority - bus dependent */ 85 krwlock_t ih_rwlock; /* read/write lock per handle */ 86 87 uint_t (*ih_cb_func)(caddr_t, caddr_t); 88 void *ih_cb_arg1; 89 void *ih_cb_arg2; 90 91 /* 92 * The following 3 members are used to support MSI-X specific features 93 */ 94 uint_t ih_flags; /* Misc flags */ 95 uint_t ih_dup_cnt; /* # of dupped msi-x vectors */ 96 struct ddi_intr_handle_impl *ih_main; 97 /* pntr to the main vector */ 98 /* 99 * The next set of members are for 'scratch' purpose only. 100 * The DDI interrupt framework uses them internally and their 101 * interpretation is left to the framework. For now, 102 * scratch1 - used to send NINTRs information 103 * to various nexus drivers. 104 * scratch2 - used to send 'behavior' flag 105 * information to the nexus drivers 106 * from ddi_intr_alloc(). It is also 107 * used to send 'h_array' to the nexus drivers 108 * for ddi_intr_block_enable/disable() on x86. 109 * private - On X86 it usually carries a pointer to 110 * ihdl_plat_t. Not used on SPARC platforms. 111 */ 112 void *ih_private; /* Platform specific data */ 113 uint_t ih_scratch1; /* Scratch1: #interrupts */ 114 void *ih_scratch2; /* Scratch2: flag/h_array */ 115 } ddi_intr_handle_impl_t; 116 117 /* values for ih_state (strictly for interrupt handle) */ 118 #define DDI_IHDL_STATE_ALLOC 0x01 /* Allocated. ddi_intr_alloc() called */ 119 #define DDI_IHDL_STATE_ADDED 0x02 /* Added interrupt handler */ 120 /* ddi_intr_add_handler() called */ 121 #define DDI_IHDL_STATE_ENABLE 0x04 /* Enabled. ddi_intr_enable() called */ 122 123 #define DDI_INTR_IS_MSI_OR_MSIX(type) \ 124 ((type) == DDI_INTR_TYPE_MSI || (type) == DDI_INTR_TYPE_MSIX) 125 126 #define DDI_INTR_BEHAVIOR_FLAG_VALID(f) \ 127 (((f) == DDI_INTR_ALLOC_NORMAL) || ((f) == DDI_INTR_ALLOC_STRICT)) 128 129 #define DDI_INTR_TYPE_FLAG_VALID(t) \ 130 (((t) == DDI_INTR_TYPE_FIXED) || \ 131 ((t) == DDI_INTR_TYPE_MSI) || \ 132 ((t) == DDI_INTR_TYPE_MSIX)) 133 134 /* values for ih_flags */ 135 #define DDI_INTR_MSIX_DUP 0x01 /* MSI-X vector which has been dupped */ 136 137 /* Maximum number of MSI resources to allocate */ 138 #define DDI_MAX_MSI_ALLOC 2 139 140 /* 141 * The following MSI-X limits will change with Interrupt Resource Management 142 * (IRM) support. 143 */ 144 /* Default number of MSI-X resources to allocate */ 145 #define DDI_DEFAULT_MSIX_ALLOC 2 146 147 /* Maximum number of MSI-X resources to allocate */ 148 #define DDI_MAX_MSIX_ALLOC 8 149 150 struct av_softinfo; 151 152 /* 153 * One such data structure is allocated per ddi_soft_intr_handle 154 * This is the incore copy of the softint info. 155 */ 156 typedef struct ddi_softint_hdl_impl { 157 dev_info_t *ih_dip; /* dip associated with handle */ 158 uint_t ih_pri; /* priority - bus dependent */ 159 krwlock_t ih_rwlock; /* read/write lock per handle */ 160 struct av_softinfo *ih_pending; /* whether softint is pending */ 161 162 uint_t (*ih_cb_func)(caddr_t, caddr_t); 163 /* cb function for soft ints */ 164 void *ih_cb_arg1; /* arg1 of callback function */ 165 void *ih_cb_arg2; /* arg2 passed to "trigger" */ 166 167 /* 168 * The next member is for 'scratch' purpose only. 169 * The DDI interrupt framework uses it internally and its 170 * interpretation is left to the framework. 171 * private - used by the DDI framework to pass back 172 * and forth 'softid' information on SPARC 173 * side only. Not used on X86 platform. 174 */ 175 void *ih_private; /* Platform specific data */ 176 } ddi_softint_hdl_impl_t; 177 178 /* Softint internal implementation defines */ 179 #define DDI_SOFT_INTR_PRI_M 4 180 #define DDI_SOFT_INTR_PRI_H 6 181 182 /* 183 * One such data structure is allocated for MSI-X enabled 184 * device. If no MSI-X is enabled then it is NULL 185 */ 186 typedef struct ddi_intr_msix { 187 /* MSI-X Table related information */ 188 ddi_acc_handle_t msix_tbl_hdl; /* MSI-X table handle */ 189 uint32_t *msix_tbl_addr; /* MSI-X table addr */ 190 uint32_t msix_tbl_offset; /* MSI-X table offset */ 191 192 /* MSI-X PBA Table related information */ 193 ddi_acc_handle_t msix_pba_hdl; /* MSI-X PBA handle */ 194 uint32_t *msix_pba_addr; /* MSI-X PBA addr */ 195 uint32_t msix_pba_offset; /* MSI-X PBA offset */ 196 197 ddi_device_acc_attr_t msix_dev_attr; /* MSI-X device attr */ 198 } ddi_intr_msix_t; 199 200 /* 201 * Interrupt Resource Management (IRM). 202 */ 203 204 #define DDI_IRM_POLICY_LARGE 1 205 #define DDI_IRM_POLICY_EVEN 2 206 207 #define DDI_IRM_POLICY_VALID(p) (((p) == DDI_IRM_POLICY_LARGE) || \ 208 ((p) == DDI_IRM_POLICY_EVEN)) 209 210 #define DDI_IRM_FLAG_ACTIVE 0x1 /* Pool is active */ 211 #define DDI_IRM_FLAG_QUEUED 0x2 /* Pool is queued */ 212 #define DDI_IRM_FLAG_WAITERS 0x4 /* Pool has waiters */ 213 #define DDI_IRM_FLAG_EXIT 0x8 /* Balance thread must exit */ 214 #define DDI_IRM_FLAG_NEW 0x10 /* Request is new */ 215 #define DDI_IRM_FLAG_CALLBACK 0x20 /* Request has callback */ 216 217 /* 218 * One such data structure for each supply of interrupt vectors. 219 * Contains information about the size and policies defining the 220 * supply, and a list of associated device-specific requests. 221 */ 222 typedef struct ddi_irm_pool { 223 int ipool_flags; /* Status flags of the pool */ 224 int ipool_types; /* Types of interrupts */ 225 int ipool_policy; /* Rebalancing policy */ 226 uint_t ipool_totsz; /* Total size of the pool */ 227 uint_t ipool_defsz; /* Default allocation size */ 228 uint_t ipool_minno; /* Minimum number consumed */ 229 uint_t ipool_reqno; /* Total number requested */ 230 uint_t ipool_resno; /* Total number reserved */ 231 kmutex_t ipool_lock; /* Protects all pool usage */ 232 kmutex_t ipool_navail_lock; /* Protects 'navail' of reqs */ 233 kcondvar_t ipool_cv; /* Condition variable */ 234 kthread_t *ipool_thread; /* Balancing thread */ 235 dev_info_t *ipool_owner; /* Device that created pool */ 236 list_t ipool_req_list; /* All requests in pool */ 237 list_t ipool_scratch_list; /* Requests being reduced */ 238 list_node_t ipool_link; /* Links in global pool list */ 239 } ddi_irm_pool_t; 240 241 /* 242 * One such data structure for each dip's devinfo_intr_t. 243 * Contains information about vectors requested from IRM. 244 */ 245 typedef struct ddi_irm_req { 246 int ireq_flags; /* Flags for request */ 247 int ireq_type; /* Type requested */ 248 uint_t ireq_nreq; /* Number requested */ 249 uint_t ireq_navail; /* Number available */ 250 uint_t ireq_scratch; /* Scratch value */ 251 dev_info_t *ireq_dip; /* Requesting device */ 252 ddi_irm_pool_t *ireq_pool_p; /* Supplying pool */ 253 list_node_t ireq_link; /* Request list link */ 254 list_node_t ireq_scratch_link; /* Scratch list link */ 255 } ddi_irm_req_t; 256 257 /* 258 * This structure is used to pass parameters to ndi_create_irm(), 259 * and describes the operating parameters of an IRM pool. 260 */ 261 typedef struct ddi_irm_params { 262 int iparams_types; /* Types of interrupts in pool */ 263 uint_t iparams_total; /* Total size of the pool */ 264 uint_t iparams_default; /* Default allocation size */ 265 } ddi_irm_params_t; 266 267 /* 268 * One such data structure is allocated for each dip. 269 * It has interrupt related information that can be 270 * stored/retrieved for convenience. 271 */ 272 typedef struct devinfo_intr { 273 /* These three fields show what the device is capable of */ 274 uint_t devi_intr_sup_types; /* Intrs supported by device */ 275 276 ddi_intr_msix_t *devi_msix_p; /* MSI-X info, if supported */ 277 278 /* Next three fields show current status for the device */ 279 uint_t devi_intr_curr_type; /* Interrupt type being used */ 280 uint_t devi_intr_sup_nintrs; /* #intr supported */ 281 uint_t devi_intr_curr_nintrs; /* #intr currently being used */ 282 283 ddi_intr_handle_t *devi_intr_handle_p; /* Hdl for legacy intr APIs */ 284 285 #if defined(__i386) || defined(__amd64) 286 /* Save the PCI config space handle */ 287 ddi_acc_handle_t devi_cfg_handle; 288 int devi_cap_ptr; /* MSI or MSI-X cap pointer */ 289 #endif 290 291 ddi_irm_req_t *devi_irm_req_p; /* IRM request information */ 292 } devinfo_intr_t; 293 294 #define NEXUS_HAS_INTR_OP(dip) \ 295 ((DEVI(dip)->devi_ops->devo_bus_ops) && \ 296 (DEVI(dip)->devi_ops->devo_bus_ops->busops_rev >= BUSO_REV_9) && \ 297 (DEVI(dip)->devi_ops->devo_bus_ops->bus_intr_op)) 298 299 int i_ddi_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t op, 300 ddi_intr_handle_impl_t *hdlp, void *result); 301 302 int i_ddi_add_softint(ddi_softint_hdl_impl_t *); 303 void i_ddi_remove_softint(ddi_softint_hdl_impl_t *); 304 int i_ddi_trigger_softint(ddi_softint_hdl_impl_t *, void *); 305 int i_ddi_set_softint_pri(ddi_softint_hdl_impl_t *, uint_t); 306 307 void i_ddi_intr_devi_init(dev_info_t *dip); 308 void i_ddi_intr_devi_fini(dev_info_t *dip); 309 310 uint_t i_ddi_intr_get_supported_types(dev_info_t *dip); 311 void i_ddi_intr_set_supported_types(dev_info_t *dip, int sup_type); 312 uint_t i_ddi_intr_get_current_type(dev_info_t *dip); 313 void i_ddi_intr_set_current_type(dev_info_t *dip, int intr_type); 314 uint_t i_ddi_intr_get_supported_nintrs(dev_info_t *dip, int intr_type); 315 void i_ddi_intr_set_supported_nintrs(dev_info_t *dip, int nintrs); 316 uint_t i_ddi_intr_get_current_nintrs(dev_info_t *dip); 317 void i_ddi_intr_set_current_nintrs(dev_info_t *dip, int nintrs); 318 uint_t i_ddi_intr_get_current_navail(dev_info_t *dip, int intr_type); 319 320 ddi_irm_pool_t *i_ddi_intr_get_pool(dev_info_t *dip, int intr_type); 321 322 void irm_init(void); 323 int i_ddi_irm_insert(dev_info_t *dip, int intr_type, int count); 324 int i_ddi_irm_modify(dev_info_t *dip, int nreq); 325 int i_ddi_irm_remove(dev_info_t *dip); 326 void i_ddi_irm_set_cb(dev_info_t *dip, boolean_t cb_flag); 327 328 ddi_intr_handle_t i_ddi_get_intr_handle(dev_info_t *dip, int inum); 329 void i_ddi_set_intr_handle(dev_info_t *dip, int inum, ddi_intr_handle_t hdl); 330 331 ddi_intr_msix_t *i_ddi_get_msix(dev_info_t *dip); 332 void i_ddi_set_msix(dev_info_t *dip, ddi_intr_msix_t *msix_p); 333 334 #if defined(__i386) || defined(__amd64) 335 ddi_acc_handle_t i_ddi_get_pci_config_handle(dev_info_t *dip); 336 void i_ddi_set_pci_config_handle(dev_info_t *dip, ddi_acc_handle_t handle); 337 int i_ddi_get_msi_msix_cap_ptr(dev_info_t *dip); 338 void i_ddi_set_msi_msix_cap_ptr(dev_info_t *dip, int cap_ptr); 339 #endif 340 341 uint_t i_ddi_get_msix_alloc_limit(dev_info_t *dip); 342 343 int32_t i_ddi_get_intr_weight(dev_info_t *); 344 int32_t i_ddi_set_intr_weight(dev_info_t *, int32_t); 345 346 void i_ddi_alloc_intr_phdl(ddi_intr_handle_impl_t *); 347 void i_ddi_free_intr_phdl(ddi_intr_handle_impl_t *); 348 349 #define DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, func, arg1, arg2) \ 350 hdlp->ih_cb_func = func; \ 351 hdlp->ih_cb_arg1 = arg1; \ 352 hdlp->ih_cb_arg2 = arg2; 353 354 #ifdef DEBUG 355 #define I_DDI_VERIFY_MSIX_HANDLE(hdlp) \ 356 if ((hdlp->ih_type == DDI_INTR_TYPE_MSIX) && \ 357 (hdlp->ih_flags & DDI_INTR_MSIX_DUP)) { \ 358 ASSERT(hdlp->ih_dip == hdlp->ih_main->ih_dip); \ 359 ASSERT(hdlp->ih_type == hdlp->ih_main->ih_type); \ 360 ASSERT(hdlp->ih_vector == hdlp->ih_main->ih_vector); \ 361 ASSERT(hdlp->ih_ver == hdlp->ih_main->ih_ver); \ 362 ASSERT(hdlp->ih_cap == hdlp->ih_main->ih_cap); \ 363 ASSERT(hdlp->ih_pri == hdlp->ih_main->ih_pri); \ 364 } 365 #else 366 #define I_DDI_VERIFY_MSIX_HANDLE(hdlp) 367 #endif 368 369 #else /* _KERNEL */ 370 371 typedef struct devinfo_intr devinfo_intr_t; 372 373 #endif /* _KERNEL */ 374 375 /* 376 * Used only by old DDI interrupt interfaces. 377 */ 378 379 /* 380 * This structure represents one interrupt possible from the given 381 * device. It is used in an array for devices with multiple interrupts. 382 */ 383 struct intrspec { 384 uint_t intrspec_pri; /* interrupt priority */ 385 uint_t intrspec_vec; /* vector # (0 if none) */ 386 uint_t (*intrspec_func)(); /* function to call for interrupt, */ 387 /* If (uint_t (*)()) 0, none. */ 388 /* If (uint_t (*)()) 1, then */ 389 }; 390 391 #ifdef _KERNEL 392 393 /* 394 * Figure out how many FIXED nintrs are supported 395 */ 396 int i_ddi_get_intx_nintrs(dev_info_t *dip); 397 398 /* 399 * NOTE: 400 * The following 4 busops entry points are obsoleted with version 401 * 9 or greater. Use i_ddi_intr_op interface in place of these 402 * obsolete interfaces. 403 * 404 * Remove these busops entry points and all related data structures 405 * in future minor/major solaris release. 406 */ 407 typedef enum {DDI_INTR_CTLOPS_NONE} ddi_intr_ctlop_t; 408 409 /* The following are obsolete interfaces */ 410 ddi_intrspec_t i_ddi_get_intrspec(dev_info_t *dip, dev_info_t *rdip, 411 uint_t inumber); 412 413 int i_ddi_add_intrspec(dev_info_t *dip, dev_info_t *rdip, 414 ddi_intrspec_t intrspec, ddi_iblock_cookie_t *iblock_cookiep, 415 ddi_idevice_cookie_t *idevice_cookiep, 416 uint_t (*int_handler)(caddr_t int_handler_arg), 417 caddr_t int_handler_arg, int kind); 418 419 void i_ddi_remove_intrspec(dev_info_t *dip, dev_info_t *rdip, 420 ddi_intrspec_t intrspec, ddi_iblock_cookie_t iblock_cookie); 421 422 int i_ddi_intr_ctlops(dev_info_t *dip, dev_info_t *rdip, 423 ddi_intr_ctlop_t op, void *arg, void *val); 424 425 #endif /* _KERNEL */ 426 427 #ifdef __cplusplus 428 } 429 #endif 430 431 #endif /* _SYS_DDI_INTR_IMPL_H */ 432