1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * CAUTION: This header file has not gone through a formal review process. 29 * Thus its commitment level is very low and may change or be removed 30 * at any time. 31 */ 32 33 #ifndef _SYS_AC97_H 34 #define _SYS_AC97_H 35 36 #pragma ident "%Z%%M% %I% %E% SMI" 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 #ifdef _KERNEL 43 44 /* 45 * This header file describes the AC-97 V2.1 Codec register set. See the 46 * spec for a detailed description of each register. 47 */ 48 49 struct ac97_v21 { 50 uint16_t ac97_reset; /* 00h */ 51 uint16_t ac97_master_volume; /* 02h */ 52 uint16_t ac97_headphone_volume; /* 04h, optional */ 53 uint16_t ac97_master_mono_volume; /* 06h, optional */ 54 uint16_t ac97_master_tone; /* 08h, optional */ 55 uint16_t ac97_pc_beep_volume; /* 0ah, optional */ 56 uint16_t ac97_phone_volume; /* 0ch, optional */ 57 uint16_t ac97_mic_volume; /* 0eh */ 58 uint16_t ac97_line_in_volume; /* 10h */ 59 uint16_t ac97_cd_volume; /* 12h */ 60 uint16_t ac97_video_volume; /* 14h, optional */ 61 uint16_t ac97_aux_volume; /* 16h, optional */ 62 uint16_t ac97_PCM_out_volume; /* 18h */ 63 uint16_t ac97_record_select; /* 1ah */ 64 uint16_t ac97_record_gain; /* 1ch */ 65 uint16_t ac97_record_gain_mic; /* 1eh, optional */ 66 uint16_t ac97_general_purpose; /* 20h, optional */ 67 uint16_t ac97_threeD_control; /* 22h, optional */ 68 uint16_t ac97_reserved_1; /* 24h */ 69 uint16_t ac97_pwrdwn_ctrl_stat; /* 26h */ 70 71 /* extended audio registers */ 72 73 uint16_t ac97_ext_audio_id; /* 28h, optional */ 74 uint16_t ac97_ext_audio_stat_ctrl; /* 2ah, optional */ 75 uint16_t ac97_ext_front_DAC_rate; /* 2ch, optional */ 76 uint16_t ac97_ext_surround_DAC_rate; /* 2eh, optional */ 77 uint16_t ac97_ext_LFE_DAC_rate; /* 30h, optional */ 78 uint16_t ac97_ext_LR_ADC_rate; /* 32h, optional */ 79 uint16_t ac97_ext_mic_ADC_rate; /* 34h, optional */ 80 uint16_t ac97_ext_C_LFE_volume; /* 36h, optional */ 81 uint16_t ac97_ext_LR_surround_volume; /* 38h, optional */ 82 uint16_t ac97_ext_reserved_1; /* 3ah, optional */ 83 84 /* extended modem registers */ 85 86 uint16_t ac97_ext_modem_id; /* 3ch, optional */ 87 uint16_t ac97_ext_modem_stat_ctrl; /* 3eh, optional */ 88 uint16_t ac97_ext_line1_DAC_ADC_rate; /* 40h, optional */ 89 uint16_t ac97_ext_line2_DAC_ADC_rate; /* 42h, optional */ 90 uint16_t ac97_ext_hndst_DAC_ADC_rate; /* 44h, optional */ 91 uint16_t ac97_ext_line1_DAC_ADC_level; /* 46h, optional */ 92 uint16_t ac97_ext_line2_DAC_ADC_level; /* 48h, optional */ 93 uint16_t ac97_ext_hndst_DAC_ADC_level; /* 4ah, optional */ 94 uint16_t ac97_ext_GPIO_pin_config; /* 4ch, optional */ 95 uint16_t ac97_ext_GPIO_pin_polarity; /* 4eh, optional */ 96 uint16_t ac97_ext_GPIO_pin_sticky; /* 50h, optional */ 97 uint16_t ac97_ext_GPIO_pin_wakeup; /* 52h, optional */ 98 uint16_t ac97_ext_GPIO_pin_status; /* 54h, optional */ 99 uint16_t ac97_ext_modem_AFE_stat_ctrl; /* 56h, optional */ 100 uint16_t ac97_ext_reserved_2; /* 58h, optional */ 101 102 /* reserved for vendor usage */ 103 uint16_t ac97_vendor_01; /* 5ah, optional */ 104 uint16_t ac97_vendor_02; /* 5ch, optional */ 105 uint16_t ac97_vendor_03; /* 5eh, optional */ 106 uint16_t ac97_vendor_04; /* 60h, optional */ 107 uint16_t ac97_vendor_05; /* 62h, optional */ 108 uint16_t ac97_vendor_06; /* 64h, optional */ 109 uint16_t ac97_vendor_07; /* 66h, optional */ 110 uint16_t ac97_vendor_08; /* 68h, optional */ 111 uint16_t ac97_vendor_09; /* 6ah, optional */ 112 uint16_t ac97_vendor_10; /* 6ch, optional */ 113 uint16_t ac97_vendor_11; /* 6eh, optional */ 114 uint16_t ac97_vendor_12; /* 70h, optional */ 115 uint16_t ac97_vendor_13; /* 72h, optional */ 116 uint16_t ac97_vendor_14; /* 74h, optional */ 117 uint16_t ac97_vendor_15; /* 76h, optional */ 118 uint16_t ac97_vendor_16; /* 78h, optional */ 119 uint16_t ac97_vendor_17; /* 7ah, optional */ 120 121 uint16_t ac97_vendor_id1; /* 7ch */ 122 uint16_t ac97_vendor_id2; /* 7eh */ 123 }; 124 typedef struct ac97_v21 ac97_v21_t; 125 126 /* 127 * Defines for the V2.1 registers. 128 */ 129 130 /* Reset Register Index 00h */ 131 #define AC97_RESET_REGISTER 0x00 132 #define RR_DEDICATED_MIC 0x0001 133 #define RR_RESERVED 0x0002 134 #define RR_BASS_TREBLE 0x0004 135 #define RR_PSEUDO_STEREO 0x0008 136 #define RR_HEADPHONE_SUPPORT 0x0010 137 #define RR_LOUDNESS_SUPPORT 0x0020 138 #define RR_18_BIT_DAC 0x0040 139 #define RR_20_BIT_DAC 0x0080 140 #define RR_18_BIT_ADC 0x0100 141 #define RR_20_BIT_ADC 0x0200 142 #define RR_3D_STEREO_ENHANCE_MASK 0x7c00 143 144 /* Master Volume Register Index 02h */ 145 #define AC97_MASTER_VOLUME_REGISTER 0x02 146 #define MVR_RIGHT_MASK 0x001f 147 #define MVR_RIGHT_0dB_ATTEN 0x0000 148 #define MVR_RIGHT_OPTIONAL_MASK 0x003f 149 #define MVR_LEFT_MASK 0x1f00 150 #define MVR_LEFT_0dB_ATTEN 0x0000 151 #define MVR_LEFT_OPTIONAL_MASK 0x3f00 152 #define MVR_MUTE 0x8000 153 154 /* Headphone Volume Register Index 04h - Optional */ 155 #define AC97_HEADPHONE_VOLUME_REGISTER 0x04 156 #define HPVR_RIGHT_MASK 0x001f 157 #define HPVR_RIGHT_0dB_ATTEN 0x0000 158 #define HPVR_RIGHT_OPTIONAL_MASK 0x003f 159 #define HPVR_LEFT_MASK 0x1f00 160 #define HPVR_LEFT_0dB_ATTEN 0x0000 161 #define HPVR_LEFT_OPTIONAL_MASK 0x3f00 162 #define HPVR_MUTE 0x8000 163 164 /* Mono Master Volume Register Index 06h - Optional */ 165 #define AC97_MONO_MASTER_VOLUME_REGSITER 0x06 166 #define MMVR_MASK 0x001f 167 #define MMVR_0dB_ATTEN 0x0000 168 #define MMVR_OPTIONAL_MASK 0x003f 169 #define MMVR_MUTE 0x8000 170 171 /* Master Tone Control Register Index 08h - Optional */ 172 #define AC97_MASTER_TONE_CONTROL_REGISTER 0x08 173 #define MTCR_TREBLE_MASK 0x000e 174 #define MTCR_TREBLE_OPTIONAL_MASK 0x000f 175 #define MTCR_TREBLE_BYPASS 0x000f 176 #define MTCR_BASS_MASK 0x0e00 177 #define MTCR_BASS_OPTIONAL_MASK 0x0f00 178 #define MTCR_BASS_BYPASS 0x0f00 179 180 /* PC Beep Register Index 0ah - Optional */ 181 #define AC97_PC_BEEP_REGISTER 0x0a 182 #define PCBR_VOLUME_MASK 0x001e 183 #define PCBR_0dB_ATTEN 0x0000 184 #define PCBR_MUTE 0x8000 185 186 /* Phone Volume Register Index 0ch - Optional */ 187 #define AC97_PHONE_VOLUME_REGISTER 0x0c 188 #define PVR_GAIN_MASK 0x001f 189 #define PVR_0dB_GAIN 0x0010 190 #define PVR_MAX_ATTEN 0x001f 191 #define PVR_MUTE 0x8000 192 193 /* Mic Volume Register Index 0eh */ 194 #define AC97_MIC_VOLUME_REGISTER 0x0e 195 #define MICVR_GAIN_MASK 0x001f 196 #define MICVR_0dB_GAIN 0x0008 197 #define MICVR_MAX_ATTEN 0x001f 198 #define MICVR_20dB_BOOST 0x0040 199 #define MICVR_20dB_NOBOOST 0x0000 200 #define MICVR_MUTE 0x8000 201 202 /* Line In Volume Register Index 10h */ 203 #define AC97_LINE_IN_VOLUME_REGISTER 0x10 204 #define LIVR_RIGHT_GAIN_MASK 0x001f 205 #define LIVR_RIGHT_0dB_GAIN 0x0010 206 #define LIVR_RIGHT_MAX_ATTEN 0x001f 207 #define LIVR_LEFT_GAIN_MASK 0x1f00 208 #define LIVR_LEFT_0dB_GAIN 0x1000 209 #define LIVR_LEFT_MAX_ATTEN 0x1f00 210 #define LIVR_MUTE 0x8000 211 212 /* CD Volume Register Index 12h */ 213 #define AC97_CD_VOLUME_REGISTER 0x12 214 #define CDVR_RIGHT_GAIN_MASK 0x001f 215 #define CDVR_RIGHT_0dB_GAIN 0x0010 216 #define CDVR_RIGHT_MAX_ATTEN 0x001f 217 #define CDVR_LEFT_GAIN_MASK 0x1f00 218 #define CDVR_LEFT_0dB_GAIN 0x1000 219 #define CDVR_LEFT_MAX_ATTEN 0x1f00 220 #define CDVR_MUTE 0x8000 221 222 /* Video Volume Register Index 14h - Optional */ 223 #define AC97_VIDEO_VOLUME_REGISTER 0x14 224 #define VIDVR_RIGHT_GAIN_MASK 0x001f 225 #define VIDVR_RIGHT_0dB_GAIN 0x0010 226 #define VIDVR_RIGHT_MAX_ATTEN 0x001f 227 #define VIDVR_LEFT_GAIN_MASK 0x1f00 228 #define VIDVR_LEFT_0dB_GAIN 0x1000 229 #define VIDVR_LEFT_MAX_ATTEN 0x1f00 230 #define VIDVR_MUTE 0x8000 231 232 /* Aux Volume Register Index 16h - Optional */ 233 #define AC97_AUX_VOLUME_REGISTER 0x16 234 #define AUXVR_RIGHT_GAIN_MASK 0x001f 235 #define AUXVR_RIGHT_0dB_GAIN 0x0010 236 #define AUXVR_RIGHT_MAX_ATTEN 0x001f 237 #define AUXVR_LEFT_GAIN_MASK 0x1f00 238 #define AUXVR_LEFT_0dB_GAIN 0x1000 239 #define AUXVR_LEFT_MAX_ATTEN 0x1f00 240 #define AUXVR_MUTE 0x8000 241 242 /* PCM Out Input Volume Register Index 18h */ 243 #define AC97_PCM_OUT_VOLUME_REGISTER 0x18 244 #define PCMOVR_RIGHT_GAIN_MASK 0x001f 245 #define PCMOVR_RIGHT_0dB_GAIN 0x0010 246 #define PCMOVR_RIGHT_MAX_ATTEN 0x001f 247 #define PCMOVR_LEFT_GAIN_MASK 0x1f00 248 #define PCMOVR_LEFT_0dB_GAIN 0x1000 249 #define PCMOVR_LEFT_MAX_ATTEN 0x1f00 250 #define PCMOVR_MUTE 0x8000 251 #define PCMOVR_GAIN_BITS 5 252 253 /* Record Select Control Register Index 1ah */ 254 #define AC97_RECORD_SELECT_CTRL_REGISTER 0x1a 255 #define RSCR_R_MIC 0x0000 256 #define RSCR_R_CD 0x0001 257 #define RSCR_R_VIDEO 0x0002 258 #define RSCR_R_AUX 0x0003 259 #define RSCR_R_LINE_IN 0x0004 260 #define RSCR_R_STEREO_MIX 0x0005 261 #define RSCR_R_MONO_MIX 0x0006 262 #define RSCR_R_PHONE 0x0007 263 #define RSCR_L_MIC 0x0000 264 #define RSCR_L_CD 0x0100 265 #define RSCR_L_VIDEO 0x0200 266 #define RSCR_L_AUX 0x0300 267 #define RSCR_L_LINE_IN 0x0400 268 #define RSCR_L_STEREO_MIX 0x0500 269 #define RSCR_L_MONO_MIX 0x0600 270 #define RSCR_L_PHONE 0x0700 271 272 /* Record Gain Register Index 1ch */ 273 #define AC97_RECORD_GAIN_REGISTER 0x1c 274 #define RGR_RIGHT_MASK 0x000f 275 #define RGR_RIGHT_0db_GAIN 0x0000 276 #define RGR_RIGHT_MAX_GAIN 0x000f 277 #define RGR_LEFT_MASK 0x0f00 278 #define RGR_LEFT_0db_GAIN 0x0000 279 #define RGR_LEFT_MAX_GAIN 0x0f00 280 #define RGR_MUTE 0x8000 281 282 /* Record Gain Mic Register Index 1eh - Optional */ 283 #define AC97_RECORD_GAIN_MIC_REGISTER 0x1e 284 #define RGMR_MASK 0x000f 285 #define RGMR_MUTE 0x8000 286 #define RGMR_MASK 0x000f 287 #define RGMR_0db_GAIN 0x0000 288 #define RGMR_MAX_GAIN 0x000f 289 290 /* General Purpose Register Index 20h - Optional */ 291 #define AC97_GENERAL_PURPOSE_REGISTER 0x20 292 #define GPR_LPBK 0x0080 293 #define GPR_MS_MIC1 0x0000 294 #define GPR_MS_MIC2 0x0100 295 #define GPR_MONO_MIX_IN 0x0000 296 #define GPR_MONO_MIC_IN 0x0200 297 #define GPR_BASS_BOOST 0x1000 298 #define GPR_3D_STEREO_ENHANCE 0x2000 299 #define GPR_ST 0x4000 300 #define GPR_POP_PRE_3D 0x0000 301 #define GPR_POP_POST_3D 0x8000 302 303 /* 3D Control Regsiter Index 22h - Optional */ 304 #define AC97_THREE_D_CONTROL_REGISTER 0x22 305 #define TDCR_DEPTH_MASK 0x000f 306 #define TDCR_CENTER_MASK 0x0f00 307 #define TDCR_NULL 0x0000 308 309 /* Powerdown Control Status Register Index 26h */ 310 #define AC97_POWERDOWN_CTRL_STAT_REGISTER 0x26 311 #define PCSR_ADC 0x0001 312 #define PCSR_DAC 0x0002 313 #define PCSR_ANL 0x0004 314 #define PCSR_REF 0x0008 315 #define PCSR_POWERD_UP (PCSR_ADC|PCSR_DAC|\ 316 PCSR_ANL|PCSR_REF) 317 #define PCSR_PR0 0x0100 318 #define PCSR_PR1 0x0200 319 #define PCSR_PR2 0x0400 320 #define PCSR_PR3 0x0800 321 #define PCSR_PR4 0x1000 322 #define PCSR_PR5 0x2000 323 #define PCSR_PR6 0x4000 324 #define PCSR_EAPD 0x8000 325 326 /* Extended Audio Register Index 28h - Optional */ 327 #define AC97_EXTENDED_AUDIO_REGISTER 0x28 328 #define EAR_VRA 0x0001 329 #define EAR_DRA 0x0002 330 #define EAR_VRM 0x0008 331 #define EAR_CDAC 0x0040 332 #define EAR_SDAC 0x0080 333 #define EAR_LDAC 0x0100 334 #define EAR_AMAP 0x0200 335 #define EAR_PRIMARY_CODEC 0x0000 336 #define EAR_SECONDARY_01_CODEC 0x4000 337 #define EAR_SECONDARY_10_CODEC 0x8000 338 #define EAR_SECONDARY_11_CODEC 0xc000 339 340 /* Extended Audio Status and Control Register Index 2ah - Optional */ 341 #define AC97_EXTENDED_AUDIO_STAT_CTRL_REGISTER 0x2a 342 #define EASCR_VRA 0x0001 343 #define EASCR_DRA 0x0002 344 #define EASCR_VRM 0x0008 345 #define EASCR_CDAC 0x0040 346 #define EASCR_SDAC 0x0080 347 #define EASCR_LDAC 0x0100 348 #define EASCR_MADC 0x0200 349 #define EASCR_PRI 0x0800 350 #define EASCR_PRJ 0x1000 351 #define EASCR_PRK 0x2000 352 #define EASCR_PRL 0x4000 353 354 /* Extended Front DAC Rate Register 2ch - Optional */ 355 #define AC97_EXTENDED_FRONT_DAC_RATE_REGISTER 0x2c 356 #define AC97_SAMPLE_RATE_48000 0xbb80 357 358 /* Extended Surround DAC Rate Register 2eh - Optional */ 359 #define AC97_EXTENDED_SURROUND_DAC_RATE_REGISTER 0x2e 360 361 /* Extended LFE DAC Rate Register 30h - Optional */ 362 #define AC97_EXTENDED_LFE_DAC_RATE_REGISTER 0x30 363 364 /* Extended LR DAC Rate Register 32h - Optional */ 365 #define AC97_EXTENDED_LR_DAC_RATE_REGISTER 0x32 366 367 /* Extended Mic ADC Rate Register 34h - Optional */ 368 #define AC97_EXTENDED_MIC_ADC_RATE_REGISTER 0x34 369 370 /* Extended Center and LFE Volume Register 36h - Optional */ 371 #define AC97_EXTENDED_C_LFE_VOLUME_REGISTER 0x36 372 #define EXLFEVR_CENTER_MASK 0x001f 373 #define EXLFEVR_CENTER_OPTIONAL_MASK 0x003f 374 #define EXLFEVR_CENTER_MTUE 0x0080 375 #define EXLFEVR_LFE_MASK 0x1f00 376 #define EXLFEVR_LFE_OPTIONAL_MASK 0x3f00 377 #define EXLFEVR_LFE_MUTE 0x8000 378 379 /* Extended Left and Right Surround Volume Register 38h - Optional */ 380 #define AC97_EXTENDED_LRS_VOLUME_REGISTER 0x38 381 #define EXLFEVR_RIGHT_MASK 0x001f 382 #define EXLFEVR_RIGHT_OPTIONAL_MASK 0x003f 383 #define EXLFEVR_RIGHT_MTUE 0x0080 384 #define EXLFEVR_LEFT_MASK 0x1f00 385 #define EXLFEVR_LEFT_OPTIONAL_MASK 0x3f00 386 #define EXLFEVR_LEFT_MUTE 0x8000 387 388 /* Extended Modem ID Register 3ch - Optional */ 389 #define AC97_EXTENDED_MODEM_ID_REGISTER 0x3c 390 #define EMIDR_LINE1 0x0001 391 #define EMIDR_LINE2 0x0002 392 #define EMIDR_HSET 0x0004 393 #define EMIDR_CID1 0x0008 394 #define EMIDR_CID2 0x0010 395 #define EMIDR_PRIMARY_CODEC 0x0000 396 #define EMIDR_SECONDARY_01_CODEC 0x4000 397 #define EMIDR_SECONDARY_10_CODEC 0x8000 398 #define EMIDR_SECONDARY_11_CODEC 0xc000 399 400 /* Extended Modem Status and Control Register 3eh - Optional */ 401 #define AC97_EXTENDED_MODE_STAT_CTRL_REGISTER 0x3e 402 #define EMSCR_BPIO 0x0001 403 #define EMSCR_MREF 0x0002 404 #define EMSCR_ADC1 0x0004 405 #define EMSCR_DAC1 0x0008 406 #define EMSCR_ADC2 0x0010 407 #define EMSCR_DAC2 0x0020 408 #define EMSCR_HADC 0x0040 409 #define EMSCR_HDAC 0x0080 410 #define EMSCR_PRA 0x0100 411 #define EMSCR_PRB 0x0200 412 #define EMSCR_PRC 0x0400 413 #define EMSCR_PRD 0x0800 414 #define EMSCR_PRE 0x1000 415 #define EMSCR_PRF 0x2000 416 #define EMSCR_PRG 0x4000 417 #define EMSCR_PRH 0x8000 418 419 /* Extended Modem Line 1 DAC/ADC Sample Rate Register 40h - Optional */ 420 #define AC97_EXTENDED_MODEM_LINE1_RATE_REGISTER 0x40 421 422 /* Extended Modem Line 2 DAC/ADC Sample Rate Register 42h - Optional */ 423 #define AC97_EXTENDED_MODEM_LINE2_RATE_REGISTER 0x42 424 425 /* Extended Modem Handset Sample Rate Register 44h - Optional */ 426 #define AC97_EXTENDED_MODEM_HANDSET_RATE_REGISTER 0x44 427 428 /* Extended Modem Line 1 DAC/ADC Level Register 46h - Optional */ 429 #define AC97_EXTENDED_MODEM_LINE1_LEVEL_REGISTER 0x46 430 #define EML1LR_ADC_LEVEL_MASK 0x000f 431 #define EML1LR_ADC_LEVEL_MUTE 0x0080 432 #define EML1LR_DAC_LEVEL_MASK 0x0f00 433 #define EML1LR_DAC_LEVEL_MUTE 0x8000 434 435 /* Extended Modem Line 2 DAC/ADC Level Register 48h - Optional */ 436 #define AC97_EXTENDED_MODEM_LINE2_LEVEL_REGISTER 0x48 437 #define EML2LR_ADC_LEVEL_MASK 0x000f 438 #define EML2LR_ADC_LEVEL_MUTE 0x0080 439 #define EML2LR_DAC_LEVEL_MASK 0x0f00 440 #define EML2LR_DAC_LEVEL_MUTE 0x8000 441 442 /* Extended Modem Handset DAC/ADC Level Register 4ah - Optional */ 443 #define AC97_EXTENDED_MODEM_HANDSET_LEVEL_REGISTER 0x4a 444 #define EMHLR_ADC_LEVEL_MASK 0x000f 445 #define EMHLR_ADC_LEVEL_MUTE 0x0080 446 #define EMHLR_DAC_LEVEL_MASK 0x0f00 447 #define EMHLR_DAC_LEVEL_MUTE 0x8000 448 449 /* Extended Modem GPIO Pin Configuration Register 4ch - Optional */ 450 #define AC97_EXTENDED_MODEM_GPIO_PIN_REGISTER 0x4c 451 452 /* Extended Modem GPIO Pin Polarity Register 4eh - Optional */ 453 #define AC97_EXTENDED_MODEM_GPIO_POLARITY_REGISTER 0x4e 454 455 /* Extended Modem GPIO Pin Sticky Register 50h - Optional */ 456 #define AC97_EXTENDED_MODEM_GPIO_STICKY_REGISTER 0x50 457 458 /* Extended Modem GPIO Pin Wake-up Mask Register 52h - Optional */ 459 #define AC97_EXTENDED_MODEM_GPIO_WAKEUP_REGISTER 0x52 460 461 /* Extended Modem GPIO Pin Status Mask Register 54h - Optional */ 462 #define AC97_EXTENDED_MODEM_GPIO_STATUS_REGISTER 0x54 463 464 /* Extended Modem AFE Status and Control Register 56h - Optional */ 465 #define AC97_EXTENDED_MODEM_AFE_STAT_CTRL_REGISTER 0x56 466 #define EMAFESCR_L1B0 0x0001 467 #define EMAFESCR_L1B1 0x0002 468 #define EMAFESCR_L1B2 0x0004 469 #define EMAFESCR_L2B0 0x0010 470 #define EMAFESCR_L2B1 0x0020 471 #define EMAFESCR_L2B2 0x0040 472 #define EMAFESCR_HSB0 0x0100 473 #define EMAFESCR_HSB1 0x0200 474 #define EMAFESCR_HSB2 0x0400 475 #define EMAFESCR_MLINK_ON 0x0000 476 #define EMAFESCR_MLINK_OFF 0x1000 477 #define EMAFESCR_CIDR 0x2000 478 #define EMAFESCR_CID1 0x4000 479 #define EMAFESCR_CID2 0x8000 480 481 /* Vender Reserved Registers 5ah - 7ah - Optional */ 482 #define AC97_VENDOR_REGISTER_01 0x5a 483 #define AC97_VENDOR_REGISTER_02 0x5c 484 #define AC97_VENDOR_REGISTER_03 0x5e 485 #define AC97_VENDOR_REGISTER_04 0x60 486 #define AC97_VENDOR_REGISTER_05 0x62 487 #define AC97_VENDOR_REGISTER_06 0x64 488 #define AC97_VENDOR_REGISTER_07 0x66 489 #define AC97_VENDOR_REGISTER_08 0x68 490 #define AC97_VENDOR_REGISTER_09 0x6a 491 #define AC97_VENDOR_REGISTER_10 0x6c 492 #define AC97_VENDOR_REGISTER_11 0x6e 493 #define AC97_VENDOR_REGISTER_12 0x70 494 #define AC97_VENDOR_REGISTER_13 0x72 495 #define AC97_VENDOR_REGISTER_14 0x74 496 #define AC97_VENDOR_REGISTER_15 0x76 497 #define AC97_VENDOR_REGISTER_16 0x78 498 #define AC97_VENDOR_REGISTER_17 0x7a 499 500 /* Vendor ID1 Register 7ch */ 501 #define AC97_VENDOR_ID1_REGISTER 0x7c 502 #define VID1R_CHAR2_MASK 0x00ff 503 #define VID1R_CHAR1_MASK 0xff00 504 505 /* Vendor ID2 Register 7eh */ 506 #define AC97_VENDOR_ID2_REGISTER 0x7e 507 #define VID2R_REVISION_MASK 0x00ff 508 #define VID2R_CHAR3_MASK 0xff00 509 510 #endif /* _KERNEL */ 511 512 #ifdef __cplusplus 513 } 514 #endif 515 516 #endif /* _SYS_AC97_H */ 517