1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_AGPDEFS_H 28 #define _SYS_AGPDEFS_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 37 * This AGP memory type is required by some hardware like i810 video 38 * card, which need physical contiguous pages to setup hardware cursor. 39 * Usually, several tens of kilo bytes are needed in this case. 40 * We use DDI DMA interfaces to allocate such memory in agpgart driver, 41 * and it can not be exported to user applications directly by calling mmap 42 * on agpgart driver. The typical usage scenario is as the following: 43 * Firstly, Xserver get the memory physical address by calling AGPIOC_ALLOCATE 44 * on agpgart driver. Secondly, Xserver use the physical address to mmap 45 * the memory to Xserver space area by xsvc driver. 46 * 47 */ 48 #define AGP_PHYSICAL 2 /* Only used for i810, HW curosr */ 49 50 #ifdef _KERNEL 51 52 /* AGP space units */ 53 #define AGP_PAGE_SHIFT 12 54 #define AGP_PAGE_SIZE (1 << AGP_PAGE_SHIFT) 55 #define AGP_PAGE_OFFSET (AGP_PAGE_SIZE - 1) 56 #define AGP_MB2PAGES(x) ((x) << 8) 57 #define AGP_PAGES2BYTES(x) ((x) << AGP_PAGE_SHIFT) 58 #define AGP_BYTES2PAGES(x) ((x) >> AGP_PAGE_SHIFT) 59 #define AGP_PAGES2KB(x) ((x) << 2) 60 #define AGP_ALIGNED(offset) (((offset) & AGP_PAGE_OFFSET) == 0) 61 62 /* stand pci register offset */ 63 #define PCI_CONF_CAP_MASK 0x10 64 #define PCI_CONF_CAPID_MASK 0xff 65 #define PCI_CONF_NCAPID_MASK 0xff00 66 67 #define INTEL_VENDOR_ID 0x8086 68 #define AMD_VENDOR_ID 0x1022 69 #define VENDOR_ID_MASK 0xffff 70 71 /* macros for device types */ 72 #define DEVICE_IS_I810 11 /* intel i810 series video card */ 73 #define DEVICE_IS_I830 12 /* intel i830, i845, i855 series */ 74 #define DEVICE_IS_AGP 21 /* external AGP video card */ 75 #define CHIP_IS_INTEL 10 /* intel agp bridge */ 76 #define CHIP_IS_AMD 20 /* amd agp bridge */ 77 78 /* AGP bridge device id */ 79 #define AMD_BR_8151 0x74541022 80 #define INTEL_BR_810 0x71208086 81 #define INTEL_BR_810DC 0x71228086 82 #define INTEL_BR_810E 0x71248086 83 #define INTEL_BR_815 0x11308086 /* include 815G/EG/P/EP */ 84 #define INTEL_BR_830M 0x35758086 85 #define INTEL_BR_845 0x25608086 /* include 845G/P */ 86 #define INTEL_BR_855GM 0x35808086 /* include 852GM/PM */ 87 #define INTEL_BR_855PM 0x33408086 88 #define INTEL_BR_865 0x25708086 89 #define INTEL_BR_915 0x25808086 90 #define INTEL_BR_915GM 0x25908086 91 #define INTEL_BR_945 0x27708086 92 #define INTEL_BR_945GM 0x27a08086 93 #define INTEL_BR_946GZ 0x29708086 94 #define INTEL_BR_965G1 0x29808086 95 #define INTEL_BR_965Q 0x29908086 96 #define INTEL_BR_965G2 0x29a08086 97 #define INTEL_BR_965GM 0x2a008086 98 #define INTEL_BR_965GME 0x2a108086 99 #define INTEL_BR_Q35 0x29b08086 100 #define INTEL_BR_G33 0x29c08086 101 #define INTEL_BR_Q33 0x29d08086 102 #define INTEL_BR_GM45 0x2a408086 103 104 /* AGP common register offset in pci configuration space */ 105 #define AGP_CONF_MISC 0x51 /* one byte */ 106 #define AGP_CONF_CAPPTR 0x34 107 #define AGP_CONF_APERBASE 0x10 108 #define AGP_CONF_STATUS 0x04 /* CAP + 0x4 */ 109 #define AGP_CONF_COMMAND 0x08 /* CAP + 0x8 */ 110 111 /* AGP target register and mask defines */ 112 #define AGP_CONF_CONTROL 0x10 /* CAP + 0x10 */ 113 #define AGP_TARGET_BAR1 1 114 #define AGP_32_APERBASE_MASK 0xffc00000 /* 4M aligned */ 115 #define AGP_64_APERBASE_MASK 0xffffc00000LL /* 4M aligned */ 116 #define AGP_CONF_APERSIZE 0x14 /* CAP + 0x14 */ 117 #define AGP_CONF_ATTBASE 0x18 /* CAP + 0x18 */ 118 #define AGP_ATTBASE_MASK 0xfffff000 119 #define AGPCTRL_GTLBEN (0x1 << 7) 120 #define AGP_APER_TYPE_MASK 0x4 121 #define AGP_APER_SIZE_MASK 0xf00 122 #define AGP_APER_128M_MASK 0x3f 123 #define AGP_APER_4G_MASK 0xf00 124 #define AGP_APER_4M 0x3f 125 #define AGP_APER_8M 0x3e 126 #define AGP_APER_16M 0x3c 127 #define AGP_APER_32M 0x38 128 #define AGP_APER_64M 0x30 129 #define AGP_APER_128M 0x20 130 #define AGP_APER_256M 0xf00 131 #define AGP_APER_512M 0xe00 132 #define AGP_APER_1024M 0xc00 133 #define AGP_APER_2048M 0x800 134 #define AGP_APER_4G 0x000 135 #define AGP_MISC_APEN 0x2 136 137 /* AGP gart table definition */ 138 #define AGP_ENTRY_VALID 0x1 139 140 /* AGP term definitions */ 141 #define AGP_CAP_ID 0x2 142 #define AGP_CAP_OFF_DEF 0xa0 143 144 /* Intel integrated video card, chipset id */ 145 #define INTEL_IGD_810 0x71218086 146 #define INTEL_IGD_810DC 0x71238086 147 #define INTEL_IGD_810E 0x71258086 148 #define INTEL_IGD_815 0x11328086 149 #define INTEL_IGD_830M 0x35778086 150 #define INTEL_IGD_845G 0x25628086 151 #define INTEL_IGD_855GM 0x35828086 152 #define INTEL_IGD_865G 0x25728086 153 #define INTEL_IGD_915 0x25828086 154 #define INTEL_IGD_915GM 0x25928086 155 #define INTEL_IGD_945 0x27728086 156 #define INTEL_IGD_945GM 0x27a28086 157 #define INTEL_IGD_946GZ 0x29728086 158 #define INTEL_IGD_965G1 0x29828086 159 #define INTEL_IGD_965Q 0x29928086 160 #define INTEL_IGD_965G2 0x29a28086 161 #define INTEL_IGD_965GM 0x2a028086 162 #define INTEL_IGD_965GME 0x2a128086 163 #define INTEL_IGD_Q35 0x29b28086 164 #define INTEL_IGD_G33 0x29c28086 165 #define INTEL_IGD_Q33 0x29d28086 166 #define INTEL_IGD_GM45 0x2a428086 167 168 /* register offsets in PCI config space */ 169 #define I8XX_CONF_GMADR 0x10 /* GMADR of i8xx series */ 170 #define I915_CONF_GMADR 0x18 /* GMADR of i915 series */ 171 /* (Mirror) GMCH Graphics Control Register (GGC, MGGC) */ 172 #define I8XX_CONF_GC 0x52 173 174 /* Intel integrated video card graphics mode mask */ 175 #define I8XX_GC_MODE_MASK 0x70 176 #define IX33_GC_MODE_MASK 0xf0 177 /* GTT Graphics Memory Size (9:8) in GMCH Graphics Control Register */ 178 #define IX33_GGMS_MASK 0x300 179 /* No VT mode, 1MB allocated for GTT */ 180 #define IX33_GGMS_1M 0x100 181 /* VT mode, 2MB allocated for GTT */ 182 #define IX33_GGMS_2M 0x200 183 184 /* Intel integrated video card GTT definition */ 185 #define GTT_PAGE_SHIFT 12 186 #define GTT_PAGE_SIZE (1 << GTT_PAGE_SHIFT) 187 #define GTT_PAGE_OFFSET (GTT_PAGE_SIZE - 1) 188 #define GTT_PTE_MASK (~GTT_PAGE_OFFSET) 189 #define GTT_PTE_VALID 0x1 190 #define GTT_TABLE_VALID 0x1 191 #define GTT_BASE_MASK 0xfffff000 192 #define GTT_MB_TO_PAGES(m) ((m) << 8) 193 #define GTT_POINTER_MASK 0xffffffff00000000 194 195 /* Intel i810 register offset */ 196 #define I810_POINTER_MASK 0xffffffffc0000000 197 #define I810_CONF_SMRAM 0x70 /* offset in PCI config space */ 198 #define I810_GMS_MASK 0xc0 /* smram register mask */ 199 /* 200 * GART and GTT entry format table 201 * 202 * AMD64 GART entry 203 * from bios and kernel develop guide for amd64 204 * ----------------------------- 205 * Bits Description | 206 * 0 valid | 207 * 1 coherent | 208 * 3:2 reserved | 209 * 11:4 physaddr[39:32] | 210 * 31:12 physaddr[31:12] | 211 * ----------------------------- 212 * Intel GTT entry 213 * Intel video programming manual 214 * ----------------------------- 215 * Bits descrition | 216 * 0 valid | 217 * 2:1 memory type | 218 * 29:12 PhysAddr[29:12] | 219 * 31:30 reserved | 220 * ----------------------------- 221 * AGP entry 222 * from AGP protocol 3.0 223 * ----------------------------- 224 * Bits descrition | 225 * 0 valid | 226 * 1 coherent | 227 * 3:2 reserved | 228 * 11:4 PhysAddr[39:32] | 229 * 31:12 PhysAddr[31:12] | 230 * 63:32 PhysAddr[71:40] | 231 * ----------------------------- 232 */ 233 234 /* 235 * gart and gtt table base register format 236 * 237 * AMD64 register format 238 * from bios and kernel develop guide for AMD64 239 * --------------------------------------------- 240 * Bits Description | 241 * 3:0 reserved | 242 * 31:4 physical addr 39:12 | 243 * ---------------------------------------------- 244 * INTEL AGPGART table base register format 245 * from AGP protocol 3.0 p142, only support 32 bits 246 * --------------------------------------------- 247 * Bits Description | 248 * 11:0 reserved | 249 * 31:12 physical addr 31:12 | 250 * 63:32 physical addr 63:32 | 251 * --------------------------------------------- 252 * INTEL i810 GTT table base register format 253 * _____________________________________________ 254 * Bits Description | 255 * 0 GTT table enable bit | 256 * 11:1 reserved | 257 * 31:12 physical addr 31:12 | 258 * --------------------------------------------- 259 */ 260 261 /* Intel agp bridge specific */ 262 #define AGP_INTEL_POINTER_MASK 0xffffffff00000000 263 264 /* Amd64 cpu gart device reigster offset */ 265 #define AMD64_APERTURE_CONTROL 0x90 266 #define AMD64_APERTURE_BASE 0x94 267 #define AMD64_GART_CACHE_CTL 0x9c 268 #define AMD64_GART_BASE 0x98 269 270 /* Amd64 cpu gart bits */ 271 #define AMD64_APERBASE_SHIFT 25 272 #define AMD64_APERBASE_MASK 0x00007fff 273 #define AMD64_GARTBASE_SHIFT 8 274 #define AMD64_GARTBASE_MASK 0xfffffff0 275 #define AMD64_POINTER_MASK 0xffffff0000000000 276 #define AMD64_INVALID_CACHE 0x1 277 #define AMD64_GART_SHIFT 12 278 #define AMD64_RESERVE_SHIFT 4 279 #define AMD64_APERSIZE_MASK 0xe 280 #define AMD64_GARTEN 0x1 281 #define AMD64_DISGARTCPU 0x10 282 #define AMD64_DISGARTIO 0x20 283 #define AMD64_ENTRY_VALID 0x1 284 285 /* Other common routines */ 286 #define MB2BYTES(m) ((m) << 20) 287 #define BYTES2MB(m) ((m) >> 20) 288 #define GIGA_MASK 0xC0000000 289 #define UI32_MASK 0xffffffffU 290 #define MAXAPERMEGAS 0x1000 /* Aper size no more than 4G */ 291 292 #endif /* _KERNEL */ 293 294 #ifdef __cplusplus 295 } 296 #endif 297 298 #endif /* _SYS_AGPDEFS_H */ 299