1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * Copyright (c) 2002-2005 Neterion, Inc. 29 * All right Reserved. 30 * 31 * FileName : xgell.h 32 * 33 * Description: Link Layer driver declaration 34 * 35 */ 36 37 #ifndef _SYS_XGELL_H 38 #define _SYS_XGELL_H 39 40 #pragma ident "%Z%%M% %I% %E% SMI" 41 42 #include <sys/types.h> 43 #include <sys/errno.h> 44 #include <sys/param.h> 45 #include <sys/stropts.h> 46 #include <sys/stream.h> 47 #include <sys/strsubr.h> 48 #include <sys/kmem.h> 49 #include <sys/conf.h> 50 #include <sys/devops.h> 51 #include <sys/ksynch.h> 52 #include <sys/stat.h> 53 #include <sys/modctl.h> 54 #include <sys/debug.h> 55 #include <sys/pci.h> 56 #include <sys/ethernet.h> 57 #include <sys/vlan.h> 58 #include <sys/dlpi.h> 59 #include <sys/taskq.h> 60 #include <sys/cyclic.h> 61 62 #include <sys/pattr.h> 63 #include <sys/strsun.h> 64 65 #include <sys/mac.h> 66 #include <sys/mac_ether.h> 67 68 #ifdef __cplusplus 69 extern "C" { 70 #endif 71 72 #define XGELL_DESC "Xframe I/II 10Gb Ethernet 1.11" 73 #define XGELL_IFNAME "xge" 74 #define XGELL_TX_LEVEL_LOW 8 75 #define XGELL_TX_LEVEL_HIGH 32 76 #define XGELL_TX_LEVEL_CHECK 3 77 #define XGELL_MAX_RING_DEFAULT 8 78 #define XGELL_MAX_FIFO_DEFAULT 1 79 80 #include <xgehal.h> 81 82 /* 83 * The definition of XGELL_RX_BUFFER_RECYCLE_CACHE is an experimental value. 84 * With this value, the lock contention between xgell_rx_buffer_recycle() 85 * and xgell_rx_1b_compl() is reduced to great extent. And multiple rx rings 86 * alleviate the lock contention further since each rx ring has its own mutex. 87 */ 88 #define XGELL_RX_BUFFER_RECYCLE_CACHE XGE_HAL_RING_RXDS_PER_BLOCK(1) * 2 89 #define MSG_SIZE 64 90 91 /* 92 * These default values can be overridden by vaules in xge.conf. 93 * In xge.conf user has to specify actual (not percentages) values. 94 */ 95 #define XGELL_RX_BUFFER_TOTAL XGE_HAL_RING_RXDS_PER_BLOCK(1) * 6 96 #define XGELL_RX_BUFFER_POST_HIWAT XGE_HAL_RING_RXDS_PER_BLOCK(1) * 5 97 98 /* Control driver to copy or DMA received packets */ 99 #define XGELL_RX_DMA_LOWAT 256 100 101 #define XGELL_RING_MAIN_QID 0 102 103 #if defined(__x86) 104 #define XGELL_TX_DMA_LOWAT 128 105 #else 106 #define XGELL_TX_DMA_LOWAT 512 107 #endif 108 109 /* 110 * Try to collapse up to XGELL_RX_PKT_BURST packets into single mblk 111 * sequence before mac_rx() is called. 112 */ 113 #define XGELL_RX_PKT_BURST 32 114 115 /* About 1s */ 116 #define XGE_DEV_POLL_TICKS drv_usectohz(1000000) 117 118 #define XGELL_LSO_MAXLEN 65535 119 #define XGELL_CONF_ENABLE_BY_DEFAULT 1 120 #define XGELL_CONF_DISABLE_BY_DEFAULT 0 121 122 /* LRO configuration */ 123 #define XGE_HAL_DEFAULT_LRO_SG_SIZE 2 /* <=2 LRO fix not required */ 124 #define XGE_HAL_DEFAULT_LRO_FRM_LEN 65535 125 126 /* 127 * Default values for tunables used in HAL. Please refer to xgehal-config.h 128 * for more details. 129 */ 130 #define XGE_HAL_DEFAULT_USE_HARDCODE -1 131 132 /* Bimodal adaptive schema defaults - ENABLED */ 133 #define XGE_HAL_DEFAULT_BIMODAL_INTERRUPTS -1 134 #define XGE_HAL_DEFAULT_BIMODAL_TIMER_LO_US 24 135 #define XGE_HAL_DEFAULT_BIMODAL_TIMER_HI_US 256 136 137 /* Interrupt moderation/utilization defaults */ 138 #define XGE_HAL_DEFAULT_TX_URANGE_A 5 139 #define XGE_HAL_DEFAULT_TX_URANGE_B 15 140 #define XGE_HAL_DEFAULT_TX_URANGE_C 30 141 #define XGE_HAL_DEFAULT_TX_UFC_A 15 142 #define XGE_HAL_DEFAULT_TX_UFC_B 30 143 #define XGE_HAL_DEFAULT_TX_UFC_C 45 144 #define XGE_HAL_DEFAULT_TX_UFC_D 60 145 #define XGE_HAL_DEFAULT_TX_TIMER_CI_EN 1 146 #define XGE_HAL_DEFAULT_TX_TIMER_AC_EN 1 147 #define XGE_HAL_DEFAULT_TX_TIMER_VAL 10000 148 #define XGE_HAL_DEFAULT_INDICATE_MAX_PKTS_B 512 /* bimodal */ 149 #define XGE_HAL_DEFAULT_INDICATE_MAX_PKTS_N 256 /* normal UFC */ 150 #define XGE_HAL_DEFAULT_RX_URANGE_A 10 151 #define XGE_HAL_DEFAULT_RX_URANGE_B 30 152 #define XGE_HAL_DEFAULT_RX_URANGE_C 50 153 #define XGE_HAL_DEFAULT_RX_UFC_A 1 154 #define XGE_HAL_DEFAULT_RX_UFC_B_J 2 155 #define XGE_HAL_DEFAULT_RX_UFC_B_N 8 156 #define XGE_HAL_DEFAULT_RX_UFC_C_J 4 157 #define XGE_HAL_DEFAULT_RX_UFC_C_N 16 158 #define XGE_HAL_DEFAULT_RX_UFC_D 32 159 #define XGE_HAL_DEFAULT_RX_TIMER_AC_EN 1 160 #define XGE_HAL_DEFAULT_RX_TIMER_VAL 384 161 162 #define XGE_HAL_DEFAULT_FIFO_QUEUE_LENGTH_J 2048 163 #define XGE_HAL_DEFAULT_FIFO_QUEUE_LENGTH_N 4096 164 #define XGE_HAL_DEFAULT_FIFO_QUEUE_INTR 0 165 #define XGE_HAL_DEFAULT_FIFO_RESERVE_THRESHOLD 0 166 #define XGE_HAL_DEFAULT_FIFO_MEMBLOCK_SIZE PAGESIZE 167 168 /* 169 * This will force HAL to allocate extra copied buffer per TXDL which 170 * size calculated by formula: 171 * 172 * (ALIGNMENT_SIZE * ALIGNED_FRAGS) 173 */ 174 #define XGE_HAL_DEFAULT_FIFO_ALIGNMENT_SIZE 4096 175 #define XGE_HAL_DEFAULT_FIFO_MAX_ALIGNED_FRAGS 1 176 #if defined(__x86) 177 #define XGE_HAL_DEFAULT_FIFO_FRAGS 128 178 #else 179 #define XGE_HAL_DEFAULT_FIFO_FRAGS 64 180 #endif 181 #define XGE_HAL_DEFAULT_FIFO_FRAGS_THRESHOLD 18 182 183 #define XGE_HAL_DEFAULT_RING_QUEUE_BLOCKS_J 2 184 #define XGE_HAL_DEFAULT_RING_QUEUE_BLOCKS_N 2 185 #define XGE_HAL_RING_QUEUE_BUFFER_MODE_DEFAULT 1 186 #define XGE_HAL_DEFAULT_BACKOFF_INTERVAL_US 64 187 #define XGE_HAL_DEFAULT_RING_PRIORITY 0 188 #define XGE_HAL_DEFAULT_RING_MEMBLOCK_SIZE PAGESIZE 189 190 #define XGE_HAL_DEFAULT_RING_NUM 8 191 #define XGE_HAL_DEFAULT_TMAC_UTIL_PERIOD 5 192 #define XGE_HAL_DEFAULT_RMAC_UTIL_PERIOD 5 193 #define XGE_HAL_DEFAULT_RMAC_HIGH_PTIME 65535 194 #define XGE_HAL_DEFAULT_MC_PAUSE_THRESHOLD_Q0Q3 187 195 #define XGE_HAL_DEFAULT_MC_PAUSE_THRESHOLD_Q4Q7 187 196 #define XGE_HAL_DEFAULT_RMAC_PAUSE_GEN_EN 1 197 #define XGE_HAL_DEFAULT_RMAC_PAUSE_GEN_DIS 0 198 #define XGE_HAL_DEFAULT_RMAC_PAUSE_RCV_EN 1 199 #define XGE_HAL_DEFAULT_RMAC_PAUSE_RCV_DIS 0 200 #define XGE_HAL_DEFAULT_INITIAL_MTU XGE_HAL_DEFAULT_MTU /* 1500 */ 201 #define XGE_HAL_DEFAULT_ISR_POLLING_CNT 0 202 #define XGE_HAL_DEFAULT_LATENCY_TIMER 255 203 #define XGE_HAL_DEFAULT_SHARED_SPLITS 0 204 #define XGE_HAL_DEFAULT_STATS_REFRESH_TIME 1 205 206 #if defined(__sparc) 207 #define XGE_HAL_DEFAULT_MMRB_COUNT \ 208 XGE_HAL_MAX_MMRB_COUNT 209 #define XGE_HAL_DEFAULT_SPLIT_TRANSACTION \ 210 XGE_HAL_EIGHT_SPLIT_TRANSACTION 211 #else 212 #define XGE_HAL_DEFAULT_MMRB_COUNT 1 /* 1k */ 213 #define XGE_HAL_DEFAULT_SPLIT_TRANSACTION \ 214 XGE_HAL_TWO_SPLIT_TRANSACTION 215 #endif 216 217 /* 218 * default the size of buffers allocated for ndd interface functions 219 */ 220 #define XGELL_STATS_BUFSIZE 8192 221 #define XGELL_PCICONF_BUFSIZE 2048 222 #define XGELL_ABOUT_BUFSIZE 512 223 #define XGELL_IOCTL_BUFSIZE 64 224 #define XGELL_DEVCONF_BUFSIZE 8192 225 226 /* 227 * xgell_event_e 228 * 229 * This enumeration derived from xgehal_event_e. It extends it 230 * for the reason to get serialized context. 231 */ 232 /* Renamb the macro from HAL */ 233 #define XGELL_EVENT_BASE XGE_LL_EVENT_BASE 234 typedef enum xgell_event_e { 235 /* LL events */ 236 XGELL_EVENT_RESCHED_NEEDED = XGELL_EVENT_BASE + 1, 237 } xgell_event_e; 238 239 typedef struct { 240 int rx_pkt_burst; 241 int rx_buffer_total; 242 int rx_buffer_post_hiwat; 243 int rx_dma_lowat; 244 int tx_dma_lowat; 245 int msix_enable; 246 int lso_enable; 247 } xgell_config_t; 248 249 typedef struct xgell_ring xgell_ring_t; 250 typedef struct xgell_fifo xgell_fifo_t; 251 252 typedef struct xgell_rx_buffer_t { 253 struct xgell_rx_buffer_t *next; 254 void *vaddr; 255 dma_addr_t dma_addr; 256 ddi_dma_handle_t dma_handle; 257 ddi_acc_handle_t dma_acch; 258 xgell_ring_t *ring; 259 frtn_t frtn; 260 } xgell_rx_buffer_t; 261 262 /* Buffer pool for all rings */ 263 typedef struct xgell_rx_buffer_pool_t { 264 uint_t total; /* total buffers */ 265 uint_t size; /* buffer size */ 266 xgell_rx_buffer_t *head; /* header pointer */ 267 uint_t free; /* free buffers */ 268 uint_t post; /* posted buffers */ 269 uint_t post_hiwat; /* hiwat to stop post */ 270 spinlock_t pool_lock; /* buffer pool lock */ 271 xgell_rx_buffer_t *recycle_head; /* recycle list's head */ 272 xgell_rx_buffer_t *recycle_tail; /* recycle list's tail */ 273 uint_t recycle; /* # of rx buffers recycled */ 274 spinlock_t recycle_lock; /* buffer recycle lock */ 275 } xgell_rx_buffer_pool_t; 276 277 typedef struct xgelldev xgelldev_t; 278 279 struct xgell_ring { 280 xge_hal_channel_h channelh; 281 xgelldev_t *lldev; 282 mac_resource_handle_t handle; /* per ring cookie */ 283 xgell_rx_buffer_pool_t bf_pool; 284 }; 285 286 struct xgell_fifo { 287 xge_hal_channel_h channelh; 288 xgelldev_t *lldev; 289 int level_low; 290 }; 291 292 struct xgelldev { 293 caddr_t ndp; 294 mac_handle_t mh; 295 int instance; 296 dev_info_t *dev_info; 297 xge_hal_device_h devh; 298 xgell_ring_t rings[XGE_HAL_MAX_RING_NUM]; 299 xgell_fifo_t fifos[XGE_HAL_MAX_FIFO_NUM]; 300 int resched_avail; 301 int resched_send; 302 int resched_retry; 303 int tx_copied_max; 304 volatile int is_initialized; 305 xgell_config_t config; 306 volatile int in_reset; 307 timeout_id_t timeout_id; 308 kmutex_t genlock; 309 ddi_intr_handle_t *intr_table; 310 uint_t intr_table_size; 311 int intr_type; 312 int intr_cnt; 313 uint_t intr_pri; 314 int intr_cap; 315 }; 316 317 typedef struct { 318 mblk_t *mblk; 319 ddi_dma_handle_t dma_handles[XGE_HAL_DEFAULT_FIFO_FRAGS]; 320 int handle_cnt; 321 } xgell_txd_priv_t; 322 323 typedef struct { 324 xgell_rx_buffer_t *rx_buffer; 325 } xgell_rxd_priv_t; 326 327 int xgell_device_alloc(xge_hal_device_h devh, dev_info_t *dev_info, 328 xgelldev_t **lldev_out); 329 330 void xgell_device_free(xgelldev_t *lldev); 331 332 int xgell_device_register(xgelldev_t *lldev, xgell_config_t *config); 333 334 int xgell_device_unregister(xgelldev_t *lldev); 335 336 void xgell_callback_link_up(void *userdata); 337 338 void xgell_callback_link_down(void *userdata); 339 340 int xgell_onerr_reset(xgelldev_t *lldev); 341 342 void xge_device_poll_now(void *data); 343 344 int xge_add_intrs(xgelldev_t *lldev); 345 346 int xge_enable_intrs(xgelldev_t *lldev); 347 348 void xge_disable_intrs(xgelldev_t *lldev); 349 350 void xge_rem_intrs(xgelldev_t *lldev); 351 352 353 354 355 #ifdef __cplusplus 356 } 357 #endif 358 359 #endif /* _SYS_XGELL_H */ 360