xref: /titanic_50/usr/src/uts/common/io/vr/vr_impl.h (revision 13237b7e1e5bd293e466307b2e06f8e0e2321a0a)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 /*
28  * Register definitions for the VIA Rhine ethernet adapters
29  */
30 #ifndef _VRREG_H
31 #define	_VRREG_H
32 
33 #ifdef __cplusplus
34 	extern "C" {
35 #endif
36 
37 /*
38  * Some definitions for the MII because miiregs doesn't have them
39  */
40 #define	MII_STATUS_100_BASE_T2_FD	(1 << 10)
41 #define	MII_STATUS_100_BASE_T2		(1 << 9)
42 #define	MII_STATUS_CAPEXT		(1 << 8)
43 #define	MII_ABILITY_ASMDIR		(1 << 6)
44 #define	MII_EXTSTATUS			0x9
45 #define	MII_EXTSTATUS_1000BASE_X_FD	0x8000
46 #define	MII_EXTSTATUS_1000BASE_X	0x4000
47 #define	MII_EXTSTATUS_1000BASE_T_FD	0x2000
48 #define	MII_EXTSTATUS_1000BASE_T	0x1000
49 
50 /*
51  * MAC address
52  */
53 #define	VR_ETHERADDR	0x00
54 
55 /*
56  * Receive Configuration
57  * The thresholds denote the level in the FIFO before transmission
58  * to host memory starts.
59  */
60 #define	VR_RXCFG			0x06
61 #define	VR_RXCFG_ACCEPTERROR		(1 << 0)
62 #define	VR_RXCFG_ACCEPTRUNT		(1 << 1)
63 #define	VR_RXCFG_ACCEPTMULTI		(1 << 2)
64 #define	VR_RXCFG_ACCEPTBROAD		(1 << 3)
65 #define	VR_RXCFG_PROMISC		(1 << 4)
66 #define	VR_RXCFG_FIFO_THRESHOLD_0	(1 << 5)
67 #define	VR_RXCFG_FIFO_THRESHOLD_1	(1 << 6)
68 #define	VR_RXCFG_FIFO_THRESHOLD_2	(1 << 7)
69 #define	VR_RXCFG_FIFO_THRESHOLD_BITS	(VR_RXCFG_FIFO_THRESHOLD_0 | \
70 					    VR_RXCFG_FIFO_THRESHOLD_1 | \
71 					    VR_RXCFG_FIFO_THRESHOLD_2)
72 #define	VR_RXCFG_FIFO_THRESHOLD_64	(0)
73 #define	VR_RXCFG_FIFO_THRESHOLD_32	(VR_RXCFG_FIFO_THRESHOLD_0)
74 #define	VR_RXCFG_FIFO_THRESHOLD_128	(VR_RXCFG_FIFO_THRESHOLD_1)
75 #define	VR_RXCFG_FIFO_THRESHOLD_256	(VR_RXCFG_FIFO_THRESHOLD_0 | \
76 					    VR_RXCFG_FIFO_THRESHOLD_1)
77 #define	VR_RXCFG_FIFO_THRESHOLD_512	(VR_RXCFG_FIFO_THRESHOLD_2)
78 #define	VR_RXCFG_FIFO_THRESHOLD_768	(VR_RXCFG_FIFO_THRESHOLD_0 | \
79 					    VR_RXCFG_FIFO_THRESHOLD_2)
80 #define	VR_RXCFG_FIFO_THRESHOLD_1024	(VR_RXCFG_FIFO_THRESHOLD_2 | \
81 					    VR_RXCFG_FIFO_THRESHOLD_1)
82 #define	VR_RXCFG_FIFO_THRESHOLD_STFW	(VR_RXCFG_FIFO_THRESHOLD_BITS)
83 
84 /*
85  * Transmit Configuration
86  * The transmission starts when the data in the FIFO reaches the threshold.
87  * Store and Forward means that a transmission starts when a complete frame
88  * is in the FIFO.
89  */
90 #define	VR_TXCFG			0x07
91 #define	VR_TXCFG_8021PQ_EN		(1 << 0)	/* VT6105M */
92 #define	VR_TXCFG_LOOPBACK_0		(1 << 1)
93 #define	VR_TXCFG_LOOPBACK_1		(2 << 2)
94 #define	VR_TXCFG_BACKOFF_NATIONAL	(1 << 3)	/* < VT6105M */
95 #define	VR_TXCFG_FIFO_THRESHOLD_0	(1 << 5)
96 #define	VR_TXCFG_FIFO_THRESHOLD_1	(1 << 6)
97 #define	VR_TXCFG_FIFO_THRESHOLD_2	(1 << 7)
98 #define	VR_TXCFG_FIFO_THRESHOLD_BITS	(VR_TXCFG_FIFO_THRESHOLD_0 | \
99 					    VR_TXCFG_FIFO_THRESHOLD_1 | \
100 					    VR_TXCFG_FIFO_THRESHOLD_2)
101 #define	VR_TXCFG_FIFO_THRESHOLD_128	(0)
102 #define	VR_TXCFG_FIFO_THRESHOLD_256	(VR_TXCFG_FIFO_THRESHOLD_0)
103 #define	VR_TXCFG_FIFO_THRESHOLD_512	(VR_TXCFG_FIFO_THRESHOLD_1)
104 #define	VR_TXCFG_FIFO_THRESHOLD_1024	(VR_TXCFG_FIFO_THRESHOLD_0 | \
105 					    VR_TXCFG_FIFO_THRESHOLD_1)
106 #define	VR_TXCFG_FIFO_THRESHOLD_STFW	(VR_TXCFG_FIFO_THRESHOLD_BITS)
107 
108 /*
109  * Chip control
110  */
111 #define	VR_CTRL0			0x08
112 #define	VR_CTRL0_RESERVED		(1 << 0)
113 #define	VR_CTRL0_DMA_ENABLE		(1 << 1)
114 #define	VR_CTRL0_DMA_STOP		(1 << 2)
115 #define	VR_CTRL0_RX_DMA_ENABLE		(1 << 3)
116 #define	VR_CTRL0_TX_DMA_ENABLE		(1 << 4)
117 #define	VR_CTRL0_TXPOLL			(1 << 5)	/* < 6105M */
118 #define	VR_CTRL0_RXPOLL			(1 << 6)	/* < 6105M */
119 
120 #define	VR_CTRL0_DMA_GO			(VR_CTRL0_DMA_ENABLE | \
121 					    VR_CTRL0_RX_DMA_ENABLE | \
122 					    VR_CTRL0_TX_DMA_ENABLE | \
123 					    VR_CTRL0_TXPOLL)
124 #define	VR_CTRL1			0x09
125 #define	VR_CTRL1_RESERVED		(1 << 0)
126 #define	VR_CTRL1_UNICAST_EN		(1 << 1)
127 #define	VR_CTRL1_MACFULLDUPLEX		(1 << 2)
128 #define	VR_CTRL1_NOAUTOPOLL		(1 << 3)
129 #define	VR_CTRL1_RESERVED2		(1 << 4)
130 #define	VR_CTRL1_TXPOLL			(1 << 5)	/* VT6105M */
131 #define	VR_CTRL1_RXPOLL			(1 << 6)	/* VT6105M */
132 #define	VR_CTRL1_RESET			(1 << 7)
133 
134 #define	VR_T_XQNWAKE			0x0a		/* VT6105M */
135 
136 /*
137  * Interrupt Status
138  * This register reflects NIC status
139  * The host reads it to determine the cause of the interrupt
140  * This register must be cleared after power-up
141  */
142 #define	VR_ISR0			0x0C
143 #define	VR_ISR0_RX_DONE		(1 << 0)
144 #define	VR_ISR0_TX_DONE		(1 << 1)
145 #define	VR_ISR0_RX_ERR		(1 << 2)
146 #define	VR_ISR0_TX_ERR		(1 << 3)
147 #define	VR_ISR0_TX_BUF_UFLOW	(1 << 4)
148 #define	VR_ISR0_RX_LINKERR	(1 << 5)
149 #define	VR_ISR0_BUSERR		(1 << 6)
150 #define	VR_ISR0_STATSMAX	(1 << 7)
151 #define	VR_ISR0_RX_EARLY	(1 << 8)
152 #define	VR_ISR0_TX_FIFO_UFLOW	(1 << 9)
153 #define	VR_ISR0_RX_FIFO_OFLOW	(1 << 10)
154 #define	VR_ISR0_RX_DROPPED	(1 << 11)
155 #define	VR_ISR0_RX_NOBUF	(1 << 12)
156 #define	VR_ISR0_TX_ABORT	(1 << 13)
157 #define	VR_ISR0_LINKSTATUS	(1 << 14)
158 #define	VR_ISR0_GENERAL		(1 << 15)
159 
160 /*
161  * Interrupt Configuration
162  * All bits in this register correspond to the bits in the Interrupt Status
163  * register Setting individual bits will enable the corresponding interrupt
164  * This register defaults to all zeros on power up
165  */
166 #define	VR_ICR0			0x0E
167 #define	VR_ICR0_RX_DONE		VR_ISR0_RX_DONE
168 #define	VR_ICR0_TX_DONE		VR_ISR0_TX_DONE
169 #define	VR_ICR0_RX_ERR		VR_ISR0_RX_ERR
170 #define	VR_ICR0_TX_ERR		VR_ISR0_TX_ERR
171 #define	VR_ICR0_TX_BUF_UFLOW	VR_ISR0_TX_BUF_UFLOW
172 #define	VR_ICR0_RX_LINKERR	VR_ISR0_RX_LINKERR
173 #define	VR_ICR0_BUSERR		VR_ISR0_BUSERR
174 #define	VR_ICR0_STATSMAX	VR_ISR0_STATSMAX
175 #define	VR_ICR0_RX_EARLY	VR_ISR0_RX_EARLY
176 #define	VR_ICR0_TX_FIFO_UFLOW	VR_ISR0_TX_FIFO_UFLOW
177 #define	VR_ICR0_RX_FIFO_OFLOW	VR_ISR0_RX_FIFO_OFLOW
178 #define	VR_ICR0_RX_DROPPED	VR_ISR0_RX_DROPPED
179 #define	VR_ICR0_RX_NOBUF	VR_ISR0_RX_NOBUF
180 #define	VR_ICR0_TX_ABORT	VR_ISR0_TX_ABORT
181 #define	VR_ICR0_LINKSTATUS	VR_ISR0_LINKSTATUS
182 #define	VR_ICR0_GENERAL		VR_ISR0_GENERAL
183 
184 /*
185  * Mulicast address registers (MAR), 8 bytes
186  */
187 #define	VR_MAR0				0x10	/* - 0x13 */
188 #define	VR_MAR1				0x14	/* - 0x17 */
189 
190 /*
191  * VT6105M has a multicast/vlan filter and the hash bits are also used as
192  * CAM data port
193  */
194 #define	VR_MCAM0			0x10	/* VT6105M */
195 #define	VR_MCAM1			0x11
196 #define	VR_MCAM2			0x12
197 #define	VR_MCAM3			0x13
198 #define	VR_MCAM4			0x14
199 #define	VR_MCAM5			0x15
200 #define	VR_VCAM0			0x16
201 #define	VR_VCAM1			0x17
202 
203 /*
204  * Start addresses of receive and transmit ring
205  */
206 #define	VR_RXADDR			0x18	/* - 0x1B */
207 #define	VR_TXADDR			0x1C	/* - 0x1F */
208 
209 /*
210  * VT6105M has 8 TX queues
211  */
212 #define	VR_TX7_ADDR			0x1C
213 #define	VR_TX6_ADDR			0x20
214 #define	VR_TX5_ADDR			0x24
215 #define	VR_TX4_ADDR			0x28
216 #define	VR_TX3_ADDR			0x2C
217 #define	VR_TX2_ADDR			0x30
218 #define	VR_TX1_ADDR			0x34
219 #define	VR_TX0_ADDR			0x38
220 
221 /*
222  * Current and receive- and transmit descriptors.
223  * These are listed in the VT6102 manual but not in the VT6105.
224  */
225 #define	VR_RXCUR_DES0			0x20	/* - 0x23 */
226 #define	VR_RXCUR_DES1			0x24	/* - 0x27 */
227 #define	VR_RXCUR_DES2			0x28	/* - 0x2B */
228 #define	VR_RXCUR_DES3			0x2C	/* - 0x2F */
229 
230 /* VIA secrets here */
231 
232 #define	VR_INTRLINE			0x3c
233 #define	VR_INTRPIN			0x3d
234 
235 /* VIA secrets here */
236 
237 #define	VR_TXCUR_DES0			0x40	/* - 0x43 */
238 #define	VR_TXCUR_DES1			0x44	/* - 0x47 */
239 #define	VR_TXCUR_DES2			0x48	/* - 0x4B */
240 #define	VR_TXCUR_DES3			0x4C	/* - 0x4F */
241 
242 #define	VR_MODE0			0x50
243 #define	VR_MODE0_QPKTDS			0x80
244 
245 #define	VR_MODE1			0x51
246 #define	VR_FIFOTST			0x51
247 
248 /*
249  * These are not in the datasheet but used in the 'fet' driver
250  */
251 #define	VR_MODE2			0x52
252 #define	VR_MODE2_PCEROPT		0x80	/* VT6102 only */
253 #define	VR_MODE2_DISABT			0x40
254 #define	VR_MODE2_MRDPL			0x08	/* VT6107A1 and above */
255 #define	VR_MODE2_MODE10T		0x02
256 
257 #define	VR_MODE3			0x53
258 #define	VR_MODE3_XONOPT			0x80
259 #define	VR_MODE3_TPACEN			0x40
260 #define	VR_MODE3_BACKOPT		0x20
261 #define	VR_MODE3_DLTSEL			0x10
262 #define	VR_MODE3_MIIDMY			0x08
263 #define	VR_MODE3_MIION			0x04
264 
265 #define	VR_PCI_DELAY_TIMER		0x54
266 #define	VR_FIFOCMD			0x56
267 #define	VR_FIFOSTA			0x57
268 
269 /* VIA secrets here */
270 
271 /*
272  * MII Configuration
273  */
274 #define	VR_MIIPHYADDR			0x6C
275 #define	VR_MIIPHYADDR_ADDR0		(1 << 0)
276 #define	VR_MIIPHYADDR_ADDR1		(1 << 1)
277 #define	VR_MIIPHYADDR_ADDR2		(1 << 2)
278 #define	VR_MIIPHYADDR_ADDR3		(1 << 3)
279 #define	VR_MIIPHYADDR_ADDR4		(1 << 4)
280 #define	VR_MIIPHYADDR_ADDRBITS		(VR_MIIPHYADDR_ADDR0 | \
281 					    VR_MIIPHYADDR_ADDR1 | \
282 					    VR_MIIPHYADDR_ADDR2 | \
283 					    VR_MIIPHYADDR_ADDR3 | \
284 					    VR_MIIPHYADDR_ADDR4)
285 #define	VR_MIIPHYADDR_MD_CLOCK_FAST	(1 << 5)
286 #define	VR_MIIPHYADDR_POLLBITS		((1 << 7) | (1 << 6))
287 #define	VR_MIIPHYADDR_POLL1024		((0 << 7) | (0 << 6))
288 #define	VR_MIIPHYADDR_POLL512		((0 << 7) | (1 << 6))
289 #define	VR_MIIPHYADDR_POLL128		((1 << 7) | (0 << 6))
290 #define	VR_MIIPHYADDR_POLL64		((1 << 7) | (1 << 6))
291 
292 /*
293  * MII status
294  */
295 #define	VR_MIISR			0x6D
296 #define	VR_MIISR_SPEED			(1 << 0) /* VT6102 and VT6105 */
297 #define	VR_MIISR_LINKFAIL		(1 << 1) /* VT6102 and VT6105 */
298 #define	VR_MIISR_DUPLEX			(1 << 2) /* VT6105 only */
299 #define	VR_MIISR_PHYERR			(1 << 3) /* VT6102 and VT6105 */
300 #define	VR_MIISR_PHYOPT			(1 << 4) /* VT6102 only */
301 #define	VR_MIISR_NWAYLINKOK		(1 << 4) /* VT6105 only */
302 #define	VR_MIISR_NWAYPAUSE		(1 << 5) /* VT6105M */
303 #define	VR_MIISR_NWAYASMPAUSE		(1 << 6) /* VT6105M */
304 #define	VR_MIISR_PHYRST			(1 << 7)
305 
306 /*
307  * Bus control
308  */
309 #define	VR_BCR0				0x6E		/* receive */
310 #define	VR_BCR0_DMA0			(1 << 0)
311 #define	VR_BCR0_DMA1			(1 << 1)
312 #define	VR_BCR0_DMA2			(1 << 2)
313 #define	VR_BCR0_DMABITS			(VR_BCR0_DMA0|VR_BCR0_DMA1 | \
314 					    VR_BCR0_DMA2)
315 #define	VR_BCR0_DMA32			(0)
316 #define	VR_BCR0_DMA64			(VR_BCR0_DMA0)
317 #define	VR_BCR0_DMA128			(VR_BCR0_DMA1)
318 #define	VR_BCR0_DMA256			(VR_BCR0_DMA0|VR_BCR0_DMA1)
319 #define	VR_BCR0_DMA512			(VR_BCR0_DMA2)
320 #define	VR_BCR0_DMA1024			(VR_BCR0_DMA0|VR_BCR0_DMA2)
321 #define	VR_BCR0_DMASTFW			(VR_BCR0_DMABITS)
322 #define	VR_BCR0_RX_FIFO_THRESHOLD_0	(1 << 3)
323 #define	VR_BCR0_RX_FIFO_THRESHOLD_1	(1 << 4)
324 #define	VR_BCR0_RX_FIFO_THRESHOLD_2	(1 << 5)
325 #define	VR_BCR0_RX_FIFO_THRESHOLD_BITS	(VR_BCR0_RX_FIFO_THRESHOLD_0 | \
326 					    VR_BCR0_RX_FIFO_THRESHOLD_1 | \
327 					    VR_BCR0_RX_FIFO_THRESHOLD_2)
328 #define	VR_BCR0_RX_FIFO_THRESHOLD_64	(0)
329 #define	VR_BCR0_RX_FIFO_THRESHOLD_32	(VR_BCR0_RX_FIFO_THRESHOLD_0)
330 #define	VR_BCR0_RX_FIFO_THRESHOLD_128	(VR_BCR0_RX_FIFO_THRESHOLD_1)
331 #define	VR_BCR0_RX_FIFO_THRESHOLD_256	(VR_BCR0_RX_FIFO_THRESHOLD_0 | \
332 					    VR_BCR0_RX_FIFO_THRESHOLD_1)
333 #define	VR_BCR0_RX_FIFO_THRESHOLD_512	(VR_BCR0_RX_FIFO_THRESHOLD_2)
334 #define	VR_BCR0_RX_FIFO_THRESHOLD_768	(VR_BCR0_RX_FIFO_THRESHOLD_0 | \
335 					    VR_BCR0_RX_FIFO_THRESHOLD_2)
336 #define	VR_BCR0_RX_FIFO_THRESHOLD_1024	(VR_BCR0_RX_FIFO_THRESHOLD_1 | \
337 					    VR_BCR0_RX_FIFO_THRESHOLD_2)
338 #define	VR_BCR0_RX_FIFO_THRESHOLD_STFW	(VR_BCR0_RX_FIFO_THRESHOLD_BITS)
339 #define	VR_BCR0_LEDCR			(1 << 6)
340 #define	VR_BCR0_MSEL			(1 << 7)
341 
342 #define	VR_BCR1				0x6F		/* transmit */
343 #define	VR_BCR1_POLLT_0			(1 << 0)
344 #define	VR_BCR1_POLLT_1			(1 << 1)
345 #define	VR_BCR1_POLLT_2			(1 << 2)
346 #define	VR_BCR1_TX_FIFO_THRESHOLD_0	(1 << 3)
347 #define	VR_BCR1_TX_FIFO_THRESHOLD_1	(1 << 4)
348 #define	VR_BCR1_TX_FIFO_THRESHOLD_2	(1 << 5)
349 #define	VR_BCR1_TX_FIFO_THRESHOLD_BITS	(VR_BCR1_TX_FIFO_THRESHOLD_0 | \
350 					    VR_BCR1_TX_FIFO_THRESHOLD_1 | \
351 					    VR_BCR1_TX_FIFO_THRESHOLD_2)
352 #define	VR_BCR1_TX_FIFO_THRESHOLD_128	(0)
353 #define	VR_BCR1_TX_FIFO_THRESHOLD_256	(VR_BCR1_TX_FIFO_THRESHOLD_0)
354 #define	VR_BCR1_TX_FIFO_THRESHOLD_512	(VR_BCR1_TX_FIFO_THRESHOLD_1)
355 #define	VR_BCR1_TX_FIFO_THRESHOLD_1024	(VR_BCR1_TX_FIFO_THRESHOLD_0 | \
356 					    VR_BCR1_FIFO_THRESHOLD_1)
357 #define	VR_BCR1_TX_FIFO_THRESHOLD_STFW	(VR_BCR1_FIFO_THRESHOLD_BITS)
358 #define	VR_BCR1_TXQPRIO			(1 << 6)	/* VT6105M */
359 #define	VR_BCR1_VLANFILTER		(1 << 7)	/* VT6105M */
360 
361 /*
362  * MII Configuration
363  */
364 #define	VR_MIICMD			0x70
365 #define	VR_MIICMD_MD_CLOCK		(1 << 0)
366 #define	VR_MIICMD_MD_CLOCK_READ		(1 << 1)
367 #define	VR_MIICMD_MD_CLOCK_WRITE	(1 << 2)
368 #define	VR_MIICMD_MD_OUT		(1 << 3)
369 #define	VR_MIICMD_MD_MODE_AUTO		(1 << 4)
370 #define	VR_MIICMD_MD_WRITE		(1 << 5)
371 #define	VR_MIICMD_MD_READ		(1 << 6)
372 #define	VR_MIICMD_MD_AUTO		(1 << 7)
373 
374 #define	VR_MIIADDR			0x71
375 #define	VR_MIIADDR_MAD0			(1 << 0)
376 #define	VR_MIIADDR_MAD1			(1 << 1)
377 #define	VR_MIIADDR_MAD2			(1 << 2)
378 #define	VR_MIIADDR_MAD3			(1 << 3)
379 #define	VR_MIIADDR_MAD4			(1 << 4)
380 #define	VR_MIIADDR_BITS			(VR_MIIADDR_MAD0 | \
381 					    VR_MIIADDR_MAD1 | \
382 					    VR_MIIADDR_MAD2 | \
383 					    VR_MIIADDR_MAD3 | \
384 					    VR_MIIADDR_MAD4)
385 #define	VR_MIIADDR_MDONE		(1 << 5)
386 #define	VR_MIIADDR_MAUTO		(1 << 6)
387 #define	VR_MIIADDR_MIDLE		(1 << 7)
388 
389 #define	VR_MIIDATA			0x72
390 #define	VR_MIIDATA_1			0x72
391 #define	VR_MIIDATA_2			0x73
392 
393 /*
394  * EEPROM Config / Status
395  */
396 #define	VR_PROMCTL			0x74
397 #define	VR_PROMCTL_DATAOUT		(1 << 0)
398 #define	VR_PROMCTL_DATAIN		(1 << 1)
399 #define	VR_PROMCTL_CLOCK		(1 << 2)
400 #define	VR_PROMCTL_CHIPSELECT		(1 << 3)
401 #define	VR_PROMCTL_DIRPROG		(1 << 4)
402 #define	VR_PROMCTL_RELOAD		(1 << 5)
403 #define	VR_PROMCTL_PROGRAM		(1 << 6)
404 #define	VR_PROMCTL_PRGSTATUS		(1 << 7)
405 
406 /*
407  * Chip Configuration A
408  */
409 #define	VR_CFGA				0x78
410 #define	VR_CFGA_PRE_ACPI_WAKEUP		(1 << 0)	/* VT6105M */
411 #define	VR_CFGA_WAKEUP_PANIC		(1 << 1)	/* VT6105M */
412 #define	VR_CFGA_VLANTAG_INCRC		(1 << 5)	/* VT6105M */
413 #define	VR_CFGA_MIIOPT			(1 << 6)
414 #define	VR_CFGA_EELOAD			(1 << 7)
415 
416 /*
417  * Chip Configuration B
418  */
419 #define	VR_CFGB				0x79
420 #define	VR_CFGB_LATENCYTIMER		(1 << 0)
421 #define	VR_CFGB_WWAIT			(1 << 1)
422 #define	VR_CFGB_RWAIT			(1 << 2)
423 #define	VR_CFGB_RXARBIT			(1 << 3)
424 #define	VR_CFGB_TXARBIT			(1 << 4)
425 #define	VR_CFGB_MRLDIS			(1 << 5)
426 #define	VR_CFGB_PERRDIS			(1 << 6)
427 #define	VR_CFGB_QPKTDIS			(1 << 7)
428 
429 /*
430  * Chip Configuration C
431  */
432 #define	VR_CFGC				0x7A
433 #define	VR_CFGC_BPS0			(1 << 0)
434 #define	VR_CFGC_BPS1			(1 << 1)
435 #define	VR_CFGC_BPS2			(1 << 2)
436 #define	VR_CFGC_BTSEL			(1 << 3)
437 #define	VR_CFGC_DLYEN			(1 << 5)
438 #define	VR_CFGC_BROPT			(1 << 6)
439 #define	VR_CFGC_MED3			(1 << 7) /* VT6102 */
440 
441 /*
442  * Chip Configuration D
443  */
444 #define	VR_CFGD				0x7B
445 #define	VR_CFGD_BAKOPT			(1 << 0)
446 #define	VR_CFGD_MBA			(1 << 1)
447 #define	VR_CFGD_CAP			(1 << 2)
448 #define	VR_CFGD_CRADOM			(1 << 3)
449 #define	VR_CFGD_PMCDIG			(1 << 4)
450 #define	VR_CFGD_MRLEN			(1 << 5)
451 #define	VR_CFGD_TAG_ON_SNAP		(1 << 5)	/* VT6105M */
452 #define	VR_CFGD_DIAG			(1 << 6)
453 #define	VR_CFGD_MMIOEN			(1 << 7)
454 
455 /*
456  * Tally counters
457  */
458 #define	VR_TALLY_MPA			0x7c	/* 16 bits */
459 #define	VR_TALLY_CRC			0x7e	/* 16 bits */
460 
461 /*
462  * Misceleneous register 0
463  */
464 #define	VR_MISC0			0x80
465 #define	VR_MISC0_TIMER0_EN		(1 << 0)
466 #define	VR_MISC0_TIMER0_SUSP		(1 << 1)
467 #define	VR_MISC0_HDXFEN			(1 << 2)
468 #define	VR_MISC0_FDXRFEN		(1 << 3)
469 #define	VR_MISC0_FDXTFEN		(1 << 4)
470 #define	VR_MISC0_TIMER0_USEC_EN		(1 << 5)
471 
472 /*
473  * Misceleneous register 1
474  */
475 #define	VR_MISC1			0x81
476 #define	VR_MISC1_TIMER1_EN		(1 << 0)
477 #define	VR_MISC1_VAXJMP			(1 << 5)
478 #define	VR_MISC1_RESET			(1 << 6)
479 
480 /*
481  * Power management
482  */
483 #define	VR_PWR				0x83
484 #define	VR_PWR_DS0			(1 << 0)
485 #define	VR_PWR_DS1			(1 << 1)
486 #define	VR_PWR_WOLEN			(1 << 2)
487 #define	VR_PWR_WOLSR			(1 << 3)
488 #define	VR_PWR_LGWOL			(1 << 7)
489 
490 /*
491  * Second interrupt register status
492  */
493 #define	VR_ISR1				0x84
494 #define	VR_ISR1_TIMER0			(1 << 0)
495 #define	VR_ISR1_TIMER1			(1 << 1)
496 #define	VR_ISR1_PHYEVENT		(1 << 2)
497 #define	VR_ISR1_TDERR			(1 << 3)
498 #define	VR_ISR1_SSRCI			(1 << 4)
499 #define	VR_ISR1_UINTR_SET		(1 << 5)
500 #define	VR_ISR1_UINTR_CLR		(1 << 6)
501 #define	VR_ISR1_PWEI			(1 << 7)
502 
503 /*
504  * Second interrupt register configuration
505  */
506 #define	VR_ICR1				0x86
507 #define	VR_ICR1_TIMER0			VR_ISR1_TIMER0
508 #define	VR_ICR1_TIMER1			VR_ISR1_TIMER1
509 #define	VR_ICR1_PHYEVENT		VR_ISR1_PHYEVENT
510 #define	VR_ICR1_TDERR			VR_ISR1_TDERR
511 #define	VR_ICR1_SSRCI			VR_ISR1_SSRCI
512 #define	VR_ICR1_UINTR_SET		VR_ISR1_UINTR_SET
513 #define	VR_ICR1_UINTR_CLR		VR_ISR1_UINTR_CLR
514 #define	VR_ICR1_PWEI			VR_ISR1_PWEI
515 
516 /*
517  * Content Addressable Memory (CAM) stuff for the VT6105M
518  */
519 #define	VR_CAM_MASK			0x88
520 
521 #define	VR_CAM_CTRL			0x92
522 #define	VR_CAM_CTRL_RD			(1 << 3)
523 #define	VR_CAM_CTRL_WR			(1 << 2)
524 #define	VR_CAM_CTRL_SELECT_VLAN		(1 << 1)
525 #define	VR_CAM_CTRL_ENABLE		(1 << 0)
526 #define	VR_CAM_CTRL_WRITE		(VR_CAM_CTRL_ENABLE | VR_CAM_CTRL_WR)
527 #define	VR_CAM_CTRL_READ		(VR_CAM_CTRL_ENABLE | VR_CAM_CTRL_RD)
528 #define	VR_CAM_CTRL_RW			(VR_CAM_CTRL_ENABLE | \
529 					    VR_CAM_CTRL_RD | VR_CAM_CTRL_WR)
530 #define	VR_CAM_CTRL_DONE		(0)
531 
532 #define	VR_CAM_ADDR			0x93
533 
534 /*
535  * MIB Control register
536  */
537 #define	VR_MIB_CTRL			0x94
538 #define	VR_MIB_CTRL_ENABLE		(1 << 4)
539 #define	VR_MIB_CTRL_HDUPLEX		(1 << 5)
540 #define	VR_MIB_CTRL_INCR		(1 << 6)
541 #define	VR_MIB_CTRL_RTN			(1 << 7)
542 
543 /*
544  * MIB port
545  */
546 #define	VR_MIB_PORT			0x96
547 
548 /*
549  * MIB data
550  */
551 #define	VR_MIB_DATA			0x97
552 
553 
554 /*
555  * Power configuration
556  */
557 #define	VR_PWRCFG			0xA1		/* VT6105LOM */
558 #define	VR_PWRCFG_WOLEN			(1 << 0)
559 #define	VR_PWRCFG_WOLSR			(1 << 1)
560 #define	VR_PWRCFG_PHYPOWERDOWN		(7 << 1)
561 
562 /*
563  * Flow control, VT6105 and above
564  */
565 #define	VR_FCR0				0x98
566 #define	VR_FCR0_RXBUFCOUNT		VR_FCR0
567 
568 #define	VR_FCR1				0x99
569 #define	VR_FCR1_HD_EN			(1 << 0)
570 #define	VR_FCR1_FD_RX_EN		(1 << 1)
571 #define	VR_FCR1_FD_TX_EN		(1 << 2)
572 #define	VR_FCR1_XONXOFF_EN		(1 << 3)
573 
574 #define	VR_FCR1_PAUSEOFFBITS		((1 << 5) | (1 << 4))
575 #define	VR_FCR1_PAUSEOFF_24		((0 << 5) | (0 << 4))
576 #define	VR_FCR1_PAUSEOFF_32		((0 << 5) | (1 << 4))
577 #define	VR_FCR1_PAUSEOFF_48		((1 << 5) | (0 << 4))
578 #define	VR_FCR1_PAUSEOFF_64		((1 << 5) | (1 << 4))
579 
580 #define	VR_FCR1_PAUSEONBITS		((1 << 7) | (1 << 6))
581 #define	VR_FCR1_PAUSEON_04		((0 << 7) | (0 << 6))
582 #define	VR_FCR1_PAUSEON_08		((0 << 7) | (1 << 6))
583 #define	VR_FCR1_PAUSEON_16		((1 << 7) | (0 << 6))
584 #define	VR_FCR1_PAUSEON_24		((1 << 7) | (1 << 6))
585 
586 #define	VR_FCR2				0x9a
587 #define	VR_FCR2_PAUSE			(VR_FCR2)
588 
589 #define	VR_TIMER0			0x9c
590 #define	VR_TIMER0_TIMEOUT		VR_TIMER0	/* 16 bits */
591 
592 #define	VR_TIMER1			0x9e
593 #define	VR_TIMER1_TIMEOUT		VR_TIMER1	/* 16 bits */
594 
595 #define	VR_CRC_PATTERN0			0xb0		/* 32 bits, VT6105M */
596 #define	VR_CRC_PATTERN1			0xb4		/* 32 bits, VT6105M */
597 #define	VR_CRC_PATTERN2			0xb8		/* 32 bits, VT6105M */
598 #define	VR_CRC_PATTERN3			0xbC		/* 32 bits, VT6105M */
599 
600 /*
601  * Receive desctriptor
602  */
603 #define	VR_RDES0_RXERR		(1 << 0)
604 #define	VR_RDES0_CRCERR		(1 << 1)
605 #define	VR_RDES0_FAE		(1 << 2)
606 #define	VR_RDES0_FOV		(1 << 3)
607 #define	VR_RDES0_LONG		(1 << 4)
608 #define	VR_RDES0_RUNT		(1 << 5)
609 #define	VR_RDES0_SERR		(1 << 6)
610 #define	VR_RDES0_BUFF		(1 << 7)
611 
612 #define	VR_RDES0_EDP		(1 << 8)
613 #define	VR_RDES0_STP		(1 << 9)
614 #define	VR_RDES0_CHN		(1 << 10)
615 #define	VR_RDES0_PHY		(1 << 11)
616 #define	VR_RDES0_BAR		(1 << 12)
617 #define	VR_RDES0_MAR		(1 << 13)
618 #define	VR_RDES0_VIDHIT		(1 << 14)	/* VT6105M or reserved */
619 #define	VR_RDES0_RXOK		(1 << 15)
620 
621 #define	VR_RDES0_ABN		((1 << 27) | (1 << 28) | (1 << 29) | (1 << 30))
622 #define	VR_RDES0_OWN		(1U << 31)
623 
624 /*
625  * Transmit descriptor
626  */
627 #define	VR_TDES0_NCR		((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3))
628 #define	VR_TDES0_COL		(1 << 4)
629 #define	VR_TDES0_CDH		(1 << 7)
630 #define	VR_TDES0_ABT		(1 << 8)
631 #define	VR_TDES0_OWC		(1 << 9)
632 #define	VR_TDES0_CRS		(1 << 10)
633 #define	VR_TDES0_UDF		(1 << 11)
634 #define	VR_TDES0_TERR		(1 << 15)
635 /* VLAN stuff is for VT6105M only */
636 #define	VR_TDES0_VLANID		((1 << 27) | (1 << 26) | (1 << 25) | (1 << 24) \
637 				    (1 << 23) | (1 << 22) | (1 << 21) | \
638 				    (1 << 20) | (1 << 19) | (1 << 18) | \
639 				    (1 << 17) | (1 << 16))
640 #define	VR_TDES0_VLANPRI	((1 << 30) | (1 << 29) | (1 << 28))
641 #define	VR_TDES0_OWN		(1U << 31)
642 
643 #define	VR_TDES1_LEN		((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | \
644 				    (1 << 4) | (1 << 5) | (1 << 6) | \
645 				    (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10))
646 
647 #define	VR_TDES1_CHN		(1 << 15)
648 #define	VR_TDES1_CRC		(1 << 16)
649 #define	VR_TDES1_STP		(1 << 21) /* EDP/STP are flipped in DS6105! */
650 #define	VR_TDES1_EDP		(1 << 22)
651 #define	VR_TDES1_INTR		(1 << 23)
652 
653 #define	VR_TDES3_SUPPRESS_INTR	(1 << 0)
654 
655 #endif	/* _VRREG_H */
656