140db2e2bSzf162725 /* 2*1a932f2eSQuaker Fang * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 340db2e2bSzf162725 * Use is subject to license terms. 440db2e2bSzf162725 */ 540db2e2bSzf162725 640db2e2bSzf162725 /* 740db2e2bSzf162725 * Copyright (c) 2005 840db2e2bSzf162725 * Damien Bergamini <damien.bergamini@free.fr> 940db2e2bSzf162725 * 1040db2e2bSzf162725 * Permission to use, copy, modify, and distribute this software for any 1140db2e2bSzf162725 * purpose with or without fee is hereby granted, provided that the above 1240db2e2bSzf162725 * copyright notice and this permission notice appear in all copies. 1340db2e2bSzf162725 * 1440db2e2bSzf162725 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 1540db2e2bSzf162725 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 1640db2e2bSzf162725 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 1740db2e2bSzf162725 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 1840db2e2bSzf162725 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 1940db2e2bSzf162725 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 2040db2e2bSzf162725 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 2140db2e2bSzf162725 */ 2240db2e2bSzf162725 #ifndef _URAL_VAR_H 2340db2e2bSzf162725 #define _URAL_VAR_H 2440db2e2bSzf162725 2540db2e2bSzf162725 #ifdef __cplusplus 2640db2e2bSzf162725 extern "C" { 2740db2e2bSzf162725 #endif 2840db2e2bSzf162725 2940db2e2bSzf162725 #define RAL_FLAG_RUNNING (1<<0) 3040db2e2bSzf162725 3140db2e2bSzf162725 #define RAL_RCR_PROMISC (1<<0) 3240db2e2bSzf162725 #define RAL_RCR_MULTI (2<<0) 3340db2e2bSzf162725 3440db2e2bSzf162725 #ifndef DDI_NT_NET_WIFI 3540db2e2bSzf162725 #define DDI_NT_NET_WIFI "ddi_network:wifi" 3640db2e2bSzf162725 #endif 3740db2e2bSzf162725 3840db2e2bSzf162725 /* 3940db2e2bSzf162725 * Bit flags in the ral_dbg_flags 4040db2e2bSzf162725 */ 4140db2e2bSzf162725 #define RAL_DBG_MSG 0x000001 4240db2e2bSzf162725 #define RAL_DBG_ERR 0x000002 4340db2e2bSzf162725 #define RAL_DBG_USB 0x000004 4440db2e2bSzf162725 #define RAL_DBG_TX 0x000008 4540db2e2bSzf162725 #define RAL_DBG_RX 0x000010 4640db2e2bSzf162725 #define RAL_DBG_IOCTL 0x000020 4740db2e2bSzf162725 #define RAL_DBG_HW 0x000040 4840db2e2bSzf162725 #define RAL_DBG_ALL 0x000fff 4940db2e2bSzf162725 5040db2e2bSzf162725 #define RAL_TX_LIST_COUNT 8 5140db2e2bSzf162725 #define RAL_RX_LIST_COUNT 8 5240db2e2bSzf162725 5340db2e2bSzf162725 struct ural_amrr { 5440db2e2bSzf162725 int txcnt; 5540db2e2bSzf162725 int retrycnt; 5640db2e2bSzf162725 int success; 5740db2e2bSzf162725 int success_threshold; 5840db2e2bSzf162725 int recovery; 5940db2e2bSzf162725 }; 6040db2e2bSzf162725 6140db2e2bSzf162725 struct ural_softc { 6240db2e2bSzf162725 struct ieee80211com sc_ic; 6340db2e2bSzf162725 dev_info_t *sc_dev; 6440db2e2bSzf162725 6540db2e2bSzf162725 usb_client_dev_data_t *sc_udev; /* usb dev */ 6640db2e2bSzf162725 6740db2e2bSzf162725 uint32_t asic_rev; 6840db2e2bSzf162725 uint8_t rf_rev; 6940db2e2bSzf162725 7040db2e2bSzf162725 kmutex_t sc_genlock; 7140db2e2bSzf162725 7240db2e2bSzf162725 usb_pipe_handle_t sc_rx_pipeh; 7340db2e2bSzf162725 usb_pipe_handle_t sc_tx_pipeh; 7440db2e2bSzf162725 7540db2e2bSzf162725 enum ieee80211_state sc_state; 7640db2e2bSzf162725 struct ural_amrr amrr; 7740db2e2bSzf162725 7840db2e2bSzf162725 kmutex_t tx_lock; 7940db2e2bSzf162725 kmutex_t rx_lock; 8040db2e2bSzf162725 8140db2e2bSzf162725 int tx_queued; 8240db2e2bSzf162725 int rx_queued; 8340db2e2bSzf162725 8440db2e2bSzf162725 int sc_tx_timer; 8540db2e2bSzf162725 8640db2e2bSzf162725 timeout_id_t sc_scan_id; 8740db2e2bSzf162725 timeout_id_t sc_amrr_id; 8840db2e2bSzf162725 8940db2e2bSzf162725 uint32_t sc_need_sched; 9040db2e2bSzf162725 uint32_t sc_flags; 9140db2e2bSzf162725 uint32_t sc_rcr; /* RAL RCR */ 9240db2e2bSzf162725 9340db2e2bSzf162725 int dwelltime; 9440db2e2bSzf162725 9540db2e2bSzf162725 uint16_t sta[11]; 9640db2e2bSzf162725 uint32_t rf_regs[4]; 9740db2e2bSzf162725 uint8_t txpow[14]; 9840db2e2bSzf162725 9940db2e2bSzf162725 #pragma pack(1) 10040db2e2bSzf162725 struct { 10140db2e2bSzf162725 uint8_t val; 10240db2e2bSzf162725 uint8_t reg; 10340db2e2bSzf162725 } bbp_prom[16]; 10440db2e2bSzf162725 #pragma pack() 10540db2e2bSzf162725 10640db2e2bSzf162725 int led_mode; 10740db2e2bSzf162725 int hw_radio; 10840db2e2bSzf162725 int rx_ant; 10940db2e2bSzf162725 int tx_ant; 11040db2e2bSzf162725 int nb_ant; 11140db2e2bSzf162725 11240db2e2bSzf162725 /* kstats */ 11340db2e2bSzf162725 uint32_t sc_tx_nobuf; 11440db2e2bSzf162725 uint32_t sc_rx_nobuf; 11540db2e2bSzf162725 uint32_t sc_tx_err; 11640db2e2bSzf162725 uint32_t sc_rx_err; 11740db2e2bSzf162725 uint32_t sc_tx_retries; 11840db2e2bSzf162725 11940db2e2bSzf162725 int (*sc_newstate)(struct ieee80211com *, 12040db2e2bSzf162725 enum ieee80211_state, int); 12140db2e2bSzf162725 12240db2e2bSzf162725 }; 12340db2e2bSzf162725 12440db2e2bSzf162725 #define RAL_IS_RUNNING(_sc) ((_sc)->sc_flags & RAL_FLAG_RUNNING) 12540db2e2bSzf162725 #define RAL_LOCK(sc) mutex_enter(&(sc)->sc_genlock) 12640db2e2bSzf162725 #define RAL_UNLOCK(sc) mutex_exit(&(sc)->sc_genlock) 12740db2e2bSzf162725 12840db2e2bSzf162725 #define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5] 12940db2e2bSzf162725 #define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x" 13040db2e2bSzf162725 13140db2e2bSzf162725 #ifdef __cplusplus 13240db2e2bSzf162725 } 13340db2e2bSzf162725 #endif 13440db2e2bSzf162725 13540db2e2bSzf162725 #endif /* _URAL_VAR_H */ 136