1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 #ifndef _TPM_TIS_H 27 #define _TPM_TIS_H 28 29 /* 30 * TPM Interface Specification Defaults 31 * ICH7 spec (pg 253) says this is the base 32 * TPM on LPC: FED40000-FED40FFF But this is only locality 0 33 * It has to include 4 localities so the real range is FED40000-FED44FFF 34 * (TIS 1.2 pg 27) 35 */ 36 #define TIS_MEM_BASE 0xFED40000 37 #define TIS_MEM_LEN 0x5000 38 39 /* Different locality(x)'s Offsets for TPM Registers (TIS 1.2 pg33-36) */ 40 /* Used to gain ownership */ 41 #define TPM_ACCESS_(x) (0x0000 | ((x)<<12)) 42 /* Enable Interrupts */ 43 #define TPM_INT_ENABLE_(x) (0x0008 | ((x)<<12)) 44 /* Interrupt vector (SIRQ values) */ 45 #define TPM_INT_VECTOR_(x) (0x000C | ((x)<<12)) 46 /* What caused interrupt */ 47 #define TPM_INT_STATUS_(x) (0x0010 | ((x)<<12)) 48 /* Supported Interrupts */ 49 #define TPM_INTF_CAP_(x) (0x0014 | ((x)<<12)) 50 /* Status Register */ 51 #define TPM_STS_(x) (0x0018 | ((x)<<12)) 52 /* I/O FIFO */ 53 #define TPM_DATA_FIFO_(x) (0x0024 | ((x)<<12)) 54 /* Vendor and Device ID */ 55 #define TPM_DID_VID_(x) (0x0F00 | ((x)<<12)) 56 /* Revision ID */ 57 #define TPM_RID_(x) (0x0F04 | ((x)<<12)) 58 59 /* The number of all ordinals */ 60 #define TSC_ORDINAL_MAX 12 61 #define TPM_ORDINAL_MAX 243 62 #define TSC_ORDINAL_MASK 0x40000000 63 64 /* Timeouts (in milliseconds) (TIS v1.2 pg 43) */ 65 #define TPM_REQUEST_TIMEOUT 9000000 /* 9 seconds...too long? */ 66 #define TPM_POLLING_TIMEOUT 10000 /* 10 ms for polling */ 67 68 enum tis_timeouts { 69 TIS_TIMEOUT_A = 750000, 70 TIS_TIMEOUT_B = 2000000, 71 TIS_TIMEOUT_C = 750000, 72 TIS_TIMEOUT_D = 750000 73 }; 74 75 #define TPM_DEFAULT_DURATION 750000 76 77 /* Possible TPM_ACCESS register bit values (TIS 1.2 pg.47-49) */ 78 enum tis_access { 79 TPM_ACCESS_VALID = 0x80, 80 TPM_ACCESS_ACTIVE_LOCALITY = 0x20, 81 TPM_ACCESS_REQUEST_PENDING = 0x04, 82 TPM_ACCESS_REQUEST_USE = 0x02 83 }; 84 85 /* Possible TPM_STS register values (TIS 1.2 pg.52-54) */ 86 enum tis_status { 87 /* bit 0 and bit 2 are reserved */ 88 TPM_STS_RESPONSE_RETRY = 0x02, /* bit 1 */ 89 TPM_STS_DATA_EXPECT = 0x08, /* bit 3 */ 90 TPM_STS_DATA_AVAIL = 0x10, /* bit 4 */ 91 TPM_STS_GO = 0x20, /* bit 5 */ 92 TPM_STS_CMD_READY = 0x40, /* bit 6 */ 93 TPM_STS_VALID = 0x80 /* bit 7 */ 94 }; 95 96 /* Possible TPM_INTF_CAPABILITY register values (TIS 1.2 pg.55) */ 97 enum tis_intf_cap { 98 TPM_INTF_BURST_COUNT_STATIC = 0x100, 99 TPM_INTF_CMD_READY_INT = 0x080, 100 TPM_INTF_INT_EDGE_FALLING = 0x040, 101 TPM_INTF_INT_EDGE_RISING = 0x020, 102 TPM_INTF_INT_LEVEL_LOW = 0x010, 103 TPM_INTF_INT_LEVEL_HIGH = 0x008, 104 TPM_INTF_INT_LOCALITY_CHANGE_INT = 0x004, 105 TPM_INTF_INT_STS_VALID_INT = 0x002, 106 TPM_INTF_INT_DATA_AVAIL_INT = 0x001 107 }; 108 109 /* Possible TPM_INT_ENABLE register values (TIS 1.2 pg.62-63) */ 110 /* Interrupt enable bit for TPM_INT_ENABLE_x register */ 111 /* Too big to fit in enum... */ 112 #define TPM_INT_GLOBAL_EN 0x80000000 113 enum tis_int_enable { 114 TPM_INT_CMD_RDY_EN = 0x80, 115 TPM_INT_LOCAL_CHANGE_INT_EN = 0x04, 116 TPM_INT_STS_VALID_EN = 0x02, 117 TPM_INT_STS_DATA_AVAIL_EN = 0x01 118 }; 119 120 #endif /* _TPM_TIS_H */ 121