xref: /titanic_50/usr/src/uts/common/io/rtw/si4136reg.h (revision 9aa73b6813b3fd35e78fcc44fd17535e765e504c)
1a72f7ea6Sql147931 /*
2*9aa73b68SQin Michael Li  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
3a72f7ea6Sql147931  * Use is subject to license terms.
4a72f7ea6Sql147931  */
5a72f7ea6Sql147931 
6a72f7ea6Sql147931 /*
7a72f7ea6Sql147931  * Copyright (c) 2005 David Young.  All rights reserved.
8a72f7ea6Sql147931  *
9a72f7ea6Sql147931  * This code was written by David Young.
10a72f7ea6Sql147931  *
11a72f7ea6Sql147931  * Redistribution and use in source and binary forms, with or without
12a72f7ea6Sql147931  * modification, are permitted provided that the following conditions
13a72f7ea6Sql147931  * are met:
14a72f7ea6Sql147931  * 1. Redistributions of source code must retain the above copyright
15a72f7ea6Sql147931  *    notice, this list of conditions and the following disclaimer.
16a72f7ea6Sql147931  * 2. Redistributions in binary form must reproduce the above copyright
17a72f7ea6Sql147931  *    notice, this list of conditions and the following disclaimer in the
18a72f7ea6Sql147931  *    documentation and/or other materials provided with the distribution.
19a72f7ea6Sql147931  * 3. Neither the name of the author nor the names of any co-contributors
20a72f7ea6Sql147931  *    may be used to endorse or promote products derived from this software
21a72f7ea6Sql147931  *    without specific prior written permission.
22a72f7ea6Sql147931  *
23a72f7ea6Sql147931  * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
24a72f7ea6Sql147931  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
25a72f7ea6Sql147931  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
26a72f7ea6Sql147931  * PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL David
27a72f7ea6Sql147931  * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
28a72f7ea6Sql147931  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
29a72f7ea6Sql147931  * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30a72f7ea6Sql147931  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
31a72f7ea6Sql147931  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32a72f7ea6Sql147931  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33a72f7ea6Sql147931  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
34a72f7ea6Sql147931  * OF SUCH DAMAGE.
35a72f7ea6Sql147931  */
36a72f7ea6Sql147931 #ifndef _SI4136REG_H_
37a72f7ea6Sql147931 #define	_SI4136REG_H_
38a72f7ea6Sql147931 
39*9aa73b68SQin Michael Li #ifdef __cplusplus
40*9aa73b68SQin Michael Li extern "C" {
41*9aa73b68SQin Michael Li #endif
42*9aa73b68SQin Michael Li 
43a72f7ea6Sql147931 /*
44a72f7ea6Sql147931  * Serial bus format for Silicon Laboratories Si4126/Si4136 RF synthesizer.
45a72f7ea6Sql147931  */
46a72f7ea6Sql147931 #define	SI4126_TWI_DATA_MASK	BITS(21, 4)
47a72f7ea6Sql147931 #define	SI4126_TWI_ADDR_MASK	BITS(3, 0)
48a72f7ea6Sql147931 
49a72f7ea6Sql147931 /*
50a72f7ea6Sql147931  * Registers for Silicon Laboratories Si4126/Si4136 RF synthesizer.
51a72f7ea6Sql147931  */
52a72f7ea6Sql147931 #define	SI4126_MAIN	0	/* main configuration */
53a72f7ea6Sql147931 #define	SI4126_MAIN_AUXSEL_MASK	BITS(13, 12)	/* aux. output pin function */
54a72f7ea6Sql147931 /*
55a72f7ea6Sql147931  * reserved
56a72f7ea6Sql147931  */
57a72f7ea6Sql147931 #define	SI4126_MAIN_AUXSEL_RSVD		LSHIFT(0x0, SI4126_MAIN_AUXSEL_MASK)
58a72f7ea6Sql147931 /*
59a72f7ea6Sql147931  * force low
60a72f7ea6Sql147931  */
61a72f7ea6Sql147931 #define	SI4126_MAIN_AUXSEL_FRCLOW	LSHIFT(0x1, SI4126_MAIN_AUXSEL_MASK)
62a72f7ea6Sql147931 /*
63a72f7ea6Sql147931  * Lock Detect (LDETB)
64a72f7ea6Sql147931  */
65a72f7ea6Sql147931 #define	SI4126_MAIN_AUXSEL_LDETB	LSHIFT(0x3, SI4126_MAIN_AUXSEL_MASK)
66a72f7ea6Sql147931 
67a72f7ea6Sql147931 /*
68a72f7ea6Sql147931  * IFOUT = IFVCO  frequency / 2**IFDIV.
69a72f7ea6Sql147931  */
70a72f7ea6Sql147931 #define	SI4126_MAIN_IFDIV_MASK	BITS(11, 10)
71a72f7ea6Sql147931 
72a72f7ea6Sql147931 #define	SI4126_MAIN_XINDIV2	BIT(6)	/* 1: divide crystal input (XIN) by 2 */
73a72f7ea6Sql147931 #define	SI4126_MAIN_LPWR	BIT(5)	/* 1: low-power mode */
74a72f7ea6Sql147931 
75a72f7ea6Sql147931 /*
76a72f7ea6Sql147931  * 1: equivalent to  reg[SI4126_POWER] <- SI4126_POWER_PDIB | SI4126_POWER_PDRB.
77a72f7ea6Sql147931  * 0: power-down under control of reg[SI4126_POWER].
78a72f7ea6Sql147931  */
79a72f7ea6Sql147931 #define	SI4126_MAIN_AUTOPDB	BIT(3)
80a72f7ea6Sql147931 #define	SI4126_GAIN	1		/* phase detector gain */
81a72f7ea6Sql147931 #define	SI4126_GAIN_KPI_MASK	BITS(5, 4)	/* IF phase detector gain */
82a72f7ea6Sql147931 #define	SI4126_GAIN_KP2_MASK	BITS(3, 2)	/* RF2 phase detector gain */
83a72f7ea6Sql147931 #define	SI4126_GAIN_KP1_MASK	BITS(1, 0)	/* RF1 phase detector gain */
84a72f7ea6Sql147931 
85a72f7ea6Sql147931 #define	SI4126_POWER	2		/* powerdown */
86a72f7ea6Sql147931 #define	SI4126_POWER_PDIB	BIT(1)	/* 1: IF synthesizer on */
87a72f7ea6Sql147931 #define	SI4126_POWER_PDRB	BIT(0)	/* 1: RF synthesizer on */
88a72f7ea6Sql147931 
89a72f7ea6Sql147931 #define	SI4126_RF1N	3		/* RF1 N divider */
90a72f7ea6Sql147931 #define	SI4126_RF2N	4		/* RF2 N divider */
91a72f7ea6Sql147931 #define	SI4126_IFN	5		/* IF N divider */
92a72f7ea6Sql147931 #define	SI4126_RF1R	6		/* RF1 R divider */
93a72f7ea6Sql147931 #define	SI4126_RF2R	7		/* RF2 R divider */
94a72f7ea6Sql147931 #define	SI4126_IFR	8		/* IF R divider */
95*9aa73b68SQin Michael Li #ifdef __cplusplus
96*9aa73b68SQin Michael Li }
97*9aa73b68SQin Michael Li #endif
98a72f7ea6Sql147931 
99a72f7ea6Sql147931 #endif /* _SI4136REG_H_ */
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