1 /* 2 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 /* 6 * Copyright (c) 2004, 2005 David Young. All rights reserved. 7 * 8 * Programmed for NetBSD by David Young. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The name of David Young may not be used to endorse or promote 19 * products derived from this software without specific prior 20 * written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 23 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 24 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 25 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 26 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 27 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 28 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 33 * OF SUCH DAMAGE. 34 */ 35 /* Macros for bit twiddling. */ 36 /* TBD factor w/ dev/ic/atwreg.h. */ 37 38 #pragma ident "%Z%%M% %I% %E% SMI" 39 40 #ifndef _RTW_REG_H_ 41 #define _RTW_REG_H_ 42 43 #ifndef _BIT_TWIDDLE 44 #define _BIT_TWIDDLE 45 /* 46 * nth bit, BIT(0) == 0x1. 47 */ 48 #define BIT(n) (((n) == 32) ? 0 : ((uint32_t)1 << (n))) 49 50 /* 51 * bits m through n, m < n. 52 */ 53 #define BITS(m, n) ((BIT(MAX((m), (n)) + 1) - 1) ^ (BIT(MIN((m), (n))) - 1)) 54 55 /* 56 * find least significant bit that is set 57 */ 58 #define LOWEST_SET_BIT(x) ((((x) - 1) & (x)) ^ (x)) 59 60 /* 61 * for x a power of two and p a non-negative integer, is x a greater 62 * power than 2**p? 63 */ 64 #define GTEQ_POWER(x, p) (((ulong_t)(x) >> (p)) != 0) 65 66 #define MASK_TO_SHIFT2(m) (GTEQ_POWER(LOWEST_SET_BIT((m)), 1) ? 1 : 0) 67 68 #define MASK_TO_SHIFT4(m) \ 69 (GTEQ_POWER(LOWEST_SET_BIT((m)), 2) \ 70 ? 2 + MASK_TO_SHIFT2((m) >> 2) \ 71 : MASK_TO_SHIFT2((m))) 72 73 #define MASK_TO_SHIFT8(m) \ 74 (GTEQ_POWER(LOWEST_SET_BIT((m)), 4) \ 75 ? 4 + MASK_TO_SHIFT4((m) >> 4) \ 76 : MASK_TO_SHIFT4((m))) 77 78 #define MASK_TO_SHIFT16(m) \ 79 (GTEQ_POWER(LOWEST_SET_BIT((m)), 8) \ 80 ? 8 + MASK_TO_SHIFT8((m) >> 8) \ 81 : MASK_TO_SHIFT8((m))) 82 83 #define MASK_TO_SHIFT(m) \ 84 (GTEQ_POWER(LOWEST_SET_BIT((m)), 16) \ 85 ? 16 + MASK_TO_SHIFT16((m) >> 16) \ 86 : MASK_TO_SHIFT16((m))) 87 88 #define MASK_AND_RSHIFT(x, mask) (((x) & (mask)) >> MASK_TO_SHIFT(mask)) 89 #define LSHIFT(x, mask) ((x) << MASK_TO_SHIFT(mask)) 90 #define MASK_AND_REPLACE(reg, val, mask) ((reg & ~mask) | LSHIFT(val, mask)) 91 #define PRESHIFT(m) MASK_AND_RSHIFT((m), (m)) 92 93 #endif /* _BIT_TWIDDLE */ 94 95 /* RTL8180L Host Control and Status Registers */ 96 97 /* 98 * ID Register: MAC addr, 6 bytes. 99 * Auto-loaded from EEPROM. Read by byte, by word, or by double word, 100 * but write only by double word. 101 */ 102 #define RTW_IDR0 0x00 103 #define RTW_IDR1 0x04 104 105 #define RTW_MAR0 0x08 /* Multicast filter, 64b. */ 106 #define RTW_MAR1 0x0c 107 108 /* 109 * Timing Synchronization Function Timer Register, 110 * low word, 32b, read-only. 111 */ 112 #define RTW_TSFTRL 0x18 113 #define RTW_TSFTRH 0x1c /* High word, 32b, read-only. */ 114 /* 115 * Transmit Low Priority Descriptors Start Address, 116 * 32b, 256-byte alignment. 117 */ 118 #define RTW_TLPDA 0x20 119 /* 120 * Transmit Normal Priority Descriptors Start Address, 121 * 32b, 256-byte alignment. 122 */ 123 #define RTW_TNPDA 0x24 124 /* 125 * Transmit High Priority Descriptors Start Address, 126 * 32b, 256-byte alignment. 127 */ 128 #define RTW_THPDA 0x28 129 130 #define RTW_BRSR 0x2c /* Basic Rate Set Register, 16b */ 131 /* 132 * 1: use short PLCP header for CTS/ACK packet, 133 * 0: use long PLCP header 134 */ 135 #define RTW_BRSR_BPLCP BIT(8) 136 #define RTW_BRSR_MBR8180_MASK BITS(1, 0) /* Maximum Basic Service Rate */ 137 #define RTW_BRSR_MBR8180_1MBPS LSHIFT(0, RTW_BRSR_MBR8180_MASK) 138 #define RTW_BRSR_MBR8180_2MBPS LSHIFT(1, RTW_BRSR_MBR8180_MASK) 139 #define RTW_BRSR_MBR8180_5MBPS LSHIFT(2, RTW_BRSR_MBR8180_MASK) 140 #define RTW_BRSR_MBR8180_11MBPS LSHIFT(3, RTW_BRSR_MBR8180_MASK) 141 142 /* 143 * 8181 and 8180 docs conflict! 144 */ 145 #define RTW_BRSR_MBR8181_1MBPS BIT(0) 146 #define RTW_BRSR_MBR8181_2MBPS BIT(1) 147 #define RTW_BRSR_MBR8181_5MBPS BIT(2) 148 #define RTW_BRSR_MBR8181_11MBPS BIT(3) 149 150 #define RTW_BSSID 0x2e 151 /* 152 * BSSID, 6 bytes 153 */ 154 #define RTW_BSSID16 0x2e /* first two bytes */ 155 #define RTW_BSSID32 (0x2e + 4) /* remaining four bytes */ 156 #define RTW_BSSID0 RTW_BSSID16 /* BSSID[0], 8b */ 157 #define RTW_BSSID1 (RTW_BSSID0 + 1) /* BSSID[1], 8b */ 158 #define RTW_BSSID2 (RTW_BSSID1 + 1) /* BSSID[2], 8b */ 159 #define RTW_BSSID3 (RTW_BSSID2 + 1) /* BSSID[3], 8b */ 160 #define RTW_BSSID4 (RTW_BSSID3 + 1) /* BSSID[4], 8b */ 161 #define RTW_BSSID5 (RTW_BSSID4 + 1) /* BSSID[5], 8b */ 162 163 #define RTW_CR 0x37 /* Command Register, 8b */ 164 /* 165 * Reset: host sets to 1 to disable 166 * transmitter & receiver, reinitialize FIFO. 167 * RTL8180L sets to 0 to signal completion. 168 */ 169 #define RTW_CR_RST BIT(4) 170 /* 171 * Receiver Enable: host enables receiver 172 * by writing 1. RTL8180L indicates receiver 173 * is active with 1. After power-up, host 174 * must wait for reset before writing. 175 */ 176 #define RTW_CR_RE BIT(3) 177 /* 178 * Transmitter Enable: host enables transmitter 179 * by writing 1. RTL8180L indicates transmitter 180 * is active with 1. After power-up, host 181 * must wait for reset before writing. 182 */ 183 #define RTW_CR_TE BIT(2) 184 /* 185 * PCI Multiple Read/Write enable: 186 * 1 enables, 187 * 0 disables. XXX RTL8180, only? 188 */ 189 #define RTW_CR_MULRW BIT(0) 190 191 #define RTW_IMR 0x3c /* Interrupt Mask Register, 16b */ 192 #define RTW_ISR 0x3e /* Interrupt status register, 16b */ 193 194 #define RTW_INTR_TXFOVW BIT(15) /* Tx FIFO Overflow */ 195 /* 196 * Time Out: 1 indicates RTW_TSFTR[0:31] = RTW_TINT 197 */ 198 #define RTW_INTR_TIMEOUT BIT(14) 199 /* 200 * Beacon Time Out: time for host to prepare beacon: 201 * RTW_TSFTR % (RTW_BCNITV_BCNITV * TU) = 202 * (RTW_BCNITV_BCNITV * TU - RTW_BINTRITV) 203 */ 204 #define RTW_INTR_BCNINT BIT(13) 205 /* 206 * ATIM Time Out: ATIM interval will pass, 207 * RTW_TSFTR % (RTW_BCNITV_BCNITV * TU) = 208 * (RTW_ATIMWND_ATIMWND * TU - RTW_ATIMTRITV) 209 */ 210 #define RTW_INTR_ATIMINT BIT(12) 211 /* 212 * Tx Beacon Descriptor Error: 213 * beacon transmission aborted because 214 * frame Rx'd 215 */ 216 #define RTW_INTR_TBDER BIT(11) 217 #define RTW_INTR_TBDOK BIT(10) /* Tx Beacon Descriptor OK */ 218 /* 219 * Tx High Priority Descriptor Error: 220 * reached short/long retry limit 221 */ 222 #define RTW_INTR_THPDER BIT(9) 223 #define RTW_INTR_THPDOK BIT(8) /* Tx High Priority Descriptor OK */ 224 /* 225 * Tx Normal Priority Descriptor Error: 226 * reached short/long retry limit 227 */ 228 #define RTW_INTR_TNPDER BIT(7) 229 #define RTW_INTR_TNPDOK BIT(6) /* Tx Normal Priority Descriptor OK */ 230 /* 231 * Rx FIFO Overflow: either RDU (see below) 232 * or PCI bus too slow/busy 233 */ 234 #define RTW_INTR_RXFOVW BIT(5) 235 #define RTW_INTR_RDU BIT(4) /* Rx Descriptor Unavailable */ 236 /* 237 * Tx Low Priority Descriptor Error 238 * reached short/long retry limit 239 */ 240 #define RTW_INTR_TLPDER BIT(3) 241 #define RTW_INTR_TLPDOK BIT(2) /* Tx Low Priority Descriptor OK */ 242 #define RTW_INTR_RER BIT(1) /* Rx Error: CRC32 or ICV error */ 243 #define RTW_INTR_ROK BIT(0) /* Rx OK */ 244 245 /* 246 * Convenient interrupt conjunctions. 247 */ 248 #define RTW_INTR_RX (RTW_INTR_RER|RTW_INTR_ROK | \ 249 RTW_INTR_RDU |RTW_INTR_RXFOVW) 250 #define RTW_INTR_TX (RTW_INTR_TLPDER|RTW_INTR_TLPDOK|RTW_INTR_THPDER|\ 251 RTW_INTR_THPDOK|RTW_INTR_TNPDER|RTW_INTR_TNPDOK|\ 252 RTW_INTR_TBDER|RTW_INTR_TBDOK) 253 #define RTW_INTR_BEACON (RTW_INTR_BCNINT) 254 #define RTW_INTR_IOERROR (RTW_INTR_TXFOVW|RTW_INTR_RXFOVW|RTW_INTR_RDU) 255 256 #define RTW_TCR 0x40 /* Transmit Configuration Register, 32b */ 257 #define RTW_TCR_CWMIN BIT(31) /* 1: CWmin = 8, 0: CWmin = 32. */ 258 /* 259 * 1: host assigns 802.11 sequence number, 260 * 0: hardware assigns sequence number 261 */ 262 #define RTW_TCR_SWSEQ BIT(30) 263 /* Hardware version ID, read-only */ 264 #define RTW_TCR_HWVERID_MASK BITS(29, 25) 265 #define RTW_TCR_HWVERID_D LSHIFT(26, RTW_TCR_HWVERID_MASK) 266 #define RTW_TCR_HWVERID_F LSHIFT(27, RTW_TCR_HWVERID_MASK) 267 #define RTW_TCR_HWVERID_RTL8180 RTW_TCR_HWVERID_F 268 269 /* 270 * Set ACK/CTS Timeout (EIFS). 271 * 1: ACK rate = max(RTW_BRSR_MBR, Rx rate) (XXX not min? typo in datasheet?) 272 * 0: ACK rate = 1Mbps 273 */ 274 #define RTW_TCR_SAT BIT(24) 275 /* Max DMA Burst Size per Tx DMA Burst */ 276 #define RTW_TCR_MXDMA_MASK BITS(23, 21) 277 #define RTW_TCR_MXDMA_16 LSHIFT(0, RTW_TCR_MXDMA_MASK) 278 #define RTW_TCR_MXDMA_32 LSHIFT(1, RTW_TCR_MXDMA_MASK) 279 #define RTW_TCR_MXDMA_64 LSHIFT(2, RTW_TCR_MXDMA_MASK) 280 #define RTW_TCR_MXDMA_128 LSHIFT(3, RTW_TCR_MXDMA_MASK) 281 #define RTW_TCR_MXDMA_256 LSHIFT(4, RTW_TCR_MXDMA_MASK) 282 #define RTW_TCR_MXDMA_512 LSHIFT(5, RTW_TCR_MXDMA_MASK) 283 #define RTW_TCR_MXDMA_1024 LSHIFT(6, RTW_TCR_MXDMA_MASK) 284 #define RTW_TCR_MXDMA_2048 LSHIFT(7, RTW_TCR_MXDMA_MASK) 285 286 #define RTW_TCR_DISCW BIT(20) /* disable 802.11 random backoff */ 287 288 /* 289 * host lets RTL8180 append ICV to WEP packets 290 */ 291 #define RTW_TCR_ICV BIT(19) 292 293 /* 294 * Loopback Test: disables TXI/TXQ outputs. 295 */ 296 #define RTW_TCR_LBK_MASK BITS(18, 17) 297 #define RTW_TCR_LBK_NORMAL LSHIFT(0, RTW_TCR_LBK_MASK) /* normal ops */ 298 #define RTW_TCR_LBK_MAC LSHIFT(1, RTW_TCR_LBK_MASK) /* MAC loopback */ 299 #define RTW_TCR_LBK_BBP LSHIFT(2, RTW_TCR_LBK_MASK) /* baseband loop. */ 300 #define RTW_TCR_LBK_CONT LSHIFT(3, RTW_TCR_LBK_MASK) /* continuous Tx */ 301 302 /* 303 * 0: RTL8180 appends CRC32 304 * 1: host appends CRC32 305 * 306 * (I *think* this is right. The docs have a mysterious 307 * description in the passive voice.) 308 */ 309 #define RTW_TCR_CRC BIT(16) 310 #define RTW_TCR_SRL_MASK BITS(15, 8) /* Short Retry Limit */ 311 #define RTW_TCR_LRL_MASK BITS(7, 0) /* Long Retry Limit */ 312 313 #define RTW_RCR 0x44 /* Receive Configuration Register, 32b */ 314 /* 315 * only do Early Rx on packets longer than 1536 bytes 316 */ 317 #define RTW_RCR_ONLYERLPKT BIT(31) 318 #define RTW_RCR_ENCS2 BIT(30) /* enable carrier sense method 2 */ 319 #define RTW_RCR_ENCS1 BIT(29) /* enable carrier sense method 1 */ 320 #define RTW_RCR_ENMARP BIT(28) /* enable MAC auto-reset PHY */ 321 /* 322 * Check BSSID/ToDS/FromDS: set "Link On" when received BSSID 323 * matches RTW_BSSID and received ToDS/FromDS are appropriate 324 * according to RTW_MSR_NETYPE. 325 */ 326 #define RTW_RCR_CBSSID BIT(23) 327 #define RTW_RCR_APWRMGT BIT(22) /* accept packets w/ PWRMGMT bit set */ 328 /* 329 * when RTW_MSR_NETYPE == RTW_MSR_NETYPE_INFRA_OK, accept 330 * broadcast/multicast packets whose 3rd address matches RTL8180's MAC. 331 */ 332 #define RTW_RCR_ADD3 BIT(21) 333 #define RTW_RCR_AMF BIT(20) /* accept management frames */ 334 #define RTW_RCR_ACF BIT(19) /* accept control frames */ 335 #define RTW_RCR_ADF BIT(18) /* accept data frames */ 336 /* 337 * Rx FIFO Threshold: RTL8180 begins PCI transfer when this many data 338 * bytes are received 339 */ 340 #define RTW_RCR_RXFTH_MASK BITS(15, 13) 341 #define RTW_RCR_RXFTH_64 LSHIFT(2, RTW_RCR_RXFTH_MASK) 342 #define RTW_RCR_RXFTH_128 LSHIFT(3, RTW_RCR_RXFTH_MASK) 343 #define RTW_RCR_RXFTH_256 LSHIFT(4, RTW_RCR_RXFTH_MASK) 344 #define RTW_RCR_RXFTH_512 LSHIFT(5, RTW_RCR_RXFTH_MASK) 345 #define RTW_RCR_RXFTH_1024 LSHIFT(6, RTW_RCR_RXFTH_MASK) 346 #define RTW_RCR_RXFTH_WHOLE LSHIFT(7, RTW_RCR_RXFTH_MASK) 347 348 #define RTW_RCR_AICV BIT(12) /* accept frames w/ ICV errors */ 349 350 /* 351 * Max DMA Burst Size per Rx DMA Burst 352 */ 353 #define RTW_RCR_MXDMA_MASK BITS(10, 8) 354 #define RTW_RCR_MXDMA_16 LSHIFT(0, RTW_RCR_MXDMA_MASK) 355 #define RTW_RCR_MXDMA_32 LSHIFT(1, RTW_RCR_MXDMA_MASK) 356 #define RTW_RCR_MXDMA_64 LSHIFT(2, RTW_RCR_MXDMA_MASK) 357 #define RTW_RCR_MXDMA_128 LSHIFT(3, RTW_RCR_MXDMA_MASK) 358 #define RTW_RCR_MXDMA_256 LSHIFT(4, RTW_RCR_MXDMA_MASK) 359 #define RTW_RCR_MXDMA_512 LSHIFT(5, RTW_RCR_MXDMA_MASK) 360 #define RTW_RCR_MXDMA_1024 LSHIFT(6, RTW_RCR_MXDMA_MASK) 361 #define RTW_RCR_MXDMA_UNLIMITED LSHIFT(7, RTW_RCR_MXDMA_MASK) 362 363 /* 364 * EEPROM type, read-only. 1: EEPROM is 93c56, 0: 93c46 365 */ 366 #define RTW_RCR_9356SEL BIT(6) 367 368 #define RTW_RCR_ACRC32 BIT(5) /* accept frames w/ CRC32 errors */ 369 #define RTW_RCR_AB BIT(3) /* accept broadcast frames */ 370 #define RTW_RCR_AM BIT(2) /* accept multicast frames */ 371 /* 372 * accept physical match frames. XXX means PLCP header ok? 373 */ 374 #define RTW_RCR_APM BIT(1) 375 #define RTW_RCR_AAP BIT(0) /* accept frames w/ destination */ 376 377 /* 378 * Additional bits to set in monitor mode. 379 */ 380 #define RTW_RCR_MONITOR ( \ 381 RTW_RCR_AAP | \ 382 RTW_RCR_ACF | \ 383 RTW_RCR_ACRC32 | \ 384 RTW_RCR_AICV | \ 385 0) 386 387 /* 388 * The packet filter bits. 389 */ 390 #define RTW_RCR_PKTFILTER_MASK (\ 391 RTW_RCR_ENCS1|RTW_RCR_ENCS2|\ 392 RTW_RCR_AAP | \ 393 RTW_RCR_AB | \ 394 RTW_RCR_ACF | \ 395 RTW_RCR_ACRC32 | \ 396 RTW_RCR_ADD3 | \ 397 RTW_RCR_ADF | \ 398 RTW_RCR_AICV | \ 399 RTW_RCR_AM | \ 400 RTW_RCR_AMF | \ 401 RTW_RCR_APM | \ 402 RTW_RCR_APWRMGT | \ 403 0) 404 405 /* 406 * Receive power-management frames and mgmt/ctrl/data frames. 407 */ 408 #define RTW_RCR_PKTFILTER_DEFAULT ( \ 409 RTW_RCR_ONLYERLPKT | \ 410 RTW_RCR_ENCS1 | \ 411 RTW_RCR_CBSSID | \ 412 RTW_RCR_ADF | \ 413 RTW_RCR_AMF | \ 414 RTW_RCR_APM | \ 415 RTW_RCR_AM | \ 416 RTW_RCR_AB | \ 417 0) 418 #define RTW_RCR_PROMIC ( \ 419 RTW_RCR_AAP | \ 420 0) 421 422 #define RTW_TINT 0x48 /* Timer Interrupt Register, 32b */ 423 /* 424 * Transmit Beacon Descriptor Start Address, 425 * 32b, 256-byte alignment 426 */ 427 #define RTW_TBDA 0x4c 428 #define RTW_9346CR 0x50 /* 93c46/93c56 Command Register, 8b */ 429 #define RTW_9346CR_EEM_MASK BITS(7, 6) /* Operating Mode */ 430 #define RTW_9346CR_EEM_NORMAL LSHIFT(0, RTW_9346CR_EEM_MASK) 431 /* 432 * Load the EEPROM. Reset registers to defaults. 433 * Takes ~2ms. RTL8180 indicates completion with RTW_9346CR_EEM_NORMAL. 434 * XXX RTL8180 only? 435 */ 436 #define RTW_9346CR_EEM_AUTOLOAD LSHIFT(1, RTW_9346CR_EEM_MASK) 437 /* 438 * Disable network & bus-master operations and enable 439 * _EECS, _EESK, _EEDI, _EEDO. 440 * XXX RTL8180 only? 441 */ 442 #define RTW_9346CR_EEM_PROGRAM LSHIFT(2, RTW_9346CR_EEM_MASK) 443 /* Enable RTW_CONFIG[0123] registers. */ 444 #define RTW_9346CR_EEM_CONFIG LSHIFT(3, RTW_9346CR_EEM_MASK) 445 /* 446 * EEPROM pin status/control in _EEM_CONFIG, _EEM_AUTOLOAD modes. 447 * XXX RTL8180 only? 448 */ 449 #define RTW_9346CR_EECS BIT(3) 450 #define RTW_9346CR_EESK BIT(2) 451 #define RTW_9346CR_EEDI BIT(1) 452 #define RTW_9346CR_EEDO BIT(0) /* read-only */ 453 454 #define RTW_CONFIG0 0x51 /* Configuration Register 0, 8b */ 455 /* 456 * implements 40-bit WEP, XXX RTL8180 only? 457 */ 458 #define RTW_CONFIG0_WEP40 BIT(7) 459 /* 460 * implements 104-bit WEP, from EEPROM, read-only XXX RTL8180 only? 461 */ 462 #define RTW_CONFIG0_WEP104 BIT(6) 463 /* 464 * 1: RTW_PSR_LEDGPO[01] control LED[01] pins. 465 * 0: LED behavior defined by RTW_CONFIG1_LEDS10_MASK 466 * XXX RTL8180 only? 467 */ 468 #define RTW_CONFIG0_LEDGPOEN BIT(4) 469 /* 470 * auxiliary power is present, read-only 471 */ 472 #define RTW_CONFIG0_AUXPWR BIT(3) 473 /* 474 * Geographic Location, read-only 475 */ 476 #define RTW_CONFIG0_GL_MASK BITS(1, 0) 477 /* 478 * _RTW_CONFIG0_GL_* is what the datasheet says, but RTW_CONFIG0_GL_* 479 * work. 480 */ 481 #define _RTW_CONFIG0_GL_USA LSHIFT(3, RTW_CONFIG0_GL_MASK) 482 #define RTW_CONFIG0_GL_EUROPE LSHIFT(2, RTW_CONFIG0_GL_MASK) 483 #define RTW_CONFIG0_GL_JAPAN LSHIFT(1, RTW_CONFIG0_GL_MASK) 484 #define RTW_CONFIG0_GL_USA LSHIFT(0, RTW_CONFIG0_GL_MASK) 485 /* 486 * RTL8181 datasheet says RTW_CONFIG0_GL_JAPAN = 0. 487 */ 488 489 #define RTW_CONFIG1 0x52 /* Configuration Register 1, 8b */ 490 491 /* 492 * LED configuration. From EEPROM. Read/write. 493 * 494 * Setting LED0 LED1 495 * ------- ---- ---- 496 * RTW_CONFIG1_LEDS_ACT_INFRA Activity Infrastructure 497 * RTW_CONFIG1_LEDS_ACT_LINK Activity Link 498 * RTW_CONFIG1_LEDS_TX_RX Tx Rx 499 * RTW_CONFIG1_LEDS_LINKACT_INFRA Link/Activity Infrastructure 500 */ 501 #define RTW_CONFIG1_LEDS_MASK BITS(7, 6) 502 #define RTW_CONFIG1_LEDS_ACT_INFRA LSHIFT(0, RTW_CONFIG1_LEDS_MASK) 503 #define RTW_CONFIG1_LEDS_ACT_LINK LSHIFT(1, RTW_CONFIG1_LEDS_MASK) 504 #define RTW_CONFIG1_LEDS_TX_RX LSHIFT(2, RTW_CONFIG1_LEDS_MASK) 505 #define RTW_CONFIG1_LEDS_LINKACT_INFRA LSHIFT(3, RTW_CONFIG1_LEDS_MASK) 506 507 /* 508 * LWAKE Output Signal. Only applicable to Cardbus. Pulse width is 150ms. 509 * 510 * RTW_CONFIG1_LWACT 511 * 0 1 512 * RTW_CONFIG4_LWPTN 0 active high active low 513 * 1 positive pulse negative pulse 514 */ 515 #define RTW_CONFIG1_LWACT BIT(4) 516 517 #define RTW_CONFIG1_MEMMAP BIT(3) /* using PCI memory space, read-only */ 518 #define RTW_CONFIG1_IOMAP BIT(2) /* using PCI I/O space, read-only */ 519 /* 520 * if set, VPD from offsets 0x40-0x7f in EEPROM are at 521 * registers 0x60-0x67 of PCI Configuration Space ( XXX huh? ) 522 */ 523 #define RTW_CONFIG1_VPD BIT(1) 524 #define RTW_CONFIG1_PMEN BIT(0) /* Power Management Enable: TBD */ 525 526 #define RTW_CONFIG2 0x53 /* Configuration Register 2, 8b */ 527 /* 528 * clocks are locked, read-only: 529 * Tx frequency & symbol clocks are derived from the same OSC 530 */ 531 #define RTW_CONFIG2_LCK BIT(7) 532 #define RTW_CONFIG2_ANT BIT(6) /* diversity enabled, read-only */ 533 /* 534 * Descriptor Polling State: enable test mode. 535 */ 536 #define RTW_CONFIG2_DPS BIT(3) 537 #define RTW_CONFIG2_PAPESIGN BIT(2) /* TBD, from EEPROM */ 538 #define RTW_CONFIG2_PAPETIME_MASK BITS(1, 0) /* TBD, from EEPROM */ 539 540 #define RTW_ANAPARM 0x54 /* Analog parameter, 32b */ 541 /* 542 * undocumented bits which appear to control the power state of the RF 543 * components 544 */ 545 #define RTW_ANAPARM_RFPOW0_MASK BITS(30, 28) 546 #define RTW_ANAPARM_RFPOW_MASK \ 547 (RTW_ANAPARM_RFPOW0_MASK|RTW_ANAPARM_RFPOW1_MASK) 548 549 /* 550 * 1: disable Tx DAC, 551 * 0: enable 552 */ 553 #define RTW_ANAPARM_TXDACOFF BIT(27) 554 /* 555 * undocumented bits which appear to control the power state of the RF 556 * components 557 */ 558 #define RTW_ANAPARM_RFPOW1_MASK BITS(26, 20) 559 560 /* 561 * Maxim On/Sleep/Off control 562 */ 563 #define RTW_ANAPARM_RFPOW_MAXIM_ON LSHIFT(0x8, RTW_ANAPARM_RFPOW1_MASK) 564 565 /* 566 * reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; 567 */ 568 #define RTW_ANAPARM_RFPOW_MAXIM_SLEEP LSHIFT(0x378, RTW_ANAPARM_RFPOW1_MASK) 569 570 /* 571 * reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; 572 */ 573 #define RTW_ANAPARM_RFPOW_MAXIM_OFF LSHIFT(0x379, RTW_ANAPARM_RFPOW1_MASK) 574 575 /* 576 * RFMD On/Sleep/Off control 577 */ 578 #define RTW_ANAPARM_RFPOW_RFMD_ON LSHIFT(0x408, RTW_ANAPARM_RFPOW1_MASK) 579 580 /* 581 * reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; 582 */ 583 #define RTW_ANAPARM_RFPOW_RFMD_SLEEP LSHIFT(0x378, RTW_ANAPARM_RFPOW1_MASK) 584 585 /* 586 * reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; 587 */ 588 #define RTW_ANAPARM_RFPOW_RFMD_OFF LSHIFT(0x379, RTW_ANAPARM_RFPOW1_MASK) 589 590 /* 591 * Philips On/Sleep/Off control 592 */ 593 #define RTW_ANAPARM_RFPOW_ANA_PHILIPS_ON \ 594 LSHIFT(0x328, RTW_ANAPARM_RFPOW1_MASK) 595 #define RTW_ANAPARM_RFPOW_DIG_PHILIPS_ON \ 596 LSHIFT(0x008, RTW_ANAPARM_RFPOW1_MASK) 597 598 /* 599 * reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; 600 */ 601 #define RTW_ANAPARM_RFPOW_PHILIPS_SLEEP\ 602 LSHIFT(0x378, RTW_ANAPARM_RFPOW1_MASK) 603 604 /* 605 * reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; 606 */ 607 #define RTW_ANAPARM_RFPOW_PHILIPS_OFF\ 608 LSHIFT(0x379, RTW_ANAPARM_RFPOW1_MASK) 609 610 #define RTW_ANAPARM_RFPOW_PHILIPS_ON LSHIFT(0x328, RTW_ANAPARM_RFPOW1_MASK) 611 612 /* 613 * undocumented card-specific bits from the EEPROM. 614 */ 615 #define RTW_ANAPARM_CARDSP_MASK BITS(19, 0) 616 617 #define RTW_MSR 0x58 /* Media Status Register, 8b */ 618 /* 619 * Network Type and Link Status 620 */ 621 #define RTW_MSR_NETYPE_MASK BITS(3, 2) 622 /* 623 * AP, XXX RTL8181 only? 624 */ 625 #define RTW_MSR_NETYPE_AP_OK LSHIFT(3, RTW_MSR_NETYPE_MASK) 626 /* 627 * infrastructure link ok 628 */ 629 #define RTW_MSR_NETYPE_INFRA_OK LSHIFT(2, RTW_MSR_NETYPE_MASK) 630 /* 631 * ad-hoc link ok 632 */ 633 #define RTW_MSR_NETYPE_ADHOC_OK LSHIFT(1, RTW_MSR_NETYPE_MASK) 634 /* 635 * no link 636 */ 637 #define RTW_MSR_NETYPE_NOLINK LSHIFT(0, RTW_MSR_NETYPE_MASK) 638 639 #define RTW_CONFIG3 0x59 /* Configuration Register 3, 8b */ 640 #define RTW_CONFIG3_GNTSEL BIT(7) /* Grant Select, read-only */ 641 /* 642 * Set RTW_CONFIG3_PARMEN and RTW_9346CR_EEM_CONFIG to 643 * allow RTW_ANAPARM writes. 644 */ 645 #define RTW_CONFIG3_PARMEN BIT(6) 646 /* 647 * Valid when RTW_CONFIG1_PMEN is set. If set, RTL8180 wakes up 648 * OS when Magic Packet is Rx'd. 649 */ 650 #define RTW_CONFIG3_MAGIC BIT(5) 651 /* 652 * Cardbus-related registers and functions are enabled, 653 * read-only. XXX RTL8180 only. 654 */ 655 #define RTW_CONFIG3_CARDBEN BIT(3) 656 /* 657 * CLKRUN enabled, read-only. XXX RTL8180 only. 658 */ 659 #define RTW_CONFIG3_CLKRUNEN BIT(2) 660 /* 661 * Function Registers Enabled, read-only. XXX RTL8180 only. 662 */ 663 #define RTW_CONFIG3_FUNCREGEN BIT(1) 664 /* 665 * Fast back-to-back enabled, read-only. 666 */ 667 #define RTW_CONFIG3_FBTBEN BIT(0) 668 #define RTW_CONFIG4 0x5A /* Configuration Register 4, 8b */ 669 /* 670 * VCO Power Down 671 * 0: normal operation 672 * (power-on default) 673 * 1: power-down VCO, RF front-end, 674 * and most RTL8180 components. 675 */ 676 #define RTW_CONFIG4_VCOPDN BIT(7) 677 /* 678 * Power Off 679 * 0: normal operation 680 * (power-on default) 681 * 1: power-down RF front-end, 682 * and most RTL8180 components, 683 * but leave VCO on. 684 * 685 * XXX RFMD front-end only? 686 */ 687 #define RTW_CONFIG4_PWROFF BIT(6) 688 /* 689 * Power Management 690 * 0: normal operation 691 * (power-on default) 692 * 1: set Tx packet's PWRMGMT bit. 693 */ 694 #define RTW_CONFIG4_PWRMGT BIT(5) 695 /* 696 * LANWAKE vs. PMEB: Cardbus-only 697 * 0: LWAKE & PMEB asserted 698 * simultaneously 699 * 1: LWAKE asserted only if 700 * both PMEB is asserted and 701 * ISOLATEB is low. 702 * XXX RTL8180 only. 703 */ 704 #define RTW_CONFIG4_LWPME BIT(4) 705 /* 706 * see RTW_CONFIG1_LWACT XXX RTL8180 only. 707 */ 708 #define RTW_CONFIG4_LWPTN BIT(2) 709 /* 710 * Radio Front-End Programming Method 711 */ 712 #define RTW_CONFIG4_RFTYPE_MASK BITS(1, 0) 713 #define RTW_CONFIG4_RFTYPE_INTERSIL LSHIFT(1, RTW_CONFIG4_RFTYPE_MASK) 714 #define RTW_CONFIG4_RFTYPE_RFMD LSHIFT(2, RTW_CONFIG4_RFTYPE_MASK) 715 #define RTW_CONFIG4_RFTYPE_PHILIPS LSHIFT(3, RTW_CONFIG4_RFTYPE_MASK) 716 717 #define RTW_TESTR 0x5B /* TEST mode register, 8b */ 718 719 #define RTW_PSR 0x5e /* Page Select Register, 8b */ 720 #define RTW_PSR_GPO BIT(7) /* Control/status of pin 52. */ 721 #define RTW_PSR_GPI BIT(6) /* Status of pin 64. */ 722 /* 723 * Status/control of LED1 pin if RTW_CONFIG0_LEDGPOEN is set. 724 */ 725 #define RTW_PSR_LEDGPO1 BIT(5) 726 /* 727 * Status/control of LED0 pin if RTW_CONFIG0_LEDGPOEN is set. 728 */ 729 #define RTW_PSR_LEDGPO0 BIT(4) 730 #define RTW_PSR_UWF BIT(1) /* Enable Unicast Wakeup Frame */ 731 #define RTW_PSR_PSEN BIT(0) /* 1: page 1, 0: page 0 */ 732 733 #define RTW_SCR 0x5f /* Security Configuration Register, 8b */ 734 #define RTW_SCR_KM_MASK BITS(5, 4) /* Key Mode */ 735 #define RTW_SCR_KM_WEP104 LSHIFT(1, RTW_SCR_KM_MASK) 736 #define RTW_SCR_KM_WEP40 LSHIFT(0, RTW_SCR_KM_MASK) 737 /* 738 * Enable Tx WEP. Invalid if neither RTW_CONFIG0_WEP40 nor 739 * RTW_CONFIG0_WEP104 is set. 740 */ 741 #define RTW_SCR_TXSECON BIT(1) 742 /* 743 * Enable Rx WEP. Invalid if neither RTW_CONFIG0_WEP40 nor 744 * RTW_CONFIG0_WEP104 is set. 745 */ 746 #define RTW_SCR_RXSECON BIT(0) 747 748 #define RTW_BCNITV 0x70 /* Beacon Interval Register, 16b */ 749 /* 750 * TU between TBTT, written by host. 751 */ 752 #define RTW_BCNITV_BCNITV_MASK BITS(9, 0) 753 #define RTW_ATIMWND 0x72 /* ATIM Window Register, 16b */ 754 /* 755 * ATIM Window length in TU, written by host. 756 */ 757 #define RTW_ATIMWND_ATIMWND BITS(9, 0) 758 759 #define RTW_BINTRITV 0x74 /* Beacon Interrupt Interval Register, 16b */ 760 /* 761 * RTL8180 wakes host with RTW_INTR_BCNINT at BINTRITV 762 * microseconds before TBTT 763 */ 764 #define RTW_BINTRITV_BINTRITV BITS(9, 0) 765 #define RTW_ATIMTRITV 0x76 /* ATIM Interrupt Interval Register, 16b */ 766 /* 767 * RTL8180 wakes host with RTW_INTR_ATIMINT at ATIMTRITV 768 * microseconds before end of ATIM Window 769 */ 770 #define RTW_ATIMTRITV_ATIMTRITV BITS(9, 0) 771 772 #define RTW_PHYDELAY 0x78 /* PHY Delay Register, 8b */ 773 /* 774 * Rev. C magic from reference driver 775 */ 776 #define RTW_PHYDELAY_REVC_MAGIC BIT(3) 777 /* 778 * microsecond Tx delay between MAC and RF front-end 779 */ 780 #define RTW_PHYDELAY_PHYDELAY BITS(2, 0) 781 #define RTW_CRCOUNT 0x79 /* Carrier Sense Counter, 8b */ 782 #define RTW_CRCOUNT_MAGIC 0x4c 783 784 #define RTW_CRC16ERR 0x7a /* CRC16 error count, 16b, XXX RTL8181 only? */ 785 786 #define RTW_BB 0x7c /* Baseband interface, 32b */ 787 /* 788 * used for writing RTL8180's integrated baseband processor 789 */ 790 #define RTW_BB_RD_MASK BITS(23, 16) /* data to read */ 791 #define RTW_BB_WR_MASK BITS(15, 8) /* data to write */ 792 #define RTW_BB_WREN BIT(7) /* write enable */ 793 #define RTW_BB_ADDR_MASK BITS(6, 0) /* address */ 794 795 #define RTW_PHYADDR 0x7c /* Address register for PHY interface, 8b */ 796 #define RTW_PHYDATAW 0x7d /* Write data to PHY, 8b, write-only */ 797 #define RTW_PHYDATAR 0x7e /* Read data from PHY, 8b (?), read-only */ 798 799 #define RTW_PHYCFG 0x80 /* PHY Configuration Register, 32b */ 800 /* 801 * if !RTW_PHYCFG_HST, host sets. MAC clears after banging bits. 802 */ 803 #define RTW_PHYCFG_MAC_POLL BIT(31) 804 /* 805 * 1: host bangs bits 806 * 0: MAC bangs bits 807 */ 808 #define RTW_PHYCFG_HST BIT(30) 809 #define RTW_PHYCFG_MAC_RFTYPE_MASK BITS(29, 28) 810 #define RTW_PHYCFG_MAC_RFTYPE_INTERSIL LSHIFT(0, RTW_PHYCFG_MAC_RFTYPE_MASK) 811 #define RTW_PHYCFG_MAC_RFTYPE_RFMD LSHIFT(1, RTW_PHYCFG_MAC_RFTYPE_MASK) 812 #define RTW_PHYCFG_MAC_RFTYPE_GCT RTW_PHYCFG_MAC_RFTYPE_RFMD 813 #define RTW_PHYCFG_MAC_RFTYPE_PHILIPS LSHIFT(3, RTW_PHYCFG_MAC_RFTYPE_MASK) 814 #define RTW_PHYCFG_MAC_PHILIPS_ADDR_MASK BITS(27, 24) 815 #define RTW_PHYCFG_MAC_PHILIPS_DATA_MASK BITS(23, 0) 816 #define RTW_PHYCFG_MAC_MAXIM_LODATA_MASK BITS(27, 24) 817 #define RTW_PHYCFG_MAC_MAXIM_ADDR_MASK BITS(11, 8) 818 #define RTW_PHYCFG_MAC_MAXIM_HIDATA_MASK BITS(7, 0) 819 #define RTW_PHYCFG_HST_EN BIT(2) 820 #define RTW_PHYCFG_HST_CLK BIT(1) 821 #define RTW_PHYCFG_HST_DATA BIT(0) 822 823 #define RTW_MAXIM_HIDATA_MASK BITS(11, 4) 824 #define RTW_MAXIM_LODATA_MASK BITS(3, 0) 825 826 /* 827 * 0x84 - 0xD3, page 1, selected when RTW_PSR[PSEN] == 1. 828 */ 829 830 #define RTW_WAKEUP0L 0x84 /* Power Management Wakeup Frame */ 831 #define RTW_WAKEUP0H 0x88 /* 32b */ 832 833 #define RTW_WAKEUP1L 0x8c 834 #define RTW_WAKEUP1H 0x90 835 836 #define RTW_WAKEUP2LL 0x94 837 #define RTW_WAKEUP2LH 0x98 838 839 #define RTW_WAKEUP2HL 0x9c 840 #define RTW_WAKEUP2HH 0xa0 841 842 #define RTW_WAKEUP3LL 0xa4 843 #define RTW_WAKEUP3LH 0xa8 844 845 #define RTW_WAKEUP3HL 0xac 846 #define RTW_WAKEUP3HH 0xb0 847 848 #define RTW_WAKEUP4LL 0xb4 849 #define RTW_WAKEUP4LH 0xb8 850 851 #define RTW_WAKEUP4HL 0xbc 852 #define RTW_WAKEUP4HH 0xc0 853 854 #define RTW_CRC0 0xc4 /* CRC of wakeup frame 0, 16b */ 855 #define RTW_CRC1 0xc6 /* CRC of wakeup frame 1, 16b */ 856 #define RTW_CRC2 0xc8 /* CRC of wakeup frame 2, 16b */ 857 #define RTW_CRC3 0xca /* CRC of wakeup frame 3, 16b */ 858 #define RTW_CRC4 0xcc /* CRC of wakeup frame 4, 16b */ 859 860 /* 861 * 0x84 - 0xD3, page 0, selected when RTW_PSR[PSEN] == 0. 862 */ 863 864 /* 865 * Default Key Registers, each 128b 866 * 867 * If RTW_SCR_KM_WEP104, 104 lsb are the key. 868 * If RTW_SCR_KM_WEP40, 40 lsb are the key. 869 */ 870 #define RTW_DK0 0x90 /* Default Key 0 Register, 128b */ 871 #define RTW_DK1 0xa0 /* Default Key 1 Register, 128b */ 872 #define RTW_DK2 0xb0 /* Default Key 2 Register, 128b */ 873 #define RTW_DK3 0xc0 /* Default Key 3 Register, 128b */ 874 875 #define RTW_CONFIG5 0xd8 /* Configuration Register 5, 8b */ 876 #define RTW_CONFIG5_TXFIFOOK BIT(7) /* Tx FIFO self-test pass, read-only */ 877 #define RTW_CONFIG5_RXFIFOOK BIT(6) /* Rx FIFO self-test pass, read-only */ 878 /* 879 * 1: start calibration cycle and raise AGCRESET pin. 880 * 0: lower AGCRESET pin 881 */ 882 #define RTW_CONFIG5_CALON BIT(5) 883 #define RTW_CONFIG5_EACPI BIT(2) /* Enable ACPI Wake up, default 0 */ 884 /* 885 * Enable LAN Wake signal, from EEPROM 886 */ 887 #define RTW_CONFIG5_LANWAKE BIT(1) 888 /* 889 * 1: both software & PCI Reset reset PME_Status 890 * 0: only software resets PME_Status 891 * 892 * From EEPROM. 893 */ 894 #define RTW_CONFIG5_PMESTS BIT(0) 895 896 /* 897 * Transmit Priority Polling Register, 8b, write-only. 898 */ 899 #define RTW_TPPOLL 0xd9 900 /* 901 * RTL8180 clears to notify host of a beacon 902 * Tx. Host writes have no effect. 903 */ 904 #define RTW_TPPOLL_BQ BIT(7) 905 /* 906 * Host writes 1 to notify RTL8180 of high-priority Tx packets, RTL8180 clears 907 * to after high-priority Tx is complete. 908 */ 909 #define RTW_TPPOLL_HPQ BIT(6) 910 /* 911 * If RTW_CONFIG2_DPS is set, host writes 1 to notify RTL8180 of 912 * normal-priority Tx packets, RTL8180 clears 913 * after normal-priority Tx is complete. 914 * 915 * If RTW_CONFIG2_DPS is clear, host writes have no effect. RTL8180 clears after 916 * normal-priority Tx is complete. 917 */ 918 #define RTW_TPPOLL_NPQ BIT(5) 919 /* 920 * Host writes 1 to notify RTL8180 of low-priority Tx packets, RTL8180 clears 921 * after low-priority Tx is complete. 922 */ 923 #define RTW_TPPOLL_LPQ BIT(4) 924 /* 925 * Host writes 1 to tell RTL8180 to stop beacon DMA. This bit is invalid 926 * when RTW_CONFIG2_DPS is set. 927 */ 928 #define RTW_TPPOLL_SBQ BIT(3) 929 /* 930 * Host writes 1 to tell RTL8180 to stop high-priority DMA. 931 */ 932 #define RTW_TPPOLL_SHPQ BIT(2) 933 /* 934 * Host writes 1 to tell RTL8180 to stop normal-priority DMA. 935 * This bit is invalid when RTW_CONFIG2_DPS is set. 936 */ 937 #define RTW_TPPOLL_SNPQ BIT(1) 938 /* 939 * Host writes 1 to tell RTL8180 to stop low-priority DMA. 940 */ 941 #define RTW_TPPOLL_SLPQ BIT(0) 942 943 /* Start all queues. */ 944 #define RTW_TPPOLL_ALL (RTW_TPPOLL_BQ | RTW_TPPOLL_HPQ | \ 945 RTW_TPPOLL_NPQ | RTW_TPPOLL_LPQ) 946 947 /* Start queues solaris required. */ 948 #define RTW_TPPOLL_LN (RTW_TPPOLL_NPQ | RTW_TPPOLL_LPQ) 949 950 /* Stop all queues. */ 951 #define RTW_TPPOLL_SALL (RTW_TPPOLL_SBQ | RTW_TPPOLL_SHPQ | \ 952 RTW_TPPOLL_SNPQ | RTW_TPPOLL_SLPQ) 953 954 #define RTW_CWR 0xdc /* Contention Window Register, 16b, read-only */ 955 /* 956 * Contention Window: indicates number of contention windows before Tx 957 */ 958 #define RTW_CWR_CW BITS(9, 0) 959 960 /* 961 * Retry Count Register, 16b, read-only 962 */ 963 #define RTW_RETRYCTR 0xde 964 /* 965 * Retry Count: indicates number of retries after Tx 966 */ 967 #define RTW_RETRYCTR_RETRYCT BITS(7, 0) 968 969 /* 970 * Receive descriptor Start Address Register, 971 * 32b, 256-byte alignment. 972 */ 973 #define RTW_RDSAR 0xe4 974 /* 975 * Function Event Register, 32b, Cardbus only. Only valid when 976 * both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN are set. 977 */ 978 #define RTW_FER 0xf0 979 #define RTW_FER_INTR BIT(15) /* set when RTW_FFER_INTR is set */ 980 #define RTW_FER_GWAKE BIT(4) /* General Wakeup */ 981 /* 982 * Function Event Mask Register, 32b, Cardbus only. Only valid when 983 * both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN are set. 984 */ 985 #define RTW_FEMR 0xf4 986 #define RTW_FEMR_INTR BIT(15) /* set when RTW_FFER_INTR is set */ 987 #define RTW_FEMR_WKUP BIT(14) /* Wakeup Mask */ 988 #define RTW_FEMR_GWAKE BIT(4) /* General Wakeup */ 989 /* 990 * Function Present State Register, 32b, read-only, Cardbus only. 991 * Only valid when both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN 992 * are set. 993 */ 994 #define RTW_FPSR 0xf8 995 #define RTW_FPSR_INTR BIT(15) /* TBD */ 996 #define RTW_FPSR_GWAKE BIT(4) /* General Wakeup: TBD */ 997 /* 998 * Function Force Event Register, 32b, write-only, Cardbus only. 999 * Only valid when both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN 1000 * are set. 1001 */ 1002 #define RTW_FFER 0xfc 1003 #define RTW_FFER_INTR BIT(15) /* TBD */ 1004 #define RTW_FFER_GWAKE BIT(4) /* General Wakeup: TBD */ 1005 1006 /* 1007 * Serial EEPROM offsets 1008 */ 1009 #define RTW_SR_ID 0x00 /* 16b */ 1010 #define RTW_SR_VID 0x02 /* 16b */ 1011 #define RTW_SR_DID 0x04 /* 16b */ 1012 #define RTW_SR_SVID 0x06 /* 16b */ 1013 #define RTW_SR_SMID 0x08 /* 16b */ 1014 #define RTW_SR_MNGNT 0x0a 1015 #define RTW_SR_MXLAT 0x0b 1016 #define RTW_SR_RFCHIPID 0x0c 1017 #define RTW_SR_CONFIG3 0x0d 1018 #define RTW_SR_MAC 0x0e /* 6 bytes */ 1019 #define RTW_SR_CONFIG0 0x14 1020 #define RTW_SR_CONFIG1 0x15 1021 #define RTW_SR_PMC 0x16 /* Power Management Capabilities, 16b */ 1022 #define RTW_SR_CONFIG2 0x18 1023 #define RTW_SR_CONFIG4 0x19 1024 #define RTW_SR_ANAPARM 0x1a /* Analog Parameters, 32b */ 1025 #define RTW_SR_TESTR 0x1e 1026 #define RTW_SR_CONFIG5 0x1f 1027 #define RTW_SR_TXPOWER1 0x20 1028 #define RTW_SR_TXPOWER2 0x21 1029 #define RTW_SR_TXPOWER3 0x22 1030 #define RTW_SR_TXPOWER4 0x23 1031 #define RTW_SR_TXPOWER5 0x24 1032 #define RTW_SR_TXPOWER6 0x25 1033 #define RTW_SR_TXPOWER7 0x26 1034 #define RTW_SR_TXPOWER8 0x27 1035 #define RTW_SR_TXPOWER9 0x28 1036 #define RTW_SR_TXPOWER10 0x29 1037 #define RTW_SR_TXPOWER11 0x2a 1038 #define RTW_SR_TXPOWER12 0x2b 1039 #define RTW_SR_TXPOWER13 0x2c 1040 #define RTW_SR_TXPOWER14 0x2d 1041 #define RTW_SR_CHANNELPLAN 0x2e /* bitmap of channels to scan */ 1042 #define RTW_SR_ENERGYDETTHR 0x2f /* energy-detect threshold */ 1043 #define RTW_SR_ENERGYDETTHR_DEFAULT 0x0c /* use this if old SROM */ 1044 #define RTW_SR_CISPOINTER 0x30 /* 16b */ 1045 #define RTW_SR_RFPARM 0x32 /* RF-specific parameter */ 1046 #define RTW_SR_RFPARM_DIGPHY BIT(0) /* 1: digital PHY */ 1047 #define RTW_SR_RFPARM_DFLANTB BIT(1) /* 1: antenna B is default */ 1048 #define RTW_SR_RFPARM_CS_MASK BITS(2, 3) /* carrier-sense type */ 1049 #define RTW_SR_VERSION 0x3c /* EEPROM content version, 16b */ 1050 #define RTW_SR_CRC 0x3e /* EEPROM content CRC, 16b */ 1051 #define RTW_SR_VPD 0x40 /* Vital Product Data, 64 bytes */ 1052 #define RTW_SR_CIS 0x80 /* CIS Data, 93c56 only, 128 bytes */ 1053 1054 /* 1055 * RTL8180 Transmit/Receive Descriptors 1056 */ 1057 1058 /* 1059 * the first descriptor in each ring must be on a 256-byte boundary 1060 */ 1061 #define RTW_DESC_ALIGNMENT 256 1062 1063 /* 1064 * Tx descriptor 1065 */ 1066 struct rtw_txdesc { 1067 uint32_t td_ctl0; 1068 uint32_t td_ctl1; 1069 uint32_t td_buf; 1070 uint32_t td_len; 1071 uint32_t td_next; 1072 uint32_t td_rsvd[3]; 1073 }; 1074 1075 #define td_stat td_ctl0 1076 1077 #define RTW_TXCTL0_OWN BIT(31) /* 1: ready to Tx */ 1078 #define RTW_TXCTL0_RSVD0 BIT(30) /* reserved */ 1079 #define RTW_TXCTL0_FS BIT(29) /* first segment */ 1080 #define RTW_TXCTL0_LS BIT(28) /* last segment */ 1081 1082 #define RTW_TXCTL0_RATE_MASK BITS(27, 24) /* Tx rate */ 1083 #define RTW_TXCTL0_RATE_1MBPS LSHIFT(0, RTW_TXCTL0_RATE_MASK) 1084 #define RTW_TXCTL0_RATE_2MBPS LSHIFT(1, RTW_TXCTL0_RATE_MASK) 1085 #define RTW_TXCTL0_RATE_5MBPS LSHIFT(2, RTW_TXCTL0_RATE_MASK) 1086 #define RTW_TXCTL0_RATE_11MBPS LSHIFT(3, RTW_TXCTL0_RATE_MASK) 1087 1088 #define RTW_TXCTL0_RTSEN BIT(23) /* RTS Enable */ 1089 1090 #define RTW_TXCTL0_RTSRATE_MASK BITS(22, 19) /* Tx rate */ 1091 #define RTW_TXCTL0_RTSRATE_1MBPS LSHIFT(0, RTW_TXCTL0_RTSRATE_MASK) 1092 #define RTW_TXCTL0_RTSRATE_2MBPS LSHIFT(1, RTW_TXCTL0_RTSRATE_MASK) 1093 #define RTW_TXCTL0_RTSRATE_5MBPS LSHIFT(2, RTW_TXCTL0_RTSRATE_MASK) 1094 #define RTW_TXCTL0_RTSRATE_11MBPS LSHIFT(3, RTW_TXCTL0_RTSRATE_MASK) 1095 1096 #define RTW_TXCTL0_BEACON BIT(18) /* packet is a beacon */ 1097 #define RTW_TXCTL0_MOREFRAG BIT(17) /* another fragment follows */ 1098 /* 1099 * add short PLCP preamble and header 1100 */ 1101 #define RTW_TXCTL0_SPLCP BIT(16) 1102 #define RTW_TXCTL0_KEYID_MASK BITS(15, 14) /* default key id */ 1103 #define RTW_TXCTL0_RSVD1_MASK BITS(13, 12) /* reserved */ 1104 /* 1105 * Tx packet size in bytes 1106 */ 1107 #define RTW_TXCTL0_TPKTSIZE_MASK BITS(11, 0) 1108 1109 #define RTW_TXSTAT_OWN RTW_TXCTL0_OWN 1110 #define RTW_TXSTAT_RSVD0 RTW_TXCTL0_RSVD0 1111 #define RTW_TXSTAT_FS RTW_TXCTL0_FS 1112 #define RTW_TXSTAT_LS RTW_TXCTL0_LS 1113 #define RTW_TXSTAT_RSVD1_MASK BITS(27, 16) 1114 #define RTW_TXSTAT_TOK BIT(15) 1115 #define RTW_TXSTAT_RTSRETRY_MASK BITS(14, 8) /* RTS retry count */ 1116 #define RTW_TXSTAT_DRC_MASK BITS(7, 0) /* Data retry count */ 1117 1118 /* 1119 * supplements _LENGTH in packets sent 5.5Mb/s or faster 1120 */ 1121 #define RTW_TXCTL1_LENGEXT BIT(31) 1122 #define RTW_TXCTL1_LENGTH_MASK BITS(30, 16) /* PLCP length (microseconds) */ 1123 /* 1124 * RTS Duration (microseconds) 1125 */ 1126 #define RTW_TXCTL1_RTSDUR_MASK BITS(15, 0) 1127 1128 #define RTW_TXLEN_LENGTH_MASK BITS(11, 0) /* Tx buffer length in bytes */ 1129 1130 /* 1131 * Rx descriptor 1132 */ 1133 struct rtw_rxdesc { 1134 uint32_t rd_ctl; 1135 uint32_t rd_rsvd0; 1136 uint32_t rd_buf; 1137 uint32_t rd_rsvd1; 1138 }; 1139 1140 #define rd_stat rd_ctl 1141 #define rd_rssi rd_rsvd0 1142 #define rd_tsftl rd_buf /* valid only when RTW_RXSTAT_LS is set */ 1143 #define rd_tsfth rd_rsvd1 /* valid only when RTW_RXSTAT_LS is set */ 1144 1145 #define RTW_RXCTL_OWN BIT(31) /* 1: owned by NIC */ 1146 #define RTW_RXCTL_EOR BIT(30) /* end of ring */ 1147 #define RTW_RXCTL_FS BIT(29) /* first segment */ 1148 #define RTW_RXCTL_LS BIT(28) /* last segment */ 1149 #define RTW_RXCTL_RSVD0_MASK BITS(29, 12) /* reserved */ 1150 #define RTW_RXCTL_LENGTH_MASK BITS(11, 0) /* Rx buffer length */ 1151 1152 #define RTW_RXSTAT_OWN RTW_RXCTL_OWN 1153 #define RTW_RXSTAT_EOR RTW_RXCTL_EOR 1154 #define RTW_RXSTAT_FS RTW_RXCTL_FS /* first segment */ 1155 #define RTW_RXSTAT_LS RTW_RXCTL_LS /* last segment */ 1156 #define RTW_RXSTAT_DMAFAIL BIT(27) /* DMA failure on this pkt */ 1157 /* 1158 * buffer overflow XXX means FIFO exhausted? 1159 */ 1160 #define RTW_RXSTAT_BOVF BIT(26) 1161 /* 1162 * Rx'd with short preamble and PLCP header 1163 */ 1164 #define RTW_RXSTAT_SPLCP BIT(25) 1165 #define RTW_RXSTAT_RSVD1 BIT(24) /* reserved */ 1166 #define RTW_RXSTAT_RATE_MASK BITS(23, 20) /* Rx rate */ 1167 #define RTW_RXSTAT_RATE_1MBPS LSHIFT(0, RTW_RXSTAT_RATE_MASK) 1168 #define RTW_RXSTAT_RATE_2MBPS LSHIFT(1, RTW_RXSTAT_RATE_MASK) 1169 #define RTW_RXSTAT_RATE_5MBPS LSHIFT(2, RTW_RXSTAT_RATE_MASK) 1170 #define RTW_RXSTAT_RATE_11MBPS LSHIFT(3, RTW_RXSTAT_RATE_MASK) 1171 #define RTW_RXSTAT_MIC BIT(19) /* XXX from reference driver */ 1172 #define RTW_RXSTAT_MAR BIT(18) /* is multicast */ 1173 #define RTW_RXSTAT_PAR BIT(17) /* matches RTL8180's MAC */ 1174 #define RTW_RXSTAT_BAR BIT(16) /* is broadcast */ 1175 /* 1176 * error summary. valid when RTW_RXSTAT_LS set. indicates 1177 * that either RTW_RXSTAT_CRC32 or RTW_RXSTAT_ICV is set. 1178 */ 1179 #define RTW_RXSTAT_RES BIT(15) 1180 #define RTW_RXSTAT_PWRMGT BIT(14) /* 802.11 PWRMGMT bit is set */ 1181 /* 1182 * XXX CRC16 error, from reference driver 1183 */ 1184 #define RTW_RXSTAT_CRC16 BIT(14) 1185 #define RTW_RXSTAT_CRC32 BIT(13) /* CRC32 error */ 1186 #define RTW_RXSTAT_ICV BIT(12) /* ICV error */ 1187 /* 1188 * frame length, including CRC32 1189 */ 1190 #define RTW_RXSTAT_LENGTH_MASK BITS(11, 0) 1191 1192 /* 1193 * Convenient status conjunction. 1194 */ 1195 #define RTW_RXSTAT_ONESEG (RTW_RXSTAT_FS|RTW_RXSTAT_LS) 1196 /* 1197 * Convenient status disjunctions. 1198 */ 1199 #define RTW_RXSTAT_IOERROR (RTW_RXSTAT_DMAFAIL|RTW_RXSTAT_BOVF) 1200 #define RTW_RXSTAT_DEBUG (RTW_RXSTAT_SPLCP|RTW_RXSTAT_MAR|\ 1201 RTW_RXSTAT_PAR|RTW_RXSTAT_BAR|\ 1202 RTW_RXSTAT_PWRMGT|RTW_RXSTAT_CRC32|\ 1203 RTW_RXSTAT_ICV) 1204 1205 1206 #define RTW_RXRSSI_VLAN BITS(32, 16) /* XXX from reference driver */ 1207 /* 1208 * for Philips RF front-ends 1209 */ 1210 #define RTW_RXRSSI_RSSI BITS(15, 8) /* RF energy at the PHY */ 1211 /* 1212 * for RF front-ends by Intersil, Maxim, RFMD 1213 */ 1214 #define RTW_RXRSSI_IMR_RSSI BITS(15, 9) /* RF energy at the PHY */ 1215 #define RTW_RXRSSI_IMR_LNA BIT(8) /* 1: LNA activated */ 1216 #define RTW_RXRSSI_SQ BITS(7, 0) /* Barker code-lock quality */ 1217 1218 #define RTW_READ8(regs, ofs) \ 1219 ddi_get8((regs)->r_handle, (uint8_t *)((regs)->r_base + (ofs))) 1220 1221 #define RTW_READ16(regs, ofs) \ 1222 ddi_get16((regs)->r_handle, (uint16_t *)((regs)->r_base + (ofs))) 1223 1224 #define RTW_READ(regs, ofs) \ 1225 ddi_get32((regs)->r_handle, (uint32_t *)((regs)->r_base + (ofs))) 1226 1227 #define RTW_WRITE8(regs, ofs, val) \ 1228 ddi_put8((regs)->r_handle, (uint8_t *)((regs)->r_base + (ofs)), val) 1229 1230 #define RTW_WRITE16(regs, ofs, val) \ 1231 ddi_put16((regs)->r_handle, (uint16_t *)((regs)->r_base + (ofs)), val) 1232 1233 #define RTW_WRITE(regs, ofs, val) \ 1234 ddi_put32((regs)->r_handle, (uint32_t *)((regs)->r_base + (ofs)), val) 1235 1236 #define RTW_ISSET(regs, reg, mask) \ 1237 (RTW_READ((regs), (reg)) & (mask)) 1238 1239 #define RTW_CLR(regs, reg, mask) \ 1240 RTW_WRITE((regs), (reg), RTW_READ((regs), (reg)) & ~(mask)) 1241 1242 /* 1243 * bus_space(9) lied? 1244 */ 1245 #ifndef BUS_SPACE_BARRIER_SYNC 1246 #define BUS_SPACE_BARRIER_SYNC (BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 1247 #endif 1248 1249 #ifndef BUS_SPACE_BARRIER_READ_BEFORE_READ 1250 #define BUS_SPACE_BARRIER_READ_BEFORE_READ BUS_SPACE_BARRIER_READ 1251 #endif 1252 1253 #ifndef BUS_SPACE_BARRIER_READ_BEFORE_WRITE 1254 #define BUS_SPACE_BARRIER_READ_BEFORE_WRITE BUS_SPACE_BARRIER_READ 1255 #endif 1256 1257 #ifndef BUS_SPACE_BARRIER_WRITE_BEFORE_READ 1258 #define BUS_SPACE_BARRIER_WRITE_BEFORE_READ BUS_SPACE_BARRIER_WRITE 1259 #endif 1260 1261 #ifndef BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE 1262 #define BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE BUS_SPACE_BARRIER_WRITE 1263 #endif 1264 1265 /* 1266 * Bus barrier 1267 * 1268 * Complete outstanding read and/or write ops on [reg0, reg1] 1269 * ([reg1, reg0]) before starting new ops on the same region. See 1270 * acceptable bus_space_barrier(9) for the flag definitions. 1271 */ 1272 #define RTW_BARRIER(regs, reg0, reg1, flags) 1273 /* 1274 * ***just define a dummy macro here in solaris*** 1275 * bus_space_barrier((regs)->r_bh, (regs)->r_bt, \ 1276 * MIN(reg0, reg1), MAX(reg0, reg1) - MIN(reg0, reg1) + 4, flags) 1277 */ 1278 /* 1279 * Barrier convenience macros. 1280 */ 1281 /* 1282 * sync 1283 */ 1284 #define RTW_SYNC(regs, reg0, reg1) \ 1285 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_SYNC) 1286 1287 /* 1288 * write-before-write 1289 */ 1290 #define RTW_WBW(regs, reg0, reg1) \ 1291 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE) 1292 1293 /* 1294 * write-before-read 1295 */ 1296 #define RTW_WBR(regs, reg0, reg1) \ 1297 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_READ) 1298 1299 /* 1300 * read-before-read 1301 */ 1302 #define RTW_RBR(regs, reg0, reg1) \ 1303 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_READ) 1304 1305 /* 1306 * read-before-read 1307 */ 1308 #define RTW_RBW(regs, reg0, reg1) \ 1309 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_WRITE) 1310 1311 #define RTW_WBRW(regs, reg0, reg1) \ 1312 RTW_BARRIER(regs, reg0, reg1, \ 1313 BUS_SPACE_BARRIER_WRITE_BEFORE_READ | \ 1314 BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE) 1315 1316 /* 1317 * Registers for RTL8180L's built-in baseband modem. 1318 */ 1319 #define RTW_BBP_SYS1 0x00 1320 #define RTW_BBP_TXAGC 0x03 /* guess: transmit auto gain control */ 1321 /* 1322 * guess: low-noise amplifier activation threshold 1323 */ 1324 #define RTW_BBP_LNADET 0x04 1325 /* 1326 * guess: intermediate frequency (IF) 1327 * auto-gain control (AGC) initial value 1328 */ 1329 #define RTW_BBP_IFAGCINI 0x05 1330 #define RTW_BBP_IFAGCLIMIT 0x06 /* guess: IF AGC maximum value */ 1331 /* 1332 * guess: activation threshold for IF AGC loop 1333 */ 1334 #define RTW_BBP_IFAGCDET 0x07 1335 1336 #define RTW_BBP_ANTATTEN 0x10 /* guess: antenna & attenuation */ 1337 #define RTW_BBP_ANTATTEN_PHILIPS_MAGIC 0x91 1338 #define RTW_BBP_ANTATTEN_INTERSIL_MAGIC 0x92 1339 #define RTW_BBP_ANTATTEN_RFMD_MAGIC 0x93 1340 #define RTW_BBP_ANTATTEN_MAXIM_MAGIC 0xb3 1341 #define RTW_BBP_ANTATTEN_DFLANTB 0x40 1342 #define RTW_BBP_ANTATTEN_CHAN14 0x0c 1343 1344 /* 1345 * guess: transmit/receive switch latency 1346 */ 1347 #define RTW_BBP_TRL 0x11 1348 #define RTW_BBP_SYS2 0x12 1349 #define RTW_BBP_SYS2_ANTDIV 0x80 /* enable antenna diversity */ 1350 /* 1351 * loopback rate? 1352 * 0: 1Mbps 1353 * 1: 2Mbps 1354 * 2: 5.5Mbps 1355 * 3: 11Mbps 1356 */ 1357 #define RTW_BBP_SYS2_RATE_MASK BITS(5, 4) 1358 #define RTW_BBP_SYS3 0x13 1359 /* 1360 * carrier-sense threshold 1361 */ 1362 #define RTW_BBP_SYS3_CSTHRESH_MASK BITS(0, 3) 1363 /* 1364 * guess: channel energy-detect threshold 1365 */ 1366 #define RTW_BBP_CHESTLIM 0x19 1367 /* 1368 * guess: channel signal-quality threshold 1369 */ 1370 #define RTW_BBP_CHSQLIM 0x1a 1371 1372 #define RTW_EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6)) 1373 #define RTW_EPROM_CMD_OPERATING_MODE_SHIFT 6 1374 #define RTW_EPROM_CS_SHIFT 3 1375 #define RTW_EPROM_CK_SHIFT 2 1376 #define RTW_EPROM_CMD_CONFIG 0x3 1377 #define RTW_EPROM_CMD_NORMAL 0 1378 #define RTW_EPROM_CMD_LOAD 1 1379 #define RTW_TX_DMA_POLLING_HIPRIORITY_SHIFT 6 1380 #define RTW_TX_DMA_POLLING_NORMPRIORITY_SHIFT 5 1381 #define RTW_TX_DMA_POLLING_LOWPRIORITY_SHIFT 4 1382 #define RTW_CONFIG2_DMA_POLLING_MODE_SHIFT 3 1383 1384 #define RTW_CMD_RST_SHIFT (4) 1385 #define RTW_TX_DMA_STOP_BEACON_SHIFT 3 1386 1387 #endif /* _RTW_REG_H_ */ 1388