1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include "rge.h" 29 30 #define REG32(rgep, reg) ((uint32_t *)(rgep->io_regs+(reg))) 31 #define REG16(rgep, reg) ((uint16_t *)(rgep->io_regs+(reg))) 32 #define REG8(rgep, reg) ((uint8_t *)(rgep->io_regs+(reg))) 33 #define PIO_ADDR(rgep, offset) ((void *)(rgep->io_regs+(offset))) 34 35 /* 36 * Patchable globals: 37 * 38 * rge_autorecover 39 * Enables/disables automatic recovery after fault detection 40 */ 41 static uint32_t rge_autorecover = 1; 42 43 /* 44 * globals: 45 */ 46 #define RGE_DBG RGE_DBG_REGS /* debug flag for this code */ 47 static uint32_t rge_watchdog_count = 1 << 16; 48 49 /* 50 * Operating register get/set access routines 51 */ 52 53 static uint32_t rge_reg_get32(rge_t *rgep, uintptr_t regno); 54 #pragma inline(rge_reg_get32) 55 56 static uint32_t 57 rge_reg_get32(rge_t *rgep, uintptr_t regno) 58 { 59 RGE_TRACE(("rge_reg_get32($%p, 0x%lx)", 60 (void *)rgep, regno)); 61 62 return (ddi_get32(rgep->io_handle, REG32(rgep, regno))); 63 } 64 65 static void rge_reg_put32(rge_t *rgep, uintptr_t regno, uint32_t data); 66 #pragma inline(rge_reg_put32) 67 68 static void 69 rge_reg_put32(rge_t *rgep, uintptr_t regno, uint32_t data) 70 { 71 RGE_TRACE(("rge_reg_put32($%p, 0x%lx, 0x%x)", 72 (void *)rgep, regno, data)); 73 74 ddi_put32(rgep->io_handle, REG32(rgep, regno), data); 75 } 76 77 static void rge_reg_set32(rge_t *rgep, uintptr_t regno, uint32_t bits); 78 #pragma inline(rge_reg_set32) 79 80 static void 81 rge_reg_set32(rge_t *rgep, uintptr_t regno, uint32_t bits) 82 { 83 uint32_t regval; 84 85 RGE_TRACE(("rge_reg_set32($%p, 0x%lx, 0x%x)", 86 (void *)rgep, regno, bits)); 87 88 regval = rge_reg_get32(rgep, regno); 89 regval |= bits; 90 rge_reg_put32(rgep, regno, regval); 91 } 92 93 static void rge_reg_clr32(rge_t *rgep, uintptr_t regno, uint32_t bits); 94 #pragma inline(rge_reg_clr32) 95 96 static void 97 rge_reg_clr32(rge_t *rgep, uintptr_t regno, uint32_t bits) 98 { 99 uint32_t regval; 100 101 RGE_TRACE(("rge_reg_clr32($%p, 0x%lx, 0x%x)", 102 (void *)rgep, regno, bits)); 103 104 regval = rge_reg_get32(rgep, regno); 105 regval &= ~bits; 106 rge_reg_put32(rgep, regno, regval); 107 } 108 109 static uint16_t rge_reg_get16(rge_t *rgep, uintptr_t regno); 110 #pragma inline(rge_reg_get16) 111 112 static uint16_t 113 rge_reg_get16(rge_t *rgep, uintptr_t regno) 114 { 115 RGE_TRACE(("rge_reg_get16($%p, 0x%lx)", 116 (void *)rgep, regno)); 117 118 return (ddi_get16(rgep->io_handle, REG16(rgep, regno))); 119 } 120 121 static void rge_reg_put16(rge_t *rgep, uintptr_t regno, uint16_t data); 122 #pragma inline(rge_reg_put16) 123 124 static void 125 rge_reg_put16(rge_t *rgep, uintptr_t regno, uint16_t data) 126 { 127 RGE_TRACE(("rge_reg_put16($%p, 0x%lx, 0x%x)", 128 (void *)rgep, regno, data)); 129 130 ddi_put16(rgep->io_handle, REG16(rgep, regno), data); 131 } 132 133 static uint8_t rge_reg_get8(rge_t *rgep, uintptr_t regno); 134 #pragma inline(rge_reg_get8) 135 136 static uint8_t 137 rge_reg_get8(rge_t *rgep, uintptr_t regno) 138 { 139 RGE_TRACE(("rge_reg_get8($%p, 0x%lx)", 140 (void *)rgep, regno)); 141 142 return (ddi_get8(rgep->io_handle, REG8(rgep, regno))); 143 } 144 145 static void rge_reg_put8(rge_t *rgep, uintptr_t regno, uint8_t data); 146 #pragma inline(rge_reg_put8) 147 148 static void 149 rge_reg_put8(rge_t *rgep, uintptr_t regno, uint8_t data) 150 { 151 RGE_TRACE(("rge_reg_put8($%p, 0x%lx, 0x%x)", 152 (void *)rgep, regno, data)); 153 154 ddi_put8(rgep->io_handle, REG8(rgep, regno), data); 155 } 156 157 static void rge_reg_set8(rge_t *rgep, uintptr_t regno, uint8_t bits); 158 #pragma inline(rge_reg_set8) 159 160 static void 161 rge_reg_set8(rge_t *rgep, uintptr_t regno, uint8_t bits) 162 { 163 uint8_t regval; 164 165 RGE_TRACE(("rge_reg_set8($%p, 0x%lx, 0x%x)", 166 (void *)rgep, regno, bits)); 167 168 regval = rge_reg_get8(rgep, regno); 169 regval |= bits; 170 rge_reg_put8(rgep, regno, regval); 171 } 172 173 static void rge_reg_clr8(rge_t *rgep, uintptr_t regno, uint8_t bits); 174 #pragma inline(rge_reg_clr8) 175 176 static void 177 rge_reg_clr8(rge_t *rgep, uintptr_t regno, uint8_t bits) 178 { 179 uint8_t regval; 180 181 RGE_TRACE(("rge_reg_clr8($%p, 0x%lx, 0x%x)", 182 (void *)rgep, regno, bits)); 183 184 regval = rge_reg_get8(rgep, regno); 185 regval &= ~bits; 186 rge_reg_put8(rgep, regno, regval); 187 } 188 189 uint16_t rge_mii_get16(rge_t *rgep, uintptr_t mii); 190 #pragma no_inline(rge_mii_get16) 191 192 uint16_t 193 rge_mii_get16(rge_t *rgep, uintptr_t mii) 194 { 195 uint32_t regval; 196 uint32_t val32; 197 uint32_t i; 198 199 regval = (mii & PHY_REG_MASK) << PHY_REG_SHIFT; 200 rge_reg_put32(rgep, PHY_ACCESS_REG, regval); 201 202 /* 203 * Waiting for PHY reading OK 204 */ 205 for (i = 0; i < PHY_RESET_LOOP; i++) { 206 drv_usecwait(1000); 207 val32 = rge_reg_get32(rgep, PHY_ACCESS_REG); 208 if (val32 & PHY_ACCESS_WR_FLAG) 209 return ((uint16_t)(val32 & 0xffff)); 210 } 211 212 RGE_REPORT((rgep, "rge_mii_get16(0x%x) fail, val = %x", mii, val32)); 213 return ((uint16_t)~0u); 214 } 215 216 void rge_mii_put16(rge_t *rgep, uintptr_t mii, uint16_t data); 217 #pragma no_inline(rge_mii_put16) 218 219 void 220 rge_mii_put16(rge_t *rgep, uintptr_t mii, uint16_t data) 221 { 222 uint32_t regval; 223 uint32_t val32; 224 uint32_t i; 225 226 regval = (mii & PHY_REG_MASK) << PHY_REG_SHIFT; 227 regval |= data & PHY_DATA_MASK; 228 regval |= PHY_ACCESS_WR_FLAG; 229 rge_reg_put32(rgep, PHY_ACCESS_REG, regval); 230 231 /* 232 * Waiting for PHY writing OK 233 */ 234 for (i = 0; i < PHY_RESET_LOOP; i++) { 235 drv_usecwait(1000); 236 val32 = rge_reg_get32(rgep, PHY_ACCESS_REG); 237 if (!(val32 & PHY_ACCESS_WR_FLAG)) 238 return; 239 } 240 RGE_REPORT((rgep, "rge_mii_put16(0x%lx, 0x%x) fail", 241 mii, data)); 242 } 243 244 void rge_ephy_put16(rge_t *rgep, uintptr_t emii, uint16_t data); 245 #pragma no_inline(rge_ephy_put16) 246 247 void 248 rge_ephy_put16(rge_t *rgep, uintptr_t emii, uint16_t data) 249 { 250 uint32_t regval; 251 uint32_t val32; 252 uint32_t i; 253 254 regval = (emii & EPHY_REG_MASK) << EPHY_REG_SHIFT; 255 regval |= data & EPHY_DATA_MASK; 256 regval |= EPHY_ACCESS_WR_FLAG; 257 rge_reg_put32(rgep, EPHY_ACCESS_REG, regval); 258 259 /* 260 * Waiting for PHY writing OK 261 */ 262 for (i = 0; i < PHY_RESET_LOOP; i++) { 263 drv_usecwait(1000); 264 val32 = rge_reg_get32(rgep, EPHY_ACCESS_REG); 265 if (!(val32 & EPHY_ACCESS_WR_FLAG)) 266 return; 267 } 268 RGE_REPORT((rgep, "rge_ephy_put16(0x%lx, 0x%x) fail", 269 emii, data)); 270 } 271 272 /* 273 * Atomically shift a 32-bit word left, returning 274 * the value it had *before* the shift was applied 275 */ 276 static uint32_t rge_atomic_shl32(uint32_t *sp, uint_t count); 277 #pragma inline(rge_mii_put16) 278 279 static uint32_t 280 rge_atomic_shl32(uint32_t *sp, uint_t count) 281 { 282 uint32_t oldval; 283 uint32_t newval; 284 285 /* ATOMICALLY */ 286 do { 287 oldval = *sp; 288 newval = oldval << count; 289 } while (cas32(sp, oldval, newval) != oldval); 290 291 return (oldval); 292 } 293 294 /* 295 * PHY operation routines 296 */ 297 #if RGE_DEBUGGING 298 299 void 300 rge_phydump(rge_t *rgep) 301 { 302 uint16_t regs[32]; 303 int i; 304 305 ASSERT(mutex_owned(rgep->genlock)); 306 307 for (i = 0; i < 32; ++i) { 308 regs[i] = rge_mii_get16(rgep, i); 309 } 310 311 for (i = 0; i < 32; i += 8) 312 RGE_DEBUG(("rge_phydump: " 313 "0x%04x %04x %04x %04x %04x %04x %04x %04x", 314 regs[i+0], regs[i+1], regs[i+2], regs[i+3], 315 regs[i+4], regs[i+5], regs[i+6], regs[i+7])); 316 } 317 318 #endif /* RGE_DEBUGGING */ 319 320 static void 321 rge_phy_check(rge_t *rgep) 322 { 323 uint16_t gig_ctl; 324 325 if (rgep->param_link_up == LINK_STATE_DOWN) { 326 /* 327 * RTL8169S/8110S PHY has the "PCS bug". Need reset PHY 328 * every 15 seconds whin link down & advertise is 1000. 329 */ 330 if (rgep->chipid.phy_ver == PHY_VER_S) { 331 gig_ctl = rge_mii_get16(rgep, MII_1000BASE_T_CONTROL); 332 if (gig_ctl & MII_1000BT_CTL_ADV_FDX) { 333 rgep->link_down_count++; 334 if (rgep->link_down_count > 15) { 335 (void) rge_phy_reset(rgep); 336 rgep->stats.phy_reset++; 337 rgep->link_down_count = 0; 338 } 339 } 340 } 341 } else { 342 rgep->link_down_count = 0; 343 } 344 } 345 346 /* 347 * Basic low-level function to reset the PHY. 348 * Doesn't incorporate any special-case workarounds. 349 * 350 * Returns TRUE on success, FALSE if the RESET bit doesn't clear 351 */ 352 boolean_t 353 rge_phy_reset(rge_t *rgep) 354 { 355 uint16_t control; 356 uint_t count; 357 358 /* 359 * Set the PHY RESET bit, then wait up to 5 ms for it to self-clear 360 */ 361 control = rge_mii_get16(rgep, MII_CONTROL); 362 rge_mii_put16(rgep, MII_CONTROL, control | MII_CONTROL_RESET); 363 for (count = 0; count < 5; count++) { 364 drv_usecwait(100); 365 control = rge_mii_get16(rgep, MII_CONTROL); 366 if (BIC(control, MII_CONTROL_RESET)) 367 return (B_TRUE); 368 } 369 370 RGE_REPORT((rgep, "rge_phy_reset: FAILED, control now 0x%x", control)); 371 return (B_FALSE); 372 } 373 374 /* 375 * Synchronise the PHY's speed/duplex/autonegotiation capabilities 376 * and advertisements with the required settings as specified by the various 377 * param_* variables that can be poked via the NDD interface. 378 * 379 * We always reset the PHY and reprogram *all* the relevant registers, 380 * not just those changed. This should cause the link to go down, and then 381 * back up again once the link is stable and autonegotiation (if enabled) 382 * is complete. We should get a link state change interrupt somewhere along 383 * the way ... 384 * 385 * NOTE: <genlock> must already be held by the caller 386 */ 387 void 388 rge_phy_update(rge_t *rgep) 389 { 390 boolean_t adv_autoneg; 391 boolean_t adv_pause; 392 boolean_t adv_asym_pause; 393 boolean_t adv_1000fdx; 394 boolean_t adv_1000hdx; 395 boolean_t adv_100fdx; 396 boolean_t adv_100hdx; 397 boolean_t adv_10fdx; 398 boolean_t adv_10hdx; 399 400 uint16_t control; 401 uint16_t gigctrl; 402 uint16_t anar; 403 404 ASSERT(mutex_owned(rgep->genlock)); 405 406 RGE_DEBUG(("rge_phy_update: autoneg %d " 407 "pause %d asym_pause %d " 408 "1000fdx %d 1000hdx %d " 409 "100fdx %d 100hdx %d " 410 "10fdx %d 10hdx %d ", 411 rgep->param_adv_autoneg, 412 rgep->param_adv_pause, rgep->param_adv_asym_pause, 413 rgep->param_adv_1000fdx, rgep->param_adv_1000hdx, 414 rgep->param_adv_100fdx, rgep->param_adv_100hdx, 415 rgep->param_adv_10fdx, rgep->param_adv_10hdx)); 416 417 control = gigctrl = anar = 0; 418 419 /* 420 * PHY settings are normally based on the param_* variables, 421 * but if any loopback mode is in effect, that takes precedence. 422 * 423 * RGE supports MAC-internal loopback, PHY-internal loopback, 424 * and External loopback at a variety of speeds (with a special 425 * cable). In all cases, autoneg is turned OFF, full-duplex 426 * is turned ON, and the speed/mastership is forced. 427 */ 428 switch (rgep->param_loop_mode) { 429 case RGE_LOOP_NONE: 430 default: 431 adv_autoneg = rgep->param_adv_autoneg; 432 adv_pause = rgep->param_adv_pause; 433 adv_asym_pause = rgep->param_adv_asym_pause; 434 adv_1000fdx = rgep->param_adv_1000fdx; 435 adv_1000hdx = rgep->param_adv_1000hdx; 436 adv_100fdx = rgep->param_adv_100fdx; 437 adv_100hdx = rgep->param_adv_100hdx; 438 adv_10fdx = rgep->param_adv_10fdx; 439 adv_10hdx = rgep->param_adv_10hdx; 440 break; 441 442 case RGE_LOOP_INTERNAL_PHY: 443 case RGE_LOOP_INTERNAL_MAC: 444 adv_autoneg = adv_pause = adv_asym_pause = B_FALSE; 445 adv_1000fdx = adv_100fdx = adv_10fdx = B_FALSE; 446 adv_1000hdx = adv_100hdx = adv_10hdx = B_FALSE; 447 rgep->param_link_duplex = LINK_DUPLEX_FULL; 448 449 switch (rgep->param_loop_mode) { 450 case RGE_LOOP_INTERNAL_PHY: 451 if (rgep->chipid.mac_ver != MAC_VER_8101E) { 452 rgep->param_link_speed = 1000; 453 adv_1000fdx = B_TRUE; 454 } else { 455 rgep->param_link_speed = 100; 456 adv_100fdx = B_TRUE; 457 } 458 control = MII_CONTROL_LOOPBACK; 459 break; 460 461 case RGE_LOOP_INTERNAL_MAC: 462 if (rgep->chipid.mac_ver != MAC_VER_8101E) { 463 rgep->param_link_speed = 1000; 464 adv_1000fdx = B_TRUE; 465 } else { 466 rgep->param_link_speed = 100; 467 adv_100fdx = B_TRUE; 468 break; 469 } 470 } 471 472 RGE_DEBUG(("rge_phy_update: autoneg %d " 473 "pause %d asym_pause %d " 474 "1000fdx %d 1000hdx %d " 475 "100fdx %d 100hdx %d " 476 "10fdx %d 10hdx %d ", 477 adv_autoneg, 478 adv_pause, adv_asym_pause, 479 adv_1000fdx, adv_1000hdx, 480 adv_100fdx, adv_100hdx, 481 adv_10fdx, adv_10hdx)); 482 483 /* 484 * We should have at least one technology capability set; 485 * if not, we select a default of 1000Mb/s full-duplex 486 */ 487 if (!adv_1000fdx && !adv_100fdx && !adv_10fdx && 488 !adv_1000hdx && !adv_100hdx && !adv_10hdx) { 489 if (rgep->chipid.mac_ver != MAC_VER_8101E) 490 adv_1000fdx = B_TRUE; 491 } else { 492 adv_1000fdx = B_FALSE; 493 adv_100fdx = B_TRUE; 494 } 495 } 496 497 /* 498 * Now transform the adv_* variables into the proper settings 499 * of the PHY registers ... 500 * 501 * If autonegotiation is (now) enabled, we want to trigger 502 * a new autonegotiation cycle once the PHY has been 503 * programmed with the capabilities to be advertised. 504 * 505 * RTL8169/8110 doesn't support 1000Mb/s half-duplex. 506 */ 507 if (adv_autoneg) 508 control |= MII_CONTROL_ANE|MII_CONTROL_RSAN; 509 510 if (adv_1000fdx) 511 control |= MII_CONTROL_1000MB|MII_CONTROL_FDUPLEX; 512 else if (adv_1000hdx) 513 control |= MII_CONTROL_1000MB; 514 else if (adv_100fdx) 515 control |= MII_CONTROL_100MB|MII_CONTROL_FDUPLEX; 516 else if (adv_100hdx) 517 control |= MII_CONTROL_100MB; 518 else if (adv_10fdx) 519 control |= MII_CONTROL_FDUPLEX; 520 else if (adv_10hdx) 521 control |= 0; 522 else 523 { _NOTE(EMPTY); } /* Can't get here anyway ... */ 524 525 if (adv_1000fdx) { 526 gigctrl |= MII_1000BT_CTL_ADV_FDX; 527 /* 528 * Chipset limitation: need set other capabilities to true 529 */ 530 if (rgep->chipid.is_pcie) 531 adv_1000hdx = B_TRUE; 532 adv_100fdx = B_TRUE; 533 adv_100hdx = B_TRUE; 534 adv_10fdx = B_TRUE; 535 adv_10hdx = B_TRUE; 536 } 537 538 if (adv_1000hdx) 539 gigctrl |= MII_1000BT_CTL_ADV_HDX; 540 541 if (adv_100fdx) 542 anar |= MII_ABILITY_100BASE_TX_FD; 543 if (adv_100hdx) 544 anar |= MII_ABILITY_100BASE_TX; 545 if (adv_10fdx) 546 anar |= MII_ABILITY_10BASE_T_FD; 547 if (adv_10hdx) 548 anar |= MII_ABILITY_10BASE_T; 549 550 if (adv_pause) 551 anar |= MII_ABILITY_PAUSE; 552 if (adv_asym_pause) 553 anar |= MII_ABILITY_ASYM_PAUSE; 554 555 /* 556 * Munge in any other fixed bits we require ... 557 */ 558 anar |= MII_AN_SELECTOR_8023; 559 560 /* 561 * Restart the PHY and write the new values. Note the 562 * time, so that we can say whether subsequent link state 563 * changes can be attributed to our reprogramming the PHY 564 */ 565 rge_phy_init(rgep); 566 rge_mii_put16(rgep, MII_AN_ADVERT, anar); 567 rge_mii_put16(rgep, MII_1000BASE_T_CONTROL, gigctrl); 568 rge_mii_put16(rgep, MII_CONTROL, control); 569 570 RGE_DEBUG(("rge_phy_update: anar <- 0x%x", anar)); 571 RGE_DEBUG(("rge_phy_update: control <- 0x%x", control)); 572 RGE_DEBUG(("rge_phy_update: gigctrl <- 0x%x", gigctrl)); 573 } 574 575 void rge_phy_init(rge_t *rgep); 576 #pragma no_inline(rge_phy_init) 577 578 void 579 rge_phy_init(rge_t *rgep) 580 { 581 rgep->phy_mii_addr = 1; 582 583 /* 584 * Below phy config steps are copied from the Programming Guide 585 * (there's no detail comments for these steps.) 586 */ 587 switch (rgep->chipid.mac_ver) { 588 case MAC_VER_8169S_D: 589 case MAC_VER_8169S_E : 590 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 591 rge_mii_put16(rgep, PHY_15_REG, 0x1000); 592 rge_mii_put16(rgep, PHY_18_REG, 0x65c7); 593 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000); 594 rge_mii_put16(rgep, PHY_ID_REG_2, 0x00a1); 595 rge_mii_put16(rgep, PHY_ID_REG_1, 0x0008); 596 rge_mii_put16(rgep, PHY_BMSR_REG, 0x1020); 597 rge_mii_put16(rgep, PHY_BMCR_REG, 0x1000); 598 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0800); 599 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000); 600 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7000); 601 rge_mii_put16(rgep, PHY_ID_REG_2, 0xff41); 602 rge_mii_put16(rgep, PHY_ID_REG_1, 0xde60); 603 rge_mii_put16(rgep, PHY_BMSR_REG, 0x0140); 604 rge_mii_put16(rgep, PHY_BMCR_REG, 0x0077); 605 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7800); 606 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7000); 607 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa000); 608 rge_mii_put16(rgep, PHY_ID_REG_2, 0xdf01); 609 rge_mii_put16(rgep, PHY_ID_REG_1, 0xdf20); 610 rge_mii_put16(rgep, PHY_BMSR_REG, 0xff95); 611 rge_mii_put16(rgep, PHY_BMCR_REG, 0xfa00); 612 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa800); 613 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa000); 614 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb000); 615 rge_mii_put16(rgep, PHY_ID_REG_2, 0xff41); 616 rge_mii_put16(rgep, PHY_ID_REG_1, 0xde20); 617 rge_mii_put16(rgep, PHY_BMSR_REG, 0x0140); 618 rge_mii_put16(rgep, PHY_BMCR_REG, 0x00bb); 619 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb800); 620 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb000); 621 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf000); 622 rge_mii_put16(rgep, PHY_ID_REG_2, 0xdf01); 623 rge_mii_put16(rgep, PHY_ID_REG_1, 0xdf20); 624 rge_mii_put16(rgep, PHY_BMSR_REG, 0xff95); 625 rge_mii_put16(rgep, PHY_BMCR_REG, 0xbf00); 626 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf800); 627 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf000); 628 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000); 629 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 630 rge_mii_put16(rgep, PHY_0B_REG, 0x0000); 631 break; 632 633 case MAC_VER_8169SB: 634 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 635 rge_mii_put16(rgep, PHY_1B_REG, 0xD41E); 636 rge_mii_put16(rgep, PHY_0E_REG, 0x7bff); 637 rge_mii_put16(rgep, PHY_GBCR_REG, GBCR_DEFAULT); 638 rge_mii_put16(rgep, PHY_1F_REG, 0x0002); 639 rge_mii_put16(rgep, PHY_BMSR_REG, 0x90D0); 640 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 641 break; 642 643 case MAC_VER_8169SC: 644 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 645 rge_mii_put16(rgep, PHY_ANER_REG, 0x0078); 646 rge_mii_put16(rgep, PHY_ANNPRR_REG, 0x05dc); 647 rge_mii_put16(rgep, PHY_GBCR_REG, 0x2672); 648 rge_mii_put16(rgep, PHY_GBSR_REG, 0x6a14); 649 rge_mii_put16(rgep, PHY_0B_REG, 0x7cb0); 650 rge_mii_put16(rgep, PHY_0C_REG, 0xdb80); 651 rge_mii_put16(rgep, PHY_1B_REG, 0xc414); 652 rge_mii_put16(rgep, PHY_1C_REG, 0xef03); 653 rge_mii_put16(rgep, PHY_1D_REG, 0x3dc8); 654 rge_mii_put16(rgep, PHY_1F_REG, 0x0003); 655 rge_mii_put16(rgep, PHY_13_REG, 0x0600); 656 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 657 break; 658 659 case MAC_VER_8168: 660 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 661 rge_mii_put16(rgep, PHY_ANER_REG, 0x00aa); 662 rge_mii_put16(rgep, PHY_ANNPTR_REG, 0x3173); 663 rge_mii_put16(rgep, PHY_ANNPRR_REG, 0x08fc); 664 rge_mii_put16(rgep, PHY_GBCR_REG, 0xe2d0); 665 rge_mii_put16(rgep, PHY_0B_REG, 0x941a); 666 rge_mii_put16(rgep, PHY_18_REG, 0x65fe); 667 rge_mii_put16(rgep, PHY_1C_REG, 0x1e02); 668 rge_mii_put16(rgep, PHY_1F_REG, 0x0002); 669 rge_mii_put16(rgep, PHY_ANNPTR_REG, 0x103e); 670 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 671 break; 672 673 case MAC_VER_8168B_B: 674 case MAC_VER_8168B_C: 675 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 676 rge_mii_put16(rgep, PHY_0B_REG, 0x94b0); 677 rge_mii_put16(rgep, PHY_1B_REG, 0xc416); 678 rge_mii_put16(rgep, PHY_1F_REG, 0x0003); 679 rge_mii_put16(rgep, PHY_12_REG, 0x6096); 680 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 681 break; 682 } 683 } 684 685 void rge_chip_ident(rge_t *rgep); 686 #pragma no_inline(rge_chip_ident) 687 688 void 689 rge_chip_ident(rge_t *rgep) 690 { 691 chip_id_t *chip = &rgep->chipid; 692 uint32_t val32; 693 uint16_t val16; 694 695 /* 696 * Read and record MAC version 697 */ 698 val32 = rge_reg_get32(rgep, TX_CONFIG_REG); 699 val32 &= HW_VERSION_ID_0 | HW_VERSION_ID_1; 700 chip->mac_ver = val32; 701 switch (chip->mac_ver) { 702 case MAC_VER_8168: 703 case MAC_VER_8168B_B: 704 case MAC_VER_8168B_C: 705 case MAC_VER_8101E: 706 chip->is_pcie = B_TRUE; 707 break; 708 709 default: 710 chip->is_pcie = B_FALSE; 711 break; 712 } 713 714 /* 715 * Read and record PHY version 716 */ 717 val16 = rge_mii_get16(rgep, PHY_ID_REG_2); 718 val16 &= PHY_VER_MASK; 719 chip->phy_ver = val16; 720 721 /* set pci latency timer */ 722 if (chip->mac_ver == MAC_VER_8169 || 723 chip->mac_ver == MAC_VER_8169S_D || 724 chip->mac_ver == MAC_VER_8169SC) 725 pci_config_put8(rgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 0x40); 726 727 if (chip->mac_ver == MAC_VER_8169SC) { 728 val16 = rge_reg_get16(rgep, RT_CONFIG_1_REG); 729 val16 &= 0x0300; 730 if (val16 == 0x1) /* 66Mhz PCI */ 731 pci_config_put32(rgep->cfg_handle, 0x7c, 0x00ff00ff); 732 else if (val16 == 0x0) /* 33Mhz PCI */ 733 pci_config_put32(rgep->cfg_handle, 0x7c, 0x00ffff00); 734 } 735 736 /* 737 * PCIE chipset require the Rx buffer start address must be 738 * 8-byte alignment and the Rx buffer size must be multiple of 8. 739 * We'll just use bcopy in receive procedure for the PCIE chipset. 740 */ 741 if (chip->is_pcie) { 742 rgep->chip_flags |= CHIP_FLAG_FORCE_BCOPY; 743 if (rgep->default_mtu > ETHERMTU) { 744 rge_notice(rgep, "Jumbo packets not supported " 745 "for this PCIE chipset"); 746 rgep->default_mtu = ETHERMTU; 747 } 748 } 749 if (rgep->chip_flags & CHIP_FLAG_FORCE_BCOPY) 750 rgep->head_room = 0; 751 else 752 rgep->head_room = RGE_HEADROOM; 753 754 /* 755 * Initialize other variables. 756 */ 757 if (rgep->default_mtu < ETHERMTU || rgep->default_mtu > RGE_JUMBO_MTU) 758 rgep->default_mtu = ETHERMTU; 759 if (rgep->default_mtu > ETHERMTU) { 760 rgep->rxbuf_size = RGE_BUFF_SIZE_JUMBO; 761 rgep->txbuf_size = RGE_BUFF_SIZE_JUMBO; 762 rgep->ethmax_size = RGE_JUMBO_SIZE; 763 } else { 764 rgep->rxbuf_size = RGE_BUFF_SIZE_STD; 765 rgep->txbuf_size = RGE_BUFF_SIZE_STD; 766 rgep->ethmax_size = ETHERMAX; 767 } 768 chip->rxconfig = RX_CONFIG_DEFAULT; 769 chip->txconfig = TX_CONFIG_DEFAULT; 770 771 RGE_TRACE(("%s: MAC version = %x, PHY version = %x", 772 rgep->ifname, chip->mac_ver, chip->phy_ver)); 773 } 774 775 /* 776 * Perform first-stage chip (re-)initialisation, using only config-space 777 * accesses: 778 * 779 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 780 * returning the data in the structure pointed to by <idp>. 781 * + Enable Memory Space accesses. 782 * + Enable Bus Mastering according. 783 */ 784 void rge_chip_cfg_init(rge_t *rgep, chip_id_t *cidp); 785 #pragma no_inline(rge_chip_cfg_init) 786 787 void 788 rge_chip_cfg_init(rge_t *rgep, chip_id_t *cidp) 789 { 790 ddi_acc_handle_t handle; 791 uint16_t commd; 792 793 handle = rgep->cfg_handle; 794 795 /* 796 * Save PCI cache line size and subsystem vendor ID 797 */ 798 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 799 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 800 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 801 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 802 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 803 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 804 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 805 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 806 807 /* 808 * Turn on Master Enable (DMA) and IO Enable bits. 809 * Enable PCI Memory Space accesses 810 */ 811 commd = cidp->command; 812 commd |= PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO; 813 pci_config_put16(handle, PCI_CONF_COMM, commd); 814 815 RGE_DEBUG(("rge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 816 cidp->vendor, cidp->device, cidp->revision)); 817 RGE_DEBUG(("rge_chip_cfg_init: subven 0x%x subdev 0x%x", 818 cidp->subven, cidp->subdev)); 819 RGE_DEBUG(("rge_chip_cfg_init: clsize %d latency %d command 0x%x", 820 cidp->clsize, cidp->latency, cidp->command)); 821 } 822 823 int rge_chip_reset(rge_t *rgep); 824 #pragma no_inline(rge_chip_reset) 825 826 int 827 rge_chip_reset(rge_t *rgep) 828 { 829 int i; 830 uint8_t val8; 831 832 /* 833 * Chip should be in STOP state 834 */ 835 rge_reg_clr8(rgep, RT_COMMAND_REG, 836 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 837 838 /* 839 * Disable interrupt 840 */ 841 rgep->int_mask = INT_MASK_NONE; 842 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 843 844 /* 845 * Clear pended interrupt 846 */ 847 rge_reg_put16(rgep, INT_STATUS_REG, INT_MASK_ALL); 848 849 /* 850 * Reset chip 851 */ 852 rge_reg_set8(rgep, RT_COMMAND_REG, RT_COMMAND_RESET); 853 854 /* 855 * Wait for reset success 856 */ 857 for (i = 0; i < CHIP_RESET_LOOP; i++) { 858 drv_usecwait(10); 859 val8 = rge_reg_get8(rgep, RT_COMMAND_REG); 860 if (!(val8 & RT_COMMAND_RESET)) { 861 rgep->rge_chip_state = RGE_CHIP_RESET; 862 return (0); 863 } 864 } 865 RGE_REPORT((rgep, "rge_chip_reset fail.")); 866 return (-1); 867 } 868 869 void rge_chip_init(rge_t *rgep); 870 #pragma no_inline(rge_chip_init) 871 872 void 873 rge_chip_init(rge_t *rgep) 874 { 875 uint32_t val32; 876 uint32_t val16; 877 uint32_t *hashp; 878 chip_id_t *chip = &rgep->chipid; 879 880 if (chip->is_pcie) { 881 /* 882 * Increase the threshold voltage of RX sensitivity 883 */ 884 if (chip->mac_ver != MAC_VER_8168) 885 rge_ephy_put16(rgep, 0x01, 0x1bd3); 886 887 val16 = rge_reg_get8(rgep, PHY_STATUS_REG); 888 val16 = 0x12<<8 | val16; 889 if (rgep->chipid.mac_ver != MAC_VER_8101E && 890 rgep->chipid.mac_ver != MAC_VER_8168B_C) { 891 rge_reg_put16(rgep, PHY_STATUS_REG, val16); 892 rge_reg_put32(rgep, RT_CSI_DATA_REG, 0x00021c01); 893 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f088); 894 rge_reg_put32(rgep, RT_CSI_DATA_REG, 0x00004000); 895 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f0b0); 896 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x0000f068); 897 val32 = rge_reg_get32(rgep, RT_CSI_DATA_REG); 898 val32 |= 0x7000; 899 val32 &= 0xffff5fff; 900 rge_reg_put32(rgep, RT_CSI_DATA_REG, val32); 901 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f068); 902 } 903 } 904 905 /* 906 * Config MII register 907 */ 908 rgep->param_link_up = LINK_STATE_DOWN; 909 rge_phy_update(rgep); 910 911 /* 912 * Enable Rx checksum offload. 913 * Then for vlan support, we must enable receive vlan de-tagging. 914 * Otherwise, there'll be checksum error. 915 */ 916 val16 = rge_reg_get16(rgep, CPLUS_COMMAND_REG); 917 val16 |= RX_CKSM_OFFLOAD | RX_VLAN_DETAG; 918 if (chip->mac_ver == MAC_VER_8169S_D) { 919 val16 |= CPLUS_BIT14 | MUL_PCI_RW_ENABLE; 920 rge_reg_put8(rgep, RESV_82_REG, 0x01); 921 } 922 rge_reg_put16(rgep, CPLUS_COMMAND_REG, val16 & (~0x03)); 923 924 /* 925 * Start transmit/receive before set tx/rx configuration register 926 */ 927 if (!chip->is_pcie) 928 rge_reg_set8(rgep, RT_COMMAND_REG, 929 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 930 931 /* 932 * Set dump tally counter register 933 */ 934 val32 = rgep->dma_area_stats.cookie.dmac_laddress >> 32; 935 rge_reg_put32(rgep, DUMP_COUNTER_REG_1, val32); 936 val32 = rge_reg_get32(rgep, DUMP_COUNTER_REG_0); 937 val32 &= DUMP_COUNTER_REG_RESV; 938 val32 |= rgep->dma_area_stats.cookie.dmac_laddress; 939 rge_reg_put32(rgep, DUMP_COUNTER_REG_0, val32); 940 941 /* 942 * Change to config register write enable mode 943 */ 944 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 945 946 /* 947 * Set Tx/Rx maximum packet size 948 */ 949 if (rgep->default_mtu > ETHERMTU) { 950 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_JUMBO); 951 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_JUMBO); 952 } else if (rgep->chipid.mac_ver != MAC_VER_8101E) { 953 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_STD); 954 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_STD); 955 } else { 956 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_STD_8101E); 957 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_STD_8101E); 958 } 959 960 /* 961 * Set receive configuration register 962 */ 963 val32 = rge_reg_get32(rgep, RX_CONFIG_REG); 964 val32 &= RX_CONFIG_REG_RESV; 965 if (rgep->promisc) 966 val32 |= RX_ACCEPT_ALL_PKT; 967 rge_reg_put32(rgep, RX_CONFIG_REG, val32 | chip->rxconfig); 968 969 /* 970 * Set transmit configuration register 971 */ 972 val32 = rge_reg_get32(rgep, TX_CONFIG_REG); 973 val32 &= TX_CONFIG_REG_RESV; 974 rge_reg_put32(rgep, TX_CONFIG_REG, val32 | chip->txconfig); 975 976 /* 977 * Set Tx/Rx descriptor register 978 */ 979 val32 = rgep->tx_desc.cookie.dmac_laddress; 980 rge_reg_put32(rgep, NORMAL_TX_RING_ADDR_LO_REG, val32); 981 val32 = rgep->tx_desc.cookie.dmac_laddress >> 32; 982 rge_reg_put32(rgep, NORMAL_TX_RING_ADDR_HI_REG, val32); 983 rge_reg_put32(rgep, HIGH_TX_RING_ADDR_LO_REG, 0); 984 rge_reg_put32(rgep, HIGH_TX_RING_ADDR_HI_REG, 0); 985 val32 = rgep->rx_desc.cookie.dmac_laddress; 986 rge_reg_put32(rgep, RX_RING_ADDR_LO_REG, val32); 987 val32 = rgep->rx_desc.cookie.dmac_laddress >> 32; 988 rge_reg_put32(rgep, RX_RING_ADDR_HI_REG, val32); 989 990 /* 991 * Suggested setting from Realtek 992 */ 993 if (rgep->chipid.mac_ver != MAC_VER_8101E) 994 rge_reg_put16(rgep, RESV_E2_REG, 0x282a); 995 else 996 rge_reg_put16(rgep, RESV_E2_REG, 0x0000); 997 998 /* 999 * Set multicast register 1000 */ 1001 hashp = (uint32_t *)rgep->mcast_hash; 1002 rge_reg_put32(rgep, MULTICAST_0_REG, hashp[0]); 1003 rge_reg_put32(rgep, MULTICAST_4_REG, hashp[1]); 1004 1005 /* 1006 * Msic register setting: 1007 * -- Missed packet counter: clear it 1008 * -- TimerInt Register 1009 * -- Timer count register 1010 */ 1011 rge_reg_put32(rgep, RX_PKT_MISS_COUNT_REG, 0); 1012 rge_reg_put32(rgep, TIMER_INT_REG, TIMER_INT_NONE); 1013 rge_reg_put32(rgep, TIMER_COUNT_REG, 0); 1014 1015 /* 1016 * Return to normal network/host communication mode 1017 */ 1018 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1019 drv_usecwait(20); 1020 } 1021 1022 /* 1023 * rge_chip_start() -- start the chip transmitting and/or receiving, 1024 * including enabling interrupts 1025 */ 1026 void rge_chip_start(rge_t *rgep); 1027 #pragma no_inline(rge_chip_start) 1028 1029 void 1030 rge_chip_start(rge_t *rgep) 1031 { 1032 /* 1033 * Clear statistics 1034 */ 1035 bzero(&rgep->stats, sizeof (rge_stats_t)); 1036 DMA_ZERO(rgep->dma_area_stats); 1037 1038 /* 1039 * Start transmit/receive 1040 */ 1041 rge_reg_set8(rgep, RT_COMMAND_REG, 1042 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1043 1044 /* 1045 * Enable interrupt 1046 */ 1047 rgep->int_mask = RGE_INT_MASK; 1048 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 1049 1050 /* 1051 * All done! 1052 */ 1053 rgep->rge_chip_state = RGE_CHIP_RUNNING; 1054 } 1055 1056 /* 1057 * rge_chip_stop() -- stop board receiving 1058 */ 1059 void rge_chip_stop(rge_t *rgep, boolean_t fault); 1060 #pragma no_inline(rge_chip_stop) 1061 1062 void 1063 rge_chip_stop(rge_t *rgep, boolean_t fault) 1064 { 1065 /* 1066 * Disable interrupt 1067 */ 1068 rgep->int_mask = INT_MASK_NONE; 1069 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 1070 1071 /* 1072 * Clear pended interrupt 1073 */ 1074 if (!rgep->suspended) { 1075 rge_reg_put16(rgep, INT_STATUS_REG, INT_MASK_ALL); 1076 } 1077 1078 /* 1079 * Stop the board and disable transmit/receive 1080 */ 1081 rge_reg_clr8(rgep, RT_COMMAND_REG, 1082 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1083 1084 if (fault) 1085 rgep->rge_chip_state = RGE_CHIP_FAULT; 1086 else 1087 rgep->rge_chip_state = RGE_CHIP_STOPPED; 1088 } 1089 1090 /* 1091 * rge_get_mac_addr() -- get the MAC address on NIC 1092 */ 1093 static void rge_get_mac_addr(rge_t *rgep); 1094 #pragma inline(rge_get_mac_addr) 1095 1096 static void 1097 rge_get_mac_addr(rge_t *rgep) 1098 { 1099 uint8_t *macaddr = rgep->netaddr; 1100 uint32_t val32; 1101 1102 /* 1103 * Read first 4-byte of mac address 1104 */ 1105 val32 = rge_reg_get32(rgep, ID_0_REG); 1106 macaddr[0] = val32 & 0xff; 1107 val32 = val32 >> 8; 1108 macaddr[1] = val32 & 0xff; 1109 val32 = val32 >> 8; 1110 macaddr[2] = val32 & 0xff; 1111 val32 = val32 >> 8; 1112 macaddr[3] = val32 & 0xff; 1113 1114 /* 1115 * Read last 2-byte of mac address 1116 */ 1117 val32 = rge_reg_get32(rgep, ID_4_REG); 1118 macaddr[4] = val32 & 0xff; 1119 val32 = val32 >> 8; 1120 macaddr[5] = val32 & 0xff; 1121 } 1122 1123 static void rge_set_mac_addr(rge_t *rgep); 1124 #pragma inline(rge_set_mac_addr) 1125 1126 static void 1127 rge_set_mac_addr(rge_t *rgep) 1128 { 1129 uint8_t *p = rgep->netaddr; 1130 uint32_t val32; 1131 1132 /* 1133 * Change to config register write enable mode 1134 */ 1135 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1136 1137 /* 1138 * Get first 4 bytes of mac address 1139 */ 1140 val32 = p[3]; 1141 val32 = val32 << 8; 1142 val32 |= p[2]; 1143 val32 = val32 << 8; 1144 val32 |= p[1]; 1145 val32 = val32 << 8; 1146 val32 |= p[0]; 1147 1148 /* 1149 * Set first 4 bytes of mac address 1150 */ 1151 rge_reg_put32(rgep, ID_0_REG, val32); 1152 1153 /* 1154 * Get last 2 bytes of mac address 1155 */ 1156 val32 = p[5]; 1157 val32 = val32 << 8; 1158 val32 |= p[4]; 1159 1160 /* 1161 * Set last 2 bytes of mac address 1162 */ 1163 val32 |= rge_reg_get32(rgep, ID_4_REG) & ~0xffff; 1164 rge_reg_put32(rgep, ID_4_REG, val32); 1165 1166 /* 1167 * Return to normal network/host communication mode 1168 */ 1169 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1170 } 1171 1172 static void rge_set_multi_addr(rge_t *rgep); 1173 #pragma inline(rge_set_multi_addr) 1174 1175 static void 1176 rge_set_multi_addr(rge_t *rgep) 1177 { 1178 uint32_t *hashp; 1179 1180 hashp = (uint32_t *)rgep->mcast_hash; 1181 1182 /* 1183 * Change to config register write enable mode 1184 */ 1185 if (rgep->chipid.mac_ver == MAC_VER_8169SC) 1186 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1187 1188 rge_reg_put32(rgep, MULTICAST_0_REG, RGE_BSWAP_32(hashp[0])); 1189 rge_reg_put32(rgep, MULTICAST_4_REG, RGE_BSWAP_32(hashp[1])); 1190 1191 /* 1192 * Return to normal network/host communication mode 1193 */ 1194 if (rgep->chipid.mac_ver == MAC_VER_8169SC) 1195 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1196 } 1197 1198 static void rge_set_promisc(rge_t *rgep); 1199 #pragma inline(rge_set_promisc) 1200 1201 static void 1202 rge_set_promisc(rge_t *rgep) 1203 { 1204 if (rgep->promisc) 1205 rge_reg_set32(rgep, RX_CONFIG_REG, RX_ACCEPT_ALL_PKT); 1206 else 1207 rge_reg_clr32(rgep, RX_CONFIG_REG, RX_ACCEPT_ALL_PKT); 1208 } 1209 1210 /* 1211 * rge_chip_sync() -- program the chip with the unicast MAC address, 1212 * the multicast hash table, the required level of promiscuity, and 1213 * the current loopback mode ... 1214 */ 1215 void rge_chip_sync(rge_t *rgep, enum rge_sync_op todo); 1216 #pragma no_inline(rge_chip_sync) 1217 1218 void 1219 rge_chip_sync(rge_t *rgep, enum rge_sync_op todo) 1220 { 1221 switch (todo) { 1222 case RGE_GET_MAC: 1223 rge_get_mac_addr(rgep); 1224 break; 1225 case RGE_SET_MAC: 1226 /* Reprogram the unicast MAC address(es) ... */ 1227 rge_set_mac_addr(rgep); 1228 break; 1229 case RGE_SET_MUL: 1230 /* Reprogram the hashed multicast address table ... */ 1231 rge_set_multi_addr(rgep); 1232 break; 1233 case RGE_SET_PROMISC: 1234 /* Set or clear the PROMISCUOUS mode bit */ 1235 rge_set_promisc(rgep); 1236 break; 1237 default: 1238 break; 1239 } 1240 } 1241 1242 void rge_chip_blank(void *arg, time_t ticks, uint_t count); 1243 #pragma no_inline(rge_chip_blank) 1244 1245 void 1246 rge_chip_blank(void *arg, time_t ticks, uint_t count) 1247 { 1248 _NOTE(ARGUNUSED(arg, ticks, count)); 1249 } 1250 1251 void rge_tx_trigger(rge_t *rgep); 1252 #pragma no_inline(rge_tx_trigger) 1253 1254 void 1255 rge_tx_trigger(rge_t *rgep) 1256 { 1257 rge_reg_set8(rgep, TX_RINGS_POLL_REG, NORMAL_TX_RING_POLL); 1258 } 1259 1260 void rge_hw_stats_dump(rge_t *rgep); 1261 #pragma no_inline(rge_tx_trigger) 1262 1263 void 1264 rge_hw_stats_dump(rge_t *rgep) 1265 { 1266 int i = 0; 1267 1268 while (rge_reg_get32(rgep, DUMP_COUNTER_REG_0) & DUMP_START) { 1269 drv_usecwait(100); 1270 if (++i > STATS_DUMP_LOOP) { 1271 RGE_DEBUG(("rge h/w statistics dump fail!")); 1272 rgep->rge_chip_state = RGE_CHIP_ERROR; 1273 return; 1274 } 1275 } 1276 DMA_SYNC(rgep->dma_area_stats, DDI_DMA_SYNC_FORKERNEL); 1277 1278 /* 1279 * Start H/W statistics dump for RTL8169 chip 1280 */ 1281 rge_reg_set32(rgep, DUMP_COUNTER_REG_0, DUMP_START); 1282 } 1283 1284 /* 1285 * ========== Hardware interrupt handler ========== 1286 */ 1287 1288 #undef RGE_DBG 1289 #define RGE_DBG RGE_DBG_INT /* debug flag for this code */ 1290 1291 static void rge_wake_factotum(rge_t *rgep); 1292 #pragma inline(rge_wake_factotum) 1293 1294 static void 1295 rge_wake_factotum(rge_t *rgep) 1296 { 1297 if (rgep->factotum_flag == 0) { 1298 rgep->factotum_flag = 1; 1299 (void) ddi_intr_trigger_softint(rgep->factotum_hdl, NULL); 1300 } 1301 } 1302 1303 /* 1304 * rge_intr() -- handle chip interrupts 1305 */ 1306 uint_t rge_intr(caddr_t arg1, caddr_t arg2); 1307 #pragma no_inline(rge_intr) 1308 1309 uint_t 1310 rge_intr(caddr_t arg1, caddr_t arg2) 1311 { 1312 rge_t *rgep = (rge_t *)arg1; 1313 uint16_t int_status; 1314 1315 _NOTE(ARGUNUSED(arg2)) 1316 1317 mutex_enter(rgep->genlock); 1318 1319 if (rgep->suspended) { 1320 mutex_exit(rgep->genlock); 1321 return (DDI_INTR_UNCLAIMED); 1322 } 1323 1324 /* 1325 * Was this interrupt caused by our device... 1326 */ 1327 int_status = rge_reg_get16(rgep, INT_STATUS_REG); 1328 if (!(int_status & rgep->int_mask)) { 1329 mutex_exit(rgep->genlock); 1330 return (DDI_INTR_UNCLAIMED); 1331 /* indicate it wasn't our interrupt */ 1332 } 1333 rgep->stats.intr++; 1334 1335 /* 1336 * Clear interrupt 1337 * For PCIE chipset, we need disable interrupt first. 1338 */ 1339 if (rgep->chipid.is_pcie) 1340 rge_reg_put16(rgep, INT_MASK_REG, INT_MASK_NONE); 1341 rge_reg_put16(rgep, INT_STATUS_REG, int_status); 1342 1343 /* 1344 * Cable link change interrupt 1345 */ 1346 if (int_status & LINK_CHANGE_INT) { 1347 rge_chip_cyclic(rgep); 1348 } 1349 1350 mutex_exit(rgep->genlock); 1351 1352 /* 1353 * Receive interrupt 1354 */ 1355 if (int_status & RGE_RX_INT) 1356 rge_receive(rgep); 1357 1358 /* 1359 * Re-enable interrupt for PCIE chipset 1360 */ 1361 if (rgep->chipid.is_pcie) 1362 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 1363 1364 return (DDI_INTR_CLAIMED); /* indicate it was our interrupt */ 1365 } 1366 1367 /* 1368 * ========== Factotum, implemented as a softint handler ========== 1369 */ 1370 1371 #undef RGE_DBG 1372 #define RGE_DBG RGE_DBG_FACT /* debug flag for this code */ 1373 1374 static boolean_t rge_factotum_link_check(rge_t *rgep); 1375 #pragma no_inline(rge_factotum_link_check) 1376 1377 static boolean_t 1378 rge_factotum_link_check(rge_t *rgep) 1379 { 1380 uint8_t media_status; 1381 int32_t link; 1382 1383 media_status = rge_reg_get8(rgep, PHY_STATUS_REG); 1384 link = (media_status & PHY_STATUS_LINK_UP) ? 1385 LINK_STATE_UP : LINK_STATE_DOWN; 1386 if (rgep->param_link_up != link) { 1387 /* 1388 * Link change. 1389 */ 1390 rgep->param_link_up = link; 1391 1392 if (link == LINK_STATE_UP) { 1393 if (media_status & PHY_STATUS_1000MF) { 1394 rgep->param_link_speed = RGE_SPEED_1000M; 1395 rgep->param_link_duplex = LINK_DUPLEX_FULL; 1396 } else { 1397 rgep->param_link_speed = 1398 (media_status & PHY_STATUS_100M) ? 1399 RGE_SPEED_100M : RGE_SPEED_10M; 1400 rgep->param_link_duplex = 1401 (media_status & PHY_STATUS_DUPLEX_FULL) ? 1402 LINK_DUPLEX_FULL : LINK_DUPLEX_HALF; 1403 } 1404 } 1405 return (B_TRUE); 1406 } 1407 return (B_FALSE); 1408 } 1409 1410 /* 1411 * Factotum routine to check for Tx stall, using the 'watchdog' counter 1412 */ 1413 static boolean_t rge_factotum_stall_check(rge_t *rgep); 1414 #pragma no_inline(rge_factotum_stall_check) 1415 1416 static boolean_t 1417 rge_factotum_stall_check(rge_t *rgep) 1418 { 1419 uint32_t dogval; 1420 1421 ASSERT(mutex_owned(rgep->genlock)); 1422 1423 /* 1424 * Specific check for Tx stall ... 1425 * 1426 * The 'watchdog' counter is incremented whenever a packet 1427 * is queued, reset to 1 when some (but not all) buffers 1428 * are reclaimed, reset to 0 (disabled) when all buffers 1429 * are reclaimed, and shifted left here. If it exceeds the 1430 * threshold value, the chip is assumed to have stalled and 1431 * is put into the ERROR state. The factotum will then reset 1432 * it on the next pass. 1433 * 1434 * All of which should ensure that we don't get into a state 1435 * where packets are left pending indefinitely! 1436 */ 1437 if (rgep->resched_needed) 1438 (void) ddi_intr_trigger_softint(rgep->resched_hdl, NULL); 1439 dogval = rge_atomic_shl32(&rgep->watchdog, 1); 1440 if (dogval < rge_watchdog_count) 1441 return (B_FALSE); 1442 1443 RGE_REPORT((rgep, "Tx stall detected, watchdog code 0x%x", dogval)); 1444 return (B_TRUE); 1445 1446 } 1447 1448 /* 1449 * The factotum is woken up when there's something to do that we'd rather 1450 * not do from inside a hardware interrupt handler or high-level cyclic. 1451 * Its two main tasks are: 1452 * reset & restart the chip after an error 1453 * check the link status whenever necessary 1454 */ 1455 uint_t rge_chip_factotum(caddr_t arg1, caddr_t arg2); 1456 #pragma no_inline(rge_chip_factotum) 1457 1458 uint_t 1459 rge_chip_factotum(caddr_t arg1, caddr_t arg2) 1460 { 1461 rge_t *rgep; 1462 uint_t result; 1463 boolean_t error; 1464 boolean_t linkchg; 1465 1466 rgep = (rge_t *)arg1; 1467 _NOTE(ARGUNUSED(arg2)) 1468 1469 if (rgep->factotum_flag == 0) 1470 return (DDI_INTR_UNCLAIMED); 1471 1472 rgep->factotum_flag = 0; 1473 result = DDI_INTR_CLAIMED; 1474 error = B_FALSE; 1475 linkchg = B_FALSE; 1476 1477 mutex_enter(rgep->genlock); 1478 switch (rgep->rge_chip_state) { 1479 default: 1480 break; 1481 1482 case RGE_CHIP_RUNNING: 1483 linkchg = rge_factotum_link_check(rgep); 1484 error = rge_factotum_stall_check(rgep); 1485 break; 1486 1487 case RGE_CHIP_ERROR: 1488 error = B_TRUE; 1489 break; 1490 1491 case RGE_CHIP_FAULT: 1492 /* 1493 * Fault detected, time to reset ... 1494 */ 1495 if (rge_autorecover) { 1496 RGE_REPORT((rgep, "automatic recovery activated")); 1497 rge_restart(rgep); 1498 } 1499 break; 1500 } 1501 1502 /* 1503 * If an error is detected, stop the chip now, marking it as 1504 * faulty, so that it will be reset next time through ... 1505 */ 1506 if (error) 1507 rge_chip_stop(rgep, B_TRUE); 1508 mutex_exit(rgep->genlock); 1509 1510 /* 1511 * If the link state changed, tell the world about it. 1512 * Note: can't do this while still holding the mutex. 1513 */ 1514 if (linkchg) 1515 mac_link_update(rgep->mh, rgep->param_link_up); 1516 1517 return (result); 1518 } 1519 1520 /* 1521 * High-level cyclic handler 1522 * 1523 * This routine schedules a (low-level) softint callback to the 1524 * factotum, and prods the chip to update the status block (which 1525 * will cause a hardware interrupt when complete). 1526 */ 1527 void rge_chip_cyclic(void *arg); 1528 #pragma no_inline(rge_chip_cyclic) 1529 1530 void 1531 rge_chip_cyclic(void *arg) 1532 { 1533 rge_t *rgep; 1534 1535 rgep = arg; 1536 1537 switch (rgep->rge_chip_state) { 1538 default: 1539 return; 1540 1541 case RGE_CHIP_RUNNING: 1542 rge_phy_check(rgep); 1543 break; 1544 1545 case RGE_CHIP_FAULT: 1546 case RGE_CHIP_ERROR: 1547 break; 1548 } 1549 1550 rge_wake_factotum(rgep); 1551 } 1552 1553 1554 /* 1555 * ========== Ioctl subfunctions ========== 1556 */ 1557 1558 #undef RGE_DBG 1559 #define RGE_DBG RGE_DBG_PPIO /* debug flag for this code */ 1560 1561 #if RGE_DEBUGGING || RGE_DO_PPIO 1562 1563 static void rge_chip_peek_cfg(rge_t *rgep, rge_peekpoke_t *ppd); 1564 #pragma no_inline(rge_chip_peek_cfg) 1565 1566 static void 1567 rge_chip_peek_cfg(rge_t *rgep, rge_peekpoke_t *ppd) 1568 { 1569 uint64_t regval; 1570 uint64_t regno; 1571 1572 RGE_TRACE(("rge_chip_peek_cfg($%p, $%p)", 1573 (void *)rgep, (void *)ppd)); 1574 1575 regno = ppd->pp_acc_offset; 1576 1577 switch (ppd->pp_acc_size) { 1578 case 1: 1579 regval = pci_config_get8(rgep->cfg_handle, regno); 1580 break; 1581 1582 case 2: 1583 regval = pci_config_get16(rgep->cfg_handle, regno); 1584 break; 1585 1586 case 4: 1587 regval = pci_config_get32(rgep->cfg_handle, regno); 1588 break; 1589 1590 case 8: 1591 regval = pci_config_get64(rgep->cfg_handle, regno); 1592 break; 1593 } 1594 1595 ppd->pp_acc_data = regval; 1596 } 1597 1598 static void rge_chip_poke_cfg(rge_t *rgep, rge_peekpoke_t *ppd); 1599 #pragma no_inline(rge_chip_poke_cfg) 1600 1601 static void 1602 rge_chip_poke_cfg(rge_t *rgep, rge_peekpoke_t *ppd) 1603 { 1604 uint64_t regval; 1605 uint64_t regno; 1606 1607 RGE_TRACE(("rge_chip_poke_cfg($%p, $%p)", 1608 (void *)rgep, (void *)ppd)); 1609 1610 regno = ppd->pp_acc_offset; 1611 regval = ppd->pp_acc_data; 1612 1613 switch (ppd->pp_acc_size) { 1614 case 1: 1615 pci_config_put8(rgep->cfg_handle, regno, regval); 1616 break; 1617 1618 case 2: 1619 pci_config_put16(rgep->cfg_handle, regno, regval); 1620 break; 1621 1622 case 4: 1623 pci_config_put32(rgep->cfg_handle, regno, regval); 1624 break; 1625 1626 case 8: 1627 pci_config_put64(rgep->cfg_handle, regno, regval); 1628 break; 1629 } 1630 } 1631 1632 static void rge_chip_peek_reg(rge_t *rgep, rge_peekpoke_t *ppd); 1633 #pragma no_inline(rge_chip_peek_reg) 1634 1635 static void 1636 rge_chip_peek_reg(rge_t *rgep, rge_peekpoke_t *ppd) 1637 { 1638 uint64_t regval; 1639 void *regaddr; 1640 1641 RGE_TRACE(("rge_chip_peek_reg($%p, $%p)", 1642 (void *)rgep, (void *)ppd)); 1643 1644 regaddr = PIO_ADDR(rgep, ppd->pp_acc_offset); 1645 1646 switch (ppd->pp_acc_size) { 1647 case 1: 1648 regval = ddi_get8(rgep->io_handle, regaddr); 1649 break; 1650 1651 case 2: 1652 regval = ddi_get16(rgep->io_handle, regaddr); 1653 break; 1654 1655 case 4: 1656 regval = ddi_get32(rgep->io_handle, regaddr); 1657 break; 1658 1659 case 8: 1660 regval = ddi_get64(rgep->io_handle, regaddr); 1661 break; 1662 } 1663 1664 ppd->pp_acc_data = regval; 1665 } 1666 1667 static void rge_chip_poke_reg(rge_t *rgep, rge_peekpoke_t *ppd); 1668 #pragma no_inline(rge_chip_peek_reg) 1669 1670 static void 1671 rge_chip_poke_reg(rge_t *rgep, rge_peekpoke_t *ppd) 1672 { 1673 uint64_t regval; 1674 void *regaddr; 1675 1676 RGE_TRACE(("rge_chip_poke_reg($%p, $%p)", 1677 (void *)rgep, (void *)ppd)); 1678 1679 regaddr = PIO_ADDR(rgep, ppd->pp_acc_offset); 1680 regval = ppd->pp_acc_data; 1681 1682 switch (ppd->pp_acc_size) { 1683 case 1: 1684 ddi_put8(rgep->io_handle, regaddr, regval); 1685 break; 1686 1687 case 2: 1688 ddi_put16(rgep->io_handle, regaddr, regval); 1689 break; 1690 1691 case 4: 1692 ddi_put32(rgep->io_handle, regaddr, regval); 1693 break; 1694 1695 case 8: 1696 ddi_put64(rgep->io_handle, regaddr, regval); 1697 break; 1698 } 1699 } 1700 1701 static void rge_chip_peek_mii(rge_t *rgep, rge_peekpoke_t *ppd); 1702 #pragma no_inline(rge_chip_peek_mii) 1703 1704 static void 1705 rge_chip_peek_mii(rge_t *rgep, rge_peekpoke_t *ppd) 1706 { 1707 RGE_TRACE(("rge_chip_peek_mii($%p, $%p)", 1708 (void *)rgep, (void *)ppd)); 1709 1710 ppd->pp_acc_data = rge_mii_get16(rgep, ppd->pp_acc_offset/2); 1711 } 1712 1713 static void rge_chip_poke_mii(rge_t *rgep, rge_peekpoke_t *ppd); 1714 #pragma no_inline(rge_chip_poke_mii) 1715 1716 static void 1717 rge_chip_poke_mii(rge_t *rgep, rge_peekpoke_t *ppd) 1718 { 1719 RGE_TRACE(("rge_chip_poke_mii($%p, $%p)", 1720 (void *)rgep, (void *)ppd)); 1721 1722 rge_mii_put16(rgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 1723 } 1724 1725 static void rge_chip_peek_mem(rge_t *rgep, rge_peekpoke_t *ppd); 1726 #pragma no_inline(rge_chip_peek_mem) 1727 1728 static void 1729 rge_chip_peek_mem(rge_t *rgep, rge_peekpoke_t *ppd) 1730 { 1731 uint64_t regval; 1732 void *vaddr; 1733 1734 RGE_TRACE(("rge_chip_peek_rge($%p, $%p)", 1735 (void *)rgep, (void *)ppd)); 1736 1737 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 1738 1739 switch (ppd->pp_acc_size) { 1740 case 1: 1741 regval = *(uint8_t *)vaddr; 1742 break; 1743 1744 case 2: 1745 regval = *(uint16_t *)vaddr; 1746 break; 1747 1748 case 4: 1749 regval = *(uint32_t *)vaddr; 1750 break; 1751 1752 case 8: 1753 regval = *(uint64_t *)vaddr; 1754 break; 1755 } 1756 1757 RGE_DEBUG(("rge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 1758 (void *)rgep, (void *)ppd, regval, vaddr)); 1759 1760 ppd->pp_acc_data = regval; 1761 } 1762 1763 static void rge_chip_poke_mem(rge_t *rgep, rge_peekpoke_t *ppd); 1764 #pragma no_inline(rge_chip_poke_mem) 1765 1766 static void 1767 rge_chip_poke_mem(rge_t *rgep, rge_peekpoke_t *ppd) 1768 { 1769 uint64_t regval; 1770 void *vaddr; 1771 1772 RGE_TRACE(("rge_chip_poke_mem($%p, $%p)", 1773 (void *)rgep, (void *)ppd)); 1774 1775 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 1776 regval = ppd->pp_acc_data; 1777 1778 RGE_DEBUG(("rge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 1779 (void *)rgep, (void *)ppd, regval, vaddr)); 1780 1781 switch (ppd->pp_acc_size) { 1782 case 1: 1783 *(uint8_t *)vaddr = (uint8_t)regval; 1784 break; 1785 1786 case 2: 1787 *(uint16_t *)vaddr = (uint16_t)regval; 1788 break; 1789 1790 case 4: 1791 *(uint32_t *)vaddr = (uint32_t)regval; 1792 break; 1793 1794 case 8: 1795 *(uint64_t *)vaddr = (uint64_t)regval; 1796 break; 1797 } 1798 } 1799 1800 static enum ioc_reply rge_pp_ioctl(rge_t *rgep, int cmd, mblk_t *mp, 1801 struct iocblk *iocp); 1802 #pragma no_inline(rge_pp_ioctl) 1803 1804 static enum ioc_reply 1805 rge_pp_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp) 1806 { 1807 void (*ppfn)(rge_t *rgep, rge_peekpoke_t *ppd); 1808 rge_peekpoke_t *ppd; 1809 dma_area_t *areap; 1810 uint64_t sizemask; 1811 uint64_t mem_va; 1812 uint64_t maxoff; 1813 boolean_t peek; 1814 1815 switch (cmd) { 1816 default: 1817 /* NOTREACHED */ 1818 rge_error(rgep, "rge_pp_ioctl: invalid cmd 0x%x", cmd); 1819 return (IOC_INVAL); 1820 1821 case RGE_PEEK: 1822 peek = B_TRUE; 1823 break; 1824 1825 case RGE_POKE: 1826 peek = B_FALSE; 1827 break; 1828 } 1829 1830 /* 1831 * Validate format of ioctl 1832 */ 1833 if (iocp->ioc_count != sizeof (rge_peekpoke_t)) 1834 return (IOC_INVAL); 1835 if (mp->b_cont == NULL) 1836 return (IOC_INVAL); 1837 ppd = (rge_peekpoke_t *)mp->b_cont->b_rptr; 1838 1839 /* 1840 * Validate request parameters 1841 */ 1842 switch (ppd->pp_acc_space) { 1843 default: 1844 return (IOC_INVAL); 1845 1846 case RGE_PP_SPACE_CFG: 1847 /* 1848 * Config space 1849 */ 1850 sizemask = 8|4|2|1; 1851 mem_va = 0; 1852 maxoff = PCI_CONF_HDR_SIZE; 1853 ppfn = peek ? rge_chip_peek_cfg : rge_chip_poke_cfg; 1854 break; 1855 1856 case RGE_PP_SPACE_REG: 1857 /* 1858 * Memory-mapped I/O space 1859 */ 1860 sizemask = 8|4|2|1; 1861 mem_va = 0; 1862 maxoff = RGE_REGISTER_MAX; 1863 ppfn = peek ? rge_chip_peek_reg : rge_chip_poke_reg; 1864 break; 1865 1866 case RGE_PP_SPACE_MII: 1867 /* 1868 * PHY's MII registers 1869 * NB: all PHY registers are two bytes, but the 1870 * addresses increment in ones (word addressing). 1871 * So we scale the address here, then undo the 1872 * transformation inside the peek/poke functions. 1873 */ 1874 ppd->pp_acc_offset *= 2; 1875 sizemask = 2; 1876 mem_va = 0; 1877 maxoff = (MII_MAXREG+1)*2; 1878 ppfn = peek ? rge_chip_peek_mii : rge_chip_poke_mii; 1879 break; 1880 1881 case RGE_PP_SPACE_RGE: 1882 /* 1883 * RGE data structure! 1884 */ 1885 sizemask = 8|4|2|1; 1886 mem_va = (uintptr_t)rgep; 1887 maxoff = sizeof (*rgep); 1888 ppfn = peek ? rge_chip_peek_mem : rge_chip_poke_mem; 1889 break; 1890 1891 case RGE_PP_SPACE_STATISTICS: 1892 case RGE_PP_SPACE_TXDESC: 1893 case RGE_PP_SPACE_TXBUFF: 1894 case RGE_PP_SPACE_RXDESC: 1895 case RGE_PP_SPACE_RXBUFF: 1896 /* 1897 * Various DMA_AREAs 1898 */ 1899 switch (ppd->pp_acc_space) { 1900 case RGE_PP_SPACE_TXDESC: 1901 areap = &rgep->dma_area_txdesc; 1902 break; 1903 case RGE_PP_SPACE_RXDESC: 1904 areap = &rgep->dma_area_rxdesc; 1905 break; 1906 case RGE_PP_SPACE_STATISTICS: 1907 areap = &rgep->dma_area_stats; 1908 break; 1909 } 1910 1911 sizemask = 8|4|2|1; 1912 mem_va = (uintptr_t)areap->mem_va; 1913 maxoff = areap->alength; 1914 ppfn = peek ? rge_chip_peek_mem : rge_chip_poke_mem; 1915 break; 1916 } 1917 1918 switch (ppd->pp_acc_size) { 1919 default: 1920 return (IOC_INVAL); 1921 1922 case 8: 1923 case 4: 1924 case 2: 1925 case 1: 1926 if ((ppd->pp_acc_size & sizemask) == 0) 1927 return (IOC_INVAL); 1928 break; 1929 } 1930 1931 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 1932 return (IOC_INVAL); 1933 1934 if (ppd->pp_acc_offset >= maxoff) 1935 return (IOC_INVAL); 1936 1937 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 1938 return (IOC_INVAL); 1939 1940 /* 1941 * All OK - go do it! 1942 */ 1943 ppd->pp_acc_offset += mem_va; 1944 (*ppfn)(rgep, ppd); 1945 return (peek ? IOC_REPLY : IOC_ACK); 1946 } 1947 1948 static enum ioc_reply rge_diag_ioctl(rge_t *rgep, int cmd, mblk_t *mp, 1949 struct iocblk *iocp); 1950 #pragma no_inline(rge_diag_ioctl) 1951 1952 static enum ioc_reply 1953 rge_diag_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp) 1954 { 1955 ASSERT(mutex_owned(rgep->genlock)); 1956 1957 switch (cmd) { 1958 default: 1959 /* NOTREACHED */ 1960 rge_error(rgep, "rge_diag_ioctl: invalid cmd 0x%x", cmd); 1961 return (IOC_INVAL); 1962 1963 case RGE_DIAG: 1964 /* 1965 * Currently a no-op 1966 */ 1967 return (IOC_ACK); 1968 1969 case RGE_PEEK: 1970 case RGE_POKE: 1971 return (rge_pp_ioctl(rgep, cmd, mp, iocp)); 1972 1973 case RGE_PHY_RESET: 1974 return (IOC_RESTART_ACK); 1975 1976 case RGE_SOFT_RESET: 1977 case RGE_HARD_RESET: 1978 /* 1979 * Reset and reinitialise the 570x hardware 1980 */ 1981 rge_restart(rgep); 1982 return (IOC_ACK); 1983 } 1984 1985 /* NOTREACHED */ 1986 } 1987 1988 #endif /* RGE_DEBUGGING || RGE_DO_PPIO */ 1989 1990 static enum ioc_reply rge_mii_ioctl(rge_t *rgep, int cmd, mblk_t *mp, 1991 struct iocblk *iocp); 1992 #pragma no_inline(rge_mii_ioctl) 1993 1994 static enum ioc_reply 1995 rge_mii_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp) 1996 { 1997 struct rge_mii_rw *miirwp; 1998 1999 /* 2000 * Validate format of ioctl 2001 */ 2002 if (iocp->ioc_count != sizeof (struct rge_mii_rw)) 2003 return (IOC_INVAL); 2004 if (mp->b_cont == NULL) 2005 return (IOC_INVAL); 2006 miirwp = (struct rge_mii_rw *)mp->b_cont->b_rptr; 2007 2008 /* 2009 * Validate request parameters ... 2010 */ 2011 if (miirwp->mii_reg > MII_MAXREG) 2012 return (IOC_INVAL); 2013 2014 switch (cmd) { 2015 default: 2016 /* NOTREACHED */ 2017 rge_error(rgep, "rge_mii_ioctl: invalid cmd 0x%x", cmd); 2018 return (IOC_INVAL); 2019 2020 case RGE_MII_READ: 2021 miirwp->mii_data = rge_mii_get16(rgep, miirwp->mii_reg); 2022 return (IOC_REPLY); 2023 2024 case RGE_MII_WRITE: 2025 rge_mii_put16(rgep, miirwp->mii_reg, miirwp->mii_data); 2026 return (IOC_ACK); 2027 } 2028 2029 /* NOTREACHED */ 2030 } 2031 2032 enum ioc_reply rge_chip_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp, 2033 struct iocblk *iocp); 2034 #pragma no_inline(rge_chip_ioctl) 2035 2036 enum ioc_reply 2037 rge_chip_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 2038 { 2039 int cmd; 2040 2041 RGE_TRACE(("rge_chip_ioctl($%p, $%p, $%p, $%p)", 2042 (void *)rgep, (void *)wq, (void *)mp, (void *)iocp)); 2043 2044 ASSERT(mutex_owned(rgep->genlock)); 2045 2046 cmd = iocp->ioc_cmd; 2047 switch (cmd) { 2048 default: 2049 /* NOTREACHED */ 2050 rge_error(rgep, "rge_chip_ioctl: invalid cmd 0x%x", cmd); 2051 return (IOC_INVAL); 2052 2053 case RGE_DIAG: 2054 case RGE_PEEK: 2055 case RGE_POKE: 2056 case RGE_PHY_RESET: 2057 case RGE_SOFT_RESET: 2058 case RGE_HARD_RESET: 2059 #if RGE_DEBUGGING || RGE_DO_PPIO 2060 return (rge_diag_ioctl(rgep, cmd, mp, iocp)); 2061 #else 2062 return (IOC_INVAL); 2063 #endif /* RGE_DEBUGGING || RGE_DO_PPIO */ 2064 2065 case RGE_MII_READ: 2066 case RGE_MII_WRITE: 2067 return (rge_mii_ioctl(rgep, cmd, mp, iocp)); 2068 2069 } 2070 2071 /* NOTREACHED */ 2072 } 2073