1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include "rge.h" 29 30 #define REG32(rgep, reg) ((uint32_t *)(rgep->io_regs+(reg))) 31 #define REG16(rgep, reg) ((uint16_t *)(rgep->io_regs+(reg))) 32 #define REG8(rgep, reg) ((uint8_t *)(rgep->io_regs+(reg))) 33 #define PIO_ADDR(rgep, offset) ((void *)(rgep->io_regs+(offset))) 34 35 /* 36 * Patchable globals: 37 * 38 * rge_autorecover 39 * Enables/disables automatic recovery after fault detection 40 */ 41 static uint32_t rge_autorecover = 1; 42 43 /* 44 * globals: 45 */ 46 #define RGE_DBG RGE_DBG_REGS /* debug flag for this code */ 47 static uint32_t rge_watchdog_count = 1 << 16; 48 49 /* 50 * Operating register get/set access routines 51 */ 52 53 static uint32_t rge_reg_get32(rge_t *rgep, uintptr_t regno); 54 #pragma inline(rge_reg_get32) 55 56 static uint32_t 57 rge_reg_get32(rge_t *rgep, uintptr_t regno) 58 { 59 RGE_TRACE(("rge_reg_get32($%p, 0x%lx)", 60 (void *)rgep, regno)); 61 62 return (ddi_get32(rgep->io_handle, REG32(rgep, regno))); 63 } 64 65 static void rge_reg_put32(rge_t *rgep, uintptr_t regno, uint32_t data); 66 #pragma inline(rge_reg_put32) 67 68 static void 69 rge_reg_put32(rge_t *rgep, uintptr_t regno, uint32_t data) 70 { 71 RGE_TRACE(("rge_reg_put32($%p, 0x%lx, 0x%x)", 72 (void *)rgep, regno, data)); 73 74 ddi_put32(rgep->io_handle, REG32(rgep, regno), data); 75 } 76 77 static void rge_reg_set32(rge_t *rgep, uintptr_t regno, uint32_t bits); 78 #pragma inline(rge_reg_set32) 79 80 static void 81 rge_reg_set32(rge_t *rgep, uintptr_t regno, uint32_t bits) 82 { 83 uint32_t regval; 84 85 RGE_TRACE(("rge_reg_set32($%p, 0x%lx, 0x%x)", 86 (void *)rgep, regno, bits)); 87 88 regval = rge_reg_get32(rgep, regno); 89 regval |= bits; 90 rge_reg_put32(rgep, regno, regval); 91 } 92 93 static void rge_reg_clr32(rge_t *rgep, uintptr_t regno, uint32_t bits); 94 #pragma inline(rge_reg_clr32) 95 96 static void 97 rge_reg_clr32(rge_t *rgep, uintptr_t regno, uint32_t bits) 98 { 99 uint32_t regval; 100 101 RGE_TRACE(("rge_reg_clr32($%p, 0x%lx, 0x%x)", 102 (void *)rgep, regno, bits)); 103 104 regval = rge_reg_get32(rgep, regno); 105 regval &= ~bits; 106 rge_reg_put32(rgep, regno, regval); 107 } 108 109 static uint16_t rge_reg_get16(rge_t *rgep, uintptr_t regno); 110 #pragma inline(rge_reg_get16) 111 112 static uint16_t 113 rge_reg_get16(rge_t *rgep, uintptr_t regno) 114 { 115 RGE_TRACE(("rge_reg_get16($%p, 0x%lx)", 116 (void *)rgep, regno)); 117 118 return (ddi_get16(rgep->io_handle, REG16(rgep, regno))); 119 } 120 121 static void rge_reg_put16(rge_t *rgep, uintptr_t regno, uint16_t data); 122 #pragma inline(rge_reg_put16) 123 124 static void 125 rge_reg_put16(rge_t *rgep, uintptr_t regno, uint16_t data) 126 { 127 RGE_TRACE(("rge_reg_put16($%p, 0x%lx, 0x%x)", 128 (void *)rgep, regno, data)); 129 130 ddi_put16(rgep->io_handle, REG16(rgep, regno), data); 131 } 132 133 static void rge_reg_set16(rge_t *rgep, uintptr_t regno, uint16_t bits); 134 #pragma inline(rge_reg_set16) 135 136 static void 137 rge_reg_set16(rge_t *rgep, uintptr_t regno, uint16_t bits) 138 { 139 uint16_t regval; 140 141 RGE_TRACE(("rge_reg_set16($%p, 0x%lx, 0x%x)", 142 (void *)rgep, regno, bits)); 143 144 regval = rge_reg_get16(rgep, regno); 145 regval |= bits; 146 rge_reg_put16(rgep, regno, regval); 147 } 148 149 static void rge_reg_clr16(rge_t *rgep, uintptr_t regno, uint16_t bits); 150 #pragma inline(rge_reg_clr16) 151 152 static void 153 rge_reg_clr16(rge_t *rgep, uintptr_t regno, uint16_t bits) 154 { 155 uint16_t regval; 156 157 RGE_TRACE(("rge_reg_clr16($%p, 0x%lx, 0x%x)", 158 (void *)rgep, regno, bits)); 159 160 regval = rge_reg_get16(rgep, regno); 161 regval &= ~bits; 162 rge_reg_put16(rgep, regno, regval); 163 } 164 165 static uint8_t rge_reg_get8(rge_t *rgep, uintptr_t regno); 166 #pragma inline(rge_reg_get8) 167 168 static uint8_t 169 rge_reg_get8(rge_t *rgep, uintptr_t regno) 170 { 171 RGE_TRACE(("rge_reg_get8($%p, 0x%lx)", 172 (void *)rgep, regno)); 173 174 return (ddi_get8(rgep->io_handle, REG8(rgep, regno))); 175 } 176 177 static void rge_reg_put8(rge_t *rgep, uintptr_t regno, uint8_t data); 178 #pragma inline(rge_reg_put8) 179 180 static void 181 rge_reg_put8(rge_t *rgep, uintptr_t regno, uint8_t data) 182 { 183 RGE_TRACE(("rge_reg_put8($%p, 0x%lx, 0x%x)", 184 (void *)rgep, regno, data)); 185 186 ddi_put8(rgep->io_handle, REG8(rgep, regno), data); 187 } 188 189 static void rge_reg_set8(rge_t *rgep, uintptr_t regno, uint8_t bits); 190 #pragma inline(rge_reg_set8) 191 192 static void 193 rge_reg_set8(rge_t *rgep, uintptr_t regno, uint8_t bits) 194 { 195 uint8_t regval; 196 197 RGE_TRACE(("rge_reg_set8($%p, 0x%lx, 0x%x)", 198 (void *)rgep, regno, bits)); 199 200 regval = rge_reg_get8(rgep, regno); 201 regval |= bits; 202 rge_reg_put8(rgep, regno, regval); 203 } 204 205 static void rge_reg_clr8(rge_t *rgep, uintptr_t regno, uint8_t bits); 206 #pragma inline(rge_reg_clr8) 207 208 static void 209 rge_reg_clr8(rge_t *rgep, uintptr_t regno, uint8_t bits) 210 { 211 uint8_t regval; 212 213 RGE_TRACE(("rge_reg_clr8($%p, 0x%lx, 0x%x)", 214 (void *)rgep, regno, bits)); 215 216 regval = rge_reg_get8(rgep, regno); 217 regval &= ~bits; 218 rge_reg_put8(rgep, regno, regval); 219 } 220 221 uint16_t rge_mii_get16(rge_t *rgep, uintptr_t mii); 222 #pragma no_inline(rge_mii_get16) 223 224 uint16_t 225 rge_mii_get16(rge_t *rgep, uintptr_t mii) 226 { 227 uint32_t regval; 228 uint32_t val32; 229 uint32_t i; 230 231 regval = (mii & PHY_REG_MASK) << PHY_REG_SHIFT; 232 rge_reg_put32(rgep, PHY_ACCESS_REG, regval); 233 234 /* 235 * Waiting for PHY reading OK 236 */ 237 for (i = 0; i < PHY_RESET_LOOP; i++) { 238 drv_usecwait(1000); 239 val32 = rge_reg_get32(rgep, PHY_ACCESS_REG); 240 if (val32 & PHY_ACCESS_WR_FLAG) 241 return ((uint16_t)(val32 & 0xffff)); 242 } 243 244 RGE_REPORT((rgep, "rge_mii_get16(0x%x) fail, val = %x", mii, val32)); 245 return ((uint16_t)~0u); 246 } 247 248 void rge_mii_put16(rge_t *rgep, uintptr_t mii, uint16_t data); 249 #pragma no_inline(rge_mii_put16) 250 251 void 252 rge_mii_put16(rge_t *rgep, uintptr_t mii, uint16_t data) 253 { 254 uint32_t regval; 255 uint32_t val32; 256 uint32_t i; 257 258 regval = (mii & PHY_REG_MASK) << PHY_REG_SHIFT; 259 regval |= data & PHY_DATA_MASK; 260 regval |= PHY_ACCESS_WR_FLAG; 261 rge_reg_put32(rgep, PHY_ACCESS_REG, regval); 262 263 /* 264 * Waiting for PHY writing OK 265 */ 266 for (i = 0; i < PHY_RESET_LOOP; i++) { 267 drv_usecwait(1000); 268 val32 = rge_reg_get32(rgep, PHY_ACCESS_REG); 269 if (!(val32 & PHY_ACCESS_WR_FLAG)) 270 return; 271 } 272 RGE_REPORT((rgep, "rge_mii_put16(0x%lx, 0x%x) fail", 273 mii, data)); 274 } 275 276 void rge_ephy_put16(rge_t *rgep, uintptr_t emii, uint16_t data); 277 #pragma no_inline(rge_ephy_put16) 278 279 void 280 rge_ephy_put16(rge_t *rgep, uintptr_t emii, uint16_t data) 281 { 282 uint32_t regval; 283 uint32_t val32; 284 uint32_t i; 285 286 regval = (emii & EPHY_REG_MASK) << EPHY_REG_SHIFT; 287 regval |= data & EPHY_DATA_MASK; 288 regval |= EPHY_ACCESS_WR_FLAG; 289 rge_reg_put32(rgep, EPHY_ACCESS_REG, regval); 290 291 /* 292 * Waiting for PHY writing OK 293 */ 294 for (i = 0; i < PHY_RESET_LOOP; i++) { 295 drv_usecwait(1000); 296 val32 = rge_reg_get32(rgep, EPHY_ACCESS_REG); 297 if (!(val32 & EPHY_ACCESS_WR_FLAG)) 298 return; 299 } 300 RGE_REPORT((rgep, "rge_ephy_put16(0x%lx, 0x%x) fail", 301 emii, data)); 302 } 303 304 /* 305 * Atomically shift a 32-bit word left, returning 306 * the value it had *before* the shift was applied 307 */ 308 static uint32_t rge_atomic_shl32(uint32_t *sp, uint_t count); 309 #pragma inline(rge_mii_put16) 310 311 static uint32_t 312 rge_atomic_shl32(uint32_t *sp, uint_t count) 313 { 314 uint32_t oldval; 315 uint32_t newval; 316 317 /* ATOMICALLY */ 318 do { 319 oldval = *sp; 320 newval = oldval << count; 321 } while (cas32(sp, oldval, newval) != oldval); 322 323 return (oldval); 324 } 325 326 /* 327 * PHY operation routines 328 */ 329 #if RGE_DEBUGGING 330 331 static void 332 rge_phydump(rge_t *rgep) 333 { 334 uint16_t regs[32]; 335 int i; 336 337 ASSERT(mutex_owned(rgep->genlock)); 338 339 for (i = 0; i < 32; ++i) { 340 regs[i] = rge_mii_get16(rgep, i); 341 } 342 343 for (i = 0; i < 32; i += 8) 344 RGE_DEBUG(("rge_phydump: " 345 "0x%04x %04x %04x %04x %04x %04x %04x %04x", 346 regs[i+0], regs[i+1], regs[i+2], regs[i+3], 347 regs[i+4], regs[i+5], regs[i+6], regs[i+7])); 348 } 349 350 #endif /* RGE_DEBUGGING */ 351 352 /* 353 * Basic low-level function to probe for a PHY 354 * 355 * Returns TRUE if the PHY responds with valid data, FALSE otherwise 356 */ 357 static boolean_t 358 rge_phy_probe(rge_t *rgep) 359 { 360 uint16_t phy_status; 361 362 ASSERT(mutex_owned(rgep->genlock)); 363 364 /* 365 * Read the MII_STATUS register twice, in 366 * order to clear any sticky bits (but they should 367 * have been cleared by the RESET, I think). 368 */ 369 phy_status = rge_mii_get16(rgep, MII_STATUS); 370 phy_status = rge_mii_get16(rgep, MII_STATUS); 371 RGE_DEBUG(("rge_phy_probe: status 0x%x", phy_status)); 372 373 /* 374 * Now check the value read; it should have at least one bit set 375 * (for the device capabilities) and at least one clear (one of 376 * the error bits). So if we see all 0s or all 1s, there's a 377 * problem. In particular, rge_mii_get16() returns all 1s if 378 * communications fails ... 379 */ 380 switch (phy_status) { 381 case 0x0000: 382 case 0xffff: 383 return (B_FALSE); 384 385 default : 386 return (B_TRUE); 387 } 388 } 389 390 static void 391 rge_phy_check(rge_t *rgep) 392 { 393 uint16_t gig_ctl; 394 395 if (rgep->param_link_up == LINK_STATE_DOWN) { 396 /* 397 * RTL8169S/8110S PHY has the "PCS bug". Need reset PHY 398 * every 15 seconds whin link down & advertise is 1000. 399 */ 400 if (rgep->chipid.phy_ver == PHY_VER_S) { 401 gig_ctl = rge_mii_get16(rgep, MII_1000BASE_T_CONTROL); 402 if (gig_ctl & MII_1000BT_CTL_ADV_FDX) { 403 rgep->link_down_count++; 404 if (rgep->link_down_count > 15) { 405 (void) rge_phy_reset(rgep); 406 rgep->stats.phy_reset++; 407 rgep->link_down_count = 0; 408 } 409 } 410 } 411 } else { 412 rgep->link_down_count = 0; 413 } 414 } 415 416 /* 417 * Basic low-level function to reset the PHY. 418 * Doesn't incorporate any special-case workarounds. 419 * 420 * Returns TRUE on success, FALSE if the RESET bit doesn't clear 421 */ 422 boolean_t 423 rge_phy_reset(rge_t *rgep) 424 { 425 uint16_t control; 426 uint_t count; 427 428 /* 429 * Set the PHY RESET bit, then wait up to 5 ms for it to self-clear 430 */ 431 control = rge_mii_get16(rgep, MII_CONTROL); 432 rge_mii_put16(rgep, MII_CONTROL, control | MII_CONTROL_RESET); 433 for (count = 0; count < 5; count++) { 434 drv_usecwait(100); 435 control = rge_mii_get16(rgep, MII_CONTROL); 436 if (BIC(control, MII_CONTROL_RESET)) 437 return (B_TRUE); 438 } 439 440 RGE_REPORT((rgep, "rge_phy_reset: FAILED, control now 0x%x", control)); 441 return (B_FALSE); 442 } 443 444 /* 445 * Synchronise the PHY's speed/duplex/autonegotiation capabilities 446 * and advertisements with the required settings as specified by the various 447 * param_* variables that can be poked via the NDD interface. 448 * 449 * We always reset the PHY and reprogram *all* the relevant registers, 450 * not just those changed. This should cause the link to go down, and then 451 * back up again once the link is stable and autonegotiation (if enabled) 452 * is complete. We should get a link state change interrupt somewhere along 453 * the way ... 454 * 455 * NOTE: <genlock> must already be held by the caller 456 */ 457 void 458 rge_phy_update(rge_t *rgep) 459 { 460 boolean_t adv_autoneg; 461 boolean_t adv_pause; 462 boolean_t adv_asym_pause; 463 boolean_t adv_1000fdx; 464 boolean_t adv_1000hdx; 465 boolean_t adv_100fdx; 466 boolean_t adv_100hdx; 467 boolean_t adv_10fdx; 468 boolean_t adv_10hdx; 469 470 uint16_t control; 471 uint16_t gigctrl; 472 uint16_t anar; 473 474 ASSERT(mutex_owned(rgep->genlock)); 475 476 RGE_DEBUG(("rge_phy_update: autoneg %d " 477 "pause %d asym_pause %d " 478 "1000fdx %d 1000hdx %d " 479 "100fdx %d 100hdx %d " 480 "10fdx %d 10hdx %d ", 481 rgep->param_adv_autoneg, 482 rgep->param_adv_pause, rgep->param_adv_asym_pause, 483 rgep->param_adv_1000fdx, rgep->param_adv_1000hdx, 484 rgep->param_adv_100fdx, rgep->param_adv_100hdx, 485 rgep->param_adv_10fdx, rgep->param_adv_10hdx)); 486 487 control = gigctrl = anar = 0; 488 489 /* 490 * PHY settings are normally based on the param_* variables, 491 * but if any loopback mode is in effect, that takes precedence. 492 * 493 * RGE supports MAC-internal loopback, PHY-internal loopback, 494 * and External loopback at a variety of speeds (with a special 495 * cable). In all cases, autoneg is turned OFF, full-duplex 496 * is turned ON, and the speed/mastership is forced. 497 */ 498 switch (rgep->param_loop_mode) { 499 case RGE_LOOP_NONE: 500 default: 501 adv_autoneg = rgep->param_adv_autoneg; 502 adv_pause = rgep->param_adv_pause; 503 adv_asym_pause = rgep->param_adv_asym_pause; 504 adv_1000fdx = rgep->param_adv_1000fdx; 505 adv_1000hdx = rgep->param_adv_1000hdx; 506 adv_100fdx = rgep->param_adv_100fdx; 507 adv_100hdx = rgep->param_adv_100hdx; 508 adv_10fdx = rgep->param_adv_10fdx; 509 adv_10hdx = rgep->param_adv_10hdx; 510 break; 511 512 case RGE_LOOP_INTERNAL_PHY: 513 case RGE_LOOP_INTERNAL_MAC: 514 adv_autoneg = adv_pause = adv_asym_pause = B_FALSE; 515 adv_1000fdx = adv_100fdx = adv_10fdx = B_FALSE; 516 adv_1000hdx = adv_100hdx = adv_10hdx = B_FALSE; 517 rgep->param_link_duplex = LINK_DUPLEX_FULL; 518 519 switch (rgep->param_loop_mode) { 520 case RGE_LOOP_INTERNAL_PHY: 521 if (rgep->chipid.mac_ver != MAC_VER_8101E) { 522 rgep->param_link_speed = 1000; 523 adv_1000fdx = B_TRUE; 524 } else { 525 rgep->param_link_speed = 100; 526 adv_100fdx = B_TRUE; 527 } 528 control = MII_CONTROL_LOOPBACK; 529 break; 530 531 case RGE_LOOP_INTERNAL_MAC: 532 if (rgep->chipid.mac_ver != MAC_VER_8101E) { 533 rgep->param_link_speed = 1000; 534 adv_1000fdx = B_TRUE; 535 } else { 536 rgep->param_link_speed = 100; 537 adv_100fdx = B_TRUE; 538 break; 539 } 540 } 541 542 RGE_DEBUG(("rge_phy_update: autoneg %d " 543 "pause %d asym_pause %d " 544 "1000fdx %d 1000hdx %d " 545 "100fdx %d 100hdx %d " 546 "10fdx %d 10hdx %d ", 547 adv_autoneg, 548 adv_pause, adv_asym_pause, 549 adv_1000fdx, adv_1000hdx, 550 adv_100fdx, adv_100hdx, 551 adv_10fdx, adv_10hdx)); 552 553 /* 554 * We should have at least one technology capability set; 555 * if not, we select a default of 1000Mb/s full-duplex 556 */ 557 if (!adv_1000fdx && !adv_100fdx && !adv_10fdx && 558 !adv_1000hdx && !adv_100hdx && !adv_10hdx) { 559 if (rgep->chipid.mac_ver != MAC_VER_8101E) 560 adv_1000fdx = B_TRUE; 561 } else { 562 adv_1000fdx = B_FALSE; 563 adv_100fdx = B_TRUE; 564 } 565 } 566 567 /* 568 * Now transform the adv_* variables into the proper settings 569 * of the PHY registers ... 570 * 571 * If autonegotiation is (now) enabled, we want to trigger 572 * a new autonegotiation cycle once the PHY has been 573 * programmed with the capabilities to be advertised. 574 * 575 * RTL8169/8110 doesn't support 1000Mb/s half-duplex. 576 */ 577 if (adv_autoneg) 578 control |= MII_CONTROL_ANE|MII_CONTROL_RSAN; 579 580 if (adv_1000fdx) 581 control |= MII_CONTROL_1000MB|MII_CONTROL_FDUPLEX; 582 else if (adv_1000hdx) 583 control |= MII_CONTROL_1000MB; 584 else if (adv_100fdx) 585 control |= MII_CONTROL_100MB|MII_CONTROL_FDUPLEX; 586 else if (adv_100hdx) 587 control |= MII_CONTROL_100MB; 588 else if (adv_10fdx) 589 control |= MII_CONTROL_FDUPLEX; 590 else if (adv_10hdx) 591 control |= 0; 592 else 593 { _NOTE(EMPTY); } /* Can't get here anyway ... */ 594 595 if (adv_1000fdx) { 596 gigctrl |= MII_1000BT_CTL_ADV_FDX; 597 /* 598 * Chipset limitation: need set other capabilities to true 599 */ 600 if (rgep->chipid.is_pcie) 601 adv_1000hdx = B_TRUE; 602 adv_100fdx = B_TRUE; 603 adv_100hdx = B_TRUE; 604 adv_10fdx = B_TRUE; 605 adv_10hdx = B_TRUE; 606 } 607 608 if (adv_1000hdx) 609 gigctrl |= MII_1000BT_CTL_ADV_HDX; 610 611 if (adv_100fdx) 612 anar |= MII_ABILITY_100BASE_TX_FD; 613 if (adv_100hdx) 614 anar |= MII_ABILITY_100BASE_TX; 615 if (adv_10fdx) 616 anar |= MII_ABILITY_10BASE_T_FD; 617 if (adv_10hdx) 618 anar |= MII_ABILITY_10BASE_T; 619 620 if (adv_pause) 621 anar |= MII_ABILITY_PAUSE; 622 if (adv_asym_pause) 623 anar |= MII_ABILITY_ASYM_PAUSE; 624 625 /* 626 * Munge in any other fixed bits we require ... 627 */ 628 anar |= MII_AN_SELECTOR_8023; 629 630 /* 631 * Restart the PHY and write the new values. Note the 632 * time, so that we can say whether subsequent link state 633 * changes can be attributed to our reprogramming the PHY 634 */ 635 rge_phy_init(rgep); 636 rge_mii_put16(rgep, MII_AN_ADVERT, anar); 637 rge_mii_put16(rgep, MII_1000BASE_T_CONTROL, gigctrl); 638 rge_mii_put16(rgep, MII_CONTROL, control); 639 640 RGE_DEBUG(("rge_phy_update: anar <- 0x%x", anar)); 641 RGE_DEBUG(("rge_phy_update: control <- 0x%x", control)); 642 RGE_DEBUG(("rge_phy_update: gigctrl <- 0x%x", gigctrl)); 643 } 644 645 void rge_phy_init(rge_t *rgep); 646 #pragma no_inline(rge_phy_init) 647 648 void 649 rge_phy_init(rge_t *rgep) 650 { 651 rgep->phy_mii_addr = 1; 652 653 /* 654 * Below phy config steps are copied from the Programming Guide 655 * (there's no detail comments for these steps.) 656 */ 657 switch (rgep->chipid.mac_ver) { 658 case MAC_VER_8169S_D: 659 case MAC_VER_8169S_E : 660 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 661 rge_mii_put16(rgep, PHY_15_REG, 0x1000); 662 rge_mii_put16(rgep, PHY_18_REG, 0x65c7); 663 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000); 664 rge_mii_put16(rgep, PHY_ID_REG_2, 0x00a1); 665 rge_mii_put16(rgep, PHY_ID_REG_1, 0x0008); 666 rge_mii_put16(rgep, PHY_BMSR_REG, 0x1020); 667 rge_mii_put16(rgep, PHY_BMCR_REG, 0x1000); 668 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0800); 669 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000); 670 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7000); 671 rge_mii_put16(rgep, PHY_ID_REG_2, 0xff41); 672 rge_mii_put16(rgep, PHY_ID_REG_1, 0xde60); 673 rge_mii_put16(rgep, PHY_BMSR_REG, 0x0140); 674 rge_mii_put16(rgep, PHY_BMCR_REG, 0x0077); 675 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7800); 676 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7000); 677 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa000); 678 rge_mii_put16(rgep, PHY_ID_REG_2, 0xdf01); 679 rge_mii_put16(rgep, PHY_ID_REG_1, 0xdf20); 680 rge_mii_put16(rgep, PHY_BMSR_REG, 0xff95); 681 rge_mii_put16(rgep, PHY_BMCR_REG, 0xfa00); 682 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa800); 683 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa000); 684 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb000); 685 rge_mii_put16(rgep, PHY_ID_REG_2, 0xff41); 686 rge_mii_put16(rgep, PHY_ID_REG_1, 0xde20); 687 rge_mii_put16(rgep, PHY_BMSR_REG, 0x0140); 688 rge_mii_put16(rgep, PHY_BMCR_REG, 0x00bb); 689 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb800); 690 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb000); 691 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf000); 692 rge_mii_put16(rgep, PHY_ID_REG_2, 0xdf01); 693 rge_mii_put16(rgep, PHY_ID_REG_1, 0xdf20); 694 rge_mii_put16(rgep, PHY_BMSR_REG, 0xff95); 695 rge_mii_put16(rgep, PHY_BMCR_REG, 0xbf00); 696 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf800); 697 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf000); 698 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000); 699 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 700 rge_mii_put16(rgep, PHY_0B_REG, 0x0000); 701 break; 702 703 case MAC_VER_8169SB: 704 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 705 rge_mii_put16(rgep, PHY_1B_REG, 0xD41E); 706 rge_mii_put16(rgep, PHY_0E_REG, 0x7bff); 707 rge_mii_put16(rgep, PHY_GBCR_REG, GBCR_DEFAULT); 708 rge_mii_put16(rgep, PHY_1F_REG, 0x0002); 709 rge_mii_put16(rgep, PHY_BMSR_REG, 0x90D0); 710 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 711 break; 712 713 case MAC_VER_8169SC: 714 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 715 rge_mii_put16(rgep, PHY_ANER_REG, 0x0078); 716 rge_mii_put16(rgep, PHY_ANNPRR_REG, 0x05dc); 717 rge_mii_put16(rgep, PHY_GBCR_REG, 0x2672); 718 rge_mii_put16(rgep, PHY_GBSR_REG, 0x6a14); 719 rge_mii_put16(rgep, PHY_0B_REG, 0x7cb0); 720 rge_mii_put16(rgep, PHY_0C_REG, 0xdb80); 721 rge_mii_put16(rgep, PHY_1B_REG, 0xc414); 722 rge_mii_put16(rgep, PHY_1C_REG, 0xef03); 723 rge_mii_put16(rgep, PHY_1D_REG, 0x3dc8); 724 rge_mii_put16(rgep, PHY_1F_REG, 0x0003); 725 rge_mii_put16(rgep, PHY_13_REG, 0x0600); 726 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 727 break; 728 729 case MAC_VER_8168: 730 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 731 rge_mii_put16(rgep, PHY_ANER_REG, 0x00aa); 732 rge_mii_put16(rgep, PHY_ANNPTR_REG, 0x3173); 733 rge_mii_put16(rgep, PHY_ANNPRR_REG, 0x08fc); 734 rge_mii_put16(rgep, PHY_GBCR_REG, 0xe2d0); 735 rge_mii_put16(rgep, PHY_0B_REG, 0x941a); 736 rge_mii_put16(rgep, PHY_18_REG, 0x65fe); 737 rge_mii_put16(rgep, PHY_1C_REG, 0x1e02); 738 rge_mii_put16(rgep, PHY_1F_REG, 0x0002); 739 rge_mii_put16(rgep, PHY_ANNPTR_REG, 0x103e); 740 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 741 break; 742 743 case MAC_VER_8168B_B: 744 case MAC_VER_8168B_C: 745 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 746 rge_mii_put16(rgep, PHY_0B_REG, 0x94b0); 747 rge_mii_put16(rgep, PHY_1B_REG, 0xc416); 748 rge_mii_put16(rgep, PHY_1F_REG, 0x0003); 749 rge_mii_put16(rgep, PHY_12_REG, 0x6096); 750 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 751 break; 752 } 753 } 754 755 void rge_chip_ident(rge_t *rgep); 756 #pragma no_inline(rge_chip_ident) 757 758 void 759 rge_chip_ident(rge_t *rgep) 760 { 761 chip_id_t *chip = &rgep->chipid; 762 uint32_t val32; 763 uint16_t val16; 764 765 /* 766 * Read and record MAC version 767 */ 768 val32 = rge_reg_get32(rgep, TX_CONFIG_REG); 769 val32 &= HW_VERSION_ID_0 | HW_VERSION_ID_1; 770 chip->mac_ver = val32; 771 switch (chip->mac_ver) { 772 case MAC_VER_8168: 773 case MAC_VER_8168B_B: 774 case MAC_VER_8168B_C: 775 case MAC_VER_8101E: 776 chip->is_pcie = B_TRUE; 777 break; 778 779 default: 780 chip->is_pcie = B_FALSE; 781 break; 782 } 783 784 /* 785 * Read and record PHY version 786 */ 787 val16 = rge_mii_get16(rgep, PHY_ID_REG_2); 788 val16 &= PHY_VER_MASK; 789 chip->phy_ver = val16; 790 791 /* set pci latency timer */ 792 if (chip->mac_ver == MAC_VER_8169 || 793 chip->mac_ver == MAC_VER_8169S_D || 794 chip->mac_ver == MAC_VER_8169SC) 795 pci_config_put8(rgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 0x40); 796 797 if (chip->mac_ver == MAC_VER_8169SC) { 798 val16 = rge_reg_get16(rgep, RT_CONFIG_1_REG); 799 val16 &= 0x0300; 800 if (val16 == 0x1) /* 66Mhz PCI */ 801 pci_config_put32(rgep->cfg_handle, 0x7c, 0x00ff00ff); 802 else if (val16 == 0x0) /* 33Mhz PCI */ 803 pci_config_put32(rgep->cfg_handle, 0x7c, 0x00ffff00); 804 } 805 806 /* 807 * PCIE chipset require the Rx buffer start address must be 808 * 8-byte alignment and the Rx buffer size must be multiple of 8. 809 * We'll just use bcopy in receive procedure for the PCIE chipset. 810 */ 811 if (chip->is_pcie) { 812 rgep->chip_flags |= CHIP_FLAG_FORCE_BCOPY; 813 if (rgep->default_mtu > ETHERMTU) { 814 rge_notice(rgep, "Jumbo packets not supported " 815 "for this PCIE chipset"); 816 rgep->default_mtu = ETHERMTU; 817 } 818 } 819 if (rgep->chip_flags & CHIP_FLAG_FORCE_BCOPY) 820 rgep->head_room = 0; 821 else 822 rgep->head_room = RGE_HEADROOM; 823 824 /* 825 * Initialize other variables. 826 */ 827 if (rgep->default_mtu < ETHERMTU || rgep->default_mtu > RGE_JUMBO_MTU) 828 rgep->default_mtu = ETHERMTU; 829 if (rgep->default_mtu > ETHERMTU) { 830 rgep->rxbuf_size = RGE_BUFF_SIZE_JUMBO; 831 rgep->txbuf_size = RGE_BUFF_SIZE_JUMBO; 832 rgep->ethmax_size = RGE_JUMBO_SIZE; 833 } else { 834 rgep->rxbuf_size = RGE_BUFF_SIZE_STD; 835 rgep->txbuf_size = RGE_BUFF_SIZE_STD; 836 rgep->ethmax_size = ETHERMAX; 837 } 838 chip->rxconfig = RX_CONFIG_DEFAULT; 839 chip->txconfig = TX_CONFIG_DEFAULT; 840 841 RGE_TRACE(("%s: MAC version = %x, PHY version = %x", 842 rgep->ifname, chip->mac_ver, chip->phy_ver)); 843 } 844 845 /* 846 * Perform first-stage chip (re-)initialisation, using only config-space 847 * accesses: 848 * 849 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 850 * returning the data in the structure pointed to by <idp>. 851 * + Enable Memory Space accesses. 852 * + Enable Bus Mastering according. 853 */ 854 void rge_chip_cfg_init(rge_t *rgep, chip_id_t *cidp); 855 #pragma no_inline(rge_chip_cfg_init) 856 857 void 858 rge_chip_cfg_init(rge_t *rgep, chip_id_t *cidp) 859 { 860 ddi_acc_handle_t handle; 861 uint16_t commd; 862 863 handle = rgep->cfg_handle; 864 865 /* 866 * Save PCI cache line size and subsystem vendor ID 867 */ 868 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 869 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 870 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 871 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 872 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 873 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 874 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 875 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 876 877 /* 878 * Turn on Master Enable (DMA) and IO Enable bits. 879 * Enable PCI Memory Space accesses 880 */ 881 commd = cidp->command; 882 commd |= PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO; 883 pci_config_put16(handle, PCI_CONF_COMM, commd); 884 885 RGE_DEBUG(("rge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 886 cidp->vendor, cidp->device, cidp->revision)); 887 RGE_DEBUG(("rge_chip_cfg_init: subven 0x%x subdev 0x%x", 888 cidp->subven, cidp->subdev)); 889 RGE_DEBUG(("rge_chip_cfg_init: clsize %d latency %d command 0x%x", 890 cidp->clsize, cidp->latency, cidp->command)); 891 } 892 893 int rge_chip_reset(rge_t *rgep); 894 #pragma no_inline(rge_chip_reset) 895 896 int 897 rge_chip_reset(rge_t *rgep) 898 { 899 int i; 900 uint8_t val8; 901 902 /* 903 * Chip should be in STOP state 904 */ 905 rge_reg_clr8(rgep, RT_COMMAND_REG, 906 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 907 908 /* 909 * Disable interrupt 910 */ 911 rgep->int_mask = INT_MASK_NONE; 912 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 913 914 /* 915 * Clear pended interrupt 916 */ 917 rge_reg_put16(rgep, INT_STATUS_REG, INT_MASK_ALL); 918 919 /* 920 * Reset chip 921 */ 922 rge_reg_set8(rgep, RT_COMMAND_REG, RT_COMMAND_RESET); 923 924 /* 925 * Wait for reset success 926 */ 927 for (i = 0; i < CHIP_RESET_LOOP; i++) { 928 drv_usecwait(10); 929 val8 = rge_reg_get8(rgep, RT_COMMAND_REG); 930 if (!(val8 & RT_COMMAND_RESET)) { 931 rgep->rge_chip_state = RGE_CHIP_RESET; 932 return (0); 933 } 934 } 935 RGE_REPORT((rgep, "rge_chip_reset fail.")); 936 return (-1); 937 } 938 939 void rge_chip_init(rge_t *rgep); 940 #pragma no_inline(rge_chip_init) 941 942 void 943 rge_chip_init(rge_t *rgep) 944 { 945 uint32_t val32; 946 uint32_t val16; 947 uint32_t *hashp; 948 chip_id_t *chip = &rgep->chipid; 949 950 if (chip->is_pcie) { 951 /* 952 * Increase the threshold voltage of RX sensitivity 953 */ 954 if (chip->mac_ver != MAC_VER_8168) 955 rge_ephy_put16(rgep, 0x01, 0x1bd3); 956 957 val16 = rge_reg_get8(rgep, PHY_STATUS_REG); 958 val16 = 0x12<<8 | val16; 959 if (rgep->chipid.mac_ver != MAC_VER_8101E && 960 rgep->chipid.mac_ver != MAC_VER_8168B_C) { 961 rge_reg_put16(rgep, PHY_STATUS_REG, val16); 962 rge_reg_put32(rgep, RT_CSI_DATA_REG, 0x00021c01); 963 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f088); 964 rge_reg_put32(rgep, RT_CSI_DATA_REG, 0x00004000); 965 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f0b0); 966 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x0000f068); 967 val32 = rge_reg_get32(rgep, RT_CSI_DATA_REG); 968 val32 |= 0x7000; 969 val32 &= 0xffff5fff; 970 rge_reg_put32(rgep, RT_CSI_DATA_REG, val32); 971 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f068); 972 } 973 } 974 975 /* 976 * Config MII register 977 */ 978 rgep->param_link_up = LINK_STATE_DOWN; 979 rge_phy_update(rgep); 980 981 /* 982 * Enable Rx checksum offload. 983 * Then for vlan support, we must enable receive vlan de-tagging. 984 * Otherwise, there'll be checksum error. 985 */ 986 val16 = rge_reg_get16(rgep, CPLUS_COMMAND_REG); 987 val16 |= RX_CKSM_OFFLOAD | RX_VLAN_DETAG; 988 if (chip->mac_ver == MAC_VER_8169S_D) { 989 val16 |= CPLUS_BIT14 | MUL_PCI_RW_ENABLE; 990 rge_reg_put8(rgep, RESV_82_REG, 0x01); 991 } 992 rge_reg_put16(rgep, CPLUS_COMMAND_REG, val16 & (~0x03)); 993 994 /* 995 * Start transmit/receive before set tx/rx configuration register 996 */ 997 if (!chip->is_pcie) 998 rge_reg_set8(rgep, RT_COMMAND_REG, 999 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1000 1001 /* 1002 * Set dump tally counter register 1003 */ 1004 val32 = rgep->dma_area_stats.cookie.dmac_laddress >> 32; 1005 rge_reg_put32(rgep, DUMP_COUNTER_REG_1, val32); 1006 val32 = rge_reg_get32(rgep, DUMP_COUNTER_REG_0); 1007 val32 &= DUMP_COUNTER_REG_RESV; 1008 val32 |= rgep->dma_area_stats.cookie.dmac_laddress; 1009 rge_reg_put32(rgep, DUMP_COUNTER_REG_0, val32); 1010 1011 /* 1012 * Change to config register write enable mode 1013 */ 1014 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1015 1016 /* 1017 * Set Tx/Rx maximum packet size 1018 */ 1019 if (rgep->default_mtu > ETHERMTU) { 1020 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_JUMBO); 1021 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_JUMBO); 1022 } else if (rgep->chipid.mac_ver != MAC_VER_8101E) { 1023 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_STD); 1024 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_STD); 1025 } else { 1026 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_STD_8101E); 1027 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_STD_8101E); 1028 } 1029 1030 /* 1031 * Set receive configuration register 1032 */ 1033 val32 = rge_reg_get32(rgep, RX_CONFIG_REG); 1034 val32 &= RX_CONFIG_REG_RESV; 1035 if (rgep->promisc) 1036 val32 |= RX_ACCEPT_ALL_PKT; 1037 rge_reg_put32(rgep, RX_CONFIG_REG, val32 | chip->rxconfig); 1038 1039 /* 1040 * Set transmit configuration register 1041 */ 1042 val32 = rge_reg_get32(rgep, TX_CONFIG_REG); 1043 val32 &= TX_CONFIG_REG_RESV; 1044 rge_reg_put32(rgep, TX_CONFIG_REG, val32 | chip->txconfig); 1045 1046 /* 1047 * Set Tx/Rx descriptor register 1048 */ 1049 val32 = rgep->tx_desc.cookie.dmac_laddress; 1050 rge_reg_put32(rgep, NORMAL_TX_RING_ADDR_LO_REG, val32); 1051 val32 = rgep->tx_desc.cookie.dmac_laddress >> 32; 1052 rge_reg_put32(rgep, NORMAL_TX_RING_ADDR_HI_REG, val32); 1053 rge_reg_put32(rgep, HIGH_TX_RING_ADDR_LO_REG, 0); 1054 rge_reg_put32(rgep, HIGH_TX_RING_ADDR_HI_REG, 0); 1055 val32 = rgep->rx_desc.cookie.dmac_laddress; 1056 rge_reg_put32(rgep, RX_RING_ADDR_LO_REG, val32); 1057 val32 = rgep->rx_desc.cookie.dmac_laddress >> 32; 1058 rge_reg_put32(rgep, RX_RING_ADDR_HI_REG, val32); 1059 1060 /* 1061 * Suggested setting from Realtek 1062 */ 1063 if (rgep->chipid.mac_ver != MAC_VER_8101E) 1064 rge_reg_put16(rgep, RESV_E2_REG, 0x282a); 1065 else 1066 rge_reg_put16(rgep, RESV_E2_REG, 0x0000); 1067 1068 /* 1069 * Set multicast register 1070 */ 1071 hashp = (uint32_t *)rgep->mcast_hash; 1072 rge_reg_put32(rgep, MULTICAST_0_REG, hashp[0]); 1073 rge_reg_put32(rgep, MULTICAST_4_REG, hashp[1]); 1074 1075 /* 1076 * Msic register setting: 1077 * -- Missed packet counter: clear it 1078 * -- TimerInt Register 1079 * -- Timer count register 1080 */ 1081 rge_reg_put32(rgep, RX_PKT_MISS_COUNT_REG, 0); 1082 rge_reg_put32(rgep, TIMER_INT_REG, TIMER_INT_NONE); 1083 rge_reg_put32(rgep, TIMER_COUNT_REG, 0); 1084 1085 /* 1086 * Return to normal network/host communication mode 1087 */ 1088 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1089 drv_usecwait(20); 1090 } 1091 1092 /* 1093 * rge_chip_start() -- start the chip transmitting and/or receiving, 1094 * including enabling interrupts 1095 */ 1096 void rge_chip_start(rge_t *rgep); 1097 #pragma no_inline(rge_chip_start) 1098 1099 void 1100 rge_chip_start(rge_t *rgep) 1101 { 1102 /* 1103 * Clear statistics 1104 */ 1105 bzero(&rgep->stats, sizeof (rge_stats_t)); 1106 DMA_ZERO(rgep->dma_area_stats); 1107 1108 /* 1109 * Start transmit/receive 1110 */ 1111 rge_reg_set8(rgep, RT_COMMAND_REG, 1112 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1113 1114 /* 1115 * Enable interrupt 1116 */ 1117 rgep->int_mask = RGE_INT_MASK; 1118 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 1119 1120 /* 1121 * All done! 1122 */ 1123 rgep->rge_chip_state = RGE_CHIP_RUNNING; 1124 } 1125 1126 /* 1127 * rge_chip_stop() -- stop board receiving 1128 */ 1129 void rge_chip_stop(rge_t *rgep, boolean_t fault); 1130 #pragma no_inline(rge_chip_stop) 1131 1132 void 1133 rge_chip_stop(rge_t *rgep, boolean_t fault) 1134 { 1135 /* 1136 * Disable interrupt 1137 */ 1138 rgep->int_mask = INT_MASK_NONE; 1139 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 1140 1141 /* 1142 * Clear pended interrupt 1143 */ 1144 rge_reg_put16(rgep, INT_STATUS_REG, INT_MASK_ALL); 1145 1146 /* 1147 * Stop the board and disable transmit/receive 1148 */ 1149 rge_reg_clr8(rgep, RT_COMMAND_REG, 1150 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1151 1152 if (fault) 1153 rgep->rge_chip_state = RGE_CHIP_FAULT; 1154 else 1155 rgep->rge_chip_state = RGE_CHIP_STOPPED; 1156 } 1157 1158 /* 1159 * rge_get_mac_addr() -- get the MAC address on NIC 1160 */ 1161 static void rge_get_mac_addr(rge_t *rgep); 1162 #pragma inline(rge_get_mac_addr) 1163 1164 static void 1165 rge_get_mac_addr(rge_t *rgep) 1166 { 1167 uint8_t *macaddr = rgep->netaddr; 1168 uint32_t val32; 1169 1170 /* 1171 * Read first 4-byte of mac address 1172 */ 1173 val32 = rge_reg_get32(rgep, ID_0_REG); 1174 macaddr[0] = val32 & 0xff; 1175 val32 = val32 >> 8; 1176 macaddr[1] = val32 & 0xff; 1177 val32 = val32 >> 8; 1178 macaddr[2] = val32 & 0xff; 1179 val32 = val32 >> 8; 1180 macaddr[3] = val32 & 0xff; 1181 1182 /* 1183 * Read last 2-byte of mac address 1184 */ 1185 val32 = rge_reg_get32(rgep, ID_4_REG); 1186 macaddr[4] = val32 & 0xff; 1187 val32 = val32 >> 8; 1188 macaddr[5] = val32 & 0xff; 1189 } 1190 1191 static void rge_set_mac_addr(rge_t *rgep); 1192 #pragma inline(rge_set_mac_addr) 1193 1194 static void 1195 rge_set_mac_addr(rge_t *rgep) 1196 { 1197 uint8_t *p = rgep->netaddr; 1198 uint32_t val32; 1199 1200 /* 1201 * Change to config register write enable mode 1202 */ 1203 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1204 1205 /* 1206 * Get first 4 bytes of mac address 1207 */ 1208 val32 = p[3]; 1209 val32 = val32 << 8; 1210 val32 |= p[2]; 1211 val32 = val32 << 8; 1212 val32 |= p[1]; 1213 val32 = val32 << 8; 1214 val32 |= p[0]; 1215 1216 /* 1217 * Set first 4 bytes of mac address 1218 */ 1219 rge_reg_put32(rgep, ID_0_REG, val32); 1220 1221 /* 1222 * Get last 2 bytes of mac address 1223 */ 1224 val32 = p[5]; 1225 val32 = val32 << 8; 1226 val32 |= p[4]; 1227 1228 /* 1229 * Set last 2 bytes of mac address 1230 */ 1231 val32 |= rge_reg_get32(rgep, ID_4_REG) & ~0xffff; 1232 rge_reg_put32(rgep, ID_4_REG, val32); 1233 1234 /* 1235 * Return to normal network/host communication mode 1236 */ 1237 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1238 } 1239 1240 static void rge_set_multi_addr(rge_t *rgep); 1241 #pragma inline(rge_set_multi_addr) 1242 1243 static void 1244 rge_set_multi_addr(rge_t *rgep) 1245 { 1246 uint32_t *hashp; 1247 1248 hashp = (uint32_t *)rgep->mcast_hash; 1249 1250 /* 1251 * Change to config register write enable mode 1252 */ 1253 if (rgep->chipid.mac_ver == MAC_VER_8169SC) 1254 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1255 1256 rge_reg_put32(rgep, MULTICAST_0_REG, RGE_BSWAP_32(hashp[0])); 1257 rge_reg_put32(rgep, MULTICAST_4_REG, RGE_BSWAP_32(hashp[1])); 1258 1259 /* 1260 * Return to normal network/host communication mode 1261 */ 1262 if (rgep->chipid.mac_ver == MAC_VER_8169SC) 1263 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1264 } 1265 1266 static void rge_set_promisc(rge_t *rgep); 1267 #pragma inline(rge_set_promisc) 1268 1269 static void 1270 rge_set_promisc(rge_t *rgep) 1271 { 1272 if (rgep->promisc) 1273 rge_reg_set32(rgep, RX_CONFIG_REG, RX_ACCEPT_ALL_PKT); 1274 else 1275 rge_reg_clr32(rgep, RX_CONFIG_REG, RX_ACCEPT_ALL_PKT); 1276 } 1277 1278 /* 1279 * rge_chip_sync() -- program the chip with the unicast MAC address, 1280 * the multicast hash table, the required level of promiscuity, and 1281 * the current loopback mode ... 1282 */ 1283 void rge_chip_sync(rge_t *rgep, enum rge_sync_op todo); 1284 #pragma no_inline(rge_chip_sync) 1285 1286 void 1287 rge_chip_sync(rge_t *rgep, enum rge_sync_op todo) 1288 { 1289 switch (todo) { 1290 case RGE_GET_MAC: 1291 rge_get_mac_addr(rgep); 1292 break; 1293 case RGE_SET_MAC: 1294 /* Reprogram the unicast MAC address(es) ... */ 1295 rge_set_mac_addr(rgep); 1296 break; 1297 case RGE_SET_MUL: 1298 /* Reprogram the hashed multicast address table ... */ 1299 rge_set_multi_addr(rgep); 1300 break; 1301 case RGE_SET_PROMISC: 1302 /* Set or clear the PROMISCUOUS mode bit */ 1303 rge_set_promisc(rgep); 1304 break; 1305 default: 1306 break; 1307 } 1308 } 1309 1310 void rge_chip_blank(void *arg, time_t ticks, uint_t count); 1311 #pragma no_inline(rge_chip_blank) 1312 1313 void 1314 rge_chip_blank(void *arg, time_t ticks, uint_t count) 1315 { 1316 _NOTE(ARGUNUSED(arg, ticks, count)); 1317 } 1318 1319 void rge_tx_trigger(rge_t *rgep); 1320 #pragma no_inline(rge_tx_trigger) 1321 1322 void 1323 rge_tx_trigger(rge_t *rgep) 1324 { 1325 rge_reg_set8(rgep, TX_RINGS_POLL_REG, NORMAL_TX_RING_POLL); 1326 } 1327 1328 void rge_hw_stats_dump(rge_t *rgep); 1329 #pragma no_inline(rge_tx_trigger) 1330 1331 void 1332 rge_hw_stats_dump(rge_t *rgep) 1333 { 1334 int i = 0; 1335 1336 while (rge_reg_get32(rgep, DUMP_COUNTER_REG_0) & DUMP_START) { 1337 drv_usecwait(100); 1338 if (++i > STATS_DUMP_LOOP) { 1339 RGE_DEBUG(("rge h/w statistics dump fail!")); 1340 rgep->rge_chip_state = RGE_CHIP_ERROR; 1341 return; 1342 } 1343 } 1344 DMA_SYNC(rgep->dma_area_stats, DDI_DMA_SYNC_FORKERNEL); 1345 1346 /* 1347 * Start H/W statistics dump for RTL8169 chip 1348 */ 1349 rge_reg_set32(rgep, DUMP_COUNTER_REG_0, DUMP_START); 1350 } 1351 1352 /* 1353 * ========== Hardware interrupt handler ========== 1354 */ 1355 1356 #undef RGE_DBG 1357 #define RGE_DBG RGE_DBG_INT /* debug flag for this code */ 1358 1359 static void rge_wake_factotum(rge_t *rgep); 1360 #pragma inline(rge_wake_factotum) 1361 1362 static void 1363 rge_wake_factotum(rge_t *rgep) 1364 { 1365 if (rgep->factotum_flag == 0) { 1366 rgep->factotum_flag = 1; 1367 (void) ddi_intr_trigger_softint(rgep->factotum_hdl, NULL); 1368 } 1369 } 1370 1371 /* 1372 * rge_intr() -- handle chip interrupts 1373 */ 1374 uint_t rge_intr(caddr_t arg1, caddr_t arg2); 1375 #pragma no_inline(rge_intr) 1376 1377 uint_t 1378 rge_intr(caddr_t arg1, caddr_t arg2) 1379 { 1380 rge_t *rgep = (rge_t *)arg1; 1381 uint16_t int_status; 1382 1383 _NOTE(ARGUNUSED(arg2)) 1384 1385 mutex_enter(rgep->genlock); 1386 /* 1387 * Was this interrupt caused by our device... 1388 */ 1389 int_status = rge_reg_get16(rgep, INT_STATUS_REG); 1390 if (!(int_status & rgep->int_mask)) { 1391 mutex_exit(rgep->genlock); 1392 return (DDI_INTR_UNCLAIMED); 1393 /* indicate it wasn't our interrupt */ 1394 } 1395 rgep->stats.intr++; 1396 1397 /* 1398 * Clear interrupt 1399 * For PCIE chipset, we need disable interrupt first. 1400 */ 1401 if (rgep->chipid.is_pcie) 1402 rge_reg_put16(rgep, INT_MASK_REG, INT_MASK_NONE); 1403 rge_reg_put16(rgep, INT_STATUS_REG, int_status); 1404 1405 /* 1406 * Cable link change interrupt 1407 */ 1408 if (int_status & LINK_CHANGE_INT) { 1409 rge_chip_cyclic(rgep); 1410 } 1411 1412 mutex_exit(rgep->genlock); 1413 1414 /* 1415 * Receive interrupt 1416 */ 1417 if (int_status & RGE_RX_INT) 1418 rge_receive(rgep); 1419 1420 /* 1421 * Re-enable interrupt for PCIE chipset 1422 */ 1423 if (rgep->chipid.is_pcie) 1424 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 1425 1426 return (DDI_INTR_CLAIMED); /* indicate it was our interrupt */ 1427 } 1428 1429 /* 1430 * ========== Factotum, implemented as a softint handler ========== 1431 */ 1432 1433 #undef RGE_DBG 1434 #define RGE_DBG RGE_DBG_FACT /* debug flag for this code */ 1435 1436 static boolean_t rge_factotum_link_check(rge_t *rgep); 1437 #pragma no_inline(rge_factotum_link_check) 1438 1439 static boolean_t 1440 rge_factotum_link_check(rge_t *rgep) 1441 { 1442 uint8_t media_status; 1443 int32_t link; 1444 1445 media_status = rge_reg_get8(rgep, PHY_STATUS_REG); 1446 link = (media_status & PHY_STATUS_LINK_UP) ? 1447 LINK_STATE_UP : LINK_STATE_DOWN; 1448 if (rgep->param_link_up != link) { 1449 /* 1450 * Link change. 1451 */ 1452 rgep->param_link_up = link; 1453 1454 if (link == LINK_STATE_UP) { 1455 if (media_status & PHY_STATUS_1000MF) { 1456 rgep->param_link_speed = RGE_SPEED_1000M; 1457 rgep->param_link_duplex = LINK_DUPLEX_FULL; 1458 } else { 1459 rgep->param_link_speed = 1460 (media_status & PHY_STATUS_100M) ? 1461 RGE_SPEED_100M : RGE_SPEED_10M; 1462 rgep->param_link_duplex = 1463 (media_status & PHY_STATUS_DUPLEX_FULL) ? 1464 LINK_DUPLEX_FULL : LINK_DUPLEX_HALF; 1465 } 1466 } 1467 return (B_TRUE); 1468 } 1469 return (B_FALSE); 1470 } 1471 1472 /* 1473 * Factotum routine to check for Tx stall, using the 'watchdog' counter 1474 */ 1475 static boolean_t rge_factotum_stall_check(rge_t *rgep); 1476 #pragma no_inline(rge_factotum_stall_check) 1477 1478 static boolean_t 1479 rge_factotum_stall_check(rge_t *rgep) 1480 { 1481 uint32_t dogval; 1482 1483 ASSERT(mutex_owned(rgep->genlock)); 1484 1485 /* 1486 * Specific check for Tx stall ... 1487 * 1488 * The 'watchdog' counter is incremented whenever a packet 1489 * is queued, reset to 1 when some (but not all) buffers 1490 * are reclaimed, reset to 0 (disabled) when all buffers 1491 * are reclaimed, and shifted left here. If it exceeds the 1492 * threshold value, the chip is assumed to have stalled and 1493 * is put into the ERROR state. The factotum will then reset 1494 * it on the next pass. 1495 * 1496 * All of which should ensure that we don't get into a state 1497 * where packets are left pending indefinitely! 1498 */ 1499 if (rgep->resched_needed) 1500 (void) ddi_intr_trigger_softint(rgep->resched_hdl, NULL); 1501 dogval = rge_atomic_shl32(&rgep->watchdog, 1); 1502 if (dogval < rge_watchdog_count) 1503 return (B_FALSE); 1504 1505 RGE_REPORT((rgep, "Tx stall detected, watchdog code 0x%x", dogval)); 1506 return (B_TRUE); 1507 1508 } 1509 1510 /* 1511 * The factotum is woken up when there's something to do that we'd rather 1512 * not do from inside a hardware interrupt handler or high-level cyclic. 1513 * Its two main tasks are: 1514 * reset & restart the chip after an error 1515 * check the link status whenever necessary 1516 */ 1517 uint_t rge_chip_factotum(caddr_t arg1, caddr_t arg2); 1518 #pragma no_inline(rge_chip_factotum) 1519 1520 uint_t 1521 rge_chip_factotum(caddr_t arg1, caddr_t arg2) 1522 { 1523 rge_t *rgep; 1524 uint_t result; 1525 boolean_t error; 1526 boolean_t linkchg; 1527 1528 rgep = (rge_t *)arg1; 1529 _NOTE(ARGUNUSED(arg2)) 1530 1531 if (rgep->factotum_flag == 0) 1532 return (DDI_INTR_UNCLAIMED); 1533 1534 rgep->factotum_flag = 0; 1535 result = DDI_INTR_CLAIMED; 1536 error = B_FALSE; 1537 linkchg = B_FALSE; 1538 1539 mutex_enter(rgep->genlock); 1540 switch (rgep->rge_chip_state) { 1541 default: 1542 break; 1543 1544 case RGE_CHIP_RUNNING: 1545 linkchg = rge_factotum_link_check(rgep); 1546 error = rge_factotum_stall_check(rgep); 1547 break; 1548 1549 case RGE_CHIP_ERROR: 1550 error = B_TRUE; 1551 break; 1552 1553 case RGE_CHIP_FAULT: 1554 /* 1555 * Fault detected, time to reset ... 1556 */ 1557 if (rge_autorecover) { 1558 RGE_REPORT((rgep, "automatic recovery activated")); 1559 rge_restart(rgep); 1560 } 1561 break; 1562 } 1563 1564 /* 1565 * If an error is detected, stop the chip now, marking it as 1566 * faulty, so that it will be reset next time through ... 1567 */ 1568 if (error) 1569 rge_chip_stop(rgep, B_TRUE); 1570 mutex_exit(rgep->genlock); 1571 1572 /* 1573 * If the link state changed, tell the world about it. 1574 * Note: can't do this while still holding the mutex. 1575 */ 1576 if (linkchg) 1577 mac_link_update(rgep->mh, rgep->param_link_up); 1578 1579 return (result); 1580 } 1581 1582 /* 1583 * High-level cyclic handler 1584 * 1585 * This routine schedules a (low-level) softint callback to the 1586 * factotum, and prods the chip to update the status block (which 1587 * will cause a hardware interrupt when complete). 1588 */ 1589 void rge_chip_cyclic(void *arg); 1590 #pragma no_inline(rge_chip_cyclic) 1591 1592 void 1593 rge_chip_cyclic(void *arg) 1594 { 1595 rge_t *rgep; 1596 1597 rgep = arg; 1598 1599 switch (rgep->rge_chip_state) { 1600 default: 1601 return; 1602 1603 case RGE_CHIP_RUNNING: 1604 rge_phy_check(rgep); 1605 break; 1606 1607 case RGE_CHIP_FAULT: 1608 case RGE_CHIP_ERROR: 1609 break; 1610 } 1611 1612 rge_wake_factotum(rgep); 1613 } 1614 1615 1616 /* 1617 * ========== Ioctl subfunctions ========== 1618 */ 1619 1620 #undef RGE_DBG 1621 #define RGE_DBG RGE_DBG_PPIO /* debug flag for this code */ 1622 1623 #if RGE_DEBUGGING || RGE_DO_PPIO 1624 1625 static void rge_chip_peek_cfg(rge_t *rgep, rge_peekpoke_t *ppd); 1626 #pragma no_inline(rge_chip_peek_cfg) 1627 1628 static void 1629 rge_chip_peek_cfg(rge_t *rgep, rge_peekpoke_t *ppd) 1630 { 1631 uint64_t regval; 1632 uint64_t regno; 1633 1634 RGE_TRACE(("rge_chip_peek_cfg($%p, $%p)", 1635 (void *)rgep, (void *)ppd)); 1636 1637 regno = ppd->pp_acc_offset; 1638 1639 switch (ppd->pp_acc_size) { 1640 case 1: 1641 regval = pci_config_get8(rgep->cfg_handle, regno); 1642 break; 1643 1644 case 2: 1645 regval = pci_config_get16(rgep->cfg_handle, regno); 1646 break; 1647 1648 case 4: 1649 regval = pci_config_get32(rgep->cfg_handle, regno); 1650 break; 1651 1652 case 8: 1653 regval = pci_config_get64(rgep->cfg_handle, regno); 1654 break; 1655 } 1656 1657 ppd->pp_acc_data = regval; 1658 } 1659 1660 static void rge_chip_poke_cfg(rge_t *rgep, rge_peekpoke_t *ppd); 1661 #pragma no_inline(rge_chip_poke_cfg) 1662 1663 static void 1664 rge_chip_poke_cfg(rge_t *rgep, rge_peekpoke_t *ppd) 1665 { 1666 uint64_t regval; 1667 uint64_t regno; 1668 1669 RGE_TRACE(("rge_chip_poke_cfg($%p, $%p)", 1670 (void *)rgep, (void *)ppd)); 1671 1672 regno = ppd->pp_acc_offset; 1673 regval = ppd->pp_acc_data; 1674 1675 switch (ppd->pp_acc_size) { 1676 case 1: 1677 pci_config_put8(rgep->cfg_handle, regno, regval); 1678 break; 1679 1680 case 2: 1681 pci_config_put16(rgep->cfg_handle, regno, regval); 1682 break; 1683 1684 case 4: 1685 pci_config_put32(rgep->cfg_handle, regno, regval); 1686 break; 1687 1688 case 8: 1689 pci_config_put64(rgep->cfg_handle, regno, regval); 1690 break; 1691 } 1692 } 1693 1694 static void rge_chip_peek_reg(rge_t *rgep, rge_peekpoke_t *ppd); 1695 #pragma no_inline(rge_chip_peek_reg) 1696 1697 static void 1698 rge_chip_peek_reg(rge_t *rgep, rge_peekpoke_t *ppd) 1699 { 1700 uint64_t regval; 1701 void *regaddr; 1702 1703 RGE_TRACE(("rge_chip_peek_reg($%p, $%p)", 1704 (void *)rgep, (void *)ppd)); 1705 1706 regaddr = PIO_ADDR(rgep, ppd->pp_acc_offset); 1707 1708 switch (ppd->pp_acc_size) { 1709 case 1: 1710 regval = ddi_get8(rgep->io_handle, regaddr); 1711 break; 1712 1713 case 2: 1714 regval = ddi_get16(rgep->io_handle, regaddr); 1715 break; 1716 1717 case 4: 1718 regval = ddi_get32(rgep->io_handle, regaddr); 1719 break; 1720 1721 case 8: 1722 regval = ddi_get64(rgep->io_handle, regaddr); 1723 break; 1724 } 1725 1726 ppd->pp_acc_data = regval; 1727 } 1728 1729 static void rge_chip_poke_reg(rge_t *rgep, rge_peekpoke_t *ppd); 1730 #pragma no_inline(rge_chip_peek_reg) 1731 1732 static void 1733 rge_chip_poke_reg(rge_t *rgep, rge_peekpoke_t *ppd) 1734 { 1735 uint64_t regval; 1736 void *regaddr; 1737 1738 RGE_TRACE(("rge_chip_poke_reg($%p, $%p)", 1739 (void *)rgep, (void *)ppd)); 1740 1741 regaddr = PIO_ADDR(rgep, ppd->pp_acc_offset); 1742 regval = ppd->pp_acc_data; 1743 1744 switch (ppd->pp_acc_size) { 1745 case 1: 1746 ddi_put8(rgep->io_handle, regaddr, regval); 1747 break; 1748 1749 case 2: 1750 ddi_put16(rgep->io_handle, regaddr, regval); 1751 break; 1752 1753 case 4: 1754 ddi_put32(rgep->io_handle, regaddr, regval); 1755 break; 1756 1757 case 8: 1758 ddi_put64(rgep->io_handle, regaddr, regval); 1759 break; 1760 } 1761 } 1762 1763 static void rge_chip_peek_mii(rge_t *rgep, rge_peekpoke_t *ppd); 1764 #pragma no_inline(rge_chip_peek_mii) 1765 1766 static void 1767 rge_chip_peek_mii(rge_t *rgep, rge_peekpoke_t *ppd) 1768 { 1769 RGE_TRACE(("rge_chip_peek_mii($%p, $%p)", 1770 (void *)rgep, (void *)ppd)); 1771 1772 ppd->pp_acc_data = rge_mii_get16(rgep, ppd->pp_acc_offset/2); 1773 } 1774 1775 static void rge_chip_poke_mii(rge_t *rgep, rge_peekpoke_t *ppd); 1776 #pragma no_inline(rge_chip_poke_mii) 1777 1778 static void 1779 rge_chip_poke_mii(rge_t *rgep, rge_peekpoke_t *ppd) 1780 { 1781 RGE_TRACE(("rge_chip_poke_mii($%p, $%p)", 1782 (void *)rgep, (void *)ppd)); 1783 1784 rge_mii_put16(rgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 1785 } 1786 1787 static void rge_chip_peek_mem(rge_t *rgep, rge_peekpoke_t *ppd); 1788 #pragma no_inline(rge_chip_peek_mem) 1789 1790 static void 1791 rge_chip_peek_mem(rge_t *rgep, rge_peekpoke_t *ppd) 1792 { 1793 uint64_t regval; 1794 void *vaddr; 1795 1796 RGE_TRACE(("rge_chip_peek_rge($%p, $%p)", 1797 (void *)rgep, (void *)ppd)); 1798 1799 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 1800 1801 switch (ppd->pp_acc_size) { 1802 case 1: 1803 regval = *(uint8_t *)vaddr; 1804 break; 1805 1806 case 2: 1807 regval = *(uint16_t *)vaddr; 1808 break; 1809 1810 case 4: 1811 regval = *(uint32_t *)vaddr; 1812 break; 1813 1814 case 8: 1815 regval = *(uint64_t *)vaddr; 1816 break; 1817 } 1818 1819 RGE_DEBUG(("rge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 1820 (void *)rgep, (void *)ppd, regval, vaddr)); 1821 1822 ppd->pp_acc_data = regval; 1823 } 1824 1825 static void rge_chip_poke_mem(rge_t *rgep, rge_peekpoke_t *ppd); 1826 #pragma no_inline(rge_chip_poke_mem) 1827 1828 static void 1829 rge_chip_poke_mem(rge_t *rgep, rge_peekpoke_t *ppd) 1830 { 1831 uint64_t regval; 1832 void *vaddr; 1833 1834 RGE_TRACE(("rge_chip_poke_mem($%p, $%p)", 1835 (void *)rgep, (void *)ppd)); 1836 1837 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 1838 regval = ppd->pp_acc_data; 1839 1840 RGE_DEBUG(("rge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 1841 (void *)rgep, (void *)ppd, regval, vaddr)); 1842 1843 switch (ppd->pp_acc_size) { 1844 case 1: 1845 *(uint8_t *)vaddr = (uint8_t)regval; 1846 break; 1847 1848 case 2: 1849 *(uint16_t *)vaddr = (uint16_t)regval; 1850 break; 1851 1852 case 4: 1853 *(uint32_t *)vaddr = (uint32_t)regval; 1854 break; 1855 1856 case 8: 1857 *(uint64_t *)vaddr = (uint64_t)regval; 1858 break; 1859 } 1860 } 1861 1862 static enum ioc_reply rge_pp_ioctl(rge_t *rgep, int cmd, mblk_t *mp, 1863 struct iocblk *iocp); 1864 #pragma no_inline(rge_pp_ioctl) 1865 1866 static enum ioc_reply 1867 rge_pp_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp) 1868 { 1869 void (*ppfn)(rge_t *rgep, rge_peekpoke_t *ppd); 1870 rge_peekpoke_t *ppd; 1871 dma_area_t *areap; 1872 uint64_t sizemask; 1873 uint64_t mem_va; 1874 uint64_t maxoff; 1875 boolean_t peek; 1876 1877 switch (cmd) { 1878 default: 1879 /* NOTREACHED */ 1880 rge_error(rgep, "rge_pp_ioctl: invalid cmd 0x%x", cmd); 1881 return (IOC_INVAL); 1882 1883 case RGE_PEEK: 1884 peek = B_TRUE; 1885 break; 1886 1887 case RGE_POKE: 1888 peek = B_FALSE; 1889 break; 1890 } 1891 1892 /* 1893 * Validate format of ioctl 1894 */ 1895 if (iocp->ioc_count != sizeof (rge_peekpoke_t)) 1896 return (IOC_INVAL); 1897 if (mp->b_cont == NULL) 1898 return (IOC_INVAL); 1899 ppd = (rge_peekpoke_t *)mp->b_cont->b_rptr; 1900 1901 /* 1902 * Validate request parameters 1903 */ 1904 switch (ppd->pp_acc_space) { 1905 default: 1906 return (IOC_INVAL); 1907 1908 case RGE_PP_SPACE_CFG: 1909 /* 1910 * Config space 1911 */ 1912 sizemask = 8|4|2|1; 1913 mem_va = 0; 1914 maxoff = PCI_CONF_HDR_SIZE; 1915 ppfn = peek ? rge_chip_peek_cfg : rge_chip_poke_cfg; 1916 break; 1917 1918 case RGE_PP_SPACE_REG: 1919 /* 1920 * Memory-mapped I/O space 1921 */ 1922 sizemask = 8|4|2|1; 1923 mem_va = 0; 1924 maxoff = RGE_REGISTER_MAX; 1925 ppfn = peek ? rge_chip_peek_reg : rge_chip_poke_reg; 1926 break; 1927 1928 case RGE_PP_SPACE_MII: 1929 /* 1930 * PHY's MII registers 1931 * NB: all PHY registers are two bytes, but the 1932 * addresses increment in ones (word addressing). 1933 * So we scale the address here, then undo the 1934 * transformation inside the peek/poke functions. 1935 */ 1936 ppd->pp_acc_offset *= 2; 1937 sizemask = 2; 1938 mem_va = 0; 1939 maxoff = (MII_MAXREG+1)*2; 1940 ppfn = peek ? rge_chip_peek_mii : rge_chip_poke_mii; 1941 break; 1942 1943 case RGE_PP_SPACE_RGE: 1944 /* 1945 * RGE data structure! 1946 */ 1947 sizemask = 8|4|2|1; 1948 mem_va = (uintptr_t)rgep; 1949 maxoff = sizeof (*rgep); 1950 ppfn = peek ? rge_chip_peek_mem : rge_chip_poke_mem; 1951 break; 1952 1953 case RGE_PP_SPACE_STATISTICS: 1954 case RGE_PP_SPACE_TXDESC: 1955 case RGE_PP_SPACE_TXBUFF: 1956 case RGE_PP_SPACE_RXDESC: 1957 case RGE_PP_SPACE_RXBUFF: 1958 /* 1959 * Various DMA_AREAs 1960 */ 1961 switch (ppd->pp_acc_space) { 1962 case RGE_PP_SPACE_TXDESC: 1963 areap = &rgep->dma_area_txdesc; 1964 break; 1965 case RGE_PP_SPACE_RXDESC: 1966 areap = &rgep->dma_area_rxdesc; 1967 break; 1968 case RGE_PP_SPACE_STATISTICS: 1969 areap = &rgep->dma_area_stats; 1970 break; 1971 } 1972 1973 sizemask = 8|4|2|1; 1974 mem_va = (uintptr_t)areap->mem_va; 1975 maxoff = areap->alength; 1976 ppfn = peek ? rge_chip_peek_mem : rge_chip_poke_mem; 1977 break; 1978 } 1979 1980 switch (ppd->pp_acc_size) { 1981 default: 1982 return (IOC_INVAL); 1983 1984 case 8: 1985 case 4: 1986 case 2: 1987 case 1: 1988 if ((ppd->pp_acc_size & sizemask) == 0) 1989 return (IOC_INVAL); 1990 break; 1991 } 1992 1993 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 1994 return (IOC_INVAL); 1995 1996 if (ppd->pp_acc_offset >= maxoff) 1997 return (IOC_INVAL); 1998 1999 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 2000 return (IOC_INVAL); 2001 2002 /* 2003 * All OK - go do it! 2004 */ 2005 ppd->pp_acc_offset += mem_va; 2006 (*ppfn)(rgep, ppd); 2007 return (peek ? IOC_REPLY : IOC_ACK); 2008 } 2009 2010 static enum ioc_reply rge_diag_ioctl(rge_t *rgep, int cmd, mblk_t *mp, 2011 struct iocblk *iocp); 2012 #pragma no_inline(rge_diag_ioctl) 2013 2014 static enum ioc_reply 2015 rge_diag_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp) 2016 { 2017 ASSERT(mutex_owned(rgep->genlock)); 2018 2019 switch (cmd) { 2020 default: 2021 /* NOTREACHED */ 2022 rge_error(rgep, "rge_diag_ioctl: invalid cmd 0x%x", cmd); 2023 return (IOC_INVAL); 2024 2025 case RGE_DIAG: 2026 /* 2027 * Currently a no-op 2028 */ 2029 return (IOC_ACK); 2030 2031 case RGE_PEEK: 2032 case RGE_POKE: 2033 return (rge_pp_ioctl(rgep, cmd, mp, iocp)); 2034 2035 case RGE_PHY_RESET: 2036 return (IOC_RESTART_ACK); 2037 2038 case RGE_SOFT_RESET: 2039 case RGE_HARD_RESET: 2040 /* 2041 * Reset and reinitialise the 570x hardware 2042 */ 2043 rge_restart(rgep); 2044 return (IOC_ACK); 2045 } 2046 2047 /* NOTREACHED */ 2048 } 2049 2050 #endif /* RGE_DEBUGGING || RGE_DO_PPIO */ 2051 2052 static enum ioc_reply rge_mii_ioctl(rge_t *rgep, int cmd, mblk_t *mp, 2053 struct iocblk *iocp); 2054 #pragma no_inline(rge_mii_ioctl) 2055 2056 static enum ioc_reply 2057 rge_mii_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp) 2058 { 2059 struct rge_mii_rw *miirwp; 2060 2061 /* 2062 * Validate format of ioctl 2063 */ 2064 if (iocp->ioc_count != sizeof (struct rge_mii_rw)) 2065 return (IOC_INVAL); 2066 if (mp->b_cont == NULL) 2067 return (IOC_INVAL); 2068 miirwp = (struct rge_mii_rw *)mp->b_cont->b_rptr; 2069 2070 /* 2071 * Validate request parameters ... 2072 */ 2073 if (miirwp->mii_reg > MII_MAXREG) 2074 return (IOC_INVAL); 2075 2076 switch (cmd) { 2077 default: 2078 /* NOTREACHED */ 2079 rge_error(rgep, "rge_mii_ioctl: invalid cmd 0x%x", cmd); 2080 return (IOC_INVAL); 2081 2082 case RGE_MII_READ: 2083 miirwp->mii_data = rge_mii_get16(rgep, miirwp->mii_reg); 2084 return (IOC_REPLY); 2085 2086 case RGE_MII_WRITE: 2087 rge_mii_put16(rgep, miirwp->mii_reg, miirwp->mii_data); 2088 return (IOC_ACK); 2089 } 2090 2091 /* NOTREACHED */ 2092 } 2093 2094 enum ioc_reply rge_chip_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp, 2095 struct iocblk *iocp); 2096 #pragma no_inline(rge_chip_ioctl) 2097 2098 enum ioc_reply 2099 rge_chip_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 2100 { 2101 int cmd; 2102 2103 RGE_TRACE(("rge_chip_ioctl($%p, $%p, $%p, $%p)", 2104 (void *)rgep, (void *)wq, (void *)mp, (void *)iocp)); 2105 2106 ASSERT(mutex_owned(rgep->genlock)); 2107 2108 cmd = iocp->ioc_cmd; 2109 switch (cmd) { 2110 default: 2111 /* NOTREACHED */ 2112 rge_error(rgep, "rge_chip_ioctl: invalid cmd 0x%x", cmd); 2113 return (IOC_INVAL); 2114 2115 case RGE_DIAG: 2116 case RGE_PEEK: 2117 case RGE_POKE: 2118 case RGE_PHY_RESET: 2119 case RGE_SOFT_RESET: 2120 case RGE_HARD_RESET: 2121 #if RGE_DEBUGGING || RGE_DO_PPIO 2122 return (rge_diag_ioctl(rgep, cmd, mp, iocp)); 2123 #else 2124 return (IOC_INVAL); 2125 #endif /* RGE_DEBUGGING || RGE_DO_PPIO */ 2126 2127 case RGE_MII_READ: 2128 case RGE_MII_WRITE: 2129 return (rge_mii_ioctl(rgep, cmd, mp, iocp)); 2130 2131 } 2132 2133 /* NOTREACHED */ 2134 } 2135