1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include "rge.h" 29 30 #define REG32(rgep, reg) ((uint32_t *)(rgep->io_regs+(reg))) 31 #define REG16(rgep, reg) ((uint16_t *)(rgep->io_regs+(reg))) 32 #define REG8(rgep, reg) ((uint8_t *)(rgep->io_regs+(reg))) 33 #define PIO_ADDR(rgep, offset) ((void *)(rgep->io_regs+(offset))) 34 35 /* 36 * Patchable globals: 37 * 38 * rge_autorecover 39 * Enables/disables automatic recovery after fault detection 40 */ 41 static uint32_t rge_autorecover = 1; 42 43 /* 44 * globals: 45 */ 46 #define RGE_DBG RGE_DBG_REGS /* debug flag for this code */ 47 static uint32_t rge_watchdog_count = 1 << 16; 48 49 /* 50 * Operating register get/set access routines 51 */ 52 #if RGE_DEBUGGING 53 54 static void rge_pci_check(rge_t *rgep); 55 #pragma no_inline(rge_pci_check) 56 57 static void 58 rge_pci_check(rge_t *rgep) 59 { 60 uint16_t pcistatus; 61 62 pcistatus = pci_config_get16(rgep->cfg_handle, PCI_CONF_STAT); 63 if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0) 64 RGE_DEBUG(("rge_pci_check($%p): PCI status 0x%x", 65 (void *)rgep, pcistatus)); 66 } 67 68 #endif /* RGE_DEBUGGING */ 69 70 static uint32_t rge_reg_get32(rge_t *rgep, uintptr_t regno); 71 #pragma inline(rge_reg_get32) 72 73 static uint32_t 74 rge_reg_get32(rge_t *rgep, uintptr_t regno) 75 { 76 RGE_TRACE(("rge_reg_get32($%p, 0x%lx)", 77 (void *)rgep, regno)); 78 79 return (ddi_get32(rgep->io_handle, REG32(rgep, regno))); 80 } 81 82 static void rge_reg_put32(rge_t *rgep, uintptr_t regno, uint32_t data); 83 #pragma inline(rge_reg_put32) 84 85 static void 86 rge_reg_put32(rge_t *rgep, uintptr_t regno, uint32_t data) 87 { 88 RGE_TRACE(("rge_reg_put32($%p, 0x%lx, 0x%x)", 89 (void *)rgep, regno, data)); 90 91 ddi_put32(rgep->io_handle, REG32(rgep, regno), data); 92 RGE_PCICHK(rgep); 93 } 94 95 static void rge_reg_set32(rge_t *rgep, uintptr_t regno, uint32_t bits); 96 #pragma inline(rge_reg_set32) 97 98 static void 99 rge_reg_set32(rge_t *rgep, uintptr_t regno, uint32_t bits) 100 { 101 uint32_t regval; 102 103 RGE_TRACE(("rge_reg_set32($%p, 0x%lx, 0x%x)", 104 (void *)rgep, regno, bits)); 105 106 regval = rge_reg_get32(rgep, regno); 107 regval |= bits; 108 rge_reg_put32(rgep, regno, regval); 109 } 110 111 static void rge_reg_clr32(rge_t *rgep, uintptr_t regno, uint32_t bits); 112 #pragma inline(rge_reg_clr32) 113 114 static void 115 rge_reg_clr32(rge_t *rgep, uintptr_t regno, uint32_t bits) 116 { 117 uint32_t regval; 118 119 RGE_TRACE(("rge_reg_clr32($%p, 0x%lx, 0x%x)", 120 (void *)rgep, regno, bits)); 121 122 regval = rge_reg_get32(rgep, regno); 123 regval &= ~bits; 124 rge_reg_put32(rgep, regno, regval); 125 } 126 127 static uint16_t rge_reg_get16(rge_t *rgep, uintptr_t regno); 128 #pragma inline(rge_reg_get16) 129 130 static uint16_t 131 rge_reg_get16(rge_t *rgep, uintptr_t regno) 132 { 133 RGE_TRACE(("rge_reg_get16($%p, 0x%lx)", 134 (void *)rgep, regno)); 135 136 return (ddi_get16(rgep->io_handle, REG16(rgep, regno))); 137 } 138 139 static void rge_reg_put16(rge_t *rgep, uintptr_t regno, uint16_t data); 140 #pragma inline(rge_reg_put16) 141 142 static void 143 rge_reg_put16(rge_t *rgep, uintptr_t regno, uint16_t data) 144 { 145 RGE_TRACE(("rge_reg_put16($%p, 0x%lx, 0x%x)", 146 (void *)rgep, regno, data)); 147 148 ddi_put16(rgep->io_handle, REG16(rgep, regno), data); 149 RGE_PCICHK(rgep); 150 } 151 152 static void rge_reg_set16(rge_t *rgep, uintptr_t regno, uint16_t bits); 153 #pragma inline(rge_reg_set16) 154 155 static void 156 rge_reg_set16(rge_t *rgep, uintptr_t regno, uint16_t bits) 157 { 158 uint16_t regval; 159 160 RGE_TRACE(("rge_reg_set16($%p, 0x%lx, 0x%x)", 161 (void *)rgep, regno, bits)); 162 163 regval = rge_reg_get16(rgep, regno); 164 regval |= bits; 165 rge_reg_put16(rgep, regno, regval); 166 } 167 168 static void rge_reg_clr16(rge_t *rgep, uintptr_t regno, uint16_t bits); 169 #pragma inline(rge_reg_clr16) 170 171 static void 172 rge_reg_clr16(rge_t *rgep, uintptr_t regno, uint16_t bits) 173 { 174 uint16_t regval; 175 176 RGE_TRACE(("rge_reg_clr16($%p, 0x%lx, 0x%x)", 177 (void *)rgep, regno, bits)); 178 179 regval = rge_reg_get16(rgep, regno); 180 regval &= ~bits; 181 rge_reg_put16(rgep, regno, regval); 182 } 183 184 static uint8_t rge_reg_get8(rge_t *rgep, uintptr_t regno); 185 #pragma inline(rge_reg_get8) 186 187 static uint8_t 188 rge_reg_get8(rge_t *rgep, uintptr_t regno) 189 { 190 RGE_TRACE(("rge_reg_get8($%p, 0x%lx)", 191 (void *)rgep, regno)); 192 193 return (ddi_get8(rgep->io_handle, REG8(rgep, regno))); 194 } 195 196 static void rge_reg_put8(rge_t *rgep, uintptr_t regno, uint8_t data); 197 #pragma inline(rge_reg_put8) 198 199 static void 200 rge_reg_put8(rge_t *rgep, uintptr_t regno, uint8_t data) 201 { 202 RGE_TRACE(("rge_reg_put8($%p, 0x%lx, 0x%x)", 203 (void *)rgep, regno, data)); 204 205 ddi_put8(rgep->io_handle, REG8(rgep, regno), data); 206 RGE_PCICHK(rgep); 207 } 208 209 static void rge_reg_set8(rge_t *rgep, uintptr_t regno, uint8_t bits); 210 #pragma inline(rge_reg_set8) 211 212 static void 213 rge_reg_set8(rge_t *rgep, uintptr_t regno, uint8_t bits) 214 { 215 uint8_t regval; 216 217 RGE_TRACE(("rge_reg_set8($%p, 0x%lx, 0x%x)", 218 (void *)rgep, regno, bits)); 219 220 regval = rge_reg_get8(rgep, regno); 221 regval |= bits; 222 rge_reg_put8(rgep, regno, regval); 223 } 224 225 static void rge_reg_clr8(rge_t *rgep, uintptr_t regno, uint8_t bits); 226 #pragma inline(rge_reg_clr8) 227 228 static void 229 rge_reg_clr8(rge_t *rgep, uintptr_t regno, uint8_t bits) 230 { 231 uint8_t regval; 232 233 RGE_TRACE(("rge_reg_clr8($%p, 0x%lx, 0x%x)", 234 (void *)rgep, regno, bits)); 235 236 regval = rge_reg_get8(rgep, regno); 237 regval &= ~bits; 238 rge_reg_put8(rgep, regno, regval); 239 } 240 241 uint16_t rge_mii_get16(rge_t *rgep, uintptr_t mii); 242 #pragma no_inline(rge_mii_get16) 243 244 uint16_t 245 rge_mii_get16(rge_t *rgep, uintptr_t mii) 246 { 247 uint32_t regval; 248 uint32_t val32; 249 uint32_t i; 250 251 regval = (mii & PHY_REG_MASK) << PHY_REG_SHIFT; 252 rge_reg_put32(rgep, PHY_ACCESS_REG, regval); 253 254 /* 255 * Waiting for PHY reading OK 256 */ 257 for (i = 0; i < PHY_RESET_LOOP; i++) { 258 drv_usecwait(100); 259 val32 = rge_reg_get32(rgep, PHY_ACCESS_REG); 260 if (val32 & PHY_ACCESS_WR_FLAG) 261 return ((uint16_t)(val32 & 0xffff)); 262 } 263 264 RGE_REPORT((rgep, "rge_mii_get16(0x%x) fail, val = %x", mii, val32)); 265 return ((uint16_t)~0u); 266 } 267 268 void rge_mii_put16(rge_t *rgep, uintptr_t mii, uint16_t data); 269 #pragma no_inline(rge_mii_put16) 270 271 void 272 rge_mii_put16(rge_t *rgep, uintptr_t mii, uint16_t data) 273 { 274 uint32_t regval; 275 uint32_t val32; 276 uint32_t i; 277 278 regval = (mii & PHY_REG_MASK) << PHY_REG_SHIFT; 279 regval |= data & PHY_DATA_MASK; 280 regval |= PHY_ACCESS_WR_FLAG; 281 rge_reg_put32(rgep, PHY_ACCESS_REG, regval); 282 283 /* 284 * Waiting for PHY writing OK 285 */ 286 for (i = 0; i < PHY_RESET_LOOP; i++) { 287 drv_usecwait(100); 288 val32 = rge_reg_get32(rgep, PHY_ACCESS_REG); 289 if (!(val32 & PHY_ACCESS_WR_FLAG)) 290 return; 291 } 292 RGE_REPORT((rgep, "rge_mii_put16(0x%lx, 0x%x) fail", 293 mii, data)); 294 } 295 296 void rge_ephy_put16(rge_t *rgep, uintptr_t emii, uint16_t data); 297 #pragma no_inline(rge_ephy_put16) 298 299 void 300 rge_ephy_put16(rge_t *rgep, uintptr_t emii, uint16_t data) 301 { 302 uint32_t regval; 303 uint32_t val32; 304 uint32_t i; 305 306 regval = (emii & EPHY_REG_MASK) << EPHY_REG_SHIFT; 307 regval |= data & EPHY_DATA_MASK; 308 regval |= EPHY_ACCESS_WR_FLAG; 309 rge_reg_put32(rgep, EPHY_ACCESS_REG, regval); 310 311 /* 312 * Waiting for PHY writing OK 313 */ 314 for (i = 0; i < PHY_RESET_LOOP; i++) { 315 drv_usecwait(100); 316 val32 = rge_reg_get32(rgep, EPHY_ACCESS_REG); 317 if (!(val32 & EPHY_ACCESS_WR_FLAG)) 318 return; 319 } 320 RGE_REPORT((rgep, "rge_ephy_put16(0x%lx, 0x%x) fail", 321 emii, data)); 322 } 323 324 /* 325 * Atomically shift a 32-bit word left, returning 326 * the value it had *before* the shift was applied 327 */ 328 static uint32_t rge_atomic_shl32(uint32_t *sp, uint_t count); 329 #pragma inline(rge_mii_put16) 330 331 static uint32_t 332 rge_atomic_shl32(uint32_t *sp, uint_t count) 333 { 334 uint32_t oldval; 335 uint32_t newval; 336 337 /* ATOMICALLY */ 338 do { 339 oldval = *sp; 340 newval = oldval << count; 341 } while (cas32(sp, oldval, newval) != oldval); 342 343 return (oldval); 344 } 345 346 /* 347 * PHY operation routines 348 */ 349 #if RGE_DEBUGGING 350 351 static void 352 rge_phydump(rge_t *rgep) 353 { 354 uint16_t regs[32]; 355 int i; 356 357 ASSERT(mutex_owned(rgep->genlock)); 358 359 for (i = 0; i < 32; ++i) { 360 regs[i] = rge_mii_get16(rgep, i); 361 } 362 363 for (i = 0; i < 32; i += 8) 364 RGE_DEBUG(("rge_phydump: " 365 "0x%04x %04x %04x %04x %04x %04x %04x %04x", 366 regs[i+0], regs[i+1], regs[i+2], regs[i+3], 367 regs[i+4], regs[i+5], regs[i+6], regs[i+7])); 368 } 369 370 #endif /* RGE_DEBUGGING */ 371 372 /* 373 * Basic low-level function to probe for a PHY 374 * 375 * Returns TRUE if the PHY responds with valid data, FALSE otherwise 376 */ 377 static boolean_t 378 rge_phy_probe(rge_t *rgep) 379 { 380 uint16_t phy_status; 381 382 ASSERT(mutex_owned(rgep->genlock)); 383 384 /* 385 * Read the MII_STATUS register twice, in 386 * order to clear any sticky bits (but they should 387 * have been cleared by the RESET, I think). 388 */ 389 phy_status = rge_mii_get16(rgep, MII_STATUS); 390 phy_status = rge_mii_get16(rgep, MII_STATUS); 391 RGE_DEBUG(("rge_phy_probe: status 0x%x", phy_status)); 392 393 /* 394 * Now check the value read; it should have at least one bit set 395 * (for the device capabilities) and at least one clear (one of 396 * the error bits). So if we see all 0s or all 1s, there's a 397 * problem. In particular, rge_mii_get16() returns all 1s if 398 * communications fails ... 399 */ 400 switch (phy_status) { 401 case 0x0000: 402 case 0xffff: 403 return (B_FALSE); 404 405 default : 406 return (B_TRUE); 407 } 408 } 409 410 static void 411 rge_phy_check(rge_t *rgep) 412 { 413 uint16_t gig_ctl; 414 415 if (rgep->param_link_up == LINK_STATE_DOWN) { 416 /* 417 * RTL8169S/8110S PHY has the "PCS bug". Need reset PHY 418 * every 15 seconds whin link down & advertise is 1000. 419 */ 420 if (rgep->chipid.phy_ver == PHY_VER_S) { 421 gig_ctl = rge_mii_get16(rgep, MII_1000BASE_T_CONTROL); 422 if (gig_ctl & MII_1000BT_CTL_ADV_FDX) { 423 rgep->link_down_count++; 424 if (rgep->link_down_count > 15) { 425 (void) rge_phy_reset(rgep); 426 rgep->stats.phy_reset++; 427 rgep->link_down_count = 0; 428 } 429 } 430 } 431 } else { 432 rgep->link_down_count = 0; 433 } 434 } 435 436 /* 437 * Basic low-level function to reset the PHY. 438 * Doesn't incorporate any special-case workarounds. 439 * 440 * Returns TRUE on success, FALSE if the RESET bit doesn't clear 441 */ 442 boolean_t 443 rge_phy_reset(rge_t *rgep) 444 { 445 uint16_t control; 446 uint_t count; 447 448 /* 449 * Set the PHY RESET bit, then wait up to 5 ms for it to self-clear 450 */ 451 control = rge_mii_get16(rgep, MII_CONTROL); 452 rge_mii_put16(rgep, MII_CONTROL, control | MII_CONTROL_RESET); 453 for (count = 0; ++count < 1000; ) { 454 drv_usecwait(100); 455 control = rge_mii_get16(rgep, MII_CONTROL); 456 if (BIC(control, MII_CONTROL_RESET)) 457 return (B_TRUE); 458 } 459 460 RGE_REPORT((rgep, "rge_phy_reset: FAILED, control now 0x%x", control)); 461 return (B_FALSE); 462 } 463 464 /* 465 * Synchronise the PHY's speed/duplex/autonegotiation capabilities 466 * and advertisements with the required settings as specified by the various 467 * param_* variables that can be poked via the NDD interface. 468 * 469 * We always reset the PHY and reprogram *all* the relevant registers, 470 * not just those changed. This should cause the link to go down, and then 471 * back up again once the link is stable and autonegotiation (if enabled) 472 * is complete. We should get a link state change interrupt somewhere along 473 * the way ... 474 * 475 * NOTE: <genlock> must already be held by the caller 476 */ 477 void 478 rge_phy_update(rge_t *rgep) 479 { 480 boolean_t adv_autoneg; 481 boolean_t adv_pause; 482 boolean_t adv_asym_pause; 483 boolean_t adv_1000fdx; 484 boolean_t adv_1000hdx; 485 boolean_t adv_100fdx; 486 boolean_t adv_100hdx; 487 boolean_t adv_10fdx; 488 boolean_t adv_10hdx; 489 490 uint16_t control; 491 uint16_t gigctrl; 492 uint16_t anar; 493 494 ASSERT(mutex_owned(rgep->genlock)); 495 496 RGE_DEBUG(("rge_phy_update: autoneg %d " 497 "pause %d asym_pause %d " 498 "1000fdx %d 1000hdx %d " 499 "100fdx %d 100hdx %d " 500 "10fdx %d 10hdx %d ", 501 rgep->param_adv_autoneg, 502 rgep->param_adv_pause, rgep->param_adv_asym_pause, 503 rgep->param_adv_1000fdx, rgep->param_adv_1000hdx, 504 rgep->param_adv_100fdx, rgep->param_adv_100hdx, 505 rgep->param_adv_10fdx, rgep->param_adv_10hdx)); 506 507 control = gigctrl = anar = 0; 508 509 /* 510 * PHY settings are normally based on the param_* variables, 511 * but if any loopback mode is in effect, that takes precedence. 512 * 513 * RGE supports MAC-internal loopback, PHY-internal loopback, 514 * and External loopback at a variety of speeds (with a special 515 * cable). In all cases, autoneg is turned OFF, full-duplex 516 * is turned ON, and the speed/mastership is forced. 517 */ 518 switch (rgep->param_loop_mode) { 519 case RGE_LOOP_NONE: 520 default: 521 adv_autoneg = rgep->param_adv_autoneg; 522 adv_pause = rgep->param_adv_pause; 523 adv_asym_pause = rgep->param_adv_asym_pause; 524 adv_1000fdx = rgep->param_adv_1000fdx; 525 adv_1000hdx = rgep->param_adv_1000hdx; 526 adv_100fdx = rgep->param_adv_100fdx; 527 adv_100hdx = rgep->param_adv_100hdx; 528 adv_10fdx = rgep->param_adv_10fdx; 529 adv_10hdx = rgep->param_adv_10hdx; 530 break; 531 532 case RGE_LOOP_INTERNAL_PHY: 533 case RGE_LOOP_INTERNAL_MAC: 534 adv_autoneg = adv_pause = adv_asym_pause = B_FALSE; 535 adv_1000fdx = adv_100fdx = adv_10fdx = B_FALSE; 536 adv_1000hdx = adv_100hdx = adv_10hdx = B_FALSE; 537 rgep->param_link_duplex = LINK_DUPLEX_FULL; 538 539 switch (rgep->param_loop_mode) { 540 case RGE_LOOP_INTERNAL_PHY: 541 rgep->param_link_speed = 1000; 542 adv_1000fdx = B_TRUE; 543 control = MII_CONTROL_LOOPBACK; 544 break; 545 546 case RGE_LOOP_INTERNAL_MAC: 547 rgep->param_link_speed = 1000; 548 adv_1000fdx = B_TRUE; 549 break; 550 } 551 } 552 553 RGE_DEBUG(("rge_phy_update: autoneg %d " 554 "pause %d asym_pause %d " 555 "1000fdx %d 1000hdx %d " 556 "100fdx %d 100hdx %d " 557 "10fdx %d 10hdx %d ", 558 adv_autoneg, 559 adv_pause, adv_asym_pause, 560 adv_1000fdx, adv_1000hdx, 561 adv_100fdx, adv_100hdx, 562 adv_10fdx, adv_10hdx)); 563 564 /* 565 * We should have at least one technology capability set; 566 * if not, we select a default of 1000Mb/s full-duplex 567 */ 568 if (!adv_1000fdx && !adv_100fdx && !adv_10fdx && 569 !adv_1000hdx && !adv_100hdx && !adv_10hdx) 570 adv_1000fdx = B_TRUE; 571 572 /* 573 * Now transform the adv_* variables into the proper settings 574 * of the PHY registers ... 575 * 576 * If autonegotiation is (now) enabled, we want to trigger 577 * a new autonegotiation cycle once the PHY has been 578 * programmed with the capabilities to be advertised. 579 * 580 * RTL8169/8110 doesn't support 1000Mb/s half-duplex. 581 */ 582 if (adv_autoneg) 583 control |= MII_CONTROL_ANE|MII_CONTROL_RSAN; 584 585 if (adv_1000fdx) 586 control |= MII_CONTROL_1000MB|MII_CONTROL_FDUPLEX; 587 else if (adv_1000hdx) 588 control |= MII_CONTROL_1000MB; 589 else if (adv_100fdx) 590 control |= MII_CONTROL_100MB|MII_CONTROL_FDUPLEX; 591 else if (adv_100hdx) 592 control |= MII_CONTROL_100MB; 593 else if (adv_10fdx) 594 control |= MII_CONTROL_FDUPLEX; 595 else if (adv_10hdx) 596 control |= 0; 597 else 598 { _NOTE(EMPTY); } /* Can't get here anyway ... */ 599 600 if (adv_1000fdx) { 601 gigctrl |= MII_1000BT_CTL_ADV_FDX; 602 /* 603 * Chipset limitation: need set other capabilities to true 604 */ 605 if (rgep->chipid.is_pcie) 606 adv_1000hdx = B_TRUE; 607 adv_100fdx = B_TRUE; 608 adv_100hdx = B_TRUE; 609 adv_10fdx = B_TRUE; 610 adv_10hdx = B_TRUE; 611 } 612 613 if (adv_1000hdx) 614 gigctrl |= MII_1000BT_CTL_ADV_HDX; 615 616 if (adv_100fdx) 617 anar |= MII_ABILITY_100BASE_TX_FD; 618 if (adv_100hdx) 619 anar |= MII_ABILITY_100BASE_TX; 620 if (adv_10fdx) 621 anar |= MII_ABILITY_10BASE_T_FD; 622 if (adv_10hdx) 623 anar |= MII_ABILITY_10BASE_T; 624 625 if (adv_pause) 626 anar |= MII_ABILITY_PAUSE; 627 if (adv_asym_pause) 628 anar |= MII_ABILITY_ASYM_PAUSE; 629 630 /* 631 * Munge in any other fixed bits we require ... 632 */ 633 anar |= MII_AN_SELECTOR_8023; 634 635 /* 636 * Restart the PHY and write the new values. Note the 637 * time, so that we can say whether subsequent link state 638 * changes can be attributed to our reprogramming the PHY 639 */ 640 rge_phy_init(rgep); 641 rge_mii_put16(rgep, MII_AN_ADVERT, anar); 642 rge_mii_put16(rgep, MII_1000BASE_T_CONTROL, gigctrl); 643 rge_mii_put16(rgep, MII_CONTROL, control); 644 645 RGE_DEBUG(("rge_phy_update: anar <- 0x%x", anar)); 646 RGE_DEBUG(("rge_phy_update: control <- 0x%x", control)); 647 RGE_DEBUG(("rge_phy_update: gigctrl <- 0x%x", gigctrl)); 648 } 649 650 void rge_phy_init(rge_t *rgep); 651 #pragma no_inline(rge_phy_init) 652 653 void 654 rge_phy_init(rge_t *rgep) 655 { 656 rgep->phy_mii_addr = 1; 657 658 /* 659 * Below phy config steps are copied from the Programming Guide 660 * (there's no detail comments for these steps.) 661 */ 662 switch (rgep->chipid.mac_ver) { 663 case MAC_VER_8169S_D: 664 case MAC_VER_8169S_E : 665 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 666 rge_mii_put16(rgep, PHY_15_REG, 0x1000); 667 rge_mii_put16(rgep, PHY_18_REG, 0x65c7); 668 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000); 669 rge_mii_put16(rgep, PHY_ID_REG_2, 0x00a1); 670 rge_mii_put16(rgep, PHY_ID_REG_1, 0x0008); 671 rge_mii_put16(rgep, PHY_BMSR_REG, 0x1020); 672 rge_mii_put16(rgep, PHY_BMCR_REG, 0x1000); 673 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0800); 674 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000); 675 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7000); 676 rge_mii_put16(rgep, PHY_ID_REG_2, 0xff41); 677 rge_mii_put16(rgep, PHY_ID_REG_1, 0xde60); 678 rge_mii_put16(rgep, PHY_BMSR_REG, 0x0140); 679 rge_mii_put16(rgep, PHY_BMCR_REG, 0x0077); 680 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7800); 681 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7000); 682 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa000); 683 rge_mii_put16(rgep, PHY_ID_REG_2, 0xdf01); 684 rge_mii_put16(rgep, PHY_ID_REG_1, 0xdf20); 685 rge_mii_put16(rgep, PHY_BMSR_REG, 0xff95); 686 rge_mii_put16(rgep, PHY_BMCR_REG, 0xfa00); 687 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa800); 688 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa000); 689 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb000); 690 rge_mii_put16(rgep, PHY_ID_REG_2, 0xff41); 691 rge_mii_put16(rgep, PHY_ID_REG_1, 0xde20); 692 rge_mii_put16(rgep, PHY_BMSR_REG, 0x0140); 693 rge_mii_put16(rgep, PHY_BMCR_REG, 0x00bb); 694 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb800); 695 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb000); 696 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf000); 697 rge_mii_put16(rgep, PHY_ID_REG_2, 0xdf01); 698 rge_mii_put16(rgep, PHY_ID_REG_1, 0xdf20); 699 rge_mii_put16(rgep, PHY_BMSR_REG, 0xff95); 700 rge_mii_put16(rgep, PHY_BMCR_REG, 0xbf00); 701 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf800); 702 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf000); 703 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000); 704 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 705 rge_mii_put16(rgep, PHY_0B_REG, 0x0000); 706 break; 707 708 case MAC_VER_8169SB: 709 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 710 rge_mii_put16(rgep, PHY_1B_REG, 0xD41E); 711 rge_mii_put16(rgep, PHY_0E_REG, 0x7bff); 712 rge_mii_put16(rgep, PHY_GBCR_REG, GBCR_DEFAULT); 713 rge_mii_put16(rgep, PHY_1F_REG, 0x0002); 714 rge_mii_put16(rgep, PHY_BMSR_REG, 0x90D0); 715 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 716 break; 717 718 case MAC_VER_8168: 719 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 720 rge_mii_put16(rgep, PHY_ANER_REG, 0x00aa); 721 rge_mii_put16(rgep, PHY_ANNPTR_REG, 0x3173); 722 rge_mii_put16(rgep, PHY_ANNPRR_REG, 0x08fc); 723 rge_mii_put16(rgep, PHY_GBCR_REG, 0xe2d0); 724 rge_mii_put16(rgep, PHY_0B_REG, 0x941a); 725 rge_mii_put16(rgep, PHY_18_REG, 0x65fe); 726 rge_mii_put16(rgep, PHY_1C_REG, 0x1e02); 727 rge_mii_put16(rgep, PHY_1F_REG, 0x0002); 728 rge_mii_put16(rgep, PHY_ANNPTR_REG, 0x103e); 729 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 730 break; 731 732 case MAC_VER_8168B_B: 733 case MAC_VER_8168B_C: 734 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 735 rge_mii_put16(rgep, PHY_0B_REG, 0x94b0); 736 rge_mii_put16(rgep, PHY_1B_REG, 0xc416); 737 rge_mii_put16(rgep, PHY_1F_REG, 0x0003); 738 rge_mii_put16(rgep, PHY_12_REG, 0x6096); 739 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 740 break; 741 } 742 } 743 744 void rge_chip_ident(rge_t *rgep); 745 #pragma no_inline(rge_chip_ident) 746 747 void 748 rge_chip_ident(rge_t *rgep) 749 { 750 chip_id_t *chip = &rgep->chipid; 751 uint32_t val32; 752 uint16_t val16; 753 754 /* 755 * Read and record MAC version 756 */ 757 val32 = rge_reg_get32(rgep, TX_CONFIG_REG); 758 val32 &= HW_VERSION_ID_0 | HW_VERSION_ID_1; 759 chip->mac_ver = val32; 760 switch (chip->mac_ver) { 761 case MAC_VER_8168: 762 case MAC_VER_8168B_B: 763 case MAC_VER_8168B_C: 764 chip->is_pcie = B_TRUE; 765 break; 766 767 default: 768 chip->is_pcie = B_FALSE; 769 break; 770 } 771 772 /* 773 * Read and record PHY version 774 */ 775 val16 = rge_mii_get16(rgep, PHY_ID_REG_2); 776 val16 &= PHY_VER_MASK; 777 chip->phy_ver = val16; 778 779 /* set pci latency timer */ 780 if (chip->mac_ver == MAC_VER_8169 || 781 chip->mac_ver == MAC_VER_8169S_D) 782 pci_config_put8(rgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 0x40); 783 784 /* 785 * PCIE chipset require the Rx buffer start address must be 786 * 8-byte alignment and the Rx buffer size must be multiple of 8. 787 * We'll just use bcopy in receive procedure for the PCIE chipset. 788 */ 789 if (chip->is_pcie) { 790 rgep->chip_flags |= CHIP_FLAG_FORCE_BCOPY; 791 if (rgep->default_mtu > ETHERMTU) { 792 rge_notice(rgep, "Jumbo packets not supported " 793 "for this PCIE chipset"); 794 rgep->default_mtu = ETHERMTU; 795 } 796 } 797 if (rgep->chip_flags & CHIP_FLAG_FORCE_BCOPY) 798 rgep->head_room = 0; 799 else 800 rgep->head_room = RGE_HEADROOM; 801 802 /* 803 * Initialize other variables. 804 */ 805 if (rgep->default_mtu < ETHERMTU || rgep->default_mtu > RGE_JUMBO_MTU) 806 rgep->default_mtu = ETHERMTU; 807 if (rgep->default_mtu > ETHERMTU) { 808 rgep->rxbuf_size = RGE_BUFF_SIZE_JUMBO; 809 rgep->txbuf_size = RGE_BUFF_SIZE_JUMBO; 810 rgep->ethmax_size = RGE_JUMBO_SIZE; 811 } else { 812 rgep->rxbuf_size = RGE_BUFF_SIZE_STD; 813 rgep->txbuf_size = RGE_BUFF_SIZE_STD; 814 rgep->ethmax_size = ETHERMAX; 815 } 816 chip->rxconfig = RX_CONFIG_DEFAULT; 817 chip->txconfig = TX_CONFIG_DEFAULT; 818 819 RGE_TRACE(("%s: MAC version = %x, PHY version = %x", 820 rgep->ifname, chip->mac_ver, chip->phy_ver)); 821 } 822 823 /* 824 * Perform first-stage chip (re-)initialisation, using only config-space 825 * accesses: 826 * 827 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 828 * returning the data in the structure pointed to by <idp>. 829 * + Enable Memory Space accesses. 830 * + Enable Bus Mastering according. 831 */ 832 void rge_chip_cfg_init(rge_t *rgep, chip_id_t *cidp); 833 #pragma no_inline(rge_chip_cfg_init) 834 835 void 836 rge_chip_cfg_init(rge_t *rgep, chip_id_t *cidp) 837 { 838 ddi_acc_handle_t handle; 839 uint16_t commd; 840 841 handle = rgep->cfg_handle; 842 843 /* 844 * Save PCI cache line size and subsystem vendor ID 845 */ 846 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 847 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 848 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 849 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 850 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 851 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 852 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 853 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 854 855 /* 856 * Turn on Master Enable (DMA) and IO Enable bits. 857 * Enable PCI Memory Space accesses 858 */ 859 commd = cidp->command; 860 commd |= PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO; 861 pci_config_put16(handle, PCI_CONF_COMM, commd); 862 863 RGE_DEBUG(("rge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 864 cidp->vendor, cidp->device, cidp->revision)); 865 RGE_DEBUG(("rge_chip_cfg_init: subven 0x%x subdev 0x%x", 866 cidp->subven, cidp->subdev)); 867 RGE_DEBUG(("rge_chip_cfg_init: clsize %d latency %d command 0x%x", 868 cidp->clsize, cidp->latency, cidp->command)); 869 } 870 871 int rge_chip_reset(rge_t *rgep); 872 #pragma no_inline(rge_chip_reset) 873 874 int 875 rge_chip_reset(rge_t *rgep) 876 { 877 int i; 878 uint8_t val8; 879 880 /* 881 * Chip should be in STOP state 882 */ 883 rge_reg_clr8(rgep, RT_COMMAND_REG, 884 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 885 886 /* 887 * Disable interrupt 888 */ 889 rgep->int_mask = INT_MASK_NONE; 890 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 891 892 /* 893 * Clear pended interrupt 894 */ 895 rge_reg_put16(rgep, INT_STATUS_REG, INT_MASK_ALL); 896 897 /* 898 * Reset chip 899 */ 900 rge_reg_set8(rgep, RT_COMMAND_REG, RT_COMMAND_RESET); 901 902 /* 903 * Wait for reset success 904 */ 905 for (i = 0; i < CHIP_RESET_LOOP; i++) { 906 drv_usecwait(10); 907 val8 = rge_reg_get8(rgep, RT_COMMAND_REG); 908 if (!(val8 & RT_COMMAND_RESET)) { 909 rgep->rge_chip_state = RGE_CHIP_RESET; 910 return (0); 911 } 912 } 913 RGE_REPORT((rgep, "rge_chip_reset fail.")); 914 return (-1); 915 } 916 917 void rge_chip_init(rge_t *rgep); 918 #pragma no_inline(rge_chip_init) 919 920 void 921 rge_chip_init(rge_t *rgep) 922 { 923 uint32_t val32; 924 uint32_t val16; 925 uint32_t *hashp; 926 chip_id_t *chip = &rgep->chipid; 927 928 if (chip->is_pcie) { 929 /* 930 * Increase the threshold voltage of RX sensitivity 931 */ 932 if (chip->mac_ver != MAC_VER_8168) 933 rge_ephy_put16(rgep, 0x01, 0x1bd3); 934 935 val16 = rge_reg_get8(rgep, PHY_STATUS_REG); 936 val16 = 0x12<<8 | val16; 937 rge_reg_put16(rgep, PHY_STATUS_REG, val16); 938 rge_reg_put32(rgep, RT_CSI_DATA_REG, 0x00021c01); 939 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f088); 940 rge_reg_put32(rgep, RT_CSI_DATA_REG, 0x00004000); 941 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f0b0); 942 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x0000f068); 943 val32 = rge_reg_get32(rgep, RT_CSI_DATA_REG); 944 val32 |= 0x7000; 945 val32 &= 0xffff5fff; 946 rge_reg_put32(rgep, RT_CSI_DATA_REG, val32); 947 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f068); 948 } 949 950 /* 951 * Config MII register 952 */ 953 rgep->param_link_up = LINK_STATE_DOWN; 954 rge_phy_update(rgep); 955 956 /* 957 * Enable Rx checksum offload. 958 * Then for vlan support, we must enable receive vlan de-tagging. 959 * Otherwise, there'll be checksum error. 960 */ 961 val16 = rge_reg_get16(rgep, CPLUS_COMMAND_REG); 962 val16 |= RX_CKSM_OFFLOAD | RX_VLAN_DETAG; 963 if (chip->mac_ver == MAC_VER_8169S_D) { 964 val16 |= CPLUS_BIT14 | MUL_PCI_RW_ENABLE; 965 rge_reg_put8(rgep, RESV_82_REG, 0x01); 966 } 967 rge_reg_put16(rgep, CPLUS_COMMAND_REG, val16 & (~0x03)); 968 969 /* 970 * Start transmit/receive before set tx/rx configuration register 971 */ 972 if (!chip->is_pcie) 973 rge_reg_set8(rgep, RT_COMMAND_REG, 974 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 975 976 /* 977 * Set dump tally counter register 978 */ 979 val32 = rgep->dma_area_stats.cookie.dmac_laddress >> 32; 980 rge_reg_put32(rgep, DUMP_COUNTER_REG_1, val32); 981 val32 = rge_reg_get32(rgep, DUMP_COUNTER_REG_0); 982 val32 &= DUMP_COUNTER_REG_RESV; 983 val32 |= rgep->dma_area_stats.cookie.dmac_laddress; 984 rge_reg_put32(rgep, DUMP_COUNTER_REG_0, val32); 985 986 /* 987 * Change to config register write enable mode 988 */ 989 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 990 991 /* 992 * Set Tx/Rx maximum packet size 993 */ 994 if (rgep->default_mtu > ETHERMTU) { 995 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_JUMBO); 996 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_JUMBO); 997 } else { 998 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_STD); 999 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_STD); 1000 } 1001 1002 /* 1003 * Set receive configuration register 1004 */ 1005 val32 = rge_reg_get32(rgep, RX_CONFIG_REG); 1006 val32 &= RX_CONFIG_REG_RESV; 1007 if (rgep->promisc) 1008 val32 |= RX_ACCEPT_ALL_PKT; 1009 rge_reg_put32(rgep, RX_CONFIG_REG, val32 | chip->rxconfig); 1010 1011 /* 1012 * Set transmit configuration register 1013 */ 1014 val32 = rge_reg_get32(rgep, TX_CONFIG_REG); 1015 val32 &= TX_CONFIG_REG_RESV; 1016 rge_reg_put32(rgep, TX_CONFIG_REG, val32 | chip->txconfig); 1017 1018 /* 1019 * Set Tx/Rx descriptor register 1020 */ 1021 val32 = rgep->tx_desc.cookie.dmac_laddress; 1022 rge_reg_put32(rgep, NORMAL_TX_RING_ADDR_LO_REG, val32); 1023 val32 = rgep->tx_desc.cookie.dmac_laddress >> 32; 1024 rge_reg_put32(rgep, NORMAL_TX_RING_ADDR_HI_REG, val32); 1025 rge_reg_put32(rgep, HIGH_TX_RING_ADDR_LO_REG, 0); 1026 rge_reg_put32(rgep, HIGH_TX_RING_ADDR_HI_REG, 0); 1027 val32 = rgep->rx_desc.cookie.dmac_laddress; 1028 rge_reg_put32(rgep, RX_RING_ADDR_LO_REG, val32); 1029 val32 = rgep->rx_desc.cookie.dmac_laddress >> 32; 1030 rge_reg_put32(rgep, RX_RING_ADDR_HI_REG, val32); 1031 1032 /* 1033 * Suggested setting from Realtek 1034 */ 1035 rge_reg_put16(rgep, RESV_E2_REG, 0x282a); 1036 1037 /* 1038 * Return to normal network/host communication mode 1039 */ 1040 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1041 drv_usecwait(20); 1042 1043 /* 1044 * Set multicast register 1045 */ 1046 hashp = (uint32_t *)rgep->mcast_hash; 1047 rge_reg_put32(rgep, MULTICAST_0_REG, hashp[0]); 1048 rge_reg_put32(rgep, MULTICAST_4_REG, hashp[1]); 1049 1050 /* 1051 * Msic register setting: 1052 * -- Missed packet counter: clear it 1053 * -- TimerInt Register 1054 * -- Timer count register 1055 */ 1056 rge_reg_put32(rgep, RX_PKT_MISS_COUNT_REG, 0); 1057 rge_reg_put32(rgep, TIMER_INT_REG, TIMER_INT_NONE); 1058 rge_reg_put32(rgep, TIMER_COUNT_REG, 0); 1059 } 1060 1061 /* 1062 * rge_chip_start() -- start the chip transmitting and/or receiving, 1063 * including enabling interrupts 1064 */ 1065 void rge_chip_start(rge_t *rgep); 1066 #pragma no_inline(rge_chip_start) 1067 1068 void 1069 rge_chip_start(rge_t *rgep) 1070 { 1071 /* 1072 * Clear statistics 1073 */ 1074 bzero(&rgep->stats, sizeof (rge_stats_t)); 1075 DMA_ZERO(rgep->dma_area_stats); 1076 1077 /* 1078 * Start transmit/receive 1079 */ 1080 rge_reg_set8(rgep, RT_COMMAND_REG, 1081 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1082 1083 /* 1084 * Enable interrupt 1085 */ 1086 rgep->int_mask = RGE_INT_MASK; 1087 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 1088 1089 /* 1090 * All done! 1091 */ 1092 rgep->rge_chip_state = RGE_CHIP_RUNNING; 1093 } 1094 1095 /* 1096 * rge_chip_stop() -- stop board receiving 1097 */ 1098 void rge_chip_stop(rge_t *rgep, boolean_t fault); 1099 #pragma no_inline(rge_chip_stop) 1100 1101 void 1102 rge_chip_stop(rge_t *rgep, boolean_t fault) 1103 { 1104 /* 1105 * Disable interrupt 1106 */ 1107 rgep->int_mask = INT_MASK_NONE; 1108 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 1109 1110 /* 1111 * Clear pended interrupt 1112 */ 1113 rge_reg_put16(rgep, INT_STATUS_REG, INT_MASK_ALL); 1114 1115 /* 1116 * Stop the board and disable transmit/receive 1117 */ 1118 rge_reg_clr8(rgep, RT_COMMAND_REG, 1119 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1120 1121 if (fault) 1122 rgep->rge_chip_state = RGE_CHIP_FAULT; 1123 else 1124 rgep->rge_chip_state = RGE_CHIP_STOPPED; 1125 } 1126 1127 /* 1128 * rge_get_mac_addr() -- get the MAC address on NIC 1129 */ 1130 static void rge_get_mac_addr(rge_t *rgep); 1131 #pragma inline(rge_get_mac_addr) 1132 1133 static void 1134 rge_get_mac_addr(rge_t *rgep) 1135 { 1136 uint8_t *macaddr = rgep->netaddr; 1137 uint32_t val32; 1138 1139 /* 1140 * Read first 4-byte of mac address 1141 */ 1142 val32 = rge_reg_get32(rgep, ID_0_REG); 1143 macaddr[0] = val32 & 0xff; 1144 val32 = val32 >> 8; 1145 macaddr[1] = val32 & 0xff; 1146 val32 = val32 >> 8; 1147 macaddr[2] = val32 & 0xff; 1148 val32 = val32 >> 8; 1149 macaddr[3] = val32 & 0xff; 1150 1151 /* 1152 * Read last 2-byte of mac address 1153 */ 1154 val32 = rge_reg_get32(rgep, ID_4_REG); 1155 macaddr[4] = val32 & 0xff; 1156 val32 = val32 >> 8; 1157 macaddr[5] = val32 & 0xff; 1158 } 1159 1160 static void rge_set_mac_addr(rge_t *rgep); 1161 #pragma inline(rge_set_mac_addr) 1162 1163 static void 1164 rge_set_mac_addr(rge_t *rgep) 1165 { 1166 uint8_t *p = rgep->netaddr; 1167 uint32_t val32; 1168 1169 /* 1170 * Change to config register write enable mode 1171 */ 1172 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1173 1174 /* 1175 * Get first 4 bytes of mac address 1176 */ 1177 val32 = p[3]; 1178 val32 = val32 << 8; 1179 val32 |= p[2]; 1180 val32 = val32 << 8; 1181 val32 |= p[1]; 1182 val32 = val32 << 8; 1183 val32 |= p[0]; 1184 1185 /* 1186 * Set first 4 bytes of mac address 1187 */ 1188 rge_reg_put32(rgep, ID_0_REG, val32); 1189 1190 /* 1191 * Get last 2 bytes of mac address 1192 */ 1193 val32 = p[5]; 1194 val32 = val32 << 8; 1195 val32 |= p[4]; 1196 1197 /* 1198 * Set last 2 bytes of mac address 1199 */ 1200 val32 |= rge_reg_get32(rgep, ID_4_REG) & ~0xffff; 1201 rge_reg_put32(rgep, ID_4_REG, val32); 1202 1203 /* 1204 * Return to normal network/host communication mode 1205 */ 1206 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1207 } 1208 1209 static void rge_set_multi_addr(rge_t *rgep); 1210 #pragma inline(rge_set_multi_addr) 1211 1212 static void 1213 rge_set_multi_addr(rge_t *rgep) 1214 { 1215 uint32_t *hashp; 1216 1217 hashp = (uint32_t *)rgep->mcast_hash; 1218 rge_reg_put32(rgep, MULTICAST_0_REG, RGE_BSWAP_32(hashp[0])); 1219 rge_reg_put32(rgep, MULTICAST_4_REG, RGE_BSWAP_32(hashp[1])); 1220 rge_reg_set8(rgep, RT_COMMAND_REG, 1221 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1222 } 1223 1224 static void rge_set_promisc(rge_t *rgep); 1225 #pragma inline(rge_set_promisc) 1226 1227 static void 1228 rge_set_promisc(rge_t *rgep) 1229 { 1230 if (rgep->promisc) 1231 rge_reg_set32(rgep, RX_CONFIG_REG, RX_ACCEPT_ALL_PKT); 1232 else 1233 rge_reg_clr32(rgep, RX_CONFIG_REG, RX_ACCEPT_ALL_PKT); 1234 1235 rge_reg_set8(rgep, RT_COMMAND_REG, 1236 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1237 } 1238 1239 /* 1240 * rge_chip_sync() -- program the chip with the unicast MAC address, 1241 * the multicast hash table, the required level of promiscuity, and 1242 * the current loopback mode ... 1243 */ 1244 void rge_chip_sync(rge_t *rgep, enum rge_sync_op todo); 1245 #pragma no_inline(rge_chip_sync) 1246 1247 void 1248 rge_chip_sync(rge_t *rgep, enum rge_sync_op todo) 1249 { 1250 switch (todo) { 1251 case RGE_GET_MAC: 1252 rge_get_mac_addr(rgep); 1253 break; 1254 case RGE_SET_MAC: 1255 /* Reprogram the unicast MAC address(es) ... */ 1256 rge_set_mac_addr(rgep); 1257 break; 1258 case RGE_SET_MUL: 1259 /* Reprogram the hashed multicast address table ... */ 1260 rge_set_multi_addr(rgep); 1261 break; 1262 case RGE_SET_PROMISC: 1263 /* Set or clear the PROMISCUOUS mode bit */ 1264 rge_set_promisc(rgep); 1265 break; 1266 default: 1267 break; 1268 } 1269 } 1270 1271 void rge_chip_blank(void *arg, time_t ticks, uint_t count); 1272 #pragma no_inline(rge_chip_blank) 1273 1274 void 1275 rge_chip_blank(void *arg, time_t ticks, uint_t count) 1276 { 1277 _NOTE(ARGUNUSED(arg, ticks, count)); 1278 } 1279 1280 void rge_tx_trigger(rge_t *rgep); 1281 #pragma no_inline(rge_tx_trigger) 1282 1283 void 1284 rge_tx_trigger(rge_t *rgep) 1285 { 1286 rge_reg_set8(rgep, TX_RINGS_POLL_REG, NORMAL_TX_RING_POLL); 1287 } 1288 1289 void rge_hw_stats_dump(rge_t *rgep); 1290 #pragma no_inline(rge_tx_trigger) 1291 1292 void 1293 rge_hw_stats_dump(rge_t *rgep) 1294 { 1295 int i = 0; 1296 1297 while (rge_reg_get32(rgep, DUMP_COUNTER_REG_0) & DUMP_START) { 1298 drv_usecwait(100); 1299 if (++i > STATS_DUMP_LOOP) { 1300 RGE_DEBUG(("rge h/w statistics dump fail!")); 1301 rgep->rge_chip_state = RGE_CHIP_ERROR; 1302 return; 1303 } 1304 } 1305 DMA_SYNC(rgep->dma_area_stats, DDI_DMA_SYNC_FORKERNEL); 1306 1307 /* 1308 * Start H/W statistics dump for RTL8169 chip 1309 */ 1310 rge_reg_set32(rgep, DUMP_COUNTER_REG_0, DUMP_START); 1311 } 1312 1313 /* 1314 * ========== Hardware interrupt handler ========== 1315 */ 1316 1317 #undef RGE_DBG 1318 #define RGE_DBG RGE_DBG_INT /* debug flag for this code */ 1319 1320 static void rge_wake_factotum(rge_t *rgep); 1321 #pragma inline(rge_wake_factotum) 1322 1323 static void 1324 rge_wake_factotum(rge_t *rgep) 1325 { 1326 if (rgep->factotum_flag == 0) { 1327 rgep->factotum_flag = 1; 1328 (void) ddi_intr_trigger_softint(rgep->factotum_hdl, NULL); 1329 } 1330 } 1331 1332 /* 1333 * rge_intr() -- handle chip interrupts 1334 */ 1335 uint_t rge_intr(caddr_t arg1, caddr_t arg2); 1336 #pragma no_inline(rge_intr) 1337 1338 uint_t 1339 rge_intr(caddr_t arg1, caddr_t arg2) 1340 { 1341 rge_t *rgep = (rge_t *)arg1; 1342 uint16_t int_status; 1343 1344 _NOTE(ARGUNUSED(arg2)) 1345 1346 mutex_enter(rgep->genlock); 1347 /* 1348 * Was this interrupt caused by our device... 1349 */ 1350 int_status = rge_reg_get16(rgep, INT_STATUS_REG); 1351 if (!(int_status & rgep->int_mask)) { 1352 mutex_exit(rgep->genlock); 1353 return (DDI_INTR_UNCLAIMED); 1354 /* indicate it wasn't our interrupt */ 1355 } 1356 rgep->stats.intr++; 1357 1358 /* 1359 * Clear interrupt 1360 * For PCIE chipset, we need disable interrupt first. 1361 */ 1362 if (rgep->chipid.is_pcie) 1363 rge_reg_put16(rgep, INT_MASK_REG, INT_MASK_NONE); 1364 rge_reg_put16(rgep, INT_STATUS_REG, int_status); 1365 1366 /* 1367 * Cable link change interrupt 1368 */ 1369 if (int_status & LINK_CHANGE_INT) { 1370 rge_chip_cyclic(rgep); 1371 } 1372 1373 mutex_exit(rgep->genlock); 1374 1375 /* 1376 * Receive interrupt 1377 */ 1378 if (int_status & RGE_RX_INT) 1379 rge_receive(rgep); 1380 1381 /* 1382 * Re-enable interrupt for PCIE chipset 1383 */ 1384 if (rgep->chipid.is_pcie) 1385 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 1386 1387 return (DDI_INTR_CLAIMED); /* indicate it was our interrupt */ 1388 } 1389 1390 /* 1391 * ========== Factotum, implemented as a softint handler ========== 1392 */ 1393 1394 #undef RGE_DBG 1395 #define RGE_DBG RGE_DBG_FACT /* debug flag for this code */ 1396 1397 static boolean_t rge_factotum_link_check(rge_t *rgep); 1398 #pragma no_inline(rge_factotum_link_check) 1399 1400 static boolean_t 1401 rge_factotum_link_check(rge_t *rgep) 1402 { 1403 uint8_t media_status; 1404 int32_t link; 1405 1406 media_status = rge_reg_get8(rgep, PHY_STATUS_REG); 1407 link = (media_status & PHY_STATUS_LINK_UP) ? 1408 LINK_STATE_UP : LINK_STATE_DOWN; 1409 if (rgep->param_link_up != link) { 1410 /* 1411 * Link change. 1412 */ 1413 rgep->param_link_up = link; 1414 1415 if (link == LINK_STATE_UP) { 1416 if (media_status & PHY_STATUS_1000MF) { 1417 rgep->param_link_speed = RGE_SPEED_1000M; 1418 rgep->param_link_duplex = LINK_DUPLEX_FULL; 1419 } else { 1420 rgep->param_link_speed = 1421 (media_status & PHY_STATUS_100M) ? 1422 RGE_SPEED_100M : RGE_SPEED_10M; 1423 rgep->param_link_duplex = 1424 (media_status & PHY_STATUS_DUPLEX_FULL) ? 1425 LINK_DUPLEX_FULL : LINK_DUPLEX_HALF; 1426 } 1427 } 1428 return (B_TRUE); 1429 } 1430 return (B_FALSE); 1431 } 1432 1433 /* 1434 * Factotum routine to check for Tx stall, using the 'watchdog' counter 1435 */ 1436 static boolean_t rge_factotum_stall_check(rge_t *rgep); 1437 #pragma no_inline(rge_factotum_stall_check) 1438 1439 static boolean_t 1440 rge_factotum_stall_check(rge_t *rgep) 1441 { 1442 uint32_t dogval; 1443 1444 ASSERT(mutex_owned(rgep->genlock)); 1445 1446 /* 1447 * Specific check for Tx stall ... 1448 * 1449 * The 'watchdog' counter is incremented whenever a packet 1450 * is queued, reset to 1 when some (but not all) buffers 1451 * are reclaimed, reset to 0 (disabled) when all buffers 1452 * are reclaimed, and shifted left here. If it exceeds the 1453 * threshold value, the chip is assumed to have stalled and 1454 * is put into the ERROR state. The factotum will then reset 1455 * it on the next pass. 1456 * 1457 * All of which should ensure that we don't get into a state 1458 * where packets are left pending indefinitely! 1459 */ 1460 if (rgep->resched_needed) 1461 (void) ddi_intr_trigger_softint(rgep->resched_hdl, NULL); 1462 dogval = rge_atomic_shl32(&rgep->watchdog, 1); 1463 if (dogval < rge_watchdog_count) 1464 return (B_FALSE); 1465 1466 RGE_REPORT((rgep, "Tx stall detected, watchdog code 0x%x", dogval)); 1467 return (B_TRUE); 1468 1469 } 1470 1471 /* 1472 * The factotum is woken up when there's something to do that we'd rather 1473 * not do from inside a hardware interrupt handler or high-level cyclic. 1474 * Its two main tasks are: 1475 * reset & restart the chip after an error 1476 * check the link status whenever necessary 1477 */ 1478 uint_t rge_chip_factotum(caddr_t arg1, caddr_t arg2); 1479 #pragma no_inline(rge_chip_factotum) 1480 1481 uint_t 1482 rge_chip_factotum(caddr_t arg1, caddr_t arg2) 1483 { 1484 rge_t *rgep; 1485 uint_t result; 1486 boolean_t error; 1487 boolean_t linkchg; 1488 1489 rgep = (rge_t *)arg1; 1490 _NOTE(ARGUNUSED(arg2)) 1491 1492 if (rgep->factotum_flag == 0) 1493 return (DDI_INTR_UNCLAIMED); 1494 1495 rgep->factotum_flag = 0; 1496 result = DDI_INTR_CLAIMED; 1497 error = B_FALSE; 1498 linkchg = B_FALSE; 1499 1500 mutex_enter(rgep->genlock); 1501 switch (rgep->rge_chip_state) { 1502 default: 1503 break; 1504 1505 case RGE_CHIP_RUNNING: 1506 linkchg = rge_factotum_link_check(rgep); 1507 error = rge_factotum_stall_check(rgep); 1508 break; 1509 1510 case RGE_CHIP_ERROR: 1511 error = B_TRUE; 1512 break; 1513 1514 case RGE_CHIP_FAULT: 1515 /* 1516 * Fault detected, time to reset ... 1517 */ 1518 if (rge_autorecover) { 1519 RGE_REPORT((rgep, "automatic recovery activated")); 1520 rge_restart(rgep); 1521 } 1522 break; 1523 } 1524 1525 /* 1526 * If an error is detected, stop the chip now, marking it as 1527 * faulty, so that it will be reset next time through ... 1528 */ 1529 if (error) 1530 rge_chip_stop(rgep, B_TRUE); 1531 mutex_exit(rgep->genlock); 1532 1533 /* 1534 * If the link state changed, tell the world about it. 1535 * Note: can't do this while still holding the mutex. 1536 */ 1537 if (linkchg) 1538 mac_link_update(rgep->mh, rgep->param_link_up); 1539 1540 return (result); 1541 } 1542 1543 /* 1544 * High-level cyclic handler 1545 * 1546 * This routine schedules a (low-level) softint callback to the 1547 * factotum, and prods the chip to update the status block (which 1548 * will cause a hardware interrupt when complete). 1549 */ 1550 void rge_chip_cyclic(void *arg); 1551 #pragma no_inline(rge_chip_cyclic) 1552 1553 void 1554 rge_chip_cyclic(void *arg) 1555 { 1556 rge_t *rgep; 1557 1558 rgep = arg; 1559 1560 switch (rgep->rge_chip_state) { 1561 default: 1562 return; 1563 1564 case RGE_CHIP_RUNNING: 1565 rge_phy_check(rgep); 1566 break; 1567 1568 case RGE_CHIP_FAULT: 1569 case RGE_CHIP_ERROR: 1570 break; 1571 } 1572 1573 rge_wake_factotum(rgep); 1574 } 1575 1576 1577 /* 1578 * ========== Ioctl subfunctions ========== 1579 */ 1580 1581 #undef RGE_DBG 1582 #define RGE_DBG RGE_DBG_PPIO /* debug flag for this code */ 1583 1584 #if RGE_DEBUGGING || RGE_DO_PPIO 1585 1586 static void rge_chip_peek_cfg(rge_t *rgep, rge_peekpoke_t *ppd); 1587 #pragma no_inline(rge_chip_peek_cfg) 1588 1589 static void 1590 rge_chip_peek_cfg(rge_t *rgep, rge_peekpoke_t *ppd) 1591 { 1592 uint64_t regval; 1593 uint64_t regno; 1594 1595 RGE_TRACE(("rge_chip_peek_cfg($%p, $%p)", 1596 (void *)rgep, (void *)ppd)); 1597 1598 regno = ppd->pp_acc_offset; 1599 1600 switch (ppd->pp_acc_size) { 1601 case 1: 1602 regval = pci_config_get8(rgep->cfg_handle, regno); 1603 break; 1604 1605 case 2: 1606 regval = pci_config_get16(rgep->cfg_handle, regno); 1607 break; 1608 1609 case 4: 1610 regval = pci_config_get32(rgep->cfg_handle, regno); 1611 break; 1612 1613 case 8: 1614 regval = pci_config_get64(rgep->cfg_handle, regno); 1615 break; 1616 } 1617 1618 ppd->pp_acc_data = regval; 1619 } 1620 1621 static void rge_chip_poke_cfg(rge_t *rgep, rge_peekpoke_t *ppd); 1622 #pragma no_inline(rge_chip_poke_cfg) 1623 1624 static void 1625 rge_chip_poke_cfg(rge_t *rgep, rge_peekpoke_t *ppd) 1626 { 1627 uint64_t regval; 1628 uint64_t regno; 1629 1630 RGE_TRACE(("rge_chip_poke_cfg($%p, $%p)", 1631 (void *)rgep, (void *)ppd)); 1632 1633 regno = ppd->pp_acc_offset; 1634 regval = ppd->pp_acc_data; 1635 1636 switch (ppd->pp_acc_size) { 1637 case 1: 1638 pci_config_put8(rgep->cfg_handle, regno, regval); 1639 break; 1640 1641 case 2: 1642 pci_config_put16(rgep->cfg_handle, regno, regval); 1643 break; 1644 1645 case 4: 1646 pci_config_put32(rgep->cfg_handle, regno, regval); 1647 break; 1648 1649 case 8: 1650 pci_config_put64(rgep->cfg_handle, regno, regval); 1651 break; 1652 } 1653 } 1654 1655 static void rge_chip_peek_reg(rge_t *rgep, rge_peekpoke_t *ppd); 1656 #pragma no_inline(rge_chip_peek_reg) 1657 1658 static void 1659 rge_chip_peek_reg(rge_t *rgep, rge_peekpoke_t *ppd) 1660 { 1661 uint64_t regval; 1662 void *regaddr; 1663 1664 RGE_TRACE(("rge_chip_peek_reg($%p, $%p)", 1665 (void *)rgep, (void *)ppd)); 1666 1667 regaddr = PIO_ADDR(rgep, ppd->pp_acc_offset); 1668 1669 switch (ppd->pp_acc_size) { 1670 case 1: 1671 regval = ddi_get8(rgep->io_handle, regaddr); 1672 break; 1673 1674 case 2: 1675 regval = ddi_get16(rgep->io_handle, regaddr); 1676 break; 1677 1678 case 4: 1679 regval = ddi_get32(rgep->io_handle, regaddr); 1680 break; 1681 1682 case 8: 1683 regval = ddi_get64(rgep->io_handle, regaddr); 1684 break; 1685 } 1686 1687 ppd->pp_acc_data = regval; 1688 } 1689 1690 static void rge_chip_poke_reg(rge_t *rgep, rge_peekpoke_t *ppd); 1691 #pragma no_inline(rge_chip_peek_reg) 1692 1693 static void 1694 rge_chip_poke_reg(rge_t *rgep, rge_peekpoke_t *ppd) 1695 { 1696 uint64_t regval; 1697 void *regaddr; 1698 1699 RGE_TRACE(("rge_chip_poke_reg($%p, $%p)", 1700 (void *)rgep, (void *)ppd)); 1701 1702 regaddr = PIO_ADDR(rgep, ppd->pp_acc_offset); 1703 regval = ppd->pp_acc_data; 1704 1705 switch (ppd->pp_acc_size) { 1706 case 1: 1707 ddi_put8(rgep->io_handle, regaddr, regval); 1708 break; 1709 1710 case 2: 1711 ddi_put16(rgep->io_handle, regaddr, regval); 1712 break; 1713 1714 case 4: 1715 ddi_put32(rgep->io_handle, regaddr, regval); 1716 break; 1717 1718 case 8: 1719 ddi_put64(rgep->io_handle, regaddr, regval); 1720 break; 1721 } 1722 RGE_PCICHK(rgep); 1723 } 1724 1725 static void rge_chip_peek_mii(rge_t *rgep, rge_peekpoke_t *ppd); 1726 #pragma no_inline(rge_chip_peek_mii) 1727 1728 static void 1729 rge_chip_peek_mii(rge_t *rgep, rge_peekpoke_t *ppd) 1730 { 1731 RGE_TRACE(("rge_chip_peek_mii($%p, $%p)", 1732 (void *)rgep, (void *)ppd)); 1733 1734 ppd->pp_acc_data = rge_mii_get16(rgep, ppd->pp_acc_offset/2); 1735 } 1736 1737 static void rge_chip_poke_mii(rge_t *rgep, rge_peekpoke_t *ppd); 1738 #pragma no_inline(rge_chip_poke_mii) 1739 1740 static void 1741 rge_chip_poke_mii(rge_t *rgep, rge_peekpoke_t *ppd) 1742 { 1743 RGE_TRACE(("rge_chip_poke_mii($%p, $%p)", 1744 (void *)rgep, (void *)ppd)); 1745 1746 rge_mii_put16(rgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 1747 } 1748 1749 static void rge_chip_peek_mem(rge_t *rgep, rge_peekpoke_t *ppd); 1750 #pragma no_inline(rge_chip_peek_mem) 1751 1752 static void 1753 rge_chip_peek_mem(rge_t *rgep, rge_peekpoke_t *ppd) 1754 { 1755 uint64_t regval; 1756 void *vaddr; 1757 1758 RGE_TRACE(("rge_chip_peek_rge($%p, $%p)", 1759 (void *)rgep, (void *)ppd)); 1760 1761 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 1762 1763 switch (ppd->pp_acc_size) { 1764 case 1: 1765 regval = *(uint8_t *)vaddr; 1766 break; 1767 1768 case 2: 1769 regval = *(uint16_t *)vaddr; 1770 break; 1771 1772 case 4: 1773 regval = *(uint32_t *)vaddr; 1774 break; 1775 1776 case 8: 1777 regval = *(uint64_t *)vaddr; 1778 break; 1779 } 1780 1781 RGE_DEBUG(("rge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 1782 (void *)rgep, (void *)ppd, regval, vaddr)); 1783 1784 ppd->pp_acc_data = regval; 1785 } 1786 1787 static void rge_chip_poke_mem(rge_t *rgep, rge_peekpoke_t *ppd); 1788 #pragma no_inline(rge_chip_poke_mem) 1789 1790 static void 1791 rge_chip_poke_mem(rge_t *rgep, rge_peekpoke_t *ppd) 1792 { 1793 uint64_t regval; 1794 void *vaddr; 1795 1796 RGE_TRACE(("rge_chip_poke_mem($%p, $%p)", 1797 (void *)rgep, (void *)ppd)); 1798 1799 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 1800 regval = ppd->pp_acc_data; 1801 1802 RGE_DEBUG(("rge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 1803 (void *)rgep, (void *)ppd, regval, vaddr)); 1804 1805 switch (ppd->pp_acc_size) { 1806 case 1: 1807 *(uint8_t *)vaddr = (uint8_t)regval; 1808 break; 1809 1810 case 2: 1811 *(uint16_t *)vaddr = (uint16_t)regval; 1812 break; 1813 1814 case 4: 1815 *(uint32_t *)vaddr = (uint32_t)regval; 1816 break; 1817 1818 case 8: 1819 *(uint64_t *)vaddr = (uint64_t)regval; 1820 break; 1821 } 1822 } 1823 1824 static enum ioc_reply rge_pp_ioctl(rge_t *rgep, int cmd, mblk_t *mp, 1825 struct iocblk *iocp); 1826 #pragma no_inline(rge_pp_ioctl) 1827 1828 static enum ioc_reply 1829 rge_pp_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp) 1830 { 1831 void (*ppfn)(rge_t *rgep, rge_peekpoke_t *ppd); 1832 rge_peekpoke_t *ppd; 1833 dma_area_t *areap; 1834 uint64_t sizemask; 1835 uint64_t mem_va; 1836 uint64_t maxoff; 1837 boolean_t peek; 1838 1839 switch (cmd) { 1840 default: 1841 /* NOTREACHED */ 1842 rge_error(rgep, "rge_pp_ioctl: invalid cmd 0x%x", cmd); 1843 return (IOC_INVAL); 1844 1845 case RGE_PEEK: 1846 peek = B_TRUE; 1847 break; 1848 1849 case RGE_POKE: 1850 peek = B_FALSE; 1851 break; 1852 } 1853 1854 /* 1855 * Validate format of ioctl 1856 */ 1857 if (iocp->ioc_count != sizeof (rge_peekpoke_t)) 1858 return (IOC_INVAL); 1859 if (mp->b_cont == NULL) 1860 return (IOC_INVAL); 1861 ppd = (rge_peekpoke_t *)mp->b_cont->b_rptr; 1862 1863 /* 1864 * Validate request parameters 1865 */ 1866 switch (ppd->pp_acc_space) { 1867 default: 1868 return (IOC_INVAL); 1869 1870 case RGE_PP_SPACE_CFG: 1871 /* 1872 * Config space 1873 */ 1874 sizemask = 8|4|2|1; 1875 mem_va = 0; 1876 maxoff = PCI_CONF_HDR_SIZE; 1877 ppfn = peek ? rge_chip_peek_cfg : rge_chip_poke_cfg; 1878 break; 1879 1880 case RGE_PP_SPACE_REG: 1881 /* 1882 * Memory-mapped I/O space 1883 */ 1884 sizemask = 8|4|2|1; 1885 mem_va = 0; 1886 maxoff = RGE_REGISTER_MAX; 1887 ppfn = peek ? rge_chip_peek_reg : rge_chip_poke_reg; 1888 break; 1889 1890 case RGE_PP_SPACE_MII: 1891 /* 1892 * PHY's MII registers 1893 * NB: all PHY registers are two bytes, but the 1894 * addresses increment in ones (word addressing). 1895 * So we scale the address here, then undo the 1896 * transformation inside the peek/poke functions. 1897 */ 1898 ppd->pp_acc_offset *= 2; 1899 sizemask = 2; 1900 mem_va = 0; 1901 maxoff = (MII_MAXREG+1)*2; 1902 ppfn = peek ? rge_chip_peek_mii : rge_chip_poke_mii; 1903 break; 1904 1905 case RGE_PP_SPACE_RGE: 1906 /* 1907 * RGE data structure! 1908 */ 1909 sizemask = 8|4|2|1; 1910 mem_va = (uintptr_t)rgep; 1911 maxoff = sizeof (*rgep); 1912 ppfn = peek ? rge_chip_peek_mem : rge_chip_poke_mem; 1913 break; 1914 1915 case RGE_PP_SPACE_STATISTICS: 1916 case RGE_PP_SPACE_TXDESC: 1917 case RGE_PP_SPACE_TXBUFF: 1918 case RGE_PP_SPACE_RXDESC: 1919 case RGE_PP_SPACE_RXBUFF: 1920 /* 1921 * Various DMA_AREAs 1922 */ 1923 switch (ppd->pp_acc_space) { 1924 case RGE_PP_SPACE_TXDESC: 1925 areap = &rgep->dma_area_txdesc; 1926 break; 1927 case RGE_PP_SPACE_RXDESC: 1928 areap = &rgep->dma_area_rxdesc; 1929 break; 1930 case RGE_PP_SPACE_STATISTICS: 1931 areap = &rgep->dma_area_stats; 1932 break; 1933 } 1934 1935 sizemask = 8|4|2|1; 1936 mem_va = (uintptr_t)areap->mem_va; 1937 maxoff = areap->alength; 1938 ppfn = peek ? rge_chip_peek_mem : rge_chip_poke_mem; 1939 break; 1940 } 1941 1942 switch (ppd->pp_acc_size) { 1943 default: 1944 return (IOC_INVAL); 1945 1946 case 8: 1947 case 4: 1948 case 2: 1949 case 1: 1950 if ((ppd->pp_acc_size & sizemask) == 0) 1951 return (IOC_INVAL); 1952 break; 1953 } 1954 1955 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 1956 return (IOC_INVAL); 1957 1958 if (ppd->pp_acc_offset >= maxoff) 1959 return (IOC_INVAL); 1960 1961 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 1962 return (IOC_INVAL); 1963 1964 /* 1965 * All OK - go do it! 1966 */ 1967 ppd->pp_acc_offset += mem_va; 1968 (*ppfn)(rgep, ppd); 1969 return (peek ? IOC_REPLY : IOC_ACK); 1970 } 1971 1972 static enum ioc_reply rge_diag_ioctl(rge_t *rgep, int cmd, mblk_t *mp, 1973 struct iocblk *iocp); 1974 #pragma no_inline(rge_diag_ioctl) 1975 1976 static enum ioc_reply 1977 rge_diag_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp) 1978 { 1979 ASSERT(mutex_owned(rgep->genlock)); 1980 1981 switch (cmd) { 1982 default: 1983 /* NOTREACHED */ 1984 rge_error(rgep, "rge_diag_ioctl: invalid cmd 0x%x", cmd); 1985 return (IOC_INVAL); 1986 1987 case RGE_DIAG: 1988 /* 1989 * Currently a no-op 1990 */ 1991 return (IOC_ACK); 1992 1993 case RGE_PEEK: 1994 case RGE_POKE: 1995 return (rge_pp_ioctl(rgep, cmd, mp, iocp)); 1996 1997 case RGE_PHY_RESET: 1998 return (IOC_RESTART_ACK); 1999 2000 case RGE_SOFT_RESET: 2001 case RGE_HARD_RESET: 2002 /* 2003 * Reset and reinitialise the 570x hardware 2004 */ 2005 rge_restart(rgep); 2006 return (IOC_ACK); 2007 } 2008 2009 /* NOTREACHED */ 2010 } 2011 2012 #endif /* RGE_DEBUGGING || RGE_DO_PPIO */ 2013 2014 static enum ioc_reply rge_mii_ioctl(rge_t *rgep, int cmd, mblk_t *mp, 2015 struct iocblk *iocp); 2016 #pragma no_inline(rge_mii_ioctl) 2017 2018 static enum ioc_reply 2019 rge_mii_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp) 2020 { 2021 struct rge_mii_rw *miirwp; 2022 2023 /* 2024 * Validate format of ioctl 2025 */ 2026 if (iocp->ioc_count != sizeof (struct rge_mii_rw)) 2027 return (IOC_INVAL); 2028 if (mp->b_cont == NULL) 2029 return (IOC_INVAL); 2030 miirwp = (struct rge_mii_rw *)mp->b_cont->b_rptr; 2031 2032 /* 2033 * Validate request parameters ... 2034 */ 2035 if (miirwp->mii_reg > MII_MAXREG) 2036 return (IOC_INVAL); 2037 2038 switch (cmd) { 2039 default: 2040 /* NOTREACHED */ 2041 rge_error(rgep, "rge_mii_ioctl: invalid cmd 0x%x", cmd); 2042 return (IOC_INVAL); 2043 2044 case RGE_MII_READ: 2045 miirwp->mii_data = rge_mii_get16(rgep, miirwp->mii_reg); 2046 return (IOC_REPLY); 2047 2048 case RGE_MII_WRITE: 2049 rge_mii_put16(rgep, miirwp->mii_reg, miirwp->mii_data); 2050 return (IOC_ACK); 2051 } 2052 2053 /* NOTREACHED */ 2054 } 2055 2056 enum ioc_reply rge_chip_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp, 2057 struct iocblk *iocp); 2058 #pragma no_inline(rge_chip_ioctl) 2059 2060 enum ioc_reply 2061 rge_chip_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 2062 { 2063 int cmd; 2064 2065 RGE_TRACE(("rge_chip_ioctl($%p, $%p, $%p, $%p)", 2066 (void *)rgep, (void *)wq, (void *)mp, (void *)iocp)); 2067 2068 ASSERT(mutex_owned(rgep->genlock)); 2069 2070 cmd = iocp->ioc_cmd; 2071 switch (cmd) { 2072 default: 2073 /* NOTREACHED */ 2074 rge_error(rgep, "rge_chip_ioctl: invalid cmd 0x%x", cmd); 2075 return (IOC_INVAL); 2076 2077 case RGE_DIAG: 2078 case RGE_PEEK: 2079 case RGE_POKE: 2080 case RGE_PHY_RESET: 2081 case RGE_SOFT_RESET: 2082 case RGE_HARD_RESET: 2083 #if RGE_DEBUGGING || RGE_DO_PPIO 2084 return (rge_diag_ioctl(rgep, cmd, mp, iocp)); 2085 #else 2086 return (IOC_INVAL); 2087 #endif /* RGE_DEBUGGING || RGE_DO_PPIO */ 2088 2089 case RGE_MII_READ: 2090 case RGE_MII_WRITE: 2091 return (rge_mii_ioctl(rgep, cmd, mp, iocp)); 2092 2093 } 2094 2095 /* NOTREACHED */ 2096 } 2097