1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _RGE_H 27 #define _RGE_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <sys/types.h> 36 #include <sys/stream.h> 37 #include <sys/strsun.h> 38 #include <sys/strsubr.h> 39 #include <sys/stat.h> 40 #include <sys/pci.h> 41 #include <sys/note.h> 42 #include <sys/modctl.h> 43 #include <sys/kstat.h> 44 #include <sys/ethernet.h> 45 #include <sys/vlan.h> 46 #include <sys/errno.h> 47 #include <sys/dlpi.h> 48 #include <sys/devops.h> 49 #include <sys/debug.h> 50 #include <sys/conf.h> 51 52 #include <netinet/ip6.h> 53 #include <inet/common.h> 54 #include <inet/ip.h> 55 #include <inet/mi.h> 56 #include <inet/nd.h> 57 #include <sys/pattr.h> 58 59 #include <sys/ddi.h> 60 #include <sys/sunddi.h> 61 62 #include <sys/mac.h> 63 #include <sys/mac_ether.h> 64 65 /* 66 * Reconfiguring the network devices requires the net_config privilege 67 * in Solaris 10+. 68 */ 69 extern int secpolicy_net_config(const cred_t *, boolean_t); 70 71 #include <sys/netlb.h> /* originally from cassini */ 72 #include <sys/miiregs.h> /* by fjlite out of intel */ 73 74 #include "rge_hw.h" 75 76 /* 77 * Name of the driver 78 */ 79 #define RGE_DRIVER_NAME "rge" 80 81 /* 82 * The driver supports the NDD ioctls ND_GET/ND_SET, and the loopback 83 * ioctls LB_GET_INFO_SIZE/LB_GET_INFO/LB_GET_MODE/LB_SET_MODE 84 * 85 * These are the values to use with LD_SET_MODE. 86 */ 87 #define RGE_LOOP_NONE 0 88 #define RGE_LOOP_INTERNAL_PHY 1 89 #define RGE_LOOP_INTERNAL_MAC 2 90 91 /* 92 * RGE-specific ioctls ... 93 */ 94 #define RGE_IOC ((((('R' << 8) + 'G') << 8) + 'E') << 8) 95 96 /* 97 * PHY register read/write ioctls, used by cable test software 98 */ 99 #define RGE_MII_READ (RGE_IOC|1) 100 #define RGE_MII_WRITE (RGE_IOC|2) 101 102 struct rge_mii_rw { 103 uint32_t mii_reg; /* PHY register number [0..31] */ 104 uint32_t mii_data; /* data to write/data read */ 105 }; 106 107 /* 108 * These diagnostic IOCTLS are enabled only in DEBUG drivers 109 */ 110 #define RGE_DIAG (RGE_IOC|10) /* currently a no-op */ 111 #define RGE_PEEK (RGE_IOC|11) 112 #define RGE_POKE (RGE_IOC|12) 113 #define RGE_PHY_RESET (RGE_IOC|13) 114 #define RGE_SOFT_RESET (RGE_IOC|14) 115 #define RGE_HARD_RESET (RGE_IOC|15) 116 117 typedef struct { 118 uint64_t pp_acc_size; /* in bytes: 1,2,4,8 */ 119 uint64_t pp_acc_space; /* See #defines below */ 120 uint64_t pp_acc_offset; 121 uint64_t pp_acc_data; /* output for peek */ 122 /* input for poke */ 123 } rge_peekpoke_t; 124 125 #define RGE_PP_SPACE_CFG 0 /* PCI config space */ 126 #define RGE_PP_SPACE_REG 1 /* PCI memory space */ 127 #define RGE_PP_SPACE_MII 2 /* PHY's MII registers */ 128 #define RGE_PP_SPACE_RGE 3 /* driver's soft state */ 129 #define RGE_PP_SPACE_TXDESC 4 /* TX descriptors */ 130 #define RGE_PP_SPACE_TXBUFF 5 /* TX buffers */ 131 #define RGE_PP_SPACE_RXDESC 6 /* RX descriptors */ 132 #define RGE_PP_SPACE_RXBUFF 7 /* RX buffers */ 133 #define RGE_PP_SPACE_STATISTICS 8 /* statistics block */ 134 135 /* 136 * RTL8169 CRC poly 137 */ 138 #define RGE_HASH_POLY 0x04C11DB7 /* 0x04C11DB6 */ 139 #define RGE_HASH_CRC 0xFFFFFFFFU 140 #define RGE_MCAST_BUF_SIZE 64 /* multicast hash table size in bits */ 141 142 /* 143 * Rx/Tx buffer parameters 144 */ 145 #define RGE_BUF_SLOTS 2048 146 #define RGE_RECV_COPY_SIZE 256 147 #define RGE_HEADROOM 6 148 149 /* 150 * Driver chip operation parameters 151 */ 152 #define RGE_CYCLIC_PERIOD (1000000000) /* ~1s */ 153 #define CHIP_RESET_LOOP 1000 154 #define PHY_RESET_LOOP 10 155 #define STATS_DUMP_LOOP 1000 156 #define RXBUFF_FREE_LOOP 1000 157 #define RGE_RX_INT_TIME 128 158 #define RGE_RX_INT_PKTS 8 159 160 /* 161 * Named Data (ND) Parameter Management Structure 162 */ 163 typedef struct { 164 int ndp_info; 165 int ndp_min; 166 int ndp_max; 167 int ndp_val; 168 char *ndp_name; 169 } nd_param_t; /* 0x18 (24) bytes */ 170 171 /* 172 * NDD parameter indexes, divided into: 173 * 174 * read-only parameters describing the hardware's capabilities 175 * read-write parameters controlling the advertised capabilities 176 * read-only parameters describing the partner's capabilities 177 * read-only parameters describing the link state 178 */ 179 enum { 180 PARAM_AUTONEG_CAP = 0, 181 PARAM_PAUSE_CAP, 182 PARAM_ASYM_PAUSE_CAP, 183 PARAM_1000FDX_CAP, 184 PARAM_1000HDX_CAP, 185 PARAM_100T4_CAP, 186 PARAM_100FDX_CAP, 187 PARAM_100HDX_CAP, 188 PARAM_10FDX_CAP, 189 PARAM_10HDX_CAP, 190 191 PARAM_ADV_AUTONEG_CAP, 192 PARAM_ADV_PAUSE_CAP, 193 PARAM_ADV_ASYM_PAUSE_CAP, 194 PARAM_ADV_1000FDX_CAP, 195 PARAM_ADV_1000HDX_CAP, 196 PARAM_ADV_100T4_CAP, 197 PARAM_ADV_100FDX_CAP, 198 PARAM_ADV_100HDX_CAP, 199 PARAM_ADV_10FDX_CAP, 200 PARAM_ADV_10HDX_CAP, 201 202 PARAM_LINK_STATUS, 203 PARAM_LINK_SPEED, 204 PARAM_LINK_DUPLEX, 205 206 PARAM_LOOP_MODE, 207 208 PARAM_COUNT 209 }; 210 211 enum rge_chip_state { 212 RGE_CHIP_FAULT = -2, /* fault, need reset */ 213 RGE_CHIP_ERROR, /* error, want reset */ 214 RGE_CHIP_INITIAL, /* Initial state only */ 215 RGE_CHIP_RESET, /* reset, need init */ 216 RGE_CHIP_STOPPED, /* Tx/Rx stopped */ 217 RGE_CHIP_RUNNING /* with interrupts */ 218 }; 219 220 enum rge_mac_state { 221 RGE_MAC_ATTACH = 0, 222 RGE_MAC_STOPPED, 223 RGE_MAC_STARTED, 224 RGE_MAC_UNATTACH 225 }; 226 227 enum rge_sync_op { 228 RGE_OP_NULL, 229 RGE_GET_MAC, /* get mac address operation */ 230 RGE_SET_MAC, /* set mac address operation */ 231 RGE_SET_MUL, /* set multicast address op */ 232 RGE_SET_PROMISC /* set promisc mode */ 233 }; 234 235 /* 236 * (Internal) return values from ioctl subroutines 237 */ 238 enum ioc_reply { 239 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 240 IOC_DONE, /* OK, reply sent */ 241 IOC_ACK, /* OK, just send ACK */ 242 IOC_REPLY, /* OK, just send reply */ 243 IOC_RESTART_ACK, /* OK, restart & ACK */ 244 IOC_RESTART_REPLY /* OK, restart & reply */ 245 }; 246 247 /* 248 * (Internal) enumeration of this driver's kstats 249 */ 250 enum { 251 RGE_KSTAT_DRIVER = 0, 252 RGE_KSTAT_COUNT 253 }; 254 255 /* 256 * Basic data types, for clarity in distinguishing 'numbers' 257 * used for different purposes ... 258 * 259 * A <rge_regno_t> is a register 'address' (offset) in any one of 260 * various address spaces (PCI config space, PCI memory-mapped I/O 261 * register space, MII registers, etc). None of these exceeds 64K, 262 * so we could use a 16-bit representation but pointer-sized objects 263 * are more "natural" in most architectures; they seem to be handled 264 * more efficiently on SPARC and no worse on x86. 265 * 266 * RGE_REGNO_NONE represents the non-existent value in this space. 267 */ 268 typedef uintptr_t rge_regno_t; /* register # (offset) */ 269 #define RGE_REGNO_NONE (~(uintptr_t)0u) 270 271 /* 272 * Describes one chunk of allocated DMA-able memory 273 * 274 * In some cases, this is a single chunk as allocated from the system; 275 * but we also use this structure to represent slices carved off such 276 * a chunk. Even when we don't really need all the information, we 277 * use this structure as a convenient way of correlating the various 278 * ways of looking at a piece of memory (kernel VA, IO space DVMA, 279 * handle+offset, etc). 280 */ 281 typedef struct { 282 ddi_acc_handle_t acc_hdl; /* handle for memory */ 283 void *mem_va; /* CPU VA of memory */ 284 uint32_t nslots; /* number of slots */ 285 uint32_t size; /* size per slot */ 286 size_t alength; /* allocated size */ 287 ddi_dma_handle_t dma_hdl; /* DMA handle */ 288 offset_t offset; /* relative to handle */ 289 ddi_dma_cookie_t cookie; /* associated cookie */ 290 uint32_t ncookies; /* must be 1 */ 291 uint32_t token; /* arbitrary identifier */ 292 } dma_area_t; 293 294 /* 295 * Software version of the Receive Buffer Descriptor 296 */ 297 typedef struct { 298 caddr_t private; /* pointer to rge */ 299 dma_area_t pbuf; /* (const) related */ 300 /* buffer area */ 301 frtn_t rx_recycle; /* recycle function */ 302 mblk_t *mp; 303 } dma_buf_t; 304 305 typedef struct sw_rbd { 306 dma_buf_t *rx_buf; 307 uint8_t flags; 308 } sw_rbd_t; 309 310 /* 311 * Software version of the Send Buffer Descriptor 312 */ 313 typedef struct sw_sbd { 314 dma_area_t desc; /* (const) related h/w */ 315 /* descriptor area */ 316 dma_area_t pbuf; /* (const) related */ 317 /* buffer area */ 318 } sw_sbd_t; 319 320 321 #define HW_RBD_INIT(rbd, slot) \ 322 rbd->flags_len |= RGE_BSWAP_32(BD_FLAG_HW_OWN); \ 323 rbd->vlan_tag = 0; \ 324 if (slot == (RGE_RECV_SLOTS -1)) \ 325 rbd->flags_len |= RGE_BSWAP_32(BD_FLAG_EOR); 326 #define HW_SBD_INIT(sbd, slot) \ 327 sbd->flags_len = 0; \ 328 if (slot == (RGE_SEND_SLOTS -1)) \ 329 sbd->flags_len |= RGE_BSWAP_32(BD_FLAG_EOR); 330 #define HW_SBD_SET(sbd, slot) \ 331 sbd->flags_len |= RGE_BSWAP_32(SBD_FLAG_TX_PKT); \ 332 if (slot == (RGE_SEND_SLOTS -1)) \ 333 sbd->flags_len |= RGE_BSWAP_32(BD_FLAG_EOR); 334 335 /* 336 * Describes the characteristics of a specific chip 337 */ 338 typedef struct { 339 uint16_t command; /* saved during attach */ 340 uint16_t vendor; /* vendor-id */ 341 uint16_t device; /* device-id */ 342 uint16_t subven; /* subsystem-vendor-id */ 343 uint16_t subdev; /* subsystem-id */ 344 uint8_t revision; /* revision-id */ 345 uint8_t clsize; /* cache-line-size */ 346 uint8_t latency; /* latency-timer */ 347 boolean_t is_pcie; 348 uint32_t mac_ver; 349 uint32_t phy_ver; 350 uint32_t rxconfig; 351 uint32_t txconfig; 352 } chip_id_t; 353 354 typedef struct rge_stats { 355 uint64_t rbytes; 356 uint64_t obytes; 357 uint32_t overflow; 358 uint32_t defer; /* dot3StatsDeferredTransmissions */ 359 uint32_t crc_err; /* dot3StatsFCSErrors */ 360 uint32_t in_short; 361 uint32_t no_rcvbuf; /* ifInDiscards */ 362 uint32_t intr; /* interrupt count */ 363 uint16_t chip_reset; 364 uint16_t phy_reset; 365 } rge_stats_t; 366 367 /* 368 * Per-instance soft-state structure 369 */ 370 typedef struct rge { 371 dev_info_t *devinfo; /* device instance */ 372 mac_handle_t mh; /* mac module handle */ 373 ddi_acc_handle_t cfg_handle; /* DDI I/O handle */ 374 ddi_acc_handle_t io_handle; /* DDI I/O handle */ 375 caddr_t io_regs; /* mapped registers */ 376 ddi_periodic_t periodic_id; /* periodical callback */ 377 ddi_softint_handle_t resched_hdl; /* reschedule callback */ 378 ddi_softint_handle_t factotum_hdl; /* factotum callback */ 379 uint_t soft_pri; 380 ddi_intr_handle_t *htable; /* For array of interrupts */ 381 int intr_type; /* What type of interrupt */ 382 int intr_rqst; /* # of request intrs count */ 383 int intr_cnt; /* # of intrs count returned */ 384 uint_t intr_pri; /* Interrupt priority */ 385 int intr_cap; /* Interrupt capabilities */ 386 boolean_t msi_enable; 387 388 uint32_t ethmax_size; 389 uint32_t default_mtu; 390 uint32_t rxbuf_size; 391 uint32_t txbuf_size; 392 uint32_t chip_flags; 393 uint32_t head_room; 394 char ifname[8]; /* "rge0" ... "rge999" */ 395 int32_t instance; 396 uint32_t progress; /* attach tracking */ 397 uint32_t debug; /* per-instance debug */ 398 chip_id_t chipid; 399 400 /* 401 * These structures describe the blocks of memory allocated during 402 * attach(). They remain unchanged thereafter, although the memory 403 * they describe is carved up into various separate regions and may 404 * therefore be described by other structures as well. 405 */ 406 dma_area_t dma_area_rxdesc; 407 dma_area_t dma_area_txdesc; 408 dma_area_t dma_area_stats; 409 /* describes hardware statistics area */ 410 411 uint8_t netaddr[ETHERADDRL]; /* mac address */ 412 uint16_t int_mask; /* interrupt mask */ 413 414 /* used for multicast/promisc mode set */ 415 char mcast_refs[RGE_MCAST_BUF_SIZE]; 416 uint8_t mcast_hash[RGE_MCAST_NUM]; 417 boolean_t promisc; /* promisc state flag */ 418 419 /* used for recv */ 420 rge_bd_t *rx_ring; 421 dma_area_t rx_desc; 422 boolean_t rx_bcopy; 423 uint32_t rx_next; /* current rx bd index */ 424 sw_rbd_t *sw_rbds; 425 sw_rbd_t *free_srbds; 426 uint32_t rf_next; /* current free buf index */ 427 uint32_t rc_next; /* current recycle buf index */ 428 uint32_t rx_free; /* number of rx free buf */ 429 mac_resource_handle_t handle; 430 431 /* used for send */ 432 rge_bd_t *tx_ring; 433 dma_area_t tx_desc; 434 uint32_t tx_free; /* number of free tx bd */ 435 uint32_t tx_next; /* current tx bd index */ 436 uint32_t tc_next; /* current tx recycle index */ 437 uint32_t tx_flow; 438 uint32_t tc_tail; 439 sw_sbd_t *sw_sbds; 440 441 /* mutex */ 442 kmutex_t genlock[1]; /* i/o reg access */ 443 krwlock_t errlock[1]; /* rge restart */ 444 kmutex_t tx_lock[1]; /* send access */ 445 kmutex_t tc_lock[1]; /* send recycle access */ 446 kmutex_t rx_lock[1]; /* receive access */ 447 kmutex_t rc_lock[1]; /* receive recycle access */ 448 449 /* 450 * Miscellaneous operating variables (not synchronised) 451 */ 452 uint32_t watchdog; /* watches for Tx stall */ 453 boolean_t resched_needed; 454 uint32_t factotum_flag; /* softint pending */ 455 456 /* 457 * Physical layer 458 */ 459 rge_regno_t phy_mii_addr; /* should be (const) 1! */ 460 uint16_t link_down_count; 461 462 /* 463 * NDD parameters (protected by genlock) 464 */ 465 caddr_t nd_data_p; 466 nd_param_t nd_params[PARAM_COUNT]; 467 468 /* 469 * Driver kstats, protected by <genlock> where necessary 470 */ 471 kstat_t *rge_kstats[RGE_KSTAT_COUNT]; 472 473 /* H/W statistics */ 474 rge_hw_stats_t *hw_stats; 475 rge_stats_t stats; 476 enum rge_mac_state rge_mac_state; /* definitions above */ 477 enum rge_chip_state rge_chip_state; /* definitions above */ 478 } rge_t; 479 480 /* 481 * 'Progress' bit flags ... 482 */ 483 #define PROGRESS_CFG 0x0001 /* config space mapped */ 484 #define PROGRESS_REGS 0x0002 /* registers mapped */ 485 #define PROGRESS_RESCHED 0x0010 /* resched softint registered */ 486 #define PROGRESS_FACTOTUM 0x0020 /* factotum softint registered */ 487 #define PROGRESS_INTR 0X0040 /* h/w interrupt registered */ 488 /* and mutexen initialised */ 489 #define PROGRESS_INIT 0x0080 /* rx/buf/tx ring initialised */ 490 #define PROGRESS_PHY 0x0100 /* PHY initialised */ 491 #define PROGRESS_NDD 0x1000 /* NDD parameters set up */ 492 #define PROGRESS_KSTATS 0x2000 /* kstats created */ 493 #define PROGRESS_READY 0x8000 /* ready for work */ 494 495 /* 496 * Special chip flags 497 */ 498 #define CHIP_FLAG_FORCE_BCOPY 0x10000000 499 500 /* 501 * Shorthand for the NDD parameters 502 */ 503 #define param_adv_autoneg nd_params[PARAM_ADV_AUTONEG_CAP].ndp_val 504 #define param_adv_pause nd_params[PARAM_ADV_PAUSE_CAP].ndp_val 505 #define param_adv_asym_pause nd_params[PARAM_ADV_ASYM_PAUSE_CAP].ndp_val 506 #define param_adv_1000fdx nd_params[PARAM_ADV_1000FDX_CAP].ndp_val 507 #define param_adv_1000hdx nd_params[PARAM_ADV_1000HDX_CAP].ndp_val 508 #define param_adv_100fdx nd_params[PARAM_ADV_100FDX_CAP].ndp_val 509 #define param_adv_100hdx nd_params[PARAM_ADV_100HDX_CAP].ndp_val 510 #define param_adv_10fdx nd_params[PARAM_ADV_10FDX_CAP].ndp_val 511 #define param_adv_10hdx nd_params[PARAM_ADV_10HDX_CAP].ndp_val 512 513 #define param_link_up nd_params[PARAM_LINK_STATUS].ndp_val 514 #define param_link_speed nd_params[PARAM_LINK_SPEED].ndp_val 515 #define param_link_duplex nd_params[PARAM_LINK_DUPLEX].ndp_val 516 517 #define param_loop_mode nd_params[PARAM_LOOP_MODE].ndp_val 518 519 /* 520 * Sync a DMA area described by a dma_area_t 521 */ 522 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_hdl, \ 523 (area).offset, (area).alength, (flag))) 524 525 /* 526 * Find the (kernel virtual) address of block of memory 527 * described by a dma_area_t 528 */ 529 #define DMA_VPTR(area) ((area).mem_va) 530 531 /* 532 * Zero a block of memory described by a dma_area_t 533 */ 534 #define DMA_ZERO(area) bzero(DMA_VPTR(area), (area).alength) 535 536 /* 537 * Next/Last value of a cyclic index 538 */ 539 #define NEXT(index, limit) ((index)+1 < (limit) ? (index)+1 : 0); 540 #define LAST(index, limit) ((index) ? (index)-1 : (limit - 1)); 541 /* 542 * Property lookups 543 */ 544 #define RGE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 545 DDI_PROP_DONTPASS, (n)) 546 #define RGE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 547 DDI_PROP_DONTPASS, (n), -1) 548 549 /* 550 * Endian swap 551 */ 552 #ifdef _BIG_ENDIAN 553 #define RGE_BSWAP_16(x) ((((x) & 0xff00) >> 8) | \ 554 (((x) & 0x00ff) << 8)) 555 #define RGE_BSWAP_32(x) ((((x) & 0xff000000) >> 24) | \ 556 (((x) & 0x00ff0000) >> 8) | \ 557 (((x) & 0x0000ff00) << 8) | \ 558 (((x) & 0x000000ff) << 24)) 559 #define RGE_BSWAP_64(x) (RGE_BSWAP_32((x) >> 32) | \ 560 (RGE_BSWAP_32(x) << 32)) 561 #else 562 #define RGE_BSWAP_16(x) (x) 563 #define RGE_BSWAP_32(x) (x) 564 #define RGE_BSWAP_64(x) (x) 565 #endif 566 567 /* 568 * Bit test macros, returning boolean_t values 569 */ 570 #define BIS(w, b) (((w) & (b)) ? B_TRUE : B_FALSE) 571 #define BIC(w, b) (((w) & (b)) ? B_FALSE : B_TRUE) 572 #define UPORDOWN(x) ((x) ? "up" : "down") 573 574 /* 575 * Bit flags in the 'debug' word ... 576 */ 577 #define RGE_DBG_STOP 0x00000001 /* early debug_enter() */ 578 #define RGE_DBG_TRACE 0x00000002 /* general flow tracing */ 579 580 #define RGE_DBG_REGS 0x00000010 /* low-level accesses */ 581 #define RGE_DBG_MII 0x00000020 /* low-level MII access */ 582 #define RGE_DBG_SEEPROM 0x00000040 /* low-level SEEPROM IO */ 583 #define RGE_DBG_CHIP 0x00000080 /* low(ish)-level code */ 584 585 #define RGE_DBG_RECV 0x00000100 /* receive-side code */ 586 #define RGE_DBG_SEND 0x00000200 /* packet-send code */ 587 588 #define RGE_DBG_INT 0x00001000 /* interrupt handler */ 589 #define RGE_DBG_FACT 0x00002000 /* factotum (softint) */ 590 591 #define RGE_DBG_PHY 0x00010000 /* Copper PHY code */ 592 #define RGE_DBG_SERDES 0x00020000 /* SerDes code */ 593 #define RGE_DBG_PHYS 0x00040000 /* Physical layer code */ 594 #define RGE_DBG_LINK 0x00080000 /* Link status check */ 595 596 #define RGE_DBG_INIT 0x00100000 /* initialisation */ 597 #define RGE_DBG_NEMO 0x00200000 /* nemo interaction */ 598 #define RGE_DBG_ADDR 0x00400000 /* address-setting code */ 599 #define RGE_DBG_STATS 0x00800000 /* statistics */ 600 601 #define RGE_DBG_IOCTL 0x01000000 /* ioctl handling */ 602 #define RGE_DBG_LOOP 0x02000000 /* loopback ioctl code */ 603 #define RGE_DBG_PPIO 0x04000000 /* Peek/poke ioctls */ 604 #define RGE_DBG_BADIOC 0x08000000 /* unknown ioctls */ 605 606 #define RGE_DBG_MCTL 0x10000000 /* mctl (csum) code */ 607 #define RGE_DBG_NDD 0x20000000 /* NDD operations */ 608 609 /* 610 * Debugging ... 611 */ 612 #ifdef DEBUG 613 #define RGE_DEBUGGING 1 614 #else 615 #define RGE_DEBUGGING 0 616 #endif /* DEBUG */ 617 618 619 /* 620 * 'Do-if-debugging' macro. The parameter <command> should be one or more 621 * C statements (but without the *final* semicolon), which will either be 622 * compiled inline or completely ignored, depending on the RGE_DEBUGGING 623 * compile-time flag. 624 * 625 * You should get a compile-time error (at least on a DEBUG build) if 626 * your statement isn't actually a statement, rather than unexpected 627 * run-time behaviour caused by unintended matching of if-then-elses etc. 628 * 629 * Note that the RGE_DDB() macro itself can only be used as a statement, 630 * not an expression, and should always be followed by a semicolon. 631 */ 632 #if RGE_DEBUGGING 633 #define RGE_DDB(command) do { \ 634 { command; } \ 635 _NOTE(CONSTANTCONDITION) \ 636 } while (0) 637 #else /* RGE_DEBUGGING */ 638 #define RGE_DDB(command) do { \ 639 { _NOTE(EMPTY); } \ 640 _NOTE(CONSTANTCONDITION) \ 641 } while (0) 642 #endif /* RGE_DEBUGGING */ 643 644 /* 645 * 'Internal' macros used to construct the TRACE/DEBUG macros below. 646 * These provide the primitive conditional-call capability required. 647 * Note: the parameter <args> is a parenthesised list of the actual 648 * printf-style arguments to be passed to the debug function ... 649 */ 650 #define RGE_XDB(b, w, f, args) RGE_DDB(if ((b) & (w)) f args) 651 #define RGE_GDB(b, args) RGE_XDB(b, rge_debug, (*rge_gdb()), args) 652 #define RGE_LDB(b, args) RGE_XDB(b, rgep->debug, (*rge_db(rgep)), args) 653 #define RGE_CDB(f, args) RGE_XDB(RGE_DBG, rgep->debug, f, args) 654 655 /* 656 * Conditional-print macros. 657 * 658 * Define RGE_DBG to be the relevant member of the set of RGE_DBG_* values 659 * above before using the RGE_GDEBUG() or RGE_DEBUG() macros. The 'G' 660 * versions look at the Global debug flag word (rge_debug); the non-G 661 * versions look in the per-instance data (rgep->debug) and so require a 662 * variable called 'rgep' to be in scope (and initialised!) before use. 663 * 664 * You could redefine RGE_TRC too if you really need two different 665 * flavours of debugging output in the same area of code, but I don't 666 * really recommend it. 667 * 668 * Note: the parameter <args> is a parenthesised list of the actual 669 * arguments to be passed to the debug function, usually a printf-style 670 * format string and corresponding values to be formatted. 671 */ 672 673 #define RGE_TRC RGE_DBG_TRACE /* default 'trace' bit */ 674 #define RGE_GTRACE(args) RGE_GDB(RGE_TRC, args) 675 #define RGE_GDEBUG(args) RGE_GDB(RGE_DBG, args) 676 #define RGE_TRACE(args) RGE_LDB(RGE_TRC, args) 677 #define RGE_DEBUG(args) RGE_LDB(RGE_DBG, args) 678 679 /* 680 * Debug-only action macros 681 */ 682 #define RGE_BRKPT(rgep, s) RGE_DDB(rge_dbg_enter(rgep, s)) 683 #define RGE_MARK(rgep) RGE_DDB(rge_led_mark(rgep)) 684 #define RGE_PCICHK(rgep) RGE_DDB(rge_pci_check(rgep)) 685 #define RGE_PKTDUMP(args) RGE_DDB(rge_pkt_dump args) 686 #define RGE_REPORT(args) RGE_DDB(rge_log args) 687 688 /* 689 * Inter-source-file linkage ... 690 */ 691 692 /* rge_chip.c */ 693 uint16_t rge_mii_get16(rge_t *rgep, uintptr_t mii); 694 void rge_mii_put16(rge_t *rgep, uintptr_t mii, uint16_t data); 695 void rge_chip_cfg_init(rge_t *rgep, chip_id_t *cidp); 696 void rge_chip_ident(rge_t *rgep); 697 int rge_chip_reset(rge_t *rgep); 698 void rge_chip_init(rge_t *rgep); 699 void rge_chip_start(rge_t *rgep); 700 void rge_chip_stop(rge_t *rgep, boolean_t fault); 701 void rge_chip_sync(rge_t *rgep, enum rge_sync_op todo); 702 void rge_chip_blank(void *arg, time_t ticks, uint_t count); 703 void rge_tx_trigger(rge_t *rgep); 704 void rge_hw_stats_dump(rge_t *rgep); 705 uint_t rge_intr(caddr_t arg1, caddr_t arg2); 706 uint_t rge_chip_factotum(caddr_t arg1, caddr_t arg2); 707 void rge_chip_cyclic(void *arg); 708 enum ioc_reply rge_chip_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp, 709 struct iocblk *iocp); 710 boolean_t rge_phy_reset(rge_t *rgep); 711 void rge_phy_init(rge_t *rgep); 712 void rge_phy_update(rge_t *rgep); 713 714 /* rge_kstats.c */ 715 void rge_init_kstats(rge_t *rgep, int instance); 716 void rge_fini_kstats(rge_t *rgep); 717 int rge_m_stat(void *arg, uint_t stat, uint64_t *val); 718 719 /* rge_log.c */ 720 #if RGE_DEBUGGING 721 void (*rge_db(rge_t *rgep))(const char *fmt, ...); 722 void (*rge_gdb(void))(const char *fmt, ...); 723 void rge_pkt_dump(rge_t *rgep, rge_bd_t *hbp, sw_rbd_t *sdp, const char *msg); 724 void rge_dbg_enter(rge_t *rgep, const char *msg); 725 #endif /* RGE_DEBUGGING */ 726 void rge_problem(rge_t *rgep, const char *fmt, ...); 727 void rge_notice(rge_t *rgep, const char *fmt, ...); 728 void rge_log(rge_t *rgep, const char *fmt, ...); 729 void rge_error(rge_t *rgep, const char *fmt, ...); 730 extern kmutex_t rge_log_mutex[1]; 731 extern uint32_t rge_debug; 732 733 /* rge_main.c */ 734 void rge_restart(rge_t *rgep); 735 736 /* rge_ndd.c */ 737 int rge_nd_init(rge_t *rgep); 738 enum ioc_reply rge_nd_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp, 739 struct iocblk *iocp); 740 void rge_nd_cleanup(rge_t *rgep); 741 742 /* rge_rxtx.c */ 743 void rge_rx_recycle(caddr_t arg); 744 void rge_receive(rge_t *rgep); 745 mblk_t *rge_m_tx(void *arg, mblk_t *mp); 746 uint_t rge_reschedule(caddr_t arg1, caddr_t arg2); 747 748 #ifdef __cplusplus 749 } 750 #endif 751 752 #endif /* _RGE_H */ 753