1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * Common x86 and SPARC PCI-E to PCI bus bridge nexus driver 28 */ 29 30 #include <sys/sysmacros.h> 31 #include <sys/conf.h> 32 #include <sys/kmem.h> 33 #include <sys/debug.h> 34 #include <sys/modctl.h> 35 #include <sys/autoconf.h> 36 #include <sys/ddi_impldefs.h> 37 #include <sys/pci.h> 38 #include <sys/ddi.h> 39 #include <sys/sunddi.h> 40 #include <sys/sunndi.h> 41 #include <sys/fm/util.h> 42 #include <sys/pcie.h> 43 #include <sys/pci_cap.h> 44 #include <sys/pcie_impl.h> 45 #include <sys/hotplug/pci/pcihp.h> 46 #include <sys/hotplug/pci/pciehpc.h> 47 #include <sys/hotplug/pci/pcishpc.h> 48 #include <sys/open.h> 49 #include <sys/stat.h> 50 #include <sys/file.h> 51 #include <sys/promif.h> /* prom_printf */ 52 #include <sys/disp.h> 53 #include <sys/pcie_pwr.h> 54 #include "pcieb.h" 55 #ifdef PX_PLX 56 #include <io/pciex/pcieb_plx.h> 57 #endif /* PX_PLX */ 58 59 /*LINTLIBRARY*/ 60 61 /* panic flag */ 62 int pcieb_die = PF_ERR_FATAL_FLAGS; 63 64 /* flag to turn on MSI support */ 65 int pcieb_enable_msi = 1; 66 67 #if defined(DEBUG) 68 uint_t pcieb_dbg_print = 0; 69 70 static char *pcieb_debug_sym [] = { /* same sequence as pcieb_debug_bit */ 71 /* 0 */ "attach", 72 /* 1 */ "pwr", 73 /* 2 */ "intr" 74 }; 75 #endif /* DEBUG */ 76 77 static int pcieb_bus_map(dev_info_t *, dev_info_t *, ddi_map_req_t *, off_t, 78 off_t, caddr_t *); 79 static int pcieb_ctlops(dev_info_t *, dev_info_t *, ddi_ctl_enum_t, void *, 80 void *); 81 static int pcieb_fm_init(pcieb_devstate_t *pcieb_p); 82 static void pcieb_fm_fini(pcieb_devstate_t *pcieb_p); 83 static int pcieb_fm_init_child(dev_info_t *dip, dev_info_t *cdip, int cap, 84 ddi_iblock_cookie_t *ibc_p); 85 static int pcieb_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, 86 ddi_dma_attr_t *attr_p, int (*waitfp)(caddr_t), caddr_t arg, 87 ddi_dma_handle_t *handlep); 88 static int pcieb_dma_mctl(dev_info_t *dip, dev_info_t *rdip, 89 ddi_dma_handle_t handle, enum ddi_dma_ctlops cmd, off_t *offp, 90 size_t *lenp, caddr_t *objp, uint_t cache_flags); 91 static int pcieb_intr_ops(dev_info_t *dip, dev_info_t *rdip, 92 ddi_intr_op_t intr_op, ddi_intr_handle_impl_t *hdlp, void *result); 93 94 static struct bus_ops pcieb_bus_ops = { 95 BUSO_REV, 96 pcieb_bus_map, 97 0, 98 0, 99 0, 100 i_ddi_map_fault, 101 ddi_dma_map, 102 pcieb_dma_allochdl, 103 ddi_dma_freehdl, 104 ddi_dma_bindhdl, 105 ddi_dma_unbindhdl, 106 ddi_dma_flush, 107 ddi_dma_win, 108 pcieb_dma_mctl, 109 pcieb_ctlops, 110 ddi_bus_prop_op, 111 ndi_busop_get_eventcookie, /* (*bus_get_eventcookie)(); */ 112 ndi_busop_add_eventcall, /* (*bus_add_eventcall)(); */ 113 ndi_busop_remove_eventcall, /* (*bus_remove_eventcall)(); */ 114 ndi_post_event, /* (*bus_post_event)(); */ 115 NULL, /* (*bus_intr_ctl)(); */ 116 NULL, /* (*bus_config)(); */ 117 NULL, /* (*bus_unconfig)(); */ 118 pcieb_fm_init_child, /* (*bus_fm_init)(); */ 119 NULL, /* (*bus_fm_fini)(); */ 120 i_ndi_busop_access_enter, /* (*bus_fm_access_enter)(); */ 121 i_ndi_busop_access_exit, /* (*bus_fm_access_exit)(); */ 122 pcie_bus_power, /* (*bus_power)(); */ 123 pcieb_intr_ops /* (*bus_intr_op)(); */ 124 }; 125 126 static int pcieb_open(dev_t *, int, int, cred_t *); 127 static int pcieb_close(dev_t, int, int, cred_t *); 128 static int pcieb_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 129 static int pcieb_prop_op(dev_t, dev_info_t *, ddi_prop_op_t, int, char *, 130 caddr_t, int *); 131 static int pcieb_info(dev_info_t *, ddi_info_cmd_t, void *, void **); 132 static uint_t pcieb_intr_handler(caddr_t arg1, caddr_t arg2); 133 134 /* PM related functions */ 135 static int pcieb_pwr_setup(dev_info_t *dip); 136 static int pcieb_pwr_init_and_raise(dev_info_t *dip, pcie_pwr_t *pwr_p); 137 static void pcieb_pwr_teardown(dev_info_t *dip); 138 static int pcieb_pwr_disable(dev_info_t *dip); 139 140 /* Hotplug related functions */ 141 static int pcieb_pciehpc_probe(dev_info_t *dip, ddi_acc_handle_t config_handle); 142 static int pcieb_pcishpc_probe(dev_info_t *dip, ddi_acc_handle_t config_handle); 143 static int pcieb_init_hotplug(pcieb_devstate_t *pcieb); 144 static void pcieb_id_props(pcieb_devstate_t *pcieb); 145 146 /* 147 * soft state pointer 148 */ 149 void *pcieb_state; 150 151 static struct cb_ops pcieb_cb_ops = { 152 pcieb_open, /* open */ 153 pcieb_close, /* close */ 154 nodev, /* strategy */ 155 nodev, /* print */ 156 nodev, /* dump */ 157 nodev, /* read */ 158 nodev, /* write */ 159 pcieb_ioctl, /* ioctl */ 160 nodev, /* devmap */ 161 nodev, /* mmap */ 162 nodev, /* segmap */ 163 nochpoll, /* poll */ 164 pcieb_prop_op, /* cb_prop_op */ 165 NULL, /* streamtab */ 166 D_NEW | D_MP | D_HOTPLUG, /* Driver compatibility flag */ 167 CB_REV, /* rev */ 168 nodev, /* int (*cb_aread)() */ 169 nodev /* int (*cb_awrite)() */ 170 }; 171 172 static int pcieb_probe(dev_info_t *); 173 static int pcieb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd); 174 static int pcieb_detach(dev_info_t *devi, ddi_detach_cmd_t cmd); 175 176 static struct dev_ops pcieb_ops = { 177 DEVO_REV, /* devo_rev */ 178 0, /* refcnt */ 179 pcieb_info, /* info */ 180 nulldev, /* identify */ 181 pcieb_probe, /* probe */ 182 pcieb_attach, /* attach */ 183 pcieb_detach, /* detach */ 184 nulldev, /* reset */ 185 &pcieb_cb_ops, /* driver operations */ 186 &pcieb_bus_ops, /* bus operations */ 187 pcie_power, /* power */ 188 ddi_quiesce_not_needed, /* quiesce */ 189 }; 190 191 /* 192 * Module linkage information for the kernel. 193 */ 194 195 static struct modldrv modldrv = { 196 &mod_driverops, /* Type of module */ 197 "PCIe to PCI nexus driver", 198 &pcieb_ops, /* driver ops */ 199 }; 200 201 static struct modlinkage modlinkage = { 202 MODREV_1, 203 (void *)&modldrv, 204 NULL 205 }; 206 207 /* 208 * forward function declarations: 209 */ 210 static void pcieb_uninitchild(dev_info_t *); 211 static int pcieb_initchild(dev_info_t *child); 212 static void pcieb_create_ranges_prop(dev_info_t *, ddi_acc_handle_t); 213 static boolean_t pcieb_is_pcie_device_type(dev_info_t *dip); 214 215 /* interrupt related declarations */ 216 static int pcieb_msi_supported(dev_info_t *); 217 static int pcieb_intr_attach(pcieb_devstate_t *pcieb); 218 static int pcieb_intr_init(pcieb_devstate_t *pcieb_p, int intr_type); 219 static void pcieb_intr_fini(pcieb_devstate_t *pcieb_p); 220 221 int 222 _init(void) 223 { 224 int e; 225 226 if ((e = ddi_soft_state_init(&pcieb_state, sizeof (pcieb_devstate_t), 227 1)) == 0 && (e = mod_install(&modlinkage)) != 0) 228 ddi_soft_state_fini(&pcieb_state); 229 return (e); 230 } 231 232 int 233 _fini(void) 234 { 235 int e; 236 237 if ((e = mod_remove(&modlinkage)) == 0) { 238 ddi_soft_state_fini(&pcieb_state); 239 } 240 return (e); 241 } 242 243 int 244 _info(struct modinfo *modinfop) 245 { 246 return (mod_info(&modlinkage, modinfop)); 247 } 248 249 /*ARGSUSED*/ 250 static int 251 pcieb_probe(dev_info_t *devi) 252 { 253 return (DDI_PROBE_SUCCESS); 254 } 255 256 static int 257 pcieb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd) 258 { 259 int instance; 260 char device_type[8]; 261 pcieb_devstate_t *pcieb; 262 pcie_bus_t *bus_p = PCIE_DIP2UPBUS(devi); 263 ddi_acc_handle_t config_handle = bus_p->bus_cfg_hdl; 264 uint8_t dev_type = bus_p->bus_dev_type; 265 266 switch (cmd) { 267 case DDI_RESUME: 268 (void) pcie_pwr_resume(devi); 269 return (DDI_SUCCESS); 270 271 default: 272 return (DDI_FAILURE); 273 274 case DDI_ATTACH: 275 break; 276 } 277 278 if (!(PCIE_IS_BDG(bus_p))) { 279 PCIEB_DEBUG(DBG_ATTACH, devi, "This is not a switch or" 280 " bridge\n"); 281 return (DDI_FAILURE); 282 } 283 284 /* 285 * If PCIE_LINKCTL_LINK_DISABLE bit in the PCIe Config 286 * Space (PCIe Capability Link Control Register) is set, 287 * then do not bind the driver. 288 */ 289 if (PCIE_CAP_GET(16, bus_p, PCIE_LINKCTL) & PCIE_LINKCTL_LINK_DISABLE) 290 return (DDI_FAILURE); 291 292 /* 293 * Allocate and get soft state structure. 294 */ 295 instance = ddi_get_instance(devi); 296 if (ddi_soft_state_zalloc(pcieb_state, instance) != DDI_SUCCESS) 297 return (DDI_FAILURE); 298 pcieb = ddi_get_soft_state(pcieb_state, instance); 299 pcieb->pcieb_dip = devi; 300 pcieb->pcieb_soft_state = PCIEB_SOFT_STATE_CLOSED; 301 302 if ((pcieb_fm_init(pcieb)) != DDI_SUCCESS) { 303 PCIEB_DEBUG(DBG_ATTACH, devi, "Failed in pcieb_fm_init\n"); 304 goto fail; 305 } 306 pcieb->pcieb_init_flags |= PCIEB_INIT_FM; 307 308 mutex_init(&pcieb->pcieb_mutex, NULL, MUTEX_DRIVER, NULL); 309 mutex_init(&pcieb->pcieb_err_mutex, NULL, MUTEX_DRIVER, 310 (void *)pcieb->pcieb_fm_ibc); 311 mutex_init(&pcieb->pcieb_peek_poke_mutex, NULL, MUTEX_DRIVER, 312 (void *)pcieb->pcieb_fm_ibc); 313 314 /* create special properties for device identification */ 315 pcieb_id_props(pcieb); 316 317 /* 318 * Power management setup. This also makes sure that switch/bridge 319 * is at D0 during attach. 320 */ 321 if (pwr_common_setup(devi) != DDI_SUCCESS) { 322 PCIEB_DEBUG(DBG_PWR, devi, "pwr_common_setup failed\n"); 323 goto fail; 324 } 325 326 if (pcieb_pwr_setup(devi) != DDI_SUCCESS) { 327 PCIEB_DEBUG(DBG_PWR, devi, "pxb_pwr_setup failed \n"); 328 goto fail; 329 } 330 331 /* 332 * Make sure the "device_type" property exists. 333 */ 334 if (pcieb_is_pcie_device_type(devi)) 335 (void) strcpy(device_type, "pciex"); 336 else 337 (void) strcpy(device_type, "pci"); 338 339 (void) ddi_prop_update_string(DDI_DEV_T_NONE, devi, 340 "device_type", device_type); 341 342 /* 343 * Check whether the "ranges" property is present. 344 * Otherwise create the ranges property by reading 345 * the configuration registers 346 */ 347 if (ddi_prop_exists(DDI_DEV_T_ANY, devi, DDI_PROP_DONTPASS, 348 "ranges") == 0) { 349 pcieb_create_ranges_prop(devi, config_handle); 350 } 351 352 if (PCIE_IS_PCI_BDG(bus_p)) 353 pcieb_set_pci_perf_parameters(devi, config_handle); 354 355 #ifdef PX_PLX 356 pcieb_attach_plx_workarounds(pcieb); 357 #endif /* PX_PLX */ 358 359 /* Initialize hotplug */ 360 pcieb->pcieb_hotplug_capable = B_FALSE; 361 362 if ((dev_type == PCIE_PCIECAP_DEV_TYPE_DOWN) || 363 (dev_type == PCIE_PCIECAP_DEV_TYPE_ROOT) || 364 (dev_type == PCIE_PCIECAP_DEV_TYPE_PCIE2PCI) || 365 (dev_type == PCIE_PCIECAP_DEV_TYPE_PCI2PCIE)) { 366 (void) pcieb_init_hotplug(pcieb); 367 } 368 369 /* 370 * Initialize interrupt handlers. Ignore return value. 371 */ 372 (void) pcieb_intr_attach(pcieb); 373 374 if (pcieb->pcieb_hotplug_capable == B_FALSE) { 375 /* 376 * (for non hotplug bus) this would create ":devctl" minor 377 * node to support DEVCTL_DEVICE_* and DEVCTL_BUS_* ioctls 378 * to this bus. 379 */ 380 if (ddi_create_minor_node(devi, "devctl", S_IFCHR, 381 PCIHP_AP_MINOR_NUM(instance, PCIHP_DEVCTL_MINOR), 382 DDI_NT_NEXUS, 0) != DDI_SUCCESS) 383 goto fail; 384 } 385 386 PCIEB_DEBUG(DBG_ATTACH, devi, 387 "pcieb_attach: this nexus %s hotplug slots\n", 388 pcieb->pcieb_hotplug_capable == B_TRUE ? "has":"has no"); 389 390 /* Do any platform specific workarounds needed at this time */ 391 pcieb_plat_attach_workaround(devi); 392 393 /* 394 * If this is a root port, determine and set the max payload size. 395 * Since this will involve scanning the fabric, all error enabling 396 * and sw workarounds should be in place before doing this. 397 */ 398 if (PCIE_IS_RP(bus_p)) 399 pcie_init_root_port_mps(devi); 400 401 ddi_report_dev(devi); 402 return (DDI_SUCCESS); 403 404 fail: 405 (void) pcieb_detach(devi, DDI_DETACH); 406 return (DDI_FAILURE); 407 } 408 409 static int 410 pcieb_detach(dev_info_t *devi, ddi_detach_cmd_t cmd) 411 { 412 pcieb_devstate_t *pcieb; 413 int error = DDI_SUCCESS; 414 415 switch (cmd) { 416 case DDI_SUSPEND: 417 error = pcie_pwr_suspend(devi); 418 return (error); 419 420 case DDI_DETACH: 421 break; 422 423 default: 424 return (DDI_FAILURE); 425 } 426 427 pcieb = ddi_get_soft_state(pcieb_state, ddi_get_instance(devi)); 428 429 /* remove interrupt handlers */ 430 pcieb_intr_fini(pcieb); 431 432 if (pcieb->pcieb_hotplug_capable == B_TRUE) { 433 if (pcihp_uninit(devi) == DDI_FAILURE) 434 error = DDI_FAILURE; 435 436 if (pcieb->pcieb_hpc_type == HPC_PCIE) 437 (void) pciehpc_uninit(devi); 438 else if (pcieb->pcieb_hpc_type == HPC_SHPC) 439 (void) pcishpc_uninit(devi); 440 441 (void) ndi_prop_remove(DDI_DEV_T_NONE, devi, "hotplug-capable"); 442 } else { 443 ddi_remove_minor_node(devi, "devctl"); 444 } 445 446 (void) ddi_prop_remove(DDI_DEV_T_NONE, devi, "device_type"); 447 448 (void) ndi_prop_remove(DDI_DEV_T_NONE, pcieb->pcieb_dip, 449 "pcie_ce_mask"); 450 451 if (pcieb->pcieb_init_flags & PCIEB_INIT_FM) 452 pcieb_fm_fini(pcieb); 453 454 pcieb_pwr_teardown(devi); 455 pwr_common_teardown(devi); 456 457 mutex_destroy(&pcieb->pcieb_peek_poke_mutex); 458 mutex_destroy(&pcieb->pcieb_err_mutex); 459 mutex_destroy(&pcieb->pcieb_mutex); 460 461 /* 462 * And finally free the per-pci soft state. 463 */ 464 ddi_soft_state_free(pcieb_state, ddi_get_instance(devi)); 465 466 return (DDI_SUCCESS); 467 } 468 469 static int 470 pcieb_bus_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, 471 off_t offset, off_t len, caddr_t *vaddrp) 472 { 473 dev_info_t *pdip; 474 475 pdip = (dev_info_t *)DEVI(dip)->devi_parent; 476 return ((DEVI(pdip)->devi_ops->devo_bus_ops->bus_map)(pdip, rdip, mp, 477 offset, len, vaddrp)); 478 } 479 480 static int 481 pcieb_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_ctl_enum_t ctlop, 482 void *arg, void *result) 483 { 484 pci_regspec_t *drv_regp; 485 int reglen; 486 int rn; 487 int totreg; 488 pcieb_devstate_t *pcieb = ddi_get_soft_state(pcieb_state, 489 ddi_get_instance(dip)); 490 struct detachspec *ds; 491 struct attachspec *as; 492 493 switch (ctlop) { 494 case DDI_CTLOPS_REPORTDEV: 495 if (rdip == (dev_info_t *)0) 496 return (DDI_FAILURE); 497 cmn_err(CE_CONT, "?PCIE-device: %s@%s, %s%d\n", 498 ddi_node_name(rdip), ddi_get_name_addr(rdip), 499 ddi_driver_name(rdip), 500 ddi_get_instance(rdip)); 501 return (DDI_SUCCESS); 502 503 case DDI_CTLOPS_INITCHILD: 504 return (pcieb_initchild((dev_info_t *)arg)); 505 506 case DDI_CTLOPS_UNINITCHILD: 507 pcieb_uninitchild((dev_info_t *)arg); 508 return (DDI_SUCCESS); 509 510 case DDI_CTLOPS_SIDDEV: 511 return (DDI_SUCCESS); 512 513 case DDI_CTLOPS_REGSIZE: 514 case DDI_CTLOPS_NREGS: 515 if (rdip == (dev_info_t *)0) 516 return (DDI_FAILURE); 517 break; 518 519 case DDI_CTLOPS_PEEK: 520 case DDI_CTLOPS_POKE: 521 return (pcieb_plat_peekpoke(dip, rdip, ctlop, arg, result)); 522 case DDI_CTLOPS_ATTACH: 523 if (!pcie_is_child(dip, rdip)) 524 return (DDI_SUCCESS); 525 526 as = (struct attachspec *)arg; 527 switch (as->when) { 528 case DDI_PRE: 529 if (as->cmd == DDI_RESUME) { 530 pcie_clear_errors(rdip); 531 if (pcieb_plat_ctlops(rdip, ctlop, arg) != 532 DDI_SUCCESS) 533 return (DDI_FAILURE); 534 } 535 536 if (as->cmd == DDI_ATTACH) 537 return (pcie_pm_hold(dip)); 538 539 return (DDI_SUCCESS); 540 541 case DDI_POST: 542 if (as->cmd == DDI_ATTACH && as->result != DDI_SUCCESS) 543 pcie_pm_release(dip); 544 545 if (as->result == DDI_SUCCESS) { 546 pf_init(rdip, (void *)pcieb->pcieb_fm_ibc, 547 as->cmd); 548 549 (void) pcieb_plat_ctlops(rdip, ctlop, arg); 550 } 551 552 /* 553 * For empty hotplug-capable slots, we should explicitly 554 * disable the errors, so that we won't panic upon 555 * unsupported hotplug messages. 556 */ 557 if ((!ddi_prop_exists(DDI_DEV_T_ANY, rdip, 558 DDI_PROP_DONTPASS, "hotplug-capable")) || 559 ddi_get_child(rdip)) { 560 (void) pcie_postattach_child(rdip); 561 return (DDI_SUCCESS); 562 } 563 564 pcie_disable_errors(rdip); 565 566 return (DDI_SUCCESS); 567 default: 568 break; 569 } 570 return (DDI_SUCCESS); 571 572 case DDI_CTLOPS_DETACH: 573 if (!pcie_is_child(dip, rdip)) 574 return (DDI_SUCCESS); 575 576 ds = (struct detachspec *)arg; 577 switch (ds->when) { 578 case DDI_PRE: 579 pf_fini(rdip, ds->cmd); 580 return (DDI_SUCCESS); 581 582 case DDI_POST: 583 if (pcieb_plat_ctlops(rdip, ctlop, arg) != DDI_SUCCESS) 584 return (DDI_FAILURE); 585 if (ds->cmd == DDI_DETACH && 586 ds->result == DDI_SUCCESS) { 587 return (pcie_pm_remove_child(dip, rdip)); 588 } 589 return (DDI_SUCCESS); 590 default: 591 break; 592 } 593 return (DDI_SUCCESS); 594 default: 595 return (ddi_ctlops(dip, rdip, ctlop, arg, result)); 596 } 597 598 *(int *)result = 0; 599 if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, 600 DDI_PROP_DONTPASS | DDI_PROP_CANSLEEP, "reg", (caddr_t)&drv_regp, 601 ®len) != DDI_SUCCESS) 602 return (DDI_FAILURE); 603 604 totreg = reglen / sizeof (pci_regspec_t); 605 if (ctlop == DDI_CTLOPS_NREGS) 606 *(int *)result = totreg; 607 else if (ctlop == DDI_CTLOPS_REGSIZE) { 608 rn = *(int *)arg; 609 if (rn >= totreg) { 610 kmem_free(drv_regp, reglen); 611 return (DDI_FAILURE); 612 } 613 614 *(off_t *)result = drv_regp[rn].pci_size_low | 615 ((uint64_t)drv_regp[rn].pci_size_hi << 32); 616 } 617 618 kmem_free(drv_regp, reglen); 619 return (DDI_SUCCESS); 620 } 621 622 /* 623 * name_child 624 * 625 * This function is called from init_child to name a node. It is 626 * also passed as a callback for node merging functions. 627 * 628 * return value: DDI_SUCCESS, DDI_FAILURE 629 */ 630 static int 631 pcieb_name_child(dev_info_t *child, char *name, int namelen) 632 { 633 pci_regspec_t *pci_rp; 634 uint_t slot, func; 635 char **unit_addr; 636 uint_t n; 637 638 /* 639 * For .conf nodes, use unit-address property as name 640 */ 641 if (ndi_dev_is_persistent_node(child) == 0) { 642 if (ddi_prop_lookup_string_array(DDI_DEV_T_ANY, child, 643 DDI_PROP_DONTPASS, "unit-address", &unit_addr, &n) != 644 DDI_PROP_SUCCESS) { 645 cmn_err(CE_WARN, 646 "cannot find unit-address in %s.conf", 647 ddi_driver_name(child)); 648 return (DDI_FAILURE); 649 } 650 if (n != 1 || *unit_addr == NULL || **unit_addr == 0) { 651 cmn_err(CE_WARN, "unit-address property in %s.conf" 652 " not well-formed", ddi_driver_name(child)); 653 ddi_prop_free(unit_addr); 654 return (DDI_FAILURE); 655 } 656 (void) snprintf(name, namelen, "%s", *unit_addr); 657 ddi_prop_free(unit_addr); 658 return (DDI_SUCCESS); 659 } 660 661 /* 662 * Get the address portion of the node name based on 663 * the function and device number. 664 */ 665 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, child, 666 DDI_PROP_DONTPASS, "reg", (int **)&pci_rp, &n) != DDI_SUCCESS) { 667 return (DDI_FAILURE); 668 } 669 670 /* copy the device identifications */ 671 slot = PCI_REG_DEV_G(pci_rp[0].pci_phys_hi); 672 func = PCI_REG_FUNC_G(pci_rp[0].pci_phys_hi); 673 674 if (func != 0) 675 (void) snprintf(name, namelen, "%x,%x", slot, func); 676 else 677 (void) snprintf(name, namelen, "%x", slot); 678 679 ddi_prop_free(pci_rp); 680 return (DDI_SUCCESS); 681 } 682 683 static int 684 pcieb_initchild(dev_info_t *child) 685 { 686 char name[MAXNAMELEN]; 687 int result = DDI_FAILURE; 688 pcieb_devstate_t *pcieb = 689 (pcieb_devstate_t *)ddi_get_soft_state(pcieb_state, 690 ddi_get_instance(ddi_get_parent(child))); 691 692 /* 693 * Name the child 694 */ 695 if (pcieb_name_child(child, name, MAXNAMELEN) != DDI_SUCCESS) { 696 result = DDI_FAILURE; 697 goto done; 698 } 699 ddi_set_name_addr(child, name); 700 701 /* 702 * Pseudo nodes indicate a prototype node with per-instance 703 * properties to be merged into the real h/w device node. 704 * The interpretation of the unit-address is DD[,F] 705 * where DD is the device id and F is the function. 706 */ 707 if (ndi_dev_is_persistent_node(child) == 0) { 708 extern int pci_allow_pseudo_children; 709 710 /* 711 * Try to merge the properties from this prototype 712 * node into real h/w nodes. 713 */ 714 if (ndi_merge_node(child, pcieb_name_child) != DDI_SUCCESS) { 715 /* 716 * Merged ok - return failure to remove the node. 717 */ 718 ddi_set_name_addr(child, NULL); 719 result = DDI_FAILURE; 720 goto done; 721 } 722 723 /* workaround for ddivs to run under PCI-E */ 724 if (pci_allow_pseudo_children) { 725 result = DDI_SUCCESS; 726 goto done; 727 } 728 729 /* 730 * The child was not merged into a h/w node, 731 * but there's not much we can do with it other 732 * than return failure to cause the node to be removed. 733 */ 734 cmn_err(CE_WARN, "!%s@%s: %s.conf properties not merged", 735 ddi_driver_name(child), ddi_get_name_addr(child), 736 ddi_driver_name(child)); 737 ddi_set_name_addr(child, NULL); 738 result = DDI_NOT_WELL_FORMED; 739 goto done; 740 } 741 742 /* platform specific initchild */ 743 pcieb_plat_initchild(child); 744 745 if (pcie_pm_hold(pcieb->pcieb_dip) != DDI_SUCCESS) { 746 PCIEB_DEBUG(DBG_PWR, pcieb->pcieb_dip, 747 "INITCHILD: px_pm_hold failed\n"); 748 result = DDI_FAILURE; 749 goto done; 750 } 751 /* Any return from here must call pcie_pm_release */ 752 753 /* 754 * If configuration registers were previously saved by 755 * child (before it entered D3), then let the child do the 756 * restore to set up the config regs as it'll first need to 757 * power the device out of D3. 758 */ 759 if (ddi_prop_exists(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, 760 "config-regs-saved-by-child") == 1) { 761 PCIEB_DEBUG(DBG_PWR, ddi_get_parent(child), 762 "INITCHILD: config regs to be restored by child" 763 " for %s@%s\n", ddi_node_name(child), 764 ddi_get_name_addr(child)); 765 766 result = DDI_SUCCESS; 767 goto cleanup; 768 } 769 770 PCIEB_DEBUG(DBG_PWR, ddi_get_parent(child), 771 "INITCHILD: config regs setup for %s@%s\n", 772 ddi_node_name(child), ddi_get_name_addr(child)); 773 774 if (!pcie_init_bus(child) || pcie_initchild(child) != DDI_SUCCESS) { 775 result = DDI_FAILURE; 776 goto cleanup; 777 } 778 779 #ifdef PX_PLX 780 if (pcieb_init_plx_workarounds(pcieb, child) == DDI_FAILURE) { 781 result = DDI_FAILURE; 782 goto cleanup; 783 } 784 #endif /* PX_PLX */ 785 786 result = DDI_SUCCESS; 787 cleanup: 788 pcie_pm_release(pcieb->pcieb_dip); 789 done: 790 return (result); 791 } 792 793 static void 794 pcieb_uninitchild(dev_info_t *dip) 795 { 796 797 pcie_uninitchild(dip); 798 799 pcieb_plat_uninitchild(dip); 800 801 ddi_set_name_addr(dip, NULL); 802 803 /* 804 * Strip the node to properly convert it back to prototype form 805 */ 806 ddi_remove_minor_node(dip, NULL); 807 808 ddi_prop_remove_all(dip); 809 } 810 811 static boolean_t 812 pcieb_is_pcie_device_type(dev_info_t *dip) 813 { 814 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 815 816 if (PCIE_IS_SW(bus_p) || PCIE_IS_RP(bus_p) || PCIE_IS_PCI2PCIE(bus_p)) 817 return (B_TRUE); 818 819 return (B_FALSE); 820 } 821 822 static int 823 pcieb_intr_attach(pcieb_devstate_t *pcieb) 824 { 825 int intr_types; 826 dev_info_t *dip = pcieb->pcieb_dip; 827 828 /* Allow platform specific code to do any initialization first */ 829 pcieb_plat_intr_attach(pcieb); 830 831 /* 832 * Initialize interrupt handlers. 833 * If both MSI and FIXED are supported, try to attach MSI first. 834 * If MSI fails for any reason, then try FIXED, but only allow one 835 * type to be attached. 836 */ 837 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) { 838 PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_get_supported_types" 839 " failed\n"); 840 goto FAIL; 841 } 842 843 if ((intr_types & DDI_INTR_TYPE_MSI) && 844 (pcieb_msi_supported(dip) == DDI_SUCCESS)) { 845 if (pcieb_intr_init(pcieb, DDI_INTR_TYPE_MSI) == DDI_SUCCESS) 846 intr_types = DDI_INTR_TYPE_MSI; 847 else { 848 PCIEB_DEBUG(DBG_ATTACH, dip, "Unable to attach MSI" 849 " handler\n"); 850 } 851 } 852 853 if (intr_types != DDI_INTR_TYPE_MSI) { 854 /* 855 * MSIs are not supported or MSI initialization failed. For Root 856 * Ports mark this so error handling might try to fallback to 857 * some other mechanism if available (machinecheck etc.). 858 */ 859 if (PCIE_IS_RP(PCIE_DIP2UPBUS(dip))) 860 pcieb->pcieb_no_aer_msi = B_TRUE; 861 } 862 863 if (intr_types & DDI_INTR_TYPE_FIXED) { 864 if (pcieb_intr_init(pcieb, DDI_INTR_TYPE_FIXED) != 865 DDI_SUCCESS) { 866 PCIEB_DEBUG(DBG_ATTACH, dip, 867 "Unable to attach INTx handler\n"); 868 goto FAIL; 869 } 870 } 871 return (DDI_SUCCESS); 872 873 FAIL: 874 return (DDI_FAILURE); 875 } 876 877 /* 878 * This function initializes internally generated interrupts only. 879 * It does not affect any interrupts generated by downstream devices 880 * or the forwarding of them. 881 * 882 * Enable Device Specific Interrupts or Hotplug features here. 883 * Enabling features may change how many interrupts are requested 884 * by the device. If features are not enabled first, the 885 * device might not ask for any interrupts. 886 */ 887 888 static int 889 pcieb_intr_init(pcieb_devstate_t *pcieb, int intr_type) 890 { 891 dev_info_t *dip = pcieb->pcieb_dip; 892 int nintrs, request, count, x; 893 int intr_cap = 0; 894 int inum = 0; 895 int ret, hp_msi_off; 896 pcie_bus_t *bus_p = PCIE_DIP2UPBUS(dip); 897 uint16_t vendorid = bus_p->bus_dev_ven_id & 0xFFFF; 898 boolean_t is_hp = B_FALSE; 899 boolean_t is_pme = B_FALSE; 900 901 PCIEB_DEBUG(DBG_ATTACH, dip, "pcieb_intr_init: Attaching %s handler\n", 902 (intr_type == DDI_INTR_TYPE_MSI) ? "MSI" : "INTx"); 903 904 request = 0; 905 if (pcieb->pcieb_hotplug_capable) { 906 request++; 907 is_hp = B_TRUE; 908 } 909 910 /* 911 * Hotplug and PME share the same MSI vector. If hotplug is not 912 * supported check if MSI is needed for PME. 913 */ 914 if ((intr_type == DDI_INTR_TYPE_MSI) && PCIE_IS_RP(bus_p) && 915 (vendorid == NVIDIA_VENDOR_ID)) { 916 is_pme = B_TRUE; 917 if (!is_hp) 918 request++; 919 } 920 921 /* 922 * Setup MSI if this device is a Rootport and has AER. Currently no 923 * SPARC Root Port supports fabric errors being reported through it. 924 */ 925 if (intr_type == DDI_INTR_TYPE_MSI) { 926 if (PCIE_IS_RP(bus_p) && PCIE_HAS_AER(bus_p)) 927 request++; 928 } 929 930 if (request == 0) 931 return (DDI_SUCCESS); 932 933 /* 934 * Get number of supported interrupts. 935 * 936 * Several Bridges/Switches will not have this property set, resulting 937 * in a FAILURE, if the device is not configured in a way that 938 * interrupts are needed. (eg. hotplugging) 939 */ 940 ret = ddi_intr_get_nintrs(dip, intr_type, &nintrs); 941 if ((ret != DDI_SUCCESS) || (nintrs == 0)) { 942 PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_get_nintrs ret:%d" 943 " req:%d\n", ret, nintrs); 944 return (DDI_FAILURE); 945 } 946 947 PCIEB_DEBUG(DBG_ATTACH, dip, "bdf 0x%x: ddi_intr_get_nintrs: nintrs %d", 948 " request %d\n", bus_p->bus_bdf, nintrs, request); 949 950 if (request > nintrs) 951 request = nintrs; 952 953 /* Allocate an array of interrupt handlers */ 954 pcieb->pcieb_htable_size = sizeof (ddi_intr_handle_t) * request; 955 pcieb->pcieb_htable = kmem_zalloc(pcieb->pcieb_htable_size, 956 KM_SLEEP); 957 pcieb->pcieb_init_flags |= PCIEB_INIT_HTABLE; 958 959 ret = ddi_intr_alloc(dip, pcieb->pcieb_htable, intr_type, inum, 960 request, &count, DDI_INTR_ALLOC_NORMAL); 961 if ((ret != DDI_SUCCESS) || (count == 0)) { 962 PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_alloc() ret: %d ask: %d" 963 " actual: %d\n", ret, request, count); 964 goto FAIL; 965 } 966 pcieb->pcieb_init_flags |= PCIEB_INIT_ALLOC; 967 968 /* Save the actual number of interrupts allocated */ 969 pcieb->pcieb_intr_count = count; 970 if (count < request) { 971 PCIEB_DEBUG(DBG_ATTACH, dip, "bdf 0%x: Requested Intr: %d" 972 " Received: %d\n", bus_p->bus_bdf, request, count); 973 } 974 975 /* 976 * NVidia (MCP55 and other) chipsets have a errata that if the number 977 * of requested MSI intrs is not allocated we have to fall back to INTx. 978 */ 979 if (intr_type == DDI_INTR_TYPE_MSI) { 980 if (PCIE_IS_RP(bus_p) && (vendorid == NVIDIA_VENDOR_ID)) { 981 if (request != count) 982 goto FAIL; 983 } 984 } 985 986 /* Get interrupt priority */ 987 ret = ddi_intr_get_pri(pcieb->pcieb_htable[0], 988 &pcieb->pcieb_intr_priority); 989 if (ret != DDI_SUCCESS) { 990 PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_get_pri() ret: %d\n", 991 ret); 992 goto FAIL; 993 } 994 995 if (pcieb->pcieb_intr_priority >= LOCK_LEVEL) { 996 pcieb->pcieb_intr_priority = LOCK_LEVEL - 1; 997 ret = ddi_intr_set_pri(pcieb->pcieb_htable[0], 998 pcieb->pcieb_intr_priority); 999 if (ret != DDI_SUCCESS) { 1000 PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_set_pri() ret:" 1001 " %d\n", ret); 1002 1003 goto FAIL; 1004 } 1005 } 1006 1007 mutex_init(&pcieb->pcieb_intr_mutex, NULL, MUTEX_DRIVER, NULL); 1008 1009 pcieb->pcieb_init_flags |= PCIEB_INIT_MUTEX; 1010 1011 for (count = 0; count < pcieb->pcieb_intr_count; count++) { 1012 ret = ddi_intr_add_handler(pcieb->pcieb_htable[count], 1013 pcieb_intr_handler, (caddr_t)pcieb, 1014 (caddr_t)(uintptr_t)(inum + count)); 1015 1016 if (ret != DDI_SUCCESS) { 1017 PCIEB_DEBUG(DBG_ATTACH, dip, "Cannot add " 1018 "interrupt(%d)\n", ret); 1019 break; 1020 } 1021 } 1022 1023 /* If unsucessful, remove the added handlers */ 1024 if (ret != DDI_SUCCESS) { 1025 for (x = 0; x < count; x++) { 1026 (void) ddi_intr_remove_handler(pcieb->pcieb_htable[x]); 1027 } 1028 goto FAIL; 1029 } 1030 1031 pcieb->pcieb_init_flags |= PCIEB_INIT_HANDLER; 1032 1033 (void) ddi_intr_get_cap(pcieb->pcieb_htable[0], &intr_cap); 1034 1035 /* 1036 * Get this intr lock because we are not quite ready to handle 1037 * interrupts immediately after enabling it. The MSI multi register 1038 * gets programmed in ddi_intr_enable after which we need to get the 1039 * MSI offsets for Hotplug/AER. 1040 */ 1041 mutex_enter(&pcieb->pcieb_intr_mutex); 1042 1043 if (intr_cap & DDI_INTR_FLAG_BLOCK) { 1044 (void) ddi_intr_block_enable(pcieb->pcieb_htable, 1045 pcieb->pcieb_intr_count); 1046 pcieb->pcieb_init_flags |= PCIEB_INIT_BLOCK; 1047 } else { 1048 for (count = 0; count < pcieb->pcieb_intr_count; count++) { 1049 (void) ddi_intr_enable(pcieb->pcieb_htable[count]); 1050 } 1051 } 1052 pcieb->pcieb_init_flags |= PCIEB_INIT_ENABLE; 1053 1054 /* Save the interrupt type */ 1055 pcieb->pcieb_intr_type = intr_type; 1056 1057 /* Get the MSI offset for hotplug/PME from the PCIe cap reg */ 1058 if (intr_type == DDI_INTR_TYPE_MSI) { 1059 hp_msi_off = PCI_CAP_GET16(bus_p->bus_cfg_hdl, NULL, 1060 bus_p->bus_pcie_off, PCIE_PCIECAP) & 1061 PCIE_PCIECAP_INT_MSG_NUM; 1062 1063 if (hp_msi_off >= count) { 1064 PCIEB_DEBUG(DBG_ATTACH, dip, "MSI number %d in PCIe " 1065 "cap > max allocated %d\n", hp_msi_off, count); 1066 mutex_exit(&pcieb->pcieb_intr_mutex); 1067 goto FAIL; 1068 } 1069 1070 if (is_hp) 1071 pcieb->pcieb_isr_tab[hp_msi_off] |= PCIEB_INTR_SRC_HP; 1072 1073 if (is_pme) 1074 pcieb->pcieb_isr_tab[hp_msi_off] |= PCIEB_INTR_SRC_PME; 1075 } else { 1076 /* INTx handles only Hotplug interrupts */ 1077 if (is_hp) 1078 pcieb->pcieb_isr_tab[0] |= PCIEB_INTR_SRC_HP; 1079 } 1080 1081 1082 /* 1083 * Get the MSI offset for errors from the AER Root Error status 1084 * register. 1085 */ 1086 if ((intr_type == DDI_INTR_TYPE_MSI) && PCIE_IS_RP(bus_p)) { 1087 if (PCIE_HAS_AER(bus_p)) { 1088 int aer_msi_off; 1089 aer_msi_off = (PCI_XCAP_GET32(bus_p->bus_cfg_hdl, NULL, 1090 bus_p->bus_aer_off, PCIE_AER_RE_STS) >> 1091 PCIE_AER_RE_STS_MSG_NUM_SHIFT) & 1092 PCIE_AER_RE_STS_MSG_NUM_MASK; 1093 1094 if (aer_msi_off >= count) { 1095 PCIEB_DEBUG(DBG_ATTACH, dip, "MSI number %d in" 1096 " AER cap > max allocated %d\n", 1097 aer_msi_off, count); 1098 mutex_exit(&pcieb->pcieb_intr_mutex); 1099 goto FAIL; 1100 } 1101 pcieb->pcieb_isr_tab[aer_msi_off] |= PCIEB_INTR_SRC_AER; 1102 } else { 1103 /* 1104 * This RP does not have AER. Fallback to the 1105 * SERR+Machinecheck approach if available. 1106 */ 1107 pcieb->pcieb_no_aer_msi = B_TRUE; 1108 } 1109 } 1110 1111 mutex_exit(&pcieb->pcieb_intr_mutex); 1112 return (DDI_SUCCESS); 1113 1114 FAIL: 1115 pcieb_intr_fini(pcieb); 1116 return (DDI_FAILURE); 1117 } 1118 1119 static void 1120 pcieb_intr_fini(pcieb_devstate_t *pcieb) 1121 { 1122 int x; 1123 int count = pcieb->pcieb_intr_count; 1124 int flags = pcieb->pcieb_init_flags; 1125 1126 if ((flags & PCIEB_INIT_ENABLE) && 1127 (flags & PCIEB_INIT_BLOCK)) { 1128 (void) ddi_intr_block_disable(pcieb->pcieb_htable, count); 1129 flags &= ~(PCIEB_INIT_ENABLE | 1130 PCIEB_INIT_BLOCK); 1131 } 1132 1133 if (flags & PCIEB_INIT_MUTEX) 1134 mutex_destroy(&pcieb->pcieb_intr_mutex); 1135 1136 for (x = 0; x < count; x++) { 1137 if (flags & PCIEB_INIT_ENABLE) 1138 (void) ddi_intr_disable(pcieb->pcieb_htable[x]); 1139 1140 if (flags & PCIEB_INIT_HANDLER) 1141 (void) ddi_intr_remove_handler(pcieb->pcieb_htable[x]); 1142 1143 if (flags & PCIEB_INIT_ALLOC) 1144 (void) ddi_intr_free(pcieb->pcieb_htable[x]); 1145 } 1146 1147 flags &= ~(PCIEB_INIT_ENABLE | PCIEB_INIT_HANDLER | PCIEB_INIT_ALLOC | 1148 PCIEB_INIT_MUTEX); 1149 1150 if (flags & PCIEB_INIT_HTABLE) 1151 kmem_free(pcieb->pcieb_htable, pcieb->pcieb_htable_size); 1152 1153 flags &= ~PCIEB_INIT_HTABLE; 1154 1155 pcieb->pcieb_init_flags &= flags; 1156 } 1157 1158 /* 1159 * Checks if this device needs MSIs enabled or not. 1160 */ 1161 /*ARGSUSED*/ 1162 static int 1163 pcieb_msi_supported(dev_info_t *dip) 1164 { 1165 return ((pcieb_enable_msi && pcieb_plat_msi_supported(dip)) ? 1166 DDI_SUCCESS: DDI_FAILURE); 1167 } 1168 1169 /*ARGSUSED*/ 1170 static int 1171 pcieb_fm_init_child(dev_info_t *dip, dev_info_t *tdip, int cap, 1172 ddi_iblock_cookie_t *ibc) 1173 { 1174 pcieb_devstate_t *pcieb = ddi_get_soft_state(pcieb_state, 1175 ddi_get_instance(dip)); 1176 1177 ASSERT(ibc != NULL); 1178 *ibc = pcieb->pcieb_fm_ibc; 1179 1180 return (DEVI(dip)->devi_fmhdl->fh_cap | DDI_FM_ACCCHK_CAPABLE | 1181 DDI_FM_DMACHK_CAPABLE); 1182 } 1183 1184 static int 1185 pcieb_fm_init(pcieb_devstate_t *pcieb_p) 1186 { 1187 dev_info_t *dip = pcieb_p->pcieb_dip; 1188 int fm_cap = DDI_FM_EREPORT_CAPABLE; 1189 1190 /* 1191 * Request our capability level and get our parents capability 1192 * and ibc. 1193 */ 1194 ddi_fm_init(dip, &fm_cap, &pcieb_p->pcieb_fm_ibc); 1195 1196 return (DDI_SUCCESS); 1197 } 1198 1199 /* 1200 * Breakdown our FMA resources 1201 */ 1202 static void 1203 pcieb_fm_fini(pcieb_devstate_t *pcieb_p) 1204 { 1205 /* 1206 * Clean up allocated fm structures 1207 */ 1208 ddi_fm_fini(pcieb_p->pcieb_dip); 1209 } 1210 1211 static int 1212 pcieb_open(dev_t *devp, int flags, int otyp, cred_t *credp) 1213 { 1214 pcieb_devstate_t *pcieb_p; 1215 minor_t minor = getminor(*devp); 1216 int instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor); 1217 1218 /* 1219 * Make sure the open is for the right file type. 1220 */ 1221 if (otyp != OTYP_CHR) 1222 return (EINVAL); 1223 1224 /* 1225 * Get the soft state structure for the device. 1226 */ 1227 pcieb_p = (pcieb_devstate_t *)ddi_get_soft_state(pcieb_state, 1228 instance); 1229 1230 if (pcieb_p == NULL) 1231 return (ENXIO); 1232 1233 if (pcieb_p->pcieb_hotplug_capable == B_TRUE) 1234 return ((pcihp_get_cb_ops())->cb_open(devp, flags, 1235 otyp, credp)); 1236 1237 /* 1238 * Handle the open by tracking the device state. 1239 */ 1240 mutex_enter(&pcieb_p->pcieb_mutex); 1241 if (flags & FEXCL) { 1242 if (pcieb_p->pcieb_soft_state != PCIEB_SOFT_STATE_CLOSED) { 1243 mutex_exit(&pcieb_p->pcieb_mutex); 1244 return (EBUSY); 1245 } 1246 pcieb_p->pcieb_soft_state = PCIEB_SOFT_STATE_OPEN_EXCL; 1247 } else { 1248 if (pcieb_p->pcieb_soft_state == PCIEB_SOFT_STATE_OPEN_EXCL) { 1249 mutex_exit(&pcieb_p->pcieb_mutex); 1250 return (EBUSY); 1251 } 1252 pcieb_p->pcieb_soft_state = PCIEB_SOFT_STATE_OPEN; 1253 } 1254 mutex_exit(&pcieb_p->pcieb_mutex); 1255 return (0); 1256 } 1257 1258 static int 1259 pcieb_close(dev_t dev, int flags, int otyp, cred_t *credp) 1260 { 1261 pcieb_devstate_t *pcieb_p; 1262 minor_t minor = getminor(dev); 1263 int instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor); 1264 1265 if (otyp != OTYP_CHR) 1266 return (EINVAL); 1267 1268 pcieb_p = (pcieb_devstate_t *)ddi_get_soft_state(pcieb_state, 1269 instance); 1270 1271 if (pcieb_p == NULL) 1272 return (ENXIO); 1273 1274 if (pcieb_p->pcieb_hotplug_capable == B_TRUE) 1275 return ((pcihp_get_cb_ops())->cb_close(dev, flags, 1276 otyp, credp)); 1277 1278 mutex_enter(&pcieb_p->pcieb_mutex); 1279 pcieb_p->pcieb_soft_state = PCIEB_SOFT_STATE_CLOSED; 1280 mutex_exit(&pcieb_p->pcieb_mutex); 1281 return (0); 1282 } 1283 1284 static int 1285 pcieb_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp, 1286 int *rvalp) 1287 { 1288 pcieb_devstate_t *pcieb_p; 1289 dev_info_t *self; 1290 struct devctl_iocdata *dcp; 1291 uint_t bus_state; 1292 int rv = 0; 1293 minor_t minor = getminor(dev); 1294 int instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor); 1295 1296 pcieb_p = (pcieb_devstate_t *)ddi_get_soft_state(pcieb_state, 1297 instance); 1298 1299 if (pcieb_p == NULL) 1300 return (ENXIO); 1301 1302 self = pcieb_p->pcieb_dip; 1303 if (pcieb_p->pcieb_hotplug_capable == B_TRUE) { 1304 rv = ((pcihp_get_cb_ops())->cb_ioctl(dev, cmd, 1305 arg, mode, credp, rvalp)); 1306 1307 pcieb_plat_ioctl_hotplug(self, rv, cmd); 1308 return (rv); 1309 } 1310 1311 /* 1312 * We can use the generic implementation for these ioctls 1313 */ 1314 switch (cmd) { 1315 case DEVCTL_DEVICE_GETSTATE: 1316 case DEVCTL_DEVICE_ONLINE: 1317 case DEVCTL_DEVICE_OFFLINE: 1318 case DEVCTL_BUS_GETSTATE: 1319 return (ndi_devctl_ioctl(self, cmd, arg, mode, 0)); 1320 } 1321 1322 /* 1323 * read devctl ioctl data 1324 */ 1325 if (ndi_dc_allochdl((void *)arg, &dcp) != NDI_SUCCESS) 1326 return (EFAULT); 1327 1328 switch (cmd) { 1329 1330 case DEVCTL_DEVICE_RESET: 1331 rv = ENOTSUP; 1332 break; 1333 1334 case DEVCTL_BUS_QUIESCE: 1335 if (ndi_get_bus_state(self, &bus_state) == NDI_SUCCESS) 1336 if (bus_state == BUS_QUIESCED) 1337 break; 1338 (void) ndi_set_bus_state(self, BUS_QUIESCED); 1339 break; 1340 1341 case DEVCTL_BUS_UNQUIESCE: 1342 if (ndi_get_bus_state(self, &bus_state) == NDI_SUCCESS) 1343 if (bus_state == BUS_ACTIVE) 1344 break; 1345 (void) ndi_set_bus_state(self, BUS_ACTIVE); 1346 break; 1347 1348 case DEVCTL_BUS_RESET: 1349 rv = ENOTSUP; 1350 break; 1351 1352 case DEVCTL_BUS_RESETALL: 1353 rv = ENOTSUP; 1354 break; 1355 1356 default: 1357 rv = ENOTTY; 1358 } 1359 1360 ndi_dc_freehdl(dcp); 1361 return (rv); 1362 } 1363 1364 static int 1365 pcieb_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op, 1366 int flags, char *name, caddr_t valuep, int *lengthp) 1367 { 1368 pcieb_devstate_t *pcieb_p; 1369 minor_t minor = getminor(dev); 1370 int instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor); 1371 1372 pcieb_p = (pcieb_devstate_t *)ddi_get_soft_state(pcieb_state, 1373 instance); 1374 1375 if (pcieb_p == NULL) 1376 return (ENXIO); 1377 1378 if (pcieb_p->pcieb_hotplug_capable == B_TRUE) 1379 return ((pcihp_get_cb_ops())->cb_prop_op(dev, dip, prop_op, 1380 flags, name, valuep, lengthp)); 1381 1382 return (ddi_prop_op(dev, dip, prop_op, flags, name, valuep, lengthp)); 1383 } 1384 1385 /*ARGSUSED*/ 1386 static int 1387 pcieb_info(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, void **result) 1388 { 1389 pcieb_devstate_t *pcieb_p; /* per pcieb state pointer */ 1390 minor_t minor = getminor((dev_t)arg); 1391 int instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor); 1392 1393 pcieb_p = (pcieb_devstate_t *)ddi_get_soft_state(pcieb_state, 1394 instance); 1395 1396 switch (infocmd) { 1397 default: 1398 return (DDI_FAILURE); 1399 1400 case DDI_INFO_DEVT2INSTANCE: 1401 *result = (void *)(intptr_t)instance; 1402 return (DDI_SUCCESS); 1403 1404 case DDI_INFO_DEVT2DEVINFO: 1405 if (pcieb_p == NULL) 1406 return (DDI_FAILURE); 1407 *result = (void *)pcieb_p->pcieb_dip; 1408 return (DDI_SUCCESS); 1409 } 1410 } 1411 1412 /* 1413 * Common interrupt handler for hotplug, PME and errors. 1414 */ 1415 static uint_t 1416 pcieb_intr_handler(caddr_t arg1, caddr_t arg2) 1417 { 1418 pcieb_devstate_t *pcieb_p = (pcieb_devstate_t *)arg1; 1419 dev_info_t *dip = pcieb_p->pcieb_dip; 1420 ddi_fm_error_t derr; 1421 int sts = 0; 1422 int ret = DDI_INTR_UNCLAIMED; 1423 int isrc; 1424 1425 if (!(pcieb_p->pcieb_init_flags & PCIEB_INIT_ENABLE)) 1426 goto FAIL; 1427 1428 mutex_enter(&pcieb_p->pcieb_intr_mutex); 1429 isrc = pcieb_p->pcieb_isr_tab[(int)(uintptr_t)arg2]; 1430 mutex_exit(&pcieb_p->pcieb_intr_mutex); 1431 1432 PCIEB_DEBUG(DBG_INTR, dip, "Received intr number %d\n", 1433 (int)(uintptr_t)arg2); 1434 1435 if (isrc == PCIEB_INTR_SRC_UNKNOWN) 1436 goto FAIL; 1437 1438 if (isrc & PCIEB_INTR_SRC_HP) { 1439 if (pcieb_p->pcieb_hpc_type == HPC_PCIE) 1440 ret = pciehpc_intr(dip); 1441 else if (pcieb_p->pcieb_hpc_type == HPC_SHPC) 1442 ret = pcishpc_intr(dip); 1443 } 1444 1445 if (isrc & PCIEB_INTR_SRC_PME) 1446 ret = DDI_INTR_CLAIMED; 1447 1448 /* AER Error */ 1449 if (isrc & PCIEB_INTR_SRC_AER) { 1450 /* 1451 * If MSI is shared with PME/hotplug then check Root Error 1452 * Status Reg before claiming it. For now it's ok since 1453 * we know we get 2 MSIs. 1454 */ 1455 ret = DDI_INTR_CLAIMED; 1456 bzero(&derr, sizeof (ddi_fm_error_t)); 1457 derr.fme_version = DDI_FME_VERSION; 1458 mutex_enter(&pcieb_p->pcieb_peek_poke_mutex); 1459 mutex_enter(&pcieb_p->pcieb_err_mutex); 1460 1461 if ((DEVI(dip)->devi_fmhdl->fh_cap) & DDI_FM_EREPORT_CAPABLE) 1462 sts = pf_scan_fabric(dip, &derr, NULL); 1463 1464 mutex_exit(&pcieb_p->pcieb_err_mutex); 1465 mutex_exit(&pcieb_p->pcieb_peek_poke_mutex); 1466 if (pcieb_die & sts) 1467 fm_panic("%s-%d: PCI(-X) Express Fatal Error. (0x%x)", 1468 ddi_driver_name(dip), ddi_get_instance(dip), sts); 1469 } 1470 FAIL: 1471 return (ret); 1472 } 1473 1474 /* 1475 * Some PCI-X to PCI-E bridges do not support full 64-bit addressing on the 1476 * PCI-X side of the bridge. We build a special version of this driver for 1477 * those bridges, which uses PCIEB_ADDR_LIMIT_LO and/or PCIEB_ADDR_LIMIT_HI 1478 * to define the range of values which the chip can handle. The code below 1479 * then clamps the DMA address range supplied by the driver, preventing the 1480 * PCI-E nexus driver from allocating any memory the bridge can't deal 1481 * with. 1482 */ 1483 static int 1484 pcieb_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, 1485 ddi_dma_attr_t *attr_p, int (*waitfp)(caddr_t), caddr_t arg, 1486 ddi_dma_handle_t *handlep) 1487 { 1488 int ret; 1489 #ifdef BCM_SW_WORKAROUNDS 1490 uint64_t lim; 1491 1492 /* 1493 * If the leaf device's limits are outside than what the Broadcom 1494 * bridge can handle, we need to clip the values passed up the chain. 1495 */ 1496 lim = attr_p->dma_attr_addr_lo; 1497 attr_p->dma_attr_addr_lo = MAX(lim, PCIEB_ADDR_LIMIT_LO); 1498 1499 lim = attr_p->dma_attr_addr_hi; 1500 attr_p->dma_attr_addr_hi = MIN(lim, PCIEB_ADDR_LIMIT_HI); 1501 1502 #endif /* BCM_SW_WORKAROUNDS */ 1503 1504 /* 1505 * This is a software workaround to fix the Broadcom 5714/5715 PCIe-PCI 1506 * bridge prefetch bug. Intercept the DMA alloc handle request and set 1507 * PX_DMAI_FLAGS_MAP_BUFZONE flag in the handle. If this flag is set, 1508 * the px nexus driver will allocate an extra page & make it valid one, 1509 * for any DVMA request that comes from any of the Broadcom bridge child 1510 * devices. 1511 */ 1512 if ((ret = ddi_dma_allochdl(dip, rdip, attr_p, waitfp, arg, 1513 handlep)) == DDI_SUCCESS) { 1514 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)*handlep; 1515 #ifdef BCM_SW_WORKAROUNDS 1516 mp->dmai_inuse |= PX_DMAI_FLAGS_MAP_BUFZONE; 1517 #endif /* BCM_SW_WORKAROUNDS */ 1518 /* 1519 * For a given rdip, update mp->dmai_bdf with the bdf value 1520 * of pcieb's immediate child or secondary bus-id of the 1521 * PCIe2PCI bridge. 1522 */ 1523 mp->dmai_minxfer = pcie_get_bdf_for_dma_xfer(dip, rdip); 1524 } 1525 1526 return (ret); 1527 } 1528 1529 /* 1530 * FDVMA feature is not supported for any child device of Broadcom 5714/5715 1531 * PCIe-PCI bridge due to prefetch bug. Return failure immediately, so that 1532 * these drivers will switch to regular DVMA path. 1533 */ 1534 /*ARGSUSED*/ 1535 static int 1536 pcieb_dma_mctl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 1537 enum ddi_dma_ctlops cmd, off_t *offp, size_t *lenp, caddr_t *objp, 1538 uint_t cache_flags) 1539 { 1540 int ret; 1541 1542 #ifdef BCM_SW_WORKAROUNDS 1543 if (cmd == DDI_DMA_RESERVE) 1544 return (DDI_FAILURE); 1545 #endif /* BCM_SW_WORKAROUNDS */ 1546 1547 if (((ret = ddi_dma_mctl(dip, rdip, handle, cmd, offp, lenp, objp, 1548 cache_flags)) == DDI_SUCCESS) && (cmd == DDI_DMA_RESERVE)) { 1549 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)*objp; 1550 1551 /* 1552 * For a given rdip, update mp->dmai_bdf with the bdf value 1553 * of pcieb's immediate child or secondary bus-id of the 1554 * PCIe2PCI bridge. 1555 */ 1556 mp->dmai_minxfer = pcie_get_bdf_for_dma_xfer(dip, rdip); 1557 } 1558 1559 return (ret); 1560 } 1561 1562 static int 1563 pcieb_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 1564 ddi_intr_handle_impl_t *hdlp, void *result) 1565 { 1566 return (pcieb_plat_intr_ops(dip, rdip, intr_op, hdlp, result)); 1567 1568 } 1569 1570 /*ARGSUSED*/ 1571 static int pcieb_pciehpc_probe(dev_info_t *dip, ddi_acc_handle_t config_handle) 1572 { 1573 uint16_t cap_ptr; 1574 1575 if ((PCI_CAP_LOCATE(config_handle, PCI_CAP_ID_PCI_E, &cap_ptr)) != 1576 DDI_FAILURE) { 1577 uint16_t slotimpl = PCI_CAP_GET16(config_handle, NULL, cap_ptr, 1578 PCIE_PCIECAP) & PCIE_PCIECAP_SLOT_IMPL; 1579 if (slotimpl) 1580 if (PCI_CAP_GET32(config_handle, NULL, cap_ptr, 1581 PCIE_SLOTCAP) & PCIE_SLOTCAP_HP_CAPABLE) 1582 return (DDI_SUCCESS); 1583 } 1584 1585 return (DDI_FAILURE); 1586 } 1587 1588 static int pcieb_pcishpc_probe(dev_info_t *dip, ddi_acc_handle_t config_handle) 1589 { 1590 return (pcieb_plat_pcishpc_probe(dip, config_handle)); 1591 } 1592 1593 /* 1594 * Initialize hotplug framework if we are hotpluggable. 1595 * Sets flag in the soft state if Hot Plug is supported and initialized 1596 * properly. 1597 */ 1598 /*ARGSUSED*/ 1599 static int 1600 pcieb_init_hotplug(pcieb_devstate_t *pcieb) 1601 { 1602 int rv = DDI_FAILURE; 1603 pcie_bus_t *bus_p = PCIE_DIP2BUS(pcieb->pcieb_dip); 1604 ddi_acc_handle_t config_handle = bus_p->bus_cfg_hdl; 1605 uint8_t dev_type = bus_p->bus_dev_type; 1606 1607 #ifdef PX_PLX 1608 uint16_t vid = bus_p->bus_dev_ven_id & 0xFFFF; 1609 uint16_t did = bus_p->bus_dev_ven_id >> 16; 1610 if ((vid == PXB_VENDOR_PLX) && (did == PXB_DEVICE_PLX_8532) && 1611 (bus_p->bus_rev_id <= PXB_DEVICE_PLX_AA_REV)) 1612 return (DDI_SUCCESS); 1613 #endif /* PX_PLX */ 1614 1615 if (((dev_type == PCIE_PCIECAP_DEV_TYPE_DOWN) || 1616 (dev_type == PCIE_PCIECAP_DEV_TYPE_PCI2PCIE) || 1617 (dev_type == PCIE_PCIECAP_DEV_TYPE_ROOT)) && 1618 (pcieb_pciehpc_probe(pcieb->pcieb_dip, 1619 config_handle) == DDI_SUCCESS)) { 1620 pcieb->pcieb_hpc_type = HPC_PCIE; 1621 } else if ((dev_type == PCIE_PCIECAP_DEV_TYPE_PCIE2PCI) && 1622 (pcieb_pcishpc_probe(pcieb->pcieb_dip, 1623 config_handle) == DDI_SUCCESS)) { 1624 pcieb->pcieb_hpc_type = HPC_SHPC; 1625 } else { 1626 pcieb->pcieb_hpc_type = HPC_NONE; 1627 return (DDI_SUCCESS); 1628 } 1629 1630 pcieb->pcieb_hotplug_capable = B_TRUE; 1631 1632 if (pcieb->pcieb_hpc_type == HPC_PCIE) 1633 rv = pciehpc_init(pcieb->pcieb_dip, NULL); 1634 else if (pcieb->pcieb_hpc_type == HPC_SHPC) 1635 rv = pcishpc_init(pcieb->pcieb_dip); 1636 1637 if (rv != DDI_SUCCESS) 1638 goto fail; 1639 1640 if (pcihp_init(pcieb->pcieb_dip) != DDI_SUCCESS) { 1641 if (pcieb->pcieb_hpc_type == HPC_PCIE) 1642 (void) pciehpc_uninit(pcieb->pcieb_dip); 1643 else if (pcieb->pcieb_hpc_type == HPC_SHPC) 1644 (void) pcishpc_uninit(pcieb->pcieb_dip); 1645 1646 goto fail; 1647 } 1648 1649 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, pcieb->pcieb_dip, 1650 "hotplug-capable"); 1651 1652 return (DDI_SUCCESS); 1653 1654 fail: 1655 pcieb->pcieb_hpc_type = HPC_NONE; 1656 pcieb->pcieb_hotplug_capable = B_FALSE; 1657 PCIEB_DEBUG(DBG_ATTACH, pcieb->pcieb_dip, "Failed setting hotplug" 1658 " framework\n"); 1659 1660 return (DDI_FAILURE); 1661 } 1662 1663 /* 1664 * Power management related initialization specific to pcieb. 1665 * Called by pcieb_attach() 1666 */ 1667 static int 1668 pcieb_pwr_setup(dev_info_t *dip) 1669 { 1670 char *comp_array[5]; 1671 int i; 1672 ddi_acc_handle_t conf_hdl; 1673 uint16_t pmcap, cap_ptr; 1674 pcie_pwr_t *pwr_p; 1675 1676 /* Some platforms/devices may choose to disable PM */ 1677 if (pcieb_plat_pwr_disable(dip)) { 1678 (void) pcieb_pwr_disable(dip); 1679 return (DDI_SUCCESS); 1680 } 1681 1682 ASSERT(PCIE_PMINFO(dip)); 1683 pwr_p = PCIE_NEXUS_PMINFO(dip); 1684 ASSERT(pwr_p); 1685 1686 /* Code taken from pci_pci driver */ 1687 if (pci_config_setup(dip, &pwr_p->pwr_conf_hdl) != DDI_SUCCESS) { 1688 PCIEB_DEBUG(DBG_PWR, dip, "pcieb_pwr_setup: pci_config_setup " 1689 "failed\n"); 1690 return (DDI_FAILURE); 1691 } 1692 conf_hdl = pwr_p->pwr_conf_hdl; 1693 1694 /* 1695 * Walk the capabilities searching for a PM entry. 1696 */ 1697 if ((PCI_CAP_LOCATE(conf_hdl, PCI_CAP_ID_PM, &cap_ptr)) == 1698 DDI_FAILURE) { 1699 PCIEB_DEBUG(DBG_PWR, dip, "switch/bridge does not support PM. " 1700 " PCI PM data structure not found in config header\n"); 1701 pci_config_teardown(&conf_hdl); 1702 return (DDI_SUCCESS); 1703 } 1704 /* 1705 * Save offset to pmcsr for future references. 1706 */ 1707 pwr_p->pwr_pmcsr_offset = cap_ptr + PCI_PMCSR; 1708 pmcap = PCI_CAP_GET16(conf_hdl, NULL, cap_ptr, PCI_PMCAP); 1709 if (pmcap & PCI_PMCAP_D1) { 1710 PCIEB_DEBUG(DBG_PWR, dip, "D1 state supported\n"); 1711 pwr_p->pwr_pmcaps |= PCIE_SUPPORTS_D1; 1712 } 1713 if (pmcap & PCI_PMCAP_D2) { 1714 PCIEB_DEBUG(DBG_PWR, dip, "D2 state supported\n"); 1715 pwr_p->pwr_pmcaps |= PCIE_SUPPORTS_D2; 1716 } 1717 1718 i = 0; 1719 comp_array[i++] = "NAME=PCIe switch/bridge PM"; 1720 comp_array[i++] = "0=Power Off (D3)"; 1721 if (pwr_p->pwr_pmcaps & PCIE_SUPPORTS_D2) 1722 comp_array[i++] = "1=D2"; 1723 if (pwr_p->pwr_pmcaps & PCIE_SUPPORTS_D1) 1724 comp_array[i++] = "2=D1"; 1725 comp_array[i++] = "3=Full Power D0"; 1726 1727 /* 1728 * Create pm-components property, if it does not exist already. 1729 */ 1730 if (ddi_prop_update_string_array(DDI_DEV_T_NONE, dip, 1731 "pm-components", comp_array, i) != DDI_PROP_SUCCESS) { 1732 PCIEB_DEBUG(DBG_PWR, dip, "could not create pm-components " 1733 " prop\n"); 1734 pci_config_teardown(&conf_hdl); 1735 return (DDI_FAILURE); 1736 } 1737 return (pcieb_pwr_init_and_raise(dip, pwr_p)); 1738 } 1739 1740 /* 1741 * undo whatever is done in pcieb_pwr_setup. called by pcieb_detach() 1742 */ 1743 static void 1744 pcieb_pwr_teardown(dev_info_t *dip) 1745 { 1746 pcie_pwr_t *pwr_p; 1747 1748 if (!PCIE_PMINFO(dip) || !(pwr_p = PCIE_NEXUS_PMINFO(dip))) 1749 return; 1750 1751 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "pm-components"); 1752 if (pwr_p->pwr_conf_hdl) 1753 pci_config_teardown(&pwr_p->pwr_conf_hdl); 1754 } 1755 1756 /* 1757 * Initializes the power level and raise the power to D0, if it is 1758 * not at D0. 1759 */ 1760 static int 1761 pcieb_pwr_init_and_raise(dev_info_t *dip, pcie_pwr_t *pwr_p) 1762 { 1763 uint16_t pmcsr; 1764 int ret = DDI_SUCCESS; 1765 1766 /* 1767 * Intialize our power level from PMCSR. The common code initializes 1768 * this to UNKNOWN. There is no guarantee that we will be at full 1769 * power at attach. If we are not at D0, raise the power. 1770 */ 1771 pmcsr = pci_config_get16(pwr_p->pwr_conf_hdl, pwr_p->pwr_pmcsr_offset); 1772 pmcsr &= PCI_PMCSR_STATE_MASK; 1773 switch (pmcsr) { 1774 case PCI_PMCSR_D0: 1775 pwr_p->pwr_func_lvl = PM_LEVEL_D0; 1776 break; 1777 1778 case PCI_PMCSR_D1: 1779 pwr_p->pwr_func_lvl = PM_LEVEL_D1; 1780 break; 1781 1782 case PCI_PMCSR_D2: 1783 pwr_p->pwr_func_lvl = PM_LEVEL_D2; 1784 break; 1785 1786 case PCI_PMCSR_D3HOT: 1787 pwr_p->pwr_func_lvl = PM_LEVEL_D3; 1788 break; 1789 1790 default: 1791 break; 1792 } 1793 1794 /* Raise the power to D0. */ 1795 if (pwr_p->pwr_func_lvl != PM_LEVEL_D0 && 1796 ((ret = pm_raise_power(dip, 0, PM_LEVEL_D0)) != DDI_SUCCESS)) { 1797 /* 1798 * Read PMCSR again. If it is at D0, ignore the return 1799 * value from pm_raise_power. 1800 */ 1801 pmcsr = pci_config_get16(pwr_p->pwr_conf_hdl, 1802 pwr_p->pwr_pmcsr_offset); 1803 if ((pmcsr & PCI_PMCSR_STATE_MASK) == PCI_PMCSR_D0) 1804 ret = DDI_SUCCESS; 1805 else { 1806 PCIEB_DEBUG(DBG_PWR, dip, "pcieb_pwr_setup: could not " 1807 "raise power to D0 \n"); 1808 } 1809 } 1810 if (ret == DDI_SUCCESS) 1811 pwr_p->pwr_func_lvl = PM_LEVEL_D0; 1812 return (ret); 1813 } 1814 1815 /* 1816 * Disable PM for x86 and PLX 8532 switch. 1817 * For PLX Transitioning one port on this switch to low power causes links 1818 * on other ports on the same station to die. Due to PLX erratum #34, we 1819 * can't allow the downstream device go to non-D0 state. 1820 */ 1821 static int 1822 pcieb_pwr_disable(dev_info_t *dip) 1823 { 1824 pcie_pwr_t *pwr_p; 1825 1826 ASSERT(PCIE_PMINFO(dip)); 1827 pwr_p = PCIE_NEXUS_PMINFO(dip); 1828 ASSERT(pwr_p); 1829 PCIEB_DEBUG(DBG_PWR, dip, "pcieb_pwr_disable: disabling PM\n"); 1830 pwr_p->pwr_func_lvl = PM_LEVEL_D0; 1831 pwr_p->pwr_flags = PCIE_NO_CHILD_PM; 1832 return (DDI_SUCCESS); 1833 } 1834 1835 #ifdef DEBUG 1836 int pcieb_dbg_intr_print = 0; 1837 void 1838 pcieb_dbg(uint_t bit, dev_info_t *dip, char *fmt, ...) 1839 { 1840 va_list ap; 1841 1842 if (!pcieb_dbg_print) 1843 return; 1844 1845 if (dip) 1846 prom_printf("%s(%d): %s", ddi_driver_name(dip), 1847 ddi_get_instance(dip), pcieb_debug_sym[bit]); 1848 1849 va_start(ap, fmt); 1850 if (servicing_interrupt()) { 1851 if (pcieb_dbg_intr_print) 1852 prom_vprintf(fmt, ap); 1853 } else { 1854 prom_vprintf(fmt, ap); 1855 } 1856 1857 va_end(ap); 1858 } 1859 #endif 1860 1861 static void 1862 pcieb_id_props(pcieb_devstate_t *pcieb) 1863 { 1864 uint64_t serialid = 0; /* 40b field of EUI-64 serial no. register */ 1865 uint16_t cap_ptr; 1866 uint8_t fic = 0; /* 1 = first in chassis device */ 1867 pcie_bus_t *bus_p = PCIE_DIP2BUS(pcieb->pcieb_dip); 1868 ddi_acc_handle_t config_handle = bus_p->bus_cfg_hdl; 1869 1870 /* 1871 * Identify first in chassis. In the special case of a Sun branded 1872 * PLX device, it obviously is first in chassis. Otherwise, in the 1873 * general case, look for an Expansion Slot Register and check its 1874 * first-in-chassis bit. 1875 */ 1876 #ifdef PX_PLX 1877 uint16_t vendor_id = bus_p->bus_dev_ven_id & 0xFFFF; 1878 uint16_t device_id = bus_p->bus_dev_ven_id >> 16; 1879 if ((vendor_id == PXB_VENDOR_SUN) && 1880 ((device_id == PXB_DEVICE_PLX_PCIX) || 1881 (device_id == PXB_DEVICE_PLX_PCIE))) { 1882 fic = 1; 1883 } 1884 #endif /* PX_PLX */ 1885 if ((fic == 0) && ((PCI_CAP_LOCATE(config_handle, 1886 PCI_CAP_ID_SLOT_ID, &cap_ptr)) != DDI_FAILURE)) { 1887 uint8_t esr = PCI_CAP_GET8(config_handle, NULL, 1888 cap_ptr, PCI_CAP_ID_REGS_OFF); 1889 if (PCI_CAPSLOT_FIC(esr)) 1890 fic = 1; 1891 } 1892 1893 if ((PCI_CAP_LOCATE(config_handle, 1894 PCI_CAP_XCFG_SPC(PCIE_EXT_CAP_ID_SER), &cap_ptr)) != DDI_FAILURE) { 1895 /* Serialid can be 0 thru a full 40b number */ 1896 serialid = PCI_XCAP_GET32(config_handle, NULL, 1897 cap_ptr, PCIE_SER_SID_UPPER_DW); 1898 serialid <<= 32; 1899 serialid |= PCI_XCAP_GET32(config_handle, NULL, 1900 cap_ptr, PCIE_SER_SID_LOWER_DW); 1901 } 1902 1903 if (fic) 1904 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, pcieb->pcieb_dip, 1905 "first-in-chassis"); 1906 if (serialid) 1907 (void) ddi_prop_update_int64(DDI_DEV_T_NONE, pcieb->pcieb_dip, 1908 "serialid#", serialid); 1909 } 1910 1911 static void 1912 pcieb_create_ranges_prop(dev_info_t *dip, 1913 ddi_acc_handle_t config_handle) 1914 { 1915 uint32_t base, limit; 1916 pcieb_ranges_t ranges[PCIEB_RANGE_LEN]; 1917 uint8_t io_base_lo, io_limit_lo; 1918 uint16_t io_base_hi, io_limit_hi, mem_base, mem_limit; 1919 int i = 0, rangelen = sizeof (pcieb_ranges_t)/sizeof (int); 1920 1921 io_base_lo = pci_config_get8(config_handle, PCI_BCNF_IO_BASE_LOW); 1922 io_limit_lo = pci_config_get8(config_handle, PCI_BCNF_IO_LIMIT_LOW); 1923 io_base_hi = pci_config_get16(config_handle, PCI_BCNF_IO_BASE_HI); 1924 io_limit_hi = pci_config_get16(config_handle, PCI_BCNF_IO_LIMIT_HI); 1925 mem_base = pci_config_get16(config_handle, PCI_BCNF_MEM_BASE); 1926 mem_limit = pci_config_get16(config_handle, PCI_BCNF_MEM_LIMIT); 1927 1928 /* 1929 * Create ranges for IO space 1930 */ 1931 ranges[i].size_low = ranges[i].size_high = 0; 1932 ranges[i].parent_mid = ranges[i].child_mid = ranges[i].parent_high = 0; 1933 ranges[i].child_high = ranges[i].parent_high |= 1934 (PCI_REG_REL_M | PCI_ADDR_IO); 1935 base = PCIEB_16bit_IOADDR(io_base_lo); 1936 limit = PCIEB_16bit_IOADDR(io_limit_lo); 1937 1938 if ((io_base_lo & 0xf) == PCIEB_32BIT_IO) { 1939 base = PCIEB_LADDR(base, io_base_hi); 1940 } 1941 if ((io_limit_lo & 0xf) == PCIEB_32BIT_IO) { 1942 limit = PCIEB_LADDR(limit, io_limit_hi); 1943 } 1944 1945 if ((io_base_lo & PCIEB_32BIT_IO) && (io_limit_hi > 0)) { 1946 base = PCIEB_LADDR(base, io_base_hi); 1947 limit = PCIEB_LADDR(limit, io_limit_hi); 1948 } 1949 1950 /* 1951 * Create ranges for 32bit memory space 1952 */ 1953 base = PCIEB_32bit_MEMADDR(mem_base); 1954 limit = PCIEB_32bit_MEMADDR(mem_limit); 1955 ranges[i].size_low = ranges[i].size_high = 0; 1956 ranges[i].parent_mid = ranges[i].child_mid = ranges[i].parent_high = 0; 1957 ranges[i].child_high = ranges[i].parent_high |= 1958 (PCI_REG_REL_M | PCI_ADDR_MEM32); 1959 ranges[i].child_low = ranges[i].parent_low = base; 1960 if (limit >= base) { 1961 ranges[i].size_low = limit - base + PCIEB_MEMGRAIN; 1962 i++; 1963 } 1964 1965 if (i) { 1966 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "ranges", 1967 (int *)ranges, i * rangelen); 1968 } 1969 } 1970 1971 /* 1972 * For PCI and PCI-X devices including PCIe2PCI bridge, initialize 1973 * cache-line-size and latency timer configuration registers. 1974 */ 1975 void 1976 pcieb_set_pci_perf_parameters(dev_info_t *dip, ddi_acc_handle_t cfg_hdl) 1977 { 1978 uint_t n; 1979 1980 /* Initialize cache-line-size configuration register if needed */ 1981 if (ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1982 "cache-line-size", 0) == 0) { 1983 pci_config_put8(cfg_hdl, PCI_CONF_CACHE_LINESZ, 1984 PCIEB_CACHE_LINE_SIZE); 1985 n = pci_config_get8(cfg_hdl, PCI_CONF_CACHE_LINESZ); 1986 if (n != 0) { 1987 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1988 "cache-line-size", n); 1989 } 1990 } 1991 1992 /* Initialize latency timer configuration registers if needed */ 1993 if (ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1994 "latency-timer", 0) == 0) { 1995 uchar_t min_gnt, latency_timer; 1996 uchar_t header_type; 1997 1998 /* Determine the configuration header type */ 1999 header_type = pci_config_get8(cfg_hdl, PCI_CONF_HEADER); 2000 2001 if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_ONE) { 2002 latency_timer = PCIEB_LATENCY_TIMER; 2003 pci_config_put8(cfg_hdl, PCI_BCNF_LATENCY_TIMER, 2004 latency_timer); 2005 } else { 2006 min_gnt = pci_config_get8(cfg_hdl, PCI_CONF_MIN_G); 2007 latency_timer = min_gnt * 8; 2008 } 2009 2010 pci_config_put8(cfg_hdl, PCI_CONF_LATENCY_TIMER, 2011 latency_timer); 2012 n = pci_config_get8(cfg_hdl, PCI_CONF_LATENCY_TIMER); 2013 if (n != 0) { 2014 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2015 "latency-timer", n); 2016 } 2017 } 2018 } 2019