1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved. 24 */ 25 26 #include <sys/sysmacros.h> 27 #include <sys/types.h> 28 #include <sys/kmem.h> 29 #include <sys/modctl.h> 30 #include <sys/ddi.h> 31 #include <sys/sunddi.h> 32 #include <sys/sunndi.h> 33 #include <sys/fm/protocol.h> 34 #include <sys/fm/util.h> 35 #include <sys/promif.h> 36 #include <sys/disp.h> 37 #include <sys/stat.h> 38 #include <sys/file.h> 39 #include <sys/pci_cap.h> 40 #include <sys/pci_impl.h> 41 #include <sys/pcie_impl.h> 42 #include <sys/hotplug/pci/pcie_hp.h> 43 #include <sys/hotplug/pci/pciehpc.h> 44 #include <sys/hotplug/pci/pcishpc.h> 45 #include <sys/hotplug/pci/pcicfg.h> 46 #include <sys/pci_cfgacc.h> 47 48 /* Local functions prototypes */ 49 static void pcie_init_pfd(dev_info_t *); 50 static void pcie_fini_pfd(dev_info_t *); 51 52 #if defined(__i386) || defined(__amd64) 53 static void pcie_check_io_mem_range(ddi_acc_handle_t, boolean_t *, boolean_t *); 54 #endif /* defined(__i386) || defined(__amd64) */ 55 56 #ifdef DEBUG 57 uint_t pcie_debug_flags = 0; 58 static void pcie_print_bus(pcie_bus_t *bus_p); 59 void pcie_dbg(char *fmt, ...); 60 #endif /* DEBUG */ 61 62 /* Variable to control default PCI-Express config settings */ 63 ushort_t pcie_command_default = 64 PCI_COMM_SERR_ENABLE | 65 PCI_COMM_WAIT_CYC_ENAB | 66 PCI_COMM_PARITY_DETECT | 67 PCI_COMM_ME | 68 PCI_COMM_MAE | 69 PCI_COMM_IO; 70 71 /* xxx_fw are bits that are controlled by FW and should not be modified */ 72 ushort_t pcie_command_default_fw = 73 PCI_COMM_SPEC_CYC | 74 PCI_COMM_MEMWR_INVAL | 75 PCI_COMM_PALETTE_SNOOP | 76 PCI_COMM_WAIT_CYC_ENAB | 77 0xF800; /* Reserved Bits */ 78 79 ushort_t pcie_bdg_command_default_fw = 80 PCI_BCNF_BCNTRL_ISA_ENABLE | 81 PCI_BCNF_BCNTRL_VGA_ENABLE | 82 0xF000; /* Reserved Bits */ 83 84 /* PCI-Express Base error defaults */ 85 ushort_t pcie_base_err_default = 86 PCIE_DEVCTL_CE_REPORTING_EN | 87 PCIE_DEVCTL_NFE_REPORTING_EN | 88 PCIE_DEVCTL_FE_REPORTING_EN | 89 PCIE_DEVCTL_UR_REPORTING_EN; 90 91 /* PCI-Express Device Control Register */ 92 uint16_t pcie_devctl_default = PCIE_DEVCTL_RO_EN | 93 PCIE_DEVCTL_MAX_READ_REQ_512; 94 95 /* PCI-Express AER Root Control Register */ 96 #define PCIE_ROOT_SYS_ERR (PCIE_ROOTCTL_SYS_ERR_ON_CE_EN | \ 97 PCIE_ROOTCTL_SYS_ERR_ON_NFE_EN | \ 98 PCIE_ROOTCTL_SYS_ERR_ON_FE_EN) 99 100 ushort_t pcie_root_ctrl_default = 101 PCIE_ROOTCTL_SYS_ERR_ON_CE_EN | 102 PCIE_ROOTCTL_SYS_ERR_ON_NFE_EN | 103 PCIE_ROOTCTL_SYS_ERR_ON_FE_EN; 104 105 /* PCI-Express Root Error Command Register */ 106 ushort_t pcie_root_error_cmd_default = 107 PCIE_AER_RE_CMD_CE_REP_EN | 108 PCIE_AER_RE_CMD_NFE_REP_EN | 109 PCIE_AER_RE_CMD_FE_REP_EN; 110 111 /* ECRC settings in the PCIe AER Control Register */ 112 uint32_t pcie_ecrc_value = 113 PCIE_AER_CTL_ECRC_GEN_ENA | 114 PCIE_AER_CTL_ECRC_CHECK_ENA; 115 116 /* 117 * If a particular platform wants to disable certain errors such as UR/MA, 118 * instead of using #defines have the platform's PCIe Root Complex driver set 119 * these masks using the pcie_get_XXX_mask and pcie_set_XXX_mask functions. For 120 * x86 the closest thing to a PCIe root complex driver is NPE. For SPARC the 121 * closest PCIe root complex driver is PX. 122 * 123 * pcie_serr_disable_flag : disable SERR only (in RCR and command reg) x86 124 * systems may want to disable SERR in general. For root ports, enabling SERR 125 * causes NMIs which are not handled and results in a watchdog timeout error. 126 */ 127 uint32_t pcie_aer_uce_mask = 0; /* AER UE Mask */ 128 uint32_t pcie_aer_ce_mask = 0; /* AER CE Mask */ 129 uint32_t pcie_aer_suce_mask = 0; /* AER Secondary UE Mask */ 130 uint32_t pcie_serr_disable_flag = 0; /* Disable SERR */ 131 132 /* Default severities needed for eversholt. Error handling doesn't care */ 133 uint32_t pcie_aer_uce_severity = PCIE_AER_UCE_MTLP | PCIE_AER_UCE_RO | \ 134 PCIE_AER_UCE_FCP | PCIE_AER_UCE_SD | PCIE_AER_UCE_DLP | \ 135 PCIE_AER_UCE_TRAINING; 136 uint32_t pcie_aer_suce_severity = PCIE_AER_SUCE_SERR_ASSERT | \ 137 PCIE_AER_SUCE_UC_ADDR_ERR | PCIE_AER_SUCE_UC_ATTR_ERR | \ 138 PCIE_AER_SUCE_USC_MSG_DATA_ERR; 139 140 int pcie_max_mps = PCIE_DEVCTL_MAX_PAYLOAD_4096 >> 5; 141 int pcie_disable_ari = 0; 142 143 static void pcie_scan_mps(dev_info_t *rc_dip, dev_info_t *dip, 144 int *max_supported); 145 static int pcie_get_max_supported(dev_info_t *dip, void *arg); 146 static int pcie_map_phys(dev_info_t *dip, pci_regspec_t *phys_spec, 147 caddr_t *addrp, ddi_acc_handle_t *handlep); 148 static void pcie_unmap_phys(ddi_acc_handle_t *handlep, pci_regspec_t *ph); 149 150 dev_info_t *pcie_get_rc_dip(dev_info_t *dip); 151 152 /* 153 * modload support 154 */ 155 156 static struct modlmisc modlmisc = { 157 &mod_miscops, /* Type of module */ 158 "PCI Express Framework Module" 159 }; 160 161 static struct modlinkage modlinkage = { 162 MODREV_1, 163 (void *)&modlmisc, 164 NULL 165 }; 166 167 /* 168 * Global Variables needed for a non-atomic version of ddi_fm_ereport_post. 169 * Currently used to send the pci.fabric ereports whose payload depends on the 170 * type of PCI device it is being sent for. 171 */ 172 char *pcie_nv_buf; 173 nv_alloc_t *pcie_nvap; 174 nvlist_t *pcie_nvl; 175 176 int 177 _init(void) 178 { 179 int rval; 180 181 pcie_nv_buf = kmem_alloc(ERPT_DATA_SZ, KM_SLEEP); 182 pcie_nvap = fm_nva_xcreate(pcie_nv_buf, ERPT_DATA_SZ); 183 pcie_nvl = fm_nvlist_create(pcie_nvap); 184 185 rval = mod_install(&modlinkage); 186 return (rval); 187 } 188 189 int 190 _fini() 191 { 192 int rval; 193 194 fm_nvlist_destroy(pcie_nvl, FM_NVA_RETAIN); 195 fm_nva_xdestroy(pcie_nvap); 196 kmem_free(pcie_nv_buf, ERPT_DATA_SZ); 197 198 rval = mod_remove(&modlinkage); 199 return (rval); 200 } 201 202 int 203 _info(struct modinfo *modinfop) 204 { 205 return (mod_info(&modlinkage, modinfop)); 206 } 207 208 /* ARGSUSED */ 209 int 210 pcie_init(dev_info_t *dip, caddr_t arg) 211 { 212 int ret = DDI_SUCCESS; 213 214 /* 215 * Create a "devctl" minor node to support DEVCTL_DEVICE_* 216 * and DEVCTL_BUS_* ioctls to this bus. 217 */ 218 if ((ret = ddi_create_minor_node(dip, "devctl", S_IFCHR, 219 PCI_MINOR_NUM(ddi_get_instance(dip), PCI_DEVCTL_MINOR), 220 DDI_NT_NEXUS, 0)) != DDI_SUCCESS) { 221 PCIE_DBG("Failed to create devctl minor node for %s%d\n", 222 ddi_driver_name(dip), ddi_get_instance(dip)); 223 224 return (ret); 225 } 226 227 if ((ret = pcie_hp_init(dip, arg)) != DDI_SUCCESS) { 228 /* 229 * On some x86 platforms, we observed unexpected hotplug 230 * initialization failures in recent years. The known cause 231 * is a hardware issue: while the problem PCI bridges have 232 * the Hotplug Capable registers set, the machine actually 233 * does not implement the expected ACPI object. 234 * 235 * We don't want to stop PCI driver attach and system boot 236 * just because of this hotplug initialization failure. 237 * Continue with a debug message printed. 238 */ 239 PCIE_DBG("%s%d: Failed setting hotplug framework\n", 240 ddi_driver_name(dip), ddi_get_instance(dip)); 241 242 #if defined(__sparc) 243 ddi_remove_minor_node(dip, "devctl"); 244 245 return (ret); 246 #endif /* defined(__sparc) */ 247 } 248 249 return (DDI_SUCCESS); 250 } 251 252 /* ARGSUSED */ 253 int 254 pcie_uninit(dev_info_t *dip) 255 { 256 int ret = DDI_SUCCESS; 257 258 if (pcie_ari_is_enabled(dip) == PCIE_ARI_FORW_ENABLED) 259 (void) pcie_ari_disable(dip); 260 261 if ((ret = pcie_hp_uninit(dip)) != DDI_SUCCESS) { 262 PCIE_DBG("Failed to uninitialize hotplug for %s%d\n", 263 ddi_driver_name(dip), ddi_get_instance(dip)); 264 265 return (ret); 266 } 267 268 ddi_remove_minor_node(dip, "devctl"); 269 270 return (ret); 271 } 272 273 /* 274 * PCIe module interface for enabling hotplug interrupt. 275 * 276 * It should be called after pcie_init() is done and bus driver's 277 * interrupt handlers have being attached. 278 */ 279 int 280 pcie_hpintr_enable(dev_info_t *dip) 281 { 282 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 283 pcie_hp_ctrl_t *ctrl_p = PCIE_GET_HP_CTRL(dip); 284 285 if (PCIE_IS_PCIE_HOTPLUG_ENABLED(bus_p)) { 286 (void) (ctrl_p->hc_ops.enable_hpc_intr)(ctrl_p); 287 } else if (PCIE_IS_PCI_HOTPLUG_ENABLED(bus_p)) { 288 (void) pcishpc_enable_irqs(ctrl_p); 289 } 290 return (DDI_SUCCESS); 291 } 292 293 /* 294 * PCIe module interface for disabling hotplug interrupt. 295 * 296 * It should be called before pcie_uninit() is called and bus driver's 297 * interrupt handlers is dettached. 298 */ 299 int 300 pcie_hpintr_disable(dev_info_t *dip) 301 { 302 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 303 pcie_hp_ctrl_t *ctrl_p = PCIE_GET_HP_CTRL(dip); 304 305 if (PCIE_IS_PCIE_HOTPLUG_ENABLED(bus_p)) { 306 (void) (ctrl_p->hc_ops.disable_hpc_intr)(ctrl_p); 307 } else if (PCIE_IS_PCI_HOTPLUG_ENABLED(bus_p)) { 308 (void) pcishpc_disable_irqs(ctrl_p); 309 } 310 return (DDI_SUCCESS); 311 } 312 313 /* ARGSUSED */ 314 int 315 pcie_intr(dev_info_t *dip) 316 { 317 return (pcie_hp_intr(dip)); 318 } 319 320 /* ARGSUSED */ 321 int 322 pcie_open(dev_info_t *dip, dev_t *devp, int flags, int otyp, cred_t *credp) 323 { 324 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 325 326 /* 327 * Make sure the open is for the right file type. 328 */ 329 if (otyp != OTYP_CHR) 330 return (EINVAL); 331 332 /* 333 * Handle the open by tracking the device state. 334 */ 335 if ((bus_p->bus_soft_state == PCI_SOFT_STATE_OPEN_EXCL) || 336 ((flags & FEXCL) && 337 (bus_p->bus_soft_state != PCI_SOFT_STATE_CLOSED))) { 338 return (EBUSY); 339 } 340 341 if (flags & FEXCL) 342 bus_p->bus_soft_state = PCI_SOFT_STATE_OPEN_EXCL; 343 else 344 bus_p->bus_soft_state = PCI_SOFT_STATE_OPEN; 345 346 return (0); 347 } 348 349 /* ARGSUSED */ 350 int 351 pcie_close(dev_info_t *dip, dev_t dev, int flags, int otyp, cred_t *credp) 352 { 353 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 354 355 if (otyp != OTYP_CHR) 356 return (EINVAL); 357 358 bus_p->bus_soft_state = PCI_SOFT_STATE_CLOSED; 359 360 return (0); 361 } 362 363 /* ARGSUSED */ 364 int 365 pcie_ioctl(dev_info_t *dip, dev_t dev, int cmd, intptr_t arg, int mode, 366 cred_t *credp, int *rvalp) 367 { 368 struct devctl_iocdata *dcp; 369 uint_t bus_state; 370 int rv = DDI_SUCCESS; 371 372 /* 373 * We can use the generic implementation for devctl ioctl 374 */ 375 switch (cmd) { 376 case DEVCTL_DEVICE_GETSTATE: 377 case DEVCTL_DEVICE_ONLINE: 378 case DEVCTL_DEVICE_OFFLINE: 379 case DEVCTL_BUS_GETSTATE: 380 return (ndi_devctl_ioctl(dip, cmd, arg, mode, 0)); 381 default: 382 break; 383 } 384 385 /* 386 * read devctl ioctl data 387 */ 388 if (ndi_dc_allochdl((void *)arg, &dcp) != NDI_SUCCESS) 389 return (EFAULT); 390 391 switch (cmd) { 392 case DEVCTL_BUS_QUIESCE: 393 if (ndi_get_bus_state(dip, &bus_state) == NDI_SUCCESS) 394 if (bus_state == BUS_QUIESCED) 395 break; 396 (void) ndi_set_bus_state(dip, BUS_QUIESCED); 397 break; 398 case DEVCTL_BUS_UNQUIESCE: 399 if (ndi_get_bus_state(dip, &bus_state) == NDI_SUCCESS) 400 if (bus_state == BUS_ACTIVE) 401 break; 402 (void) ndi_set_bus_state(dip, BUS_ACTIVE); 403 break; 404 case DEVCTL_BUS_RESET: 405 case DEVCTL_BUS_RESETALL: 406 case DEVCTL_DEVICE_RESET: 407 rv = ENOTSUP; 408 break; 409 default: 410 rv = ENOTTY; 411 } 412 413 ndi_dc_freehdl(dcp); 414 return (rv); 415 } 416 417 /* ARGSUSED */ 418 int 419 pcie_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op, 420 int flags, char *name, caddr_t valuep, int *lengthp) 421 { 422 if (dev == DDI_DEV_T_ANY) 423 goto skip; 424 425 if (PCIE_IS_HOTPLUG_CAPABLE(dip) && 426 strcmp(name, "pci-occupant") == 0) { 427 int pci_dev = PCI_MINOR_NUM_TO_PCI_DEVNUM(getminor(dev)); 428 429 pcie_hp_create_occupant_props(dip, dev, pci_dev); 430 } 431 432 skip: 433 return (ddi_prop_op(dev, dip, prop_op, flags, name, valuep, lengthp)); 434 } 435 436 int 437 pcie_init_cfghdl(dev_info_t *cdip) 438 { 439 pcie_bus_t *bus_p; 440 ddi_acc_handle_t eh = NULL; 441 442 bus_p = PCIE_DIP2BUS(cdip); 443 if (bus_p == NULL) 444 return (DDI_FAILURE); 445 446 /* Create an config access special to error handling */ 447 if (pci_config_setup(cdip, &eh) != DDI_SUCCESS) { 448 cmn_err(CE_WARN, "Cannot setup config access" 449 " for BDF 0x%x\n", bus_p->bus_bdf); 450 return (DDI_FAILURE); 451 } 452 453 bus_p->bus_cfg_hdl = eh; 454 return (DDI_SUCCESS); 455 } 456 457 void 458 pcie_fini_cfghdl(dev_info_t *cdip) 459 { 460 pcie_bus_t *bus_p = PCIE_DIP2BUS(cdip); 461 462 pci_config_teardown(&bus_p->bus_cfg_hdl); 463 } 464 465 /* 466 * PCI-Express child device initialization. 467 * This function enables generic pci-express interrupts and error 468 * handling. 469 * 470 * @param pdip root dip (root nexus's dip) 471 * @param cdip child's dip (device's dip) 472 * @return DDI_SUCCESS or DDI_FAILURE 473 */ 474 /* ARGSUSED */ 475 int 476 pcie_initchild(dev_info_t *cdip) 477 { 478 uint16_t tmp16, reg16; 479 pcie_bus_t *bus_p; 480 uint32_t devid, venid; 481 482 bus_p = PCIE_DIP2BUS(cdip); 483 if (bus_p == NULL) { 484 PCIE_DBG("%s: BUS not found.\n", 485 ddi_driver_name(cdip)); 486 487 return (DDI_FAILURE); 488 } 489 490 if (pcie_init_cfghdl(cdip) != DDI_SUCCESS) 491 return (DDI_FAILURE); 492 493 /* 494 * Update pcie_bus_t with real Vendor Id Device Id. 495 * 496 * For assigned devices in IOV environment, the OBP will return 497 * faked device id/vendor id on configration read and for both 498 * properties in root domain. translate_devid() function will 499 * update the properties with real device-id/vendor-id on such 500 * platforms, so that we can utilize the properties here to get 501 * real device-id/vendor-id and overwrite the faked ids. 502 * 503 * For unassigned devices or devices in non-IOV environment, the 504 * operation below won't make a difference. 505 * 506 * The IOV implementation only supports assignment of PCIE 507 * endpoint devices. Devices under pci-pci bridges don't need 508 * operation like this. 509 */ 510 devid = ddi_prop_get_int(DDI_DEV_T_ANY, cdip, DDI_PROP_DONTPASS, 511 "device-id", -1); 512 venid = ddi_prop_get_int(DDI_DEV_T_ANY, cdip, DDI_PROP_DONTPASS, 513 "vendor-id", -1); 514 bus_p->bus_dev_ven_id = (devid << 16) | (venid & 0xffff); 515 516 /* Clear the device's status register */ 517 reg16 = PCIE_GET(16, bus_p, PCI_CONF_STAT); 518 PCIE_PUT(16, bus_p, PCI_CONF_STAT, reg16); 519 520 /* Setup the device's command register */ 521 reg16 = PCIE_GET(16, bus_p, PCI_CONF_COMM); 522 tmp16 = (reg16 & pcie_command_default_fw) | pcie_command_default; 523 524 #if defined(__i386) || defined(__amd64) 525 boolean_t empty_io_range = B_FALSE; 526 boolean_t empty_mem_range = B_FALSE; 527 /* 528 * Check for empty IO and Mem ranges on bridges. If so disable IO/Mem 529 * access as it can cause a hang if enabled. 530 */ 531 pcie_check_io_mem_range(bus_p->bus_cfg_hdl, &empty_io_range, 532 &empty_mem_range); 533 if ((empty_io_range == B_TRUE) && 534 (pcie_command_default & PCI_COMM_IO)) { 535 tmp16 &= ~PCI_COMM_IO; 536 PCIE_DBG("No I/O range found for %s, bdf 0x%x\n", 537 ddi_driver_name(cdip), bus_p->bus_bdf); 538 } 539 if ((empty_mem_range == B_TRUE) && 540 (pcie_command_default & PCI_COMM_MAE)) { 541 tmp16 &= ~PCI_COMM_MAE; 542 PCIE_DBG("No Mem range found for %s, bdf 0x%x\n", 543 ddi_driver_name(cdip), bus_p->bus_bdf); 544 } 545 #endif /* defined(__i386) || defined(__amd64) */ 546 547 if (pcie_serr_disable_flag && PCIE_IS_PCIE(bus_p)) 548 tmp16 &= ~PCI_COMM_SERR_ENABLE; 549 550 PCIE_PUT(16, bus_p, PCI_CONF_COMM, tmp16); 551 PCIE_DBG_CFG(cdip, bus_p, "COMMAND", 16, PCI_CONF_COMM, reg16); 552 553 /* 554 * If the device has a bus control register then program it 555 * based on the settings in the command register. 556 */ 557 if (PCIE_IS_BDG(bus_p)) { 558 /* Clear the device's secondary status register */ 559 reg16 = PCIE_GET(16, bus_p, PCI_BCNF_SEC_STATUS); 560 PCIE_PUT(16, bus_p, PCI_BCNF_SEC_STATUS, reg16); 561 562 /* Setup the device's secondary command register */ 563 reg16 = PCIE_GET(16, bus_p, PCI_BCNF_BCNTRL); 564 tmp16 = (reg16 & pcie_bdg_command_default_fw); 565 566 tmp16 |= PCI_BCNF_BCNTRL_SERR_ENABLE; 567 /* 568 * Workaround for this Nvidia bridge. Don't enable the SERR 569 * enable bit in the bridge control register as it could lead to 570 * bogus NMIs. 571 */ 572 if (bus_p->bus_dev_ven_id == 0x037010DE) 573 tmp16 &= ~PCI_BCNF_BCNTRL_SERR_ENABLE; 574 575 if (pcie_command_default & PCI_COMM_PARITY_DETECT) 576 tmp16 |= PCI_BCNF_BCNTRL_PARITY_ENABLE; 577 578 /* 579 * Enable Master Abort Mode only if URs have not been masked. 580 * For PCI and PCIe-PCI bridges, enabling this bit causes a 581 * Master Aborts/UR to be forwarded as a UR/TA or SERR. If this 582 * bit is masked, posted requests are dropped and non-posted 583 * requests are returned with -1. 584 */ 585 if (pcie_aer_uce_mask & PCIE_AER_UCE_UR) 586 tmp16 &= ~PCI_BCNF_BCNTRL_MAST_AB_MODE; 587 else 588 tmp16 |= PCI_BCNF_BCNTRL_MAST_AB_MODE; 589 PCIE_PUT(16, bus_p, PCI_BCNF_BCNTRL, tmp16); 590 PCIE_DBG_CFG(cdip, bus_p, "SEC CMD", 16, PCI_BCNF_BCNTRL, 591 reg16); 592 } 593 594 if (PCIE_IS_PCIE(bus_p)) { 595 /* Setup PCIe device control register */ 596 reg16 = PCIE_CAP_GET(16, bus_p, PCIE_DEVCTL); 597 tmp16 = pcie_devctl_default; 598 PCIE_CAP_PUT(16, bus_p, PCIE_DEVCTL, tmp16); 599 PCIE_DBG_CAP(cdip, bus_p, "DEVCTL", 16, PCIE_DEVCTL, reg16); 600 601 /* Enable PCIe errors */ 602 pcie_enable_errors(cdip); 603 } 604 605 bus_p->bus_ari = B_FALSE; 606 if ((pcie_ari_is_enabled(ddi_get_parent(cdip)) 607 == PCIE_ARI_FORW_ENABLED) && (pcie_ari_device(cdip) 608 == PCIE_ARI_DEVICE)) { 609 bus_p->bus_ari = B_TRUE; 610 } 611 612 if (pcie_initchild_mps(cdip) == DDI_FAILURE) { 613 pcie_fini_cfghdl(cdip); 614 return (DDI_FAILURE); 615 } 616 617 return (DDI_SUCCESS); 618 } 619 620 static void 621 pcie_init_pfd(dev_info_t *dip) 622 { 623 pf_data_t *pfd_p = PCIE_ZALLOC(pf_data_t); 624 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 625 626 PCIE_DIP2PFD(dip) = pfd_p; 627 628 pfd_p->pe_bus_p = bus_p; 629 pfd_p->pe_severity_flags = 0; 630 pfd_p->pe_orig_severity_flags = 0; 631 pfd_p->pe_lock = B_FALSE; 632 pfd_p->pe_valid = B_FALSE; 633 634 /* Allocate the root fault struct for both RC and RP */ 635 if (PCIE_IS_ROOT(bus_p)) { 636 PCIE_ROOT_FAULT(pfd_p) = PCIE_ZALLOC(pf_root_fault_t); 637 PCIE_ROOT_FAULT(pfd_p)->scan_bdf = PCIE_INVALID_BDF; 638 PCIE_ROOT_EH_SRC(pfd_p) = PCIE_ZALLOC(pf_root_eh_src_t); 639 } 640 641 PCI_ERR_REG(pfd_p) = PCIE_ZALLOC(pf_pci_err_regs_t); 642 PFD_AFFECTED_DEV(pfd_p) = PCIE_ZALLOC(pf_affected_dev_t); 643 PFD_AFFECTED_DEV(pfd_p)->pe_affected_bdf = PCIE_INVALID_BDF; 644 645 if (PCIE_IS_BDG(bus_p)) 646 PCI_BDG_ERR_REG(pfd_p) = PCIE_ZALLOC(pf_pci_bdg_err_regs_t); 647 648 if (PCIE_IS_PCIE(bus_p)) { 649 PCIE_ERR_REG(pfd_p) = PCIE_ZALLOC(pf_pcie_err_regs_t); 650 651 if (PCIE_IS_RP(bus_p)) 652 PCIE_RP_REG(pfd_p) = 653 PCIE_ZALLOC(pf_pcie_rp_err_regs_t); 654 655 PCIE_ADV_REG(pfd_p) = PCIE_ZALLOC(pf_pcie_adv_err_regs_t); 656 PCIE_ADV_REG(pfd_p)->pcie_ue_tgt_bdf = PCIE_INVALID_BDF; 657 658 if (PCIE_IS_RP(bus_p)) { 659 PCIE_ADV_RP_REG(pfd_p) = 660 PCIE_ZALLOC(pf_pcie_adv_rp_err_regs_t); 661 PCIE_ADV_RP_REG(pfd_p)->pcie_rp_ce_src_id = 662 PCIE_INVALID_BDF; 663 PCIE_ADV_RP_REG(pfd_p)->pcie_rp_ue_src_id = 664 PCIE_INVALID_BDF; 665 } else if (PCIE_IS_PCIE_BDG(bus_p)) { 666 PCIE_ADV_BDG_REG(pfd_p) = 667 PCIE_ZALLOC(pf_pcie_adv_bdg_err_regs_t); 668 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_tgt_bdf = 669 PCIE_INVALID_BDF; 670 } 671 672 if (PCIE_IS_PCIE_BDG(bus_p) && PCIE_IS_PCIX(bus_p)) { 673 PCIX_BDG_ERR_REG(pfd_p) = 674 PCIE_ZALLOC(pf_pcix_bdg_err_regs_t); 675 676 if (PCIX_ECC_VERSION_CHECK(bus_p)) { 677 PCIX_BDG_ECC_REG(pfd_p, 0) = 678 PCIE_ZALLOC(pf_pcix_ecc_regs_t); 679 PCIX_BDG_ECC_REG(pfd_p, 1) = 680 PCIE_ZALLOC(pf_pcix_ecc_regs_t); 681 } 682 } 683 } else if (PCIE_IS_PCIX(bus_p)) { 684 if (PCIE_IS_BDG(bus_p)) { 685 PCIX_BDG_ERR_REG(pfd_p) = 686 PCIE_ZALLOC(pf_pcix_bdg_err_regs_t); 687 688 if (PCIX_ECC_VERSION_CHECK(bus_p)) { 689 PCIX_BDG_ECC_REG(pfd_p, 0) = 690 PCIE_ZALLOC(pf_pcix_ecc_regs_t); 691 PCIX_BDG_ECC_REG(pfd_p, 1) = 692 PCIE_ZALLOC(pf_pcix_ecc_regs_t); 693 } 694 } else { 695 PCIX_ERR_REG(pfd_p) = PCIE_ZALLOC(pf_pcix_err_regs_t); 696 697 if (PCIX_ECC_VERSION_CHECK(bus_p)) 698 PCIX_ECC_REG(pfd_p) = 699 PCIE_ZALLOC(pf_pcix_ecc_regs_t); 700 } 701 } 702 } 703 704 static void 705 pcie_fini_pfd(dev_info_t *dip) 706 { 707 pf_data_t *pfd_p = PCIE_DIP2PFD(dip); 708 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 709 710 if (PCIE_IS_PCIE(bus_p)) { 711 if (PCIE_IS_PCIE_BDG(bus_p) && PCIE_IS_PCIX(bus_p)) { 712 if (PCIX_ECC_VERSION_CHECK(bus_p)) { 713 kmem_free(PCIX_BDG_ECC_REG(pfd_p, 0), 714 sizeof (pf_pcix_ecc_regs_t)); 715 kmem_free(PCIX_BDG_ECC_REG(pfd_p, 1), 716 sizeof (pf_pcix_ecc_regs_t)); 717 } 718 719 kmem_free(PCIX_BDG_ERR_REG(pfd_p), 720 sizeof (pf_pcix_bdg_err_regs_t)); 721 } 722 723 if (PCIE_IS_RP(bus_p)) 724 kmem_free(PCIE_ADV_RP_REG(pfd_p), 725 sizeof (pf_pcie_adv_rp_err_regs_t)); 726 else if (PCIE_IS_PCIE_BDG(bus_p)) 727 kmem_free(PCIE_ADV_BDG_REG(pfd_p), 728 sizeof (pf_pcie_adv_bdg_err_regs_t)); 729 730 kmem_free(PCIE_ADV_REG(pfd_p), 731 sizeof (pf_pcie_adv_err_regs_t)); 732 733 if (PCIE_IS_RP(bus_p)) 734 kmem_free(PCIE_RP_REG(pfd_p), 735 sizeof (pf_pcie_rp_err_regs_t)); 736 737 kmem_free(PCIE_ERR_REG(pfd_p), sizeof (pf_pcie_err_regs_t)); 738 } else if (PCIE_IS_PCIX(bus_p)) { 739 if (PCIE_IS_BDG(bus_p)) { 740 if (PCIX_ECC_VERSION_CHECK(bus_p)) { 741 kmem_free(PCIX_BDG_ECC_REG(pfd_p, 0), 742 sizeof (pf_pcix_ecc_regs_t)); 743 kmem_free(PCIX_BDG_ECC_REG(pfd_p, 1), 744 sizeof (pf_pcix_ecc_regs_t)); 745 } 746 747 kmem_free(PCIX_BDG_ERR_REG(pfd_p), 748 sizeof (pf_pcix_bdg_err_regs_t)); 749 } else { 750 if (PCIX_ECC_VERSION_CHECK(bus_p)) 751 kmem_free(PCIX_ECC_REG(pfd_p), 752 sizeof (pf_pcix_ecc_regs_t)); 753 754 kmem_free(PCIX_ERR_REG(pfd_p), 755 sizeof (pf_pcix_err_regs_t)); 756 } 757 } 758 759 if (PCIE_IS_BDG(bus_p)) 760 kmem_free(PCI_BDG_ERR_REG(pfd_p), 761 sizeof (pf_pci_bdg_err_regs_t)); 762 763 kmem_free(PFD_AFFECTED_DEV(pfd_p), sizeof (pf_affected_dev_t)); 764 kmem_free(PCI_ERR_REG(pfd_p), sizeof (pf_pci_err_regs_t)); 765 766 if (PCIE_IS_ROOT(bus_p)) { 767 kmem_free(PCIE_ROOT_FAULT(pfd_p), sizeof (pf_root_fault_t)); 768 kmem_free(PCIE_ROOT_EH_SRC(pfd_p), sizeof (pf_root_eh_src_t)); 769 } 770 771 kmem_free(PCIE_DIP2PFD(dip), sizeof (pf_data_t)); 772 773 PCIE_DIP2PFD(dip) = NULL; 774 } 775 776 777 /* 778 * Special functions to allocate pf_data_t's for PCIe root complexes. 779 * Note: Root Complex not Root Port 780 */ 781 void 782 pcie_rc_init_pfd(dev_info_t *dip, pf_data_t *pfd_p) 783 { 784 pfd_p->pe_bus_p = PCIE_DIP2DOWNBUS(dip); 785 pfd_p->pe_severity_flags = 0; 786 pfd_p->pe_orig_severity_flags = 0; 787 pfd_p->pe_lock = B_FALSE; 788 pfd_p->pe_valid = B_FALSE; 789 790 PCIE_ROOT_FAULT(pfd_p) = PCIE_ZALLOC(pf_root_fault_t); 791 PCIE_ROOT_FAULT(pfd_p)->scan_bdf = PCIE_INVALID_BDF; 792 PCIE_ROOT_EH_SRC(pfd_p) = PCIE_ZALLOC(pf_root_eh_src_t); 793 PCI_ERR_REG(pfd_p) = PCIE_ZALLOC(pf_pci_err_regs_t); 794 PFD_AFFECTED_DEV(pfd_p) = PCIE_ZALLOC(pf_affected_dev_t); 795 PFD_AFFECTED_DEV(pfd_p)->pe_affected_bdf = PCIE_INVALID_BDF; 796 PCI_BDG_ERR_REG(pfd_p) = PCIE_ZALLOC(pf_pci_bdg_err_regs_t); 797 PCIE_ERR_REG(pfd_p) = PCIE_ZALLOC(pf_pcie_err_regs_t); 798 PCIE_RP_REG(pfd_p) = PCIE_ZALLOC(pf_pcie_rp_err_regs_t); 799 PCIE_ADV_REG(pfd_p) = PCIE_ZALLOC(pf_pcie_adv_err_regs_t); 800 PCIE_ADV_RP_REG(pfd_p) = PCIE_ZALLOC(pf_pcie_adv_rp_err_regs_t); 801 PCIE_ADV_RP_REG(pfd_p)->pcie_rp_ce_src_id = PCIE_INVALID_BDF; 802 PCIE_ADV_RP_REG(pfd_p)->pcie_rp_ue_src_id = PCIE_INVALID_BDF; 803 804 PCIE_ADV_REG(pfd_p)->pcie_ue_sev = pcie_aer_uce_severity; 805 } 806 807 void 808 pcie_rc_fini_pfd(pf_data_t *pfd_p) 809 { 810 kmem_free(PCIE_ADV_RP_REG(pfd_p), sizeof (pf_pcie_adv_rp_err_regs_t)); 811 kmem_free(PCIE_ADV_REG(pfd_p), sizeof (pf_pcie_adv_err_regs_t)); 812 kmem_free(PCIE_RP_REG(pfd_p), sizeof (pf_pcie_rp_err_regs_t)); 813 kmem_free(PCIE_ERR_REG(pfd_p), sizeof (pf_pcie_err_regs_t)); 814 kmem_free(PCI_BDG_ERR_REG(pfd_p), sizeof (pf_pci_bdg_err_regs_t)); 815 kmem_free(PFD_AFFECTED_DEV(pfd_p), sizeof (pf_affected_dev_t)); 816 kmem_free(PCI_ERR_REG(pfd_p), sizeof (pf_pci_err_regs_t)); 817 kmem_free(PCIE_ROOT_FAULT(pfd_p), sizeof (pf_root_fault_t)); 818 kmem_free(PCIE_ROOT_EH_SRC(pfd_p), sizeof (pf_root_eh_src_t)); 819 } 820 821 /* 822 * init pcie_bus_t for root complex 823 * 824 * Only a few of the fields in bus_t is valid for root complex. 825 * The fields that are bracketed are initialized in this routine: 826 * 827 * dev_info_t * <bus_dip> 828 * dev_info_t * bus_rp_dip 829 * ddi_acc_handle_t bus_cfg_hdl 830 * uint_t <bus_fm_flags> 831 * pcie_req_id_t bus_bdf 832 * pcie_req_id_t bus_rp_bdf 833 * uint32_t bus_dev_ven_id 834 * uint8_t bus_rev_id 835 * uint8_t <bus_hdr_type> 836 * uint16_t <bus_dev_type> 837 * uint8_t bus_bdg_secbus 838 * uint16_t bus_pcie_off 839 * uint16_t <bus_aer_off> 840 * uint16_t bus_pcix_off 841 * uint16_t bus_ecc_ver 842 * pci_bus_range_t bus_bus_range 843 * ppb_ranges_t * bus_addr_ranges 844 * int bus_addr_entries 845 * pci_regspec_t * bus_assigned_addr 846 * int bus_assigned_entries 847 * pf_data_t * bus_pfd 848 * pcie_domain_t * <bus_dom> 849 * int bus_mps 850 * uint64_t bus_cfgacc_base 851 * void * bus_plat_private 852 */ 853 void 854 pcie_rc_init_bus(dev_info_t *dip) 855 { 856 pcie_bus_t *bus_p; 857 858 bus_p = (pcie_bus_t *)kmem_zalloc(sizeof (pcie_bus_t), KM_SLEEP); 859 bus_p->bus_dip = dip; 860 bus_p->bus_dev_type = PCIE_PCIECAP_DEV_TYPE_RC_PSEUDO; 861 bus_p->bus_hdr_type = PCI_HEADER_ONE; 862 863 /* Fake that there are AER logs */ 864 bus_p->bus_aer_off = (uint16_t)-1; 865 866 /* Needed only for handle lookup */ 867 bus_p->bus_fm_flags |= PF_FM_READY; 868 869 ndi_set_bus_private(dip, B_FALSE, DEVI_PORT_TYPE_PCI, bus_p); 870 871 PCIE_BUS2DOM(bus_p) = PCIE_ZALLOC(pcie_domain_t); 872 } 873 874 void 875 pcie_rc_fini_bus(dev_info_t *dip) 876 { 877 pcie_bus_t *bus_p = PCIE_DIP2DOWNBUS(dip); 878 ndi_set_bus_private(dip, B_FALSE, NULL, NULL); 879 kmem_free(PCIE_BUS2DOM(bus_p), sizeof (pcie_domain_t)); 880 kmem_free(bus_p, sizeof (pcie_bus_t)); 881 } 882 883 /* 884 * partially init pcie_bus_t for device (dip,bdf) for accessing pci 885 * config space 886 * 887 * This routine is invoked during boot, either after creating a devinfo node 888 * (x86 case) or during px driver attach (sparc case); it is also invoked 889 * in hotplug context after a devinfo node is created. 890 * 891 * The fields that are bracketed are initialized if flag PCIE_BUS_INITIAL 892 * is set: 893 * 894 * dev_info_t * <bus_dip> 895 * dev_info_t * <bus_rp_dip> 896 * ddi_acc_handle_t bus_cfg_hdl 897 * uint_t bus_fm_flags 898 * pcie_req_id_t <bus_bdf> 899 * pcie_req_id_t <bus_rp_bdf> 900 * uint32_t <bus_dev_ven_id> 901 * uint8_t <bus_rev_id> 902 * uint8_t <bus_hdr_type> 903 * uint16_t <bus_dev_type> 904 * uint8_t <bus_bdg_secbus 905 * uint16_t <bus_pcie_off> 906 * uint16_t <bus_aer_off> 907 * uint16_t <bus_pcix_off> 908 * uint16_t <bus_ecc_ver> 909 * pci_bus_range_t bus_bus_range 910 * ppb_ranges_t * bus_addr_ranges 911 * int bus_addr_entries 912 * pci_regspec_t * bus_assigned_addr 913 * int bus_assigned_entries 914 * pf_data_t * bus_pfd 915 * pcie_domain_t * bus_dom 916 * int bus_mps 917 * uint64_t bus_cfgacc_base 918 * void * bus_plat_private 919 * 920 * The fields that are bracketed are initialized if flag PCIE_BUS_FINAL 921 * is set: 922 * 923 * dev_info_t * bus_dip 924 * dev_info_t * bus_rp_dip 925 * ddi_acc_handle_t bus_cfg_hdl 926 * uint_t bus_fm_flags 927 * pcie_req_id_t bus_bdf 928 * pcie_req_id_t bus_rp_bdf 929 * uint32_t bus_dev_ven_id 930 * uint8_t bus_rev_id 931 * uint8_t bus_hdr_type 932 * uint16_t bus_dev_type 933 * uint8_t <bus_bdg_secbus> 934 * uint16_t bus_pcie_off 935 * uint16_t bus_aer_off 936 * uint16_t bus_pcix_off 937 * uint16_t bus_ecc_ver 938 * pci_bus_range_t <bus_bus_range> 939 * ppb_ranges_t * <bus_addr_ranges> 940 * int <bus_addr_entries> 941 * pci_regspec_t * <bus_assigned_addr> 942 * int <bus_assigned_entries> 943 * pf_data_t * <bus_pfd> 944 * pcie_domain_t * bus_dom 945 * int bus_mps 946 * uint64_t bus_cfgacc_base 947 * void * <bus_plat_private> 948 */ 949 950 pcie_bus_t * 951 pcie_init_bus(dev_info_t *dip, pcie_req_id_t bdf, uint8_t flags) 952 { 953 uint16_t status, base, baseptr, num_cap; 954 uint32_t capid; 955 int range_size; 956 pcie_bus_t *bus_p; 957 dev_info_t *rcdip; 958 dev_info_t *pdip; 959 const char *errstr = NULL; 960 961 if (!(flags & PCIE_BUS_INITIAL)) 962 goto initial_done; 963 964 bus_p = kmem_zalloc(sizeof (pcie_bus_t), KM_SLEEP); 965 966 bus_p->bus_dip = dip; 967 bus_p->bus_bdf = bdf; 968 969 rcdip = pcie_get_rc_dip(dip); 970 ASSERT(rcdip != NULL); 971 972 /* Save the Vendor ID, Device ID and revision ID */ 973 bus_p->bus_dev_ven_id = pci_cfgacc_get32(rcdip, bdf, PCI_CONF_VENID); 974 bus_p->bus_rev_id = pci_cfgacc_get8(rcdip, bdf, PCI_CONF_REVID); 975 /* Save the Header Type */ 976 bus_p->bus_hdr_type = pci_cfgacc_get8(rcdip, bdf, PCI_CONF_HEADER); 977 bus_p->bus_hdr_type &= PCI_HEADER_TYPE_M; 978 979 /* 980 * Figure out the device type and all the relavant capability offsets 981 */ 982 /* set default value */ 983 bus_p->bus_dev_type = PCIE_PCIECAP_DEV_TYPE_PCI_PSEUDO; 984 985 status = pci_cfgacc_get16(rcdip, bdf, PCI_CONF_STAT); 986 if (status == PCI_CAP_EINVAL16 || !(status & PCI_STAT_CAP)) 987 goto caps_done; /* capability not supported */ 988 989 /* Relevant conventional capabilities first */ 990 991 /* Conventional caps: PCI_CAP_ID_PCI_E, PCI_CAP_ID_PCIX */ 992 num_cap = 2; 993 994 switch (bus_p->bus_hdr_type) { 995 case PCI_HEADER_ZERO: 996 baseptr = PCI_CONF_CAP_PTR; 997 break; 998 case PCI_HEADER_PPB: 999 baseptr = PCI_BCNF_CAP_PTR; 1000 break; 1001 case PCI_HEADER_CARDBUS: 1002 baseptr = PCI_CBUS_CAP_PTR; 1003 break; 1004 default: 1005 cmn_err(CE_WARN, "%s: unexpected pci header type:%x", 1006 __func__, bus_p->bus_hdr_type); 1007 goto caps_done; 1008 } 1009 1010 base = baseptr; 1011 for (base = pci_cfgacc_get8(rcdip, bdf, base); base && num_cap; 1012 base = pci_cfgacc_get8(rcdip, bdf, base + PCI_CAP_NEXT_PTR)) { 1013 capid = pci_cfgacc_get8(rcdip, bdf, base); 1014 switch (capid) { 1015 case PCI_CAP_ID_PCI_E: 1016 bus_p->bus_pcie_off = base; 1017 bus_p->bus_dev_type = pci_cfgacc_get16(rcdip, bdf, 1018 base + PCIE_PCIECAP) & PCIE_PCIECAP_DEV_TYPE_MASK; 1019 1020 /* Check and save PCIe hotplug capability information */ 1021 if ((PCIE_IS_RP(bus_p) || PCIE_IS_SWD(bus_p)) && 1022 (pci_cfgacc_get16(rcdip, bdf, base + PCIE_PCIECAP) 1023 & PCIE_PCIECAP_SLOT_IMPL) && 1024 (pci_cfgacc_get32(rcdip, bdf, base + PCIE_SLOTCAP) 1025 & PCIE_SLOTCAP_HP_CAPABLE)) 1026 bus_p->bus_hp_sup_modes |= PCIE_NATIVE_HP_MODE; 1027 1028 num_cap--; 1029 break; 1030 case PCI_CAP_ID_PCIX: 1031 bus_p->bus_pcix_off = base; 1032 if (PCIE_IS_BDG(bus_p)) 1033 bus_p->bus_ecc_ver = 1034 pci_cfgacc_get16(rcdip, bdf, base + 1035 PCI_PCIX_SEC_STATUS) & PCI_PCIX_VER_MASK; 1036 else 1037 bus_p->bus_ecc_ver = 1038 pci_cfgacc_get16(rcdip, bdf, base + 1039 PCI_PCIX_COMMAND) & PCI_PCIX_VER_MASK; 1040 num_cap--; 1041 break; 1042 default: 1043 break; 1044 } 1045 } 1046 1047 /* Check and save PCI hotplug (SHPC) capability information */ 1048 if (PCIE_IS_BDG(bus_p)) { 1049 base = baseptr; 1050 for (base = pci_cfgacc_get8(rcdip, bdf, base); 1051 base; base = pci_cfgacc_get8(rcdip, bdf, 1052 base + PCI_CAP_NEXT_PTR)) { 1053 capid = pci_cfgacc_get8(rcdip, bdf, base); 1054 if (capid == PCI_CAP_ID_PCI_HOTPLUG) { 1055 bus_p->bus_pci_hp_off = base; 1056 bus_p->bus_hp_sup_modes |= PCIE_PCI_HP_MODE; 1057 break; 1058 } 1059 } 1060 } 1061 1062 /* Then, relevant extended capabilities */ 1063 1064 if (!PCIE_IS_PCIE(bus_p)) 1065 goto caps_done; 1066 1067 /* Extended caps: PCIE_EXT_CAP_ID_AER */ 1068 for (base = PCIE_EXT_CAP; base; base = (capid >> 1069 PCIE_EXT_CAP_NEXT_PTR_SHIFT) & PCIE_EXT_CAP_NEXT_PTR_MASK) { 1070 capid = pci_cfgacc_get32(rcdip, bdf, base); 1071 if (capid == PCI_CAP_EINVAL32) 1072 break; 1073 if (((capid >> PCIE_EXT_CAP_ID_SHIFT) & PCIE_EXT_CAP_ID_MASK) 1074 == PCIE_EXT_CAP_ID_AER) { 1075 bus_p->bus_aer_off = base; 1076 break; 1077 } 1078 } 1079 1080 caps_done: 1081 /* save RP dip and RP bdf */ 1082 if (PCIE_IS_RP(bus_p)) { 1083 bus_p->bus_rp_dip = dip; 1084 bus_p->bus_rp_bdf = bus_p->bus_bdf; 1085 } else { 1086 for (pdip = ddi_get_parent(dip); pdip; 1087 pdip = ddi_get_parent(pdip)) { 1088 pcie_bus_t *parent_bus_p = PCIE_DIP2BUS(pdip); 1089 1090 /* 1091 * If RP dip and RP bdf in parent's bus_t have 1092 * been initialized, simply use these instead of 1093 * continuing up to the RC. 1094 */ 1095 if (parent_bus_p->bus_rp_dip != NULL) { 1096 bus_p->bus_rp_dip = parent_bus_p->bus_rp_dip; 1097 bus_p->bus_rp_bdf = parent_bus_p->bus_rp_bdf; 1098 break; 1099 } 1100 1101 /* 1102 * When debugging be aware that some NVIDIA x86 1103 * architectures have 2 nodes for each RP, One at Bus 1104 * 0x0 and one at Bus 0x80. The requester is from Bus 1105 * 0x80 1106 */ 1107 if (PCIE_IS_ROOT(parent_bus_p)) { 1108 bus_p->bus_rp_dip = pdip; 1109 bus_p->bus_rp_bdf = parent_bus_p->bus_bdf; 1110 break; 1111 } 1112 } 1113 } 1114 1115 bus_p->bus_soft_state = PCI_SOFT_STATE_CLOSED; 1116 bus_p->bus_fm_flags = 0; 1117 bus_p->bus_mps = 0; 1118 1119 ndi_set_bus_private(dip, B_TRUE, DEVI_PORT_TYPE_PCI, (void *)bus_p); 1120 1121 if (PCIE_IS_HOTPLUG_CAPABLE(dip)) 1122 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 1123 "hotplug-capable"); 1124 1125 initial_done: 1126 if (!(flags & PCIE_BUS_FINAL)) 1127 goto final_done; 1128 1129 /* already initialized? */ 1130 bus_p = PCIE_DIP2BUS(dip); 1131 1132 /* Save the Range information if device is a switch/bridge */ 1133 if (PCIE_IS_BDG(bus_p)) { 1134 /* get "bus_range" property */ 1135 range_size = sizeof (pci_bus_range_t); 1136 if (ddi_getlongprop_buf(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1137 "bus-range", (caddr_t)&bus_p->bus_bus_range, &range_size) 1138 != DDI_PROP_SUCCESS) { 1139 errstr = "Cannot find \"bus-range\" property"; 1140 cmn_err(CE_WARN, 1141 "PCIE init err info failed BDF 0x%x:%s\n", 1142 bus_p->bus_bdf, errstr); 1143 } 1144 1145 /* get secondary bus number */ 1146 rcdip = pcie_get_rc_dip(dip); 1147 ASSERT(rcdip != NULL); 1148 1149 bus_p->bus_bdg_secbus = pci_cfgacc_get8(rcdip, 1150 bus_p->bus_bdf, PCI_BCNF_SECBUS); 1151 1152 /* Get "ranges" property */ 1153 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1154 "ranges", (caddr_t)&bus_p->bus_addr_ranges, 1155 &bus_p->bus_addr_entries) != DDI_PROP_SUCCESS) 1156 bus_p->bus_addr_entries = 0; 1157 bus_p->bus_addr_entries /= sizeof (ppb_ranges_t); 1158 } 1159 1160 /* save "assigned-addresses" property array, ignore failues */ 1161 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1162 "assigned-addresses", (caddr_t)&bus_p->bus_assigned_addr, 1163 &bus_p->bus_assigned_entries) == DDI_PROP_SUCCESS) 1164 bus_p->bus_assigned_entries /= sizeof (pci_regspec_t); 1165 else 1166 bus_p->bus_assigned_entries = 0; 1167 1168 pcie_init_pfd(dip); 1169 1170 pcie_init_plat(dip); 1171 1172 final_done: 1173 1174 PCIE_DBG("Add %s(dip 0x%p, bdf 0x%x, secbus 0x%x)\n", 1175 ddi_driver_name(dip), (void *)dip, bus_p->bus_bdf, 1176 bus_p->bus_bdg_secbus); 1177 #ifdef DEBUG 1178 pcie_print_bus(bus_p); 1179 #endif 1180 1181 return (bus_p); 1182 } 1183 1184 /* 1185 * Invoked before destroying devinfo node, mostly during hotplug 1186 * operation to free pcie_bus_t data structure 1187 */ 1188 /* ARGSUSED */ 1189 void 1190 pcie_fini_bus(dev_info_t *dip, uint8_t flags) 1191 { 1192 pcie_bus_t *bus_p = PCIE_DIP2UPBUS(dip); 1193 ASSERT(bus_p); 1194 1195 if (flags & PCIE_BUS_INITIAL) { 1196 pcie_fini_plat(dip); 1197 pcie_fini_pfd(dip); 1198 1199 kmem_free(bus_p->bus_assigned_addr, 1200 (sizeof (pci_regspec_t) * bus_p->bus_assigned_entries)); 1201 kmem_free(bus_p->bus_addr_ranges, 1202 (sizeof (ppb_ranges_t) * bus_p->bus_addr_entries)); 1203 /* zero out the fields that have been destroyed */ 1204 bus_p->bus_assigned_addr = NULL; 1205 bus_p->bus_addr_ranges = NULL; 1206 bus_p->bus_assigned_entries = 0; 1207 bus_p->bus_addr_entries = 0; 1208 } 1209 1210 if (flags & PCIE_BUS_FINAL) { 1211 if (PCIE_IS_HOTPLUG_CAPABLE(dip)) { 1212 (void) ndi_prop_remove(DDI_DEV_T_NONE, dip, 1213 "hotplug-capable"); 1214 } 1215 1216 ndi_set_bus_private(dip, B_TRUE, NULL, NULL); 1217 kmem_free(bus_p, sizeof (pcie_bus_t)); 1218 } 1219 } 1220 1221 int 1222 pcie_postattach_child(dev_info_t *cdip) 1223 { 1224 pcie_bus_t *bus_p = PCIE_DIP2BUS(cdip); 1225 1226 if (!bus_p) 1227 return (DDI_FAILURE); 1228 1229 return (pcie_enable_ce(cdip)); 1230 } 1231 1232 /* 1233 * PCI-Express child device de-initialization. 1234 * This function disables generic pci-express interrupts and error 1235 * handling. 1236 */ 1237 void 1238 pcie_uninitchild(dev_info_t *cdip) 1239 { 1240 pcie_disable_errors(cdip); 1241 pcie_fini_cfghdl(cdip); 1242 pcie_fini_dom(cdip); 1243 } 1244 1245 /* 1246 * find the root complex dip 1247 */ 1248 dev_info_t * 1249 pcie_get_rc_dip(dev_info_t *dip) 1250 { 1251 dev_info_t *rcdip; 1252 pcie_bus_t *rc_bus_p; 1253 1254 for (rcdip = ddi_get_parent(dip); rcdip; 1255 rcdip = ddi_get_parent(rcdip)) { 1256 rc_bus_p = PCIE_DIP2BUS(rcdip); 1257 if (rc_bus_p && PCIE_IS_RC(rc_bus_p)) 1258 break; 1259 } 1260 1261 return (rcdip); 1262 } 1263 1264 static boolean_t 1265 pcie_is_pci_device(dev_info_t *dip) 1266 { 1267 dev_info_t *pdip; 1268 char *device_type; 1269 1270 pdip = ddi_get_parent(dip); 1271 ASSERT(pdip); 1272 1273 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pdip, DDI_PROP_DONTPASS, 1274 "device_type", &device_type) != DDI_PROP_SUCCESS) 1275 return (B_FALSE); 1276 1277 if (strcmp(device_type, "pciex") != 0 && 1278 strcmp(device_type, "pci") != 0) { 1279 ddi_prop_free(device_type); 1280 return (B_FALSE); 1281 } 1282 1283 ddi_prop_free(device_type); 1284 return (B_TRUE); 1285 } 1286 1287 typedef struct { 1288 boolean_t init; 1289 uint8_t flags; 1290 } pcie_bus_arg_t; 1291 1292 /*ARGSUSED*/ 1293 static int 1294 pcie_fab_do_init_fini(dev_info_t *dip, void *arg) 1295 { 1296 pcie_req_id_t bdf; 1297 pcie_bus_arg_t *bus_arg = (pcie_bus_arg_t *)arg; 1298 1299 if (!pcie_is_pci_device(dip)) 1300 goto out; 1301 1302 if (bus_arg->init) { 1303 if (pcie_get_bdf_from_dip(dip, &bdf) != DDI_SUCCESS) 1304 goto out; 1305 1306 (void) pcie_init_bus(dip, bdf, bus_arg->flags); 1307 } else { 1308 (void) pcie_fini_bus(dip, bus_arg->flags); 1309 } 1310 1311 return (DDI_WALK_CONTINUE); 1312 1313 out: 1314 return (DDI_WALK_PRUNECHILD); 1315 } 1316 1317 void 1318 pcie_fab_init_bus(dev_info_t *rcdip, uint8_t flags) 1319 { 1320 int circular_count; 1321 dev_info_t *dip = ddi_get_child(rcdip); 1322 pcie_bus_arg_t arg; 1323 1324 arg.init = B_TRUE; 1325 arg.flags = flags; 1326 1327 ndi_devi_enter(rcdip, &circular_count); 1328 ddi_walk_devs(dip, pcie_fab_do_init_fini, &arg); 1329 ndi_devi_exit(rcdip, circular_count); 1330 } 1331 1332 void 1333 pcie_fab_fini_bus(dev_info_t *rcdip, uint8_t flags) 1334 { 1335 int circular_count; 1336 dev_info_t *dip = ddi_get_child(rcdip); 1337 pcie_bus_arg_t arg; 1338 1339 arg.init = B_FALSE; 1340 arg.flags = flags; 1341 1342 ndi_devi_enter(rcdip, &circular_count); 1343 ddi_walk_devs(dip, pcie_fab_do_init_fini, &arg); 1344 ndi_devi_exit(rcdip, circular_count); 1345 } 1346 1347 void 1348 pcie_enable_errors(dev_info_t *dip) 1349 { 1350 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 1351 uint16_t reg16, tmp16; 1352 uint32_t reg32, tmp32; 1353 1354 ASSERT(bus_p); 1355 1356 /* 1357 * Clear any pending errors 1358 */ 1359 pcie_clear_errors(dip); 1360 1361 if (!PCIE_IS_PCIE(bus_p)) 1362 return; 1363 1364 /* 1365 * Enable Baseline Error Handling but leave CE reporting off (poweron 1366 * default). 1367 */ 1368 if ((reg16 = PCIE_CAP_GET(16, bus_p, PCIE_DEVCTL)) != 1369 PCI_CAP_EINVAL16) { 1370 tmp16 = (reg16 & (PCIE_DEVCTL_MAX_READ_REQ_MASK | 1371 PCIE_DEVCTL_MAX_PAYLOAD_MASK)) | 1372 (pcie_devctl_default & ~(PCIE_DEVCTL_MAX_READ_REQ_MASK | 1373 PCIE_DEVCTL_MAX_PAYLOAD_MASK)) | 1374 (pcie_base_err_default & (~PCIE_DEVCTL_CE_REPORTING_EN)); 1375 1376 PCIE_CAP_PUT(16, bus_p, PCIE_DEVCTL, tmp16); 1377 PCIE_DBG_CAP(dip, bus_p, "DEVCTL", 16, PCIE_DEVCTL, reg16); 1378 } 1379 1380 /* Enable Root Port Baseline Error Receiving */ 1381 if (PCIE_IS_ROOT(bus_p) && 1382 (reg16 = PCIE_CAP_GET(16, bus_p, PCIE_ROOTCTL)) != 1383 PCI_CAP_EINVAL16) { 1384 1385 tmp16 = pcie_serr_disable_flag ? 1386 (pcie_root_ctrl_default & ~PCIE_ROOT_SYS_ERR) : 1387 pcie_root_ctrl_default; 1388 PCIE_CAP_PUT(16, bus_p, PCIE_ROOTCTL, tmp16); 1389 PCIE_DBG_CAP(dip, bus_p, "ROOT DEVCTL", 16, PCIE_ROOTCTL, 1390 reg16); 1391 } 1392 1393 /* 1394 * Enable PCI-Express Advanced Error Handling if Exists 1395 */ 1396 if (!PCIE_HAS_AER(bus_p)) 1397 return; 1398 1399 /* Set Uncorrectable Severity */ 1400 if ((reg32 = PCIE_AER_GET(32, bus_p, PCIE_AER_UCE_SERV)) != 1401 PCI_CAP_EINVAL32) { 1402 tmp32 = pcie_aer_uce_severity; 1403 1404 PCIE_AER_PUT(32, bus_p, PCIE_AER_UCE_SERV, tmp32); 1405 PCIE_DBG_AER(dip, bus_p, "AER UCE SEV", 32, PCIE_AER_UCE_SERV, 1406 reg32); 1407 } 1408 1409 /* Enable Uncorrectable errors */ 1410 if ((reg32 = PCIE_AER_GET(32, bus_p, PCIE_AER_UCE_MASK)) != 1411 PCI_CAP_EINVAL32) { 1412 tmp32 = pcie_aer_uce_mask; 1413 1414 PCIE_AER_PUT(32, bus_p, PCIE_AER_UCE_MASK, tmp32); 1415 PCIE_DBG_AER(dip, bus_p, "AER UCE MASK", 32, PCIE_AER_UCE_MASK, 1416 reg32); 1417 } 1418 1419 /* Enable ECRC generation and checking */ 1420 if ((reg32 = PCIE_AER_GET(32, bus_p, PCIE_AER_CTL)) != 1421 PCI_CAP_EINVAL32) { 1422 tmp32 = reg32 | pcie_ecrc_value; 1423 PCIE_AER_PUT(32, bus_p, PCIE_AER_CTL, tmp32); 1424 PCIE_DBG_AER(dip, bus_p, "AER CTL", 32, PCIE_AER_CTL, reg32); 1425 } 1426 1427 /* Enable Secondary Uncorrectable errors if this is a bridge */ 1428 if (!PCIE_IS_PCIE_BDG(bus_p)) 1429 goto root; 1430 1431 /* Set Uncorrectable Severity */ 1432 if ((reg32 = PCIE_AER_GET(32, bus_p, PCIE_AER_SUCE_SERV)) != 1433 PCI_CAP_EINVAL32) { 1434 tmp32 = pcie_aer_suce_severity; 1435 1436 PCIE_AER_PUT(32, bus_p, PCIE_AER_SUCE_SERV, tmp32); 1437 PCIE_DBG_AER(dip, bus_p, "AER SUCE SEV", 32, PCIE_AER_SUCE_SERV, 1438 reg32); 1439 } 1440 1441 if ((reg32 = PCIE_AER_GET(32, bus_p, PCIE_AER_SUCE_MASK)) != 1442 PCI_CAP_EINVAL32) { 1443 PCIE_AER_PUT(32, bus_p, PCIE_AER_SUCE_MASK, pcie_aer_suce_mask); 1444 PCIE_DBG_AER(dip, bus_p, "AER SUCE MASK", 32, 1445 PCIE_AER_SUCE_MASK, reg32); 1446 } 1447 1448 root: 1449 /* 1450 * Enable Root Control this is a Root device 1451 */ 1452 if (!PCIE_IS_ROOT(bus_p)) 1453 return; 1454 1455 if ((reg16 = PCIE_AER_GET(16, bus_p, PCIE_AER_RE_CMD)) != 1456 PCI_CAP_EINVAL16) { 1457 PCIE_AER_PUT(16, bus_p, PCIE_AER_RE_CMD, 1458 pcie_root_error_cmd_default); 1459 PCIE_DBG_AER(dip, bus_p, "AER Root Err Cmd", 16, 1460 PCIE_AER_RE_CMD, reg16); 1461 } 1462 } 1463 1464 /* 1465 * This function is used for enabling CE reporting and setting the AER CE mask. 1466 * When called from outside the pcie module it should always be preceded by 1467 * a call to pcie_enable_errors. 1468 */ 1469 int 1470 pcie_enable_ce(dev_info_t *dip) 1471 { 1472 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 1473 uint16_t device_sts, device_ctl; 1474 uint32_t tmp_pcie_aer_ce_mask; 1475 1476 if (!PCIE_IS_PCIE(bus_p)) 1477 return (DDI_SUCCESS); 1478 1479 /* 1480 * The "pcie_ce_mask" property is used to control both the CE reporting 1481 * enable field in the device control register and the AER CE mask. We 1482 * leave CE reporting disabled if pcie_ce_mask is set to -1. 1483 */ 1484 1485 tmp_pcie_aer_ce_mask = (uint32_t)ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1486 DDI_PROP_DONTPASS, "pcie_ce_mask", pcie_aer_ce_mask); 1487 1488 if (tmp_pcie_aer_ce_mask == (uint32_t)-1) { 1489 /* 1490 * Nothing to do since CE reporting has already been disabled. 1491 */ 1492 return (DDI_SUCCESS); 1493 } 1494 1495 if (PCIE_HAS_AER(bus_p)) { 1496 /* Enable AER CE */ 1497 PCIE_AER_PUT(32, bus_p, PCIE_AER_CE_MASK, tmp_pcie_aer_ce_mask); 1498 PCIE_DBG_AER(dip, bus_p, "AER CE MASK", 32, PCIE_AER_CE_MASK, 1499 0); 1500 1501 /* Clear any pending AER CE errors */ 1502 PCIE_AER_PUT(32, bus_p, PCIE_AER_CE_STS, -1); 1503 } 1504 1505 /* clear any pending CE errors */ 1506 if ((device_sts = PCIE_CAP_GET(16, bus_p, PCIE_DEVSTS)) != 1507 PCI_CAP_EINVAL16) 1508 PCIE_CAP_PUT(16, bus_p, PCIE_DEVSTS, 1509 device_sts & (~PCIE_DEVSTS_CE_DETECTED)); 1510 1511 /* Enable CE reporting */ 1512 device_ctl = PCIE_CAP_GET(16, bus_p, PCIE_DEVCTL); 1513 PCIE_CAP_PUT(16, bus_p, PCIE_DEVCTL, 1514 (device_ctl & (~PCIE_DEVCTL_ERR_MASK)) | pcie_base_err_default); 1515 PCIE_DBG_CAP(dip, bus_p, "DEVCTL", 16, PCIE_DEVCTL, device_ctl); 1516 1517 return (DDI_SUCCESS); 1518 } 1519 1520 /* ARGSUSED */ 1521 void 1522 pcie_disable_errors(dev_info_t *dip) 1523 { 1524 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 1525 uint16_t device_ctl; 1526 uint32_t aer_reg; 1527 1528 if (!PCIE_IS_PCIE(bus_p)) 1529 return; 1530 1531 /* 1532 * Disable PCI-Express Baseline Error Handling 1533 */ 1534 device_ctl = PCIE_CAP_GET(16, bus_p, PCIE_DEVCTL); 1535 device_ctl &= ~PCIE_DEVCTL_ERR_MASK; 1536 PCIE_CAP_PUT(16, bus_p, PCIE_DEVCTL, device_ctl); 1537 1538 /* 1539 * Disable PCI-Express Advanced Error Handling if Exists 1540 */ 1541 if (!PCIE_HAS_AER(bus_p)) 1542 goto root; 1543 1544 /* Disable Uncorrectable errors */ 1545 PCIE_AER_PUT(32, bus_p, PCIE_AER_UCE_MASK, PCIE_AER_UCE_BITS); 1546 1547 /* Disable Correctable errors */ 1548 PCIE_AER_PUT(32, bus_p, PCIE_AER_CE_MASK, PCIE_AER_CE_BITS); 1549 1550 /* Disable ECRC generation and checking */ 1551 if ((aer_reg = PCIE_AER_GET(32, bus_p, PCIE_AER_CTL)) != 1552 PCI_CAP_EINVAL32) { 1553 aer_reg &= ~(PCIE_AER_CTL_ECRC_GEN_ENA | 1554 PCIE_AER_CTL_ECRC_CHECK_ENA); 1555 1556 PCIE_AER_PUT(32, bus_p, PCIE_AER_CTL, aer_reg); 1557 } 1558 /* 1559 * Disable Secondary Uncorrectable errors if this is a bridge 1560 */ 1561 if (!PCIE_IS_PCIE_BDG(bus_p)) 1562 goto root; 1563 1564 PCIE_AER_PUT(32, bus_p, PCIE_AER_SUCE_MASK, PCIE_AER_SUCE_BITS); 1565 1566 root: 1567 /* 1568 * disable Root Control this is a Root device 1569 */ 1570 if (!PCIE_IS_ROOT(bus_p)) 1571 return; 1572 1573 if (!pcie_serr_disable_flag) { 1574 device_ctl = PCIE_CAP_GET(16, bus_p, PCIE_ROOTCTL); 1575 device_ctl &= ~PCIE_ROOT_SYS_ERR; 1576 PCIE_CAP_PUT(16, bus_p, PCIE_ROOTCTL, device_ctl); 1577 } 1578 1579 if (!PCIE_HAS_AER(bus_p)) 1580 return; 1581 1582 if ((device_ctl = PCIE_CAP_GET(16, bus_p, PCIE_AER_RE_CMD)) != 1583 PCI_CAP_EINVAL16) { 1584 device_ctl &= ~pcie_root_error_cmd_default; 1585 PCIE_CAP_PUT(16, bus_p, PCIE_AER_RE_CMD, device_ctl); 1586 } 1587 } 1588 1589 /* 1590 * Extract bdf from "reg" property. 1591 */ 1592 int 1593 pcie_get_bdf_from_dip(dev_info_t *dip, pcie_req_id_t *bdf) 1594 { 1595 pci_regspec_t *regspec; 1596 int reglen; 1597 1598 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1599 "reg", (int **)®spec, (uint_t *)®len) != DDI_SUCCESS) 1600 return (DDI_FAILURE); 1601 1602 if (reglen < (sizeof (pci_regspec_t) / sizeof (int))) { 1603 ddi_prop_free(regspec); 1604 return (DDI_FAILURE); 1605 } 1606 1607 /* Get phys_hi from first element. All have same bdf. */ 1608 *bdf = (regspec->pci_phys_hi & (PCI_REG_BDFR_M ^ PCI_REG_REG_M)) >> 8; 1609 1610 ddi_prop_free(regspec); 1611 return (DDI_SUCCESS); 1612 } 1613 1614 dev_info_t * 1615 pcie_get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip) 1616 { 1617 dev_info_t *cdip = rdip; 1618 1619 for (; ddi_get_parent(cdip) != dip; cdip = ddi_get_parent(cdip)) 1620 ; 1621 1622 return (cdip); 1623 } 1624 1625 uint32_t 1626 pcie_get_bdf_for_dma_xfer(dev_info_t *dip, dev_info_t *rdip) 1627 { 1628 dev_info_t *cdip; 1629 1630 /* 1631 * As part of the probing, the PCI fcode interpreter may setup a DMA 1632 * request if a given card has a fcode on it using dip and rdip of the 1633 * hotplug connector i.e, dip and rdip of px/pcieb driver. In this 1634 * case, return a invalid value for the bdf since we cannot get to the 1635 * bdf value of the actual device which will be initiating this DMA. 1636 */ 1637 if (rdip == dip) 1638 return (PCIE_INVALID_BDF); 1639 1640 cdip = pcie_get_my_childs_dip(dip, rdip); 1641 1642 /* 1643 * For a given rdip, return the bdf value of dip's (px or pcieb) 1644 * immediate child or secondary bus-id if dip is a PCIe2PCI bridge. 1645 * 1646 * XXX - For now, return a invalid bdf value for all PCI and PCI-X 1647 * devices since this needs more work. 1648 */ 1649 return (PCI_GET_PCIE2PCI_SECBUS(cdip) ? 1650 PCIE_INVALID_BDF : PCI_GET_BDF(cdip)); 1651 } 1652 1653 uint32_t 1654 pcie_get_aer_uce_mask() { 1655 return (pcie_aer_uce_mask); 1656 } 1657 uint32_t 1658 pcie_get_aer_ce_mask() { 1659 return (pcie_aer_ce_mask); 1660 } 1661 uint32_t 1662 pcie_get_aer_suce_mask() { 1663 return (pcie_aer_suce_mask); 1664 } 1665 uint32_t 1666 pcie_get_serr_mask() { 1667 return (pcie_serr_disable_flag); 1668 } 1669 1670 void 1671 pcie_set_aer_uce_mask(uint32_t mask) { 1672 pcie_aer_uce_mask = mask; 1673 if (mask & PCIE_AER_UCE_UR) 1674 pcie_base_err_default &= ~PCIE_DEVCTL_UR_REPORTING_EN; 1675 else 1676 pcie_base_err_default |= PCIE_DEVCTL_UR_REPORTING_EN; 1677 1678 if (mask & PCIE_AER_UCE_ECRC) 1679 pcie_ecrc_value = 0; 1680 } 1681 1682 void 1683 pcie_set_aer_ce_mask(uint32_t mask) { 1684 pcie_aer_ce_mask = mask; 1685 } 1686 void 1687 pcie_set_aer_suce_mask(uint32_t mask) { 1688 pcie_aer_suce_mask = mask; 1689 } 1690 void 1691 pcie_set_serr_mask(uint32_t mask) { 1692 pcie_serr_disable_flag = mask; 1693 } 1694 1695 /* 1696 * Is the rdip a child of dip. Used for checking certain CTLOPS from bubbling 1697 * up erronously. Ex. ISA ctlops to a PCI-PCI Bridge. 1698 */ 1699 boolean_t 1700 pcie_is_child(dev_info_t *dip, dev_info_t *rdip) 1701 { 1702 dev_info_t *cdip = ddi_get_child(dip); 1703 for (; cdip; cdip = ddi_get_next_sibling(cdip)) 1704 if (cdip == rdip) 1705 break; 1706 return (cdip != NULL); 1707 } 1708 1709 boolean_t 1710 pcie_is_link_disabled(dev_info_t *dip) 1711 { 1712 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 1713 1714 if (PCIE_IS_PCIE(bus_p)) { 1715 if (PCIE_CAP_GET(16, bus_p, PCIE_LINKCTL) & 1716 PCIE_LINKCTL_LINK_DISABLE) 1717 return (B_TRUE); 1718 } 1719 return (B_FALSE); 1720 } 1721 1722 /* 1723 * Initialize the MPS for a root port. 1724 * 1725 * dip - dip of root port device. 1726 */ 1727 void 1728 pcie_init_root_port_mps(dev_info_t *dip) 1729 { 1730 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 1731 int rp_cap, max_supported = pcie_max_mps; 1732 1733 (void) pcie_get_fabric_mps(ddi_get_parent(dip), 1734 ddi_get_child(dip), &max_supported); 1735 1736 rp_cap = PCI_CAP_GET16(bus_p->bus_cfg_hdl, NULL, 1737 bus_p->bus_pcie_off, PCIE_DEVCAP) & 1738 PCIE_DEVCAP_MAX_PAYLOAD_MASK; 1739 1740 if (rp_cap < max_supported) 1741 max_supported = rp_cap; 1742 1743 bus_p->bus_mps = max_supported; 1744 (void) pcie_initchild_mps(dip); 1745 } 1746 1747 /* 1748 * Initialize the Maximum Payload Size of a device. 1749 * 1750 * cdip - dip of device. 1751 * 1752 * returns - DDI_SUCCESS or DDI_FAILURE 1753 */ 1754 int 1755 pcie_initchild_mps(dev_info_t *cdip) 1756 { 1757 pcie_bus_t *bus_p; 1758 dev_info_t *pdip = ddi_get_parent(cdip); 1759 uint8_t dev_type; 1760 1761 bus_p = PCIE_DIP2BUS(cdip); 1762 if (bus_p == NULL) { 1763 PCIE_DBG("%s: BUS not found.\n", 1764 ddi_driver_name(cdip)); 1765 return (DDI_FAILURE); 1766 } 1767 1768 dev_type = bus_p->bus_dev_type; 1769 1770 /* 1771 * For ARI Devices, only function zero's MPS needs to be set. 1772 */ 1773 if ((dev_type == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) && 1774 (pcie_ari_is_enabled(pdip) == PCIE_ARI_FORW_ENABLED)) { 1775 pcie_req_id_t child_bdf; 1776 1777 if (pcie_get_bdf_from_dip(cdip, &child_bdf) == DDI_FAILURE) 1778 return (DDI_FAILURE); 1779 if ((child_bdf & PCIE_REQ_ID_ARI_FUNC_MASK) != 0) 1780 return (DDI_SUCCESS); 1781 } 1782 1783 if (PCIE_IS_PCIE(bus_p)) { 1784 int suggested_mrrs, fabric_mps; 1785 uint16_t device_mps, device_mps_cap, device_mrrs, dev_ctrl; 1786 1787 if ((fabric_mps = (PCIE_IS_RP(bus_p) ? bus_p : 1788 PCIE_DIP2BUS(pdip))->bus_mps) < 0) 1789 return (DDI_SUCCESS); 1790 1791 dev_ctrl = PCIE_CAP_GET(16, bus_p, PCIE_DEVCTL); 1792 1793 device_mps_cap = PCIE_CAP_GET(16, bus_p, PCIE_DEVCAP) & 1794 PCIE_DEVCAP_MAX_PAYLOAD_MASK; 1795 1796 device_mrrs = (dev_ctrl & PCIE_DEVCTL_MAX_READ_REQ_MASK) >> 1797 PCIE_DEVCTL_MAX_READ_REQ_SHIFT; 1798 1799 if (device_mps_cap < fabric_mps) 1800 device_mrrs = device_mps = device_mps_cap; 1801 else 1802 device_mps = (uint16_t)fabric_mps; 1803 1804 suggested_mrrs = (uint32_t)ddi_prop_get_int(DDI_DEV_T_ANY, 1805 cdip, DDI_PROP_DONTPASS, "suggested-mrrs", device_mrrs); 1806 1807 if ((device_mps == fabric_mps) || 1808 (suggested_mrrs < device_mrrs)) 1809 device_mrrs = (uint16_t)suggested_mrrs; 1810 1811 /* 1812 * Replace MPS and MRRS settings. 1813 */ 1814 dev_ctrl &= ~(PCIE_DEVCTL_MAX_READ_REQ_MASK | 1815 PCIE_DEVCTL_MAX_PAYLOAD_MASK); 1816 1817 dev_ctrl |= ((device_mrrs << PCIE_DEVCTL_MAX_READ_REQ_SHIFT) | 1818 device_mps << PCIE_DEVCTL_MAX_PAYLOAD_SHIFT); 1819 1820 PCIE_CAP_PUT(16, bus_p, PCIE_DEVCTL, dev_ctrl); 1821 1822 bus_p->bus_mps = device_mps; 1823 } 1824 1825 return (DDI_SUCCESS); 1826 } 1827 1828 /* 1829 * Scans a device tree/branch for a maximum payload size capabilities. 1830 * 1831 * rc_dip - dip of Root Complex. 1832 * dip - dip of device where scan will begin. 1833 * max_supported (IN) - maximum allowable MPS. 1834 * max_supported (OUT) - maximum payload size capability of fabric. 1835 */ 1836 void 1837 pcie_get_fabric_mps(dev_info_t *rc_dip, dev_info_t *dip, int *max_supported) 1838 { 1839 if (dip == NULL) 1840 return; 1841 1842 /* 1843 * Perform a fabric scan to obtain Maximum Payload Capabilities 1844 */ 1845 (void) pcie_scan_mps(rc_dip, dip, max_supported); 1846 1847 PCIE_DBG("MPS: Highest Common MPS= %x\n", max_supported); 1848 } 1849 1850 /* 1851 * Scans fabric and determines Maximum Payload Size based on 1852 * highest common denominator alogorithm 1853 */ 1854 static void 1855 pcie_scan_mps(dev_info_t *rc_dip, dev_info_t *dip, int *max_supported) 1856 { 1857 int circular_count; 1858 pcie_max_supported_t max_pay_load_supported; 1859 1860 max_pay_load_supported.dip = rc_dip; 1861 max_pay_load_supported.highest_common_mps = *max_supported; 1862 1863 ndi_devi_enter(ddi_get_parent(dip), &circular_count); 1864 ddi_walk_devs(dip, pcie_get_max_supported, 1865 (void *)&max_pay_load_supported); 1866 ndi_devi_exit(ddi_get_parent(dip), circular_count); 1867 1868 *max_supported = max_pay_load_supported.highest_common_mps; 1869 } 1870 1871 /* 1872 * Called as part of the Maximum Payload Size scan. 1873 */ 1874 static int 1875 pcie_get_max_supported(dev_info_t *dip, void *arg) 1876 { 1877 uint32_t max_supported; 1878 uint16_t cap_ptr; 1879 pcie_max_supported_t *current = (pcie_max_supported_t *)arg; 1880 pci_regspec_t *reg; 1881 int rlen; 1882 caddr_t virt; 1883 ddi_acc_handle_t config_handle; 1884 1885 if (ddi_get_child(current->dip) == NULL) { 1886 goto fail1; 1887 } 1888 1889 if (pcie_dev(dip) == DDI_FAILURE) { 1890 PCIE_DBG("MPS: pcie_get_max_supported: %s: " 1891 "Not a PCIe dev\n", ddi_driver_name(dip)); 1892 goto fail1; 1893 } 1894 1895 /* 1896 * If the suggested-mrrs property exists, then don't include this 1897 * device in the MPS capabilities scan. 1898 */ 1899 if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1900 "suggested-mrrs") != 0) 1901 goto fail1; 1902 1903 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "reg", 1904 (caddr_t)®, &rlen) != DDI_PROP_SUCCESS) { 1905 PCIE_DBG("MPS: pcie_get_max_supported: %s: " 1906 "Can not read reg\n", ddi_driver_name(dip)); 1907 goto fail1; 1908 } 1909 1910 if (pcie_map_phys(ddi_get_child(current->dip), reg, &virt, 1911 &config_handle) != DDI_SUCCESS) { 1912 PCIE_DBG("MPS: pcie_get_max_supported: %s: pcie_map_phys " 1913 "failed\n", ddi_driver_name(dip)); 1914 goto fail2; 1915 } 1916 1917 if ((PCI_CAP_LOCATE(config_handle, PCI_CAP_ID_PCI_E, &cap_ptr)) == 1918 DDI_FAILURE) { 1919 goto fail3; 1920 } 1921 1922 max_supported = PCI_CAP_GET16(config_handle, NULL, cap_ptr, 1923 PCIE_DEVCAP) & PCIE_DEVCAP_MAX_PAYLOAD_MASK; 1924 1925 PCIE_DBG("PCIE MPS: %s: MPS Capabilities %x\n", ddi_driver_name(dip), 1926 max_supported); 1927 1928 if (max_supported < current->highest_common_mps) 1929 current->highest_common_mps = max_supported; 1930 1931 fail3: 1932 pcie_unmap_phys(&config_handle, reg); 1933 fail2: 1934 kmem_free(reg, rlen); 1935 fail1: 1936 return (DDI_WALK_CONTINUE); 1937 } 1938 1939 /* 1940 * Determines if there are any root ports attached to a root complex. 1941 * 1942 * dip - dip of root complex 1943 * 1944 * Returns - DDI_SUCCESS if there is at least one root port otherwise 1945 * DDI_FAILURE. 1946 */ 1947 int 1948 pcie_root_port(dev_info_t *dip) 1949 { 1950 int port_type; 1951 uint16_t cap_ptr; 1952 ddi_acc_handle_t config_handle; 1953 dev_info_t *cdip = ddi_get_child(dip); 1954 1955 /* 1956 * Determine if any of the children of the passed in dip 1957 * are root ports. 1958 */ 1959 for (; cdip; cdip = ddi_get_next_sibling(cdip)) { 1960 1961 if (pci_config_setup(cdip, &config_handle) != DDI_SUCCESS) 1962 continue; 1963 1964 if ((PCI_CAP_LOCATE(config_handle, PCI_CAP_ID_PCI_E, 1965 &cap_ptr)) == DDI_FAILURE) { 1966 pci_config_teardown(&config_handle); 1967 continue; 1968 } 1969 1970 port_type = PCI_CAP_GET16(config_handle, NULL, cap_ptr, 1971 PCIE_PCIECAP) & PCIE_PCIECAP_DEV_TYPE_MASK; 1972 1973 pci_config_teardown(&config_handle); 1974 1975 if (port_type == PCIE_PCIECAP_DEV_TYPE_ROOT) 1976 return (DDI_SUCCESS); 1977 } 1978 1979 /* No root ports were found */ 1980 1981 return (DDI_FAILURE); 1982 } 1983 1984 /* 1985 * Function that determines if a device a PCIe device. 1986 * 1987 * dip - dip of device. 1988 * 1989 * returns - DDI_SUCCESS if device is a PCIe device, otherwise DDI_FAILURE. 1990 */ 1991 int 1992 pcie_dev(dev_info_t *dip) 1993 { 1994 /* get parent device's device_type property */ 1995 char *device_type; 1996 int rc = DDI_FAILURE; 1997 dev_info_t *pdip = ddi_get_parent(dip); 1998 1999 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pdip, 2000 DDI_PROP_DONTPASS, "device_type", &device_type) 2001 != DDI_PROP_SUCCESS) { 2002 return (DDI_FAILURE); 2003 } 2004 2005 if (strcmp(device_type, "pciex") == 0) 2006 rc = DDI_SUCCESS; 2007 else 2008 rc = DDI_FAILURE; 2009 2010 ddi_prop_free(device_type); 2011 return (rc); 2012 } 2013 2014 /* 2015 * Function to map in a device's memory space. 2016 */ 2017 static int 2018 pcie_map_phys(dev_info_t *dip, pci_regspec_t *phys_spec, 2019 caddr_t *addrp, ddi_acc_handle_t *handlep) 2020 { 2021 ddi_map_req_t mr; 2022 ddi_acc_hdl_t *hp; 2023 int result; 2024 ddi_device_acc_attr_t attr; 2025 2026 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 2027 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 2028 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 2029 attr.devacc_attr_access = DDI_CAUTIOUS_ACC; 2030 2031 *handlep = impl_acc_hdl_alloc(KM_SLEEP, NULL); 2032 hp = impl_acc_hdl_get(*handlep); 2033 hp->ah_vers = VERS_ACCHDL; 2034 hp->ah_dip = dip; 2035 hp->ah_rnumber = 0; 2036 hp->ah_offset = 0; 2037 hp->ah_len = 0; 2038 hp->ah_acc = attr; 2039 2040 mr.map_op = DDI_MO_MAP_LOCKED; 2041 mr.map_type = DDI_MT_REGSPEC; 2042 mr.map_obj.rp = (struct regspec *)phys_spec; 2043 mr.map_prot = PROT_READ | PROT_WRITE; 2044 mr.map_flags = DDI_MF_KERNEL_MAPPING; 2045 mr.map_handlep = hp; 2046 mr.map_vers = DDI_MAP_VERSION; 2047 2048 result = ddi_map(dip, &mr, 0, 0, addrp); 2049 2050 if (result != DDI_SUCCESS) { 2051 impl_acc_hdl_free(*handlep); 2052 *handlep = (ddi_acc_handle_t)NULL; 2053 } else { 2054 hp->ah_addr = *addrp; 2055 } 2056 2057 return (result); 2058 } 2059 2060 /* 2061 * Map out memory that was mapped in with pcie_map_phys(); 2062 */ 2063 static void 2064 pcie_unmap_phys(ddi_acc_handle_t *handlep, pci_regspec_t *ph) 2065 { 2066 ddi_map_req_t mr; 2067 ddi_acc_hdl_t *hp; 2068 2069 hp = impl_acc_hdl_get(*handlep); 2070 ASSERT(hp); 2071 2072 mr.map_op = DDI_MO_UNMAP; 2073 mr.map_type = DDI_MT_REGSPEC; 2074 mr.map_obj.rp = (struct regspec *)ph; 2075 mr.map_prot = PROT_READ | PROT_WRITE; 2076 mr.map_flags = DDI_MF_KERNEL_MAPPING; 2077 mr.map_handlep = hp; 2078 mr.map_vers = DDI_MAP_VERSION; 2079 2080 (void) ddi_map(hp->ah_dip, &mr, hp->ah_offset, 2081 hp->ah_len, &hp->ah_addr); 2082 2083 impl_acc_hdl_free(*handlep); 2084 *handlep = (ddi_acc_handle_t)NULL; 2085 } 2086 2087 void 2088 pcie_set_rber_fatal(dev_info_t *dip, boolean_t val) 2089 { 2090 pcie_bus_t *bus_p = PCIE_DIP2UPBUS(dip); 2091 bus_p->bus_pfd->pe_rber_fatal = val; 2092 } 2093 2094 /* 2095 * Return parent Root Port's pe_rber_fatal value. 2096 */ 2097 boolean_t 2098 pcie_get_rber_fatal(dev_info_t *dip) 2099 { 2100 pcie_bus_t *bus_p = PCIE_DIP2UPBUS(dip); 2101 pcie_bus_t *rp_bus_p = PCIE_DIP2UPBUS(bus_p->bus_rp_dip); 2102 return (rp_bus_p->bus_pfd->pe_rber_fatal); 2103 } 2104 2105 int 2106 pcie_ari_supported(dev_info_t *dip) 2107 { 2108 uint32_t devcap2; 2109 uint16_t pciecap; 2110 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 2111 uint8_t dev_type; 2112 2113 PCIE_DBG("pcie_ari_supported: dip=%p\n", dip); 2114 2115 if (bus_p == NULL) 2116 return (PCIE_ARI_FORW_NOT_SUPPORTED); 2117 2118 dev_type = bus_p->bus_dev_type; 2119 2120 if ((dev_type != PCIE_PCIECAP_DEV_TYPE_DOWN) && 2121 (dev_type != PCIE_PCIECAP_DEV_TYPE_ROOT)) 2122 return (PCIE_ARI_FORW_NOT_SUPPORTED); 2123 2124 if (pcie_disable_ari) { 2125 PCIE_DBG("pcie_ari_supported: dip=%p: ARI Disabled\n", dip); 2126 return (PCIE_ARI_FORW_NOT_SUPPORTED); 2127 } 2128 2129 pciecap = PCIE_CAP_GET(16, bus_p, PCIE_PCIECAP); 2130 2131 if ((pciecap & PCIE_PCIECAP_VER_MASK) < PCIE_PCIECAP_VER_2_0) { 2132 PCIE_DBG("pcie_ari_supported: dip=%p: Not 2.0\n", dip); 2133 return (PCIE_ARI_FORW_NOT_SUPPORTED); 2134 } 2135 2136 devcap2 = PCIE_CAP_GET(32, bus_p, PCIE_DEVCAP2); 2137 2138 PCIE_DBG("pcie_ari_supported: dip=%p: DevCap2=0x%x\n", 2139 dip, devcap2); 2140 2141 if (devcap2 & PCIE_DEVCAP2_ARI_FORWARD) { 2142 PCIE_DBG("pcie_ari_supported: " 2143 "dip=%p: ARI Forwarding is supported\n", dip); 2144 return (PCIE_ARI_FORW_SUPPORTED); 2145 } 2146 return (PCIE_ARI_FORW_NOT_SUPPORTED); 2147 } 2148 2149 int 2150 pcie_ari_enable(dev_info_t *dip) 2151 { 2152 uint16_t devctl2; 2153 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 2154 2155 PCIE_DBG("pcie_ari_enable: dip=%p\n", dip); 2156 2157 if (pcie_ari_supported(dip) == PCIE_ARI_FORW_NOT_SUPPORTED) 2158 return (DDI_FAILURE); 2159 2160 devctl2 = PCIE_CAP_GET(16, bus_p, PCIE_DEVCTL2); 2161 devctl2 |= PCIE_DEVCTL2_ARI_FORWARD_EN; 2162 PCIE_CAP_PUT(16, bus_p, PCIE_DEVCTL2, devctl2); 2163 2164 PCIE_DBG("pcie_ari_enable: dip=%p: writing 0x%x to DevCtl2\n", 2165 dip, devctl2); 2166 2167 return (DDI_SUCCESS); 2168 } 2169 2170 int 2171 pcie_ari_disable(dev_info_t *dip) 2172 { 2173 uint16_t devctl2; 2174 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 2175 2176 PCIE_DBG("pcie_ari_disable: dip=%p\n", dip); 2177 2178 if (pcie_ari_supported(dip) == PCIE_ARI_FORW_NOT_SUPPORTED) 2179 return (DDI_FAILURE); 2180 2181 devctl2 = PCIE_CAP_GET(16, bus_p, PCIE_DEVCTL2); 2182 devctl2 &= ~PCIE_DEVCTL2_ARI_FORWARD_EN; 2183 PCIE_CAP_PUT(16, bus_p, PCIE_DEVCTL2, devctl2); 2184 2185 PCIE_DBG("pcie_ari_disable: dip=%p: writing 0x%x to DevCtl2\n", 2186 dip, devctl2); 2187 2188 return (DDI_SUCCESS); 2189 } 2190 2191 int 2192 pcie_ari_is_enabled(dev_info_t *dip) 2193 { 2194 uint16_t devctl2; 2195 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 2196 2197 PCIE_DBG("pcie_ari_is_enabled: dip=%p\n", dip); 2198 2199 if (pcie_ari_supported(dip) == PCIE_ARI_FORW_NOT_SUPPORTED) 2200 return (PCIE_ARI_FORW_DISABLED); 2201 2202 devctl2 = PCIE_CAP_GET(32, bus_p, PCIE_DEVCTL2); 2203 2204 PCIE_DBG("pcie_ari_is_enabled: dip=%p: DevCtl2=0x%x\n", 2205 dip, devctl2); 2206 2207 if (devctl2 & PCIE_DEVCTL2_ARI_FORWARD_EN) { 2208 PCIE_DBG("pcie_ari_is_enabled: " 2209 "dip=%p: ARI Forwarding is enabled\n", dip); 2210 return (PCIE_ARI_FORW_ENABLED); 2211 } 2212 2213 return (PCIE_ARI_FORW_DISABLED); 2214 } 2215 2216 int 2217 pcie_ari_device(dev_info_t *dip) 2218 { 2219 ddi_acc_handle_t handle; 2220 uint16_t cap_ptr; 2221 2222 PCIE_DBG("pcie_ari_device: dip=%p\n", dip); 2223 2224 /* 2225 * XXX - This function may be called before the bus_p structure 2226 * has been populated. This code can be changed to remove 2227 * pci_config_setup()/pci_config_teardown() when the RFE 2228 * to populate the bus_p structures early in boot is putback. 2229 */ 2230 2231 /* First make sure it is a PCIe device */ 2232 2233 if (pci_config_setup(dip, &handle) != DDI_SUCCESS) 2234 return (PCIE_NOT_ARI_DEVICE); 2235 2236 if ((PCI_CAP_LOCATE(handle, PCI_CAP_ID_PCI_E, &cap_ptr)) 2237 != DDI_SUCCESS) { 2238 pci_config_teardown(&handle); 2239 return (PCIE_NOT_ARI_DEVICE); 2240 } 2241 2242 /* Locate the ARI Capability */ 2243 2244 if ((PCI_CAP_LOCATE(handle, PCI_CAP_XCFG_SPC(PCIE_EXT_CAP_ID_ARI), 2245 &cap_ptr)) == DDI_FAILURE) { 2246 pci_config_teardown(&handle); 2247 return (PCIE_NOT_ARI_DEVICE); 2248 } 2249 2250 /* ARI Capability was found so it must be a ARI device */ 2251 PCIE_DBG("pcie_ari_device: ARI Device dip=%p\n", dip); 2252 2253 pci_config_teardown(&handle); 2254 return (PCIE_ARI_DEVICE); 2255 } 2256 2257 int 2258 pcie_ari_get_next_function(dev_info_t *dip, int *func) 2259 { 2260 uint32_t val; 2261 uint16_t cap_ptr, next_function; 2262 ddi_acc_handle_t handle; 2263 2264 /* 2265 * XXX - This function may be called before the bus_p structure 2266 * has been populated. This code can be changed to remove 2267 * pci_config_setup()/pci_config_teardown() when the RFE 2268 * to populate the bus_p structures early in boot is putback. 2269 */ 2270 2271 if (pci_config_setup(dip, &handle) != DDI_SUCCESS) 2272 return (DDI_FAILURE); 2273 2274 if ((PCI_CAP_LOCATE(handle, 2275 PCI_CAP_XCFG_SPC(PCIE_EXT_CAP_ID_ARI), &cap_ptr)) == DDI_FAILURE) { 2276 pci_config_teardown(&handle); 2277 return (DDI_FAILURE); 2278 } 2279 2280 val = PCI_CAP_GET32(handle, NULL, cap_ptr, PCIE_ARI_CAP); 2281 2282 next_function = (val >> PCIE_ARI_CAP_NEXT_FUNC_SHIFT) & 2283 PCIE_ARI_CAP_NEXT_FUNC_MASK; 2284 2285 pci_config_teardown(&handle); 2286 2287 *func = next_function; 2288 2289 return (DDI_SUCCESS); 2290 } 2291 2292 dev_info_t * 2293 pcie_func_to_dip(dev_info_t *dip, pcie_req_id_t function) 2294 { 2295 pcie_req_id_t child_bdf; 2296 dev_info_t *cdip; 2297 2298 for (cdip = ddi_get_child(dip); cdip; 2299 cdip = ddi_get_next_sibling(cdip)) { 2300 2301 if (pcie_get_bdf_from_dip(cdip, &child_bdf) == DDI_FAILURE) 2302 return (NULL); 2303 2304 if ((child_bdf & PCIE_REQ_ID_ARI_FUNC_MASK) == function) 2305 return (cdip); 2306 } 2307 return (NULL); 2308 } 2309 2310 #ifdef DEBUG 2311 2312 static void 2313 pcie_print_bus(pcie_bus_t *bus_p) 2314 { 2315 pcie_dbg("\tbus_dip = 0x%p\n", bus_p->bus_dip); 2316 pcie_dbg("\tbus_fm_flags = 0x%x\n", bus_p->bus_fm_flags); 2317 2318 pcie_dbg("\tbus_bdf = 0x%x\n", bus_p->bus_bdf); 2319 pcie_dbg("\tbus_dev_ven_id = 0x%x\n", bus_p->bus_dev_ven_id); 2320 pcie_dbg("\tbus_rev_id = 0x%x\n", bus_p->bus_rev_id); 2321 pcie_dbg("\tbus_hdr_type = 0x%x\n", bus_p->bus_hdr_type); 2322 pcie_dbg("\tbus_dev_type = 0x%x\n", bus_p->bus_dev_type); 2323 pcie_dbg("\tbus_bdg_secbus = 0x%x\n", bus_p->bus_bdg_secbus); 2324 pcie_dbg("\tbus_pcie_off = 0x%x\n", bus_p->bus_pcie_off); 2325 pcie_dbg("\tbus_aer_off = 0x%x\n", bus_p->bus_aer_off); 2326 pcie_dbg("\tbus_pcix_off = 0x%x\n", bus_p->bus_pcix_off); 2327 pcie_dbg("\tbus_ecc_ver = 0x%x\n", bus_p->bus_ecc_ver); 2328 } 2329 2330 /* 2331 * For debugging purposes set pcie_dbg_print != 0 to see printf messages 2332 * during interrupt. 2333 * 2334 * When a proper solution is in place this code will disappear. 2335 * Potential solutions are: 2336 * o circular buffers 2337 * o taskq to print at lower pil 2338 */ 2339 int pcie_dbg_print = 0; 2340 void 2341 pcie_dbg(char *fmt, ...) 2342 { 2343 va_list ap; 2344 2345 if (!pcie_debug_flags) { 2346 return; 2347 } 2348 va_start(ap, fmt); 2349 if (servicing_interrupt()) { 2350 if (pcie_dbg_print) { 2351 prom_vprintf(fmt, ap); 2352 } 2353 } else { 2354 prom_vprintf(fmt, ap); 2355 } 2356 va_end(ap); 2357 } 2358 #endif /* DEBUG */ 2359 2360 #if defined(__i386) || defined(__amd64) 2361 static void 2362 pcie_check_io_mem_range(ddi_acc_handle_t cfg_hdl, boolean_t *empty_io_range, 2363 boolean_t *empty_mem_range) 2364 { 2365 uint8_t class, subclass; 2366 uint_t val; 2367 2368 class = pci_config_get8(cfg_hdl, PCI_CONF_BASCLASS); 2369 subclass = pci_config_get8(cfg_hdl, PCI_CONF_SUBCLASS); 2370 2371 if ((class == PCI_CLASS_BRIDGE) && (subclass == PCI_BRIDGE_PCI)) { 2372 val = (((uint_t)pci_config_get8(cfg_hdl, PCI_BCNF_IO_BASE_LOW) & 2373 PCI_BCNF_IO_MASK) << 8); 2374 /* 2375 * Assuming that a zero based io_range[0] implies an 2376 * invalid I/O range. Likewise for mem_range[0]. 2377 */ 2378 if (val == 0) 2379 *empty_io_range = B_TRUE; 2380 val = (((uint_t)pci_config_get16(cfg_hdl, PCI_BCNF_MEM_BASE) & 2381 PCI_BCNF_MEM_MASK) << 16); 2382 if (val == 0) 2383 *empty_mem_range = B_TRUE; 2384 } 2385 } 2386 2387 #endif /* defined(__i386) || defined(__amd64) */ 2388