1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/nxge/nxge_impl.h> 29 30 extern uint32_t nxge_reclaim_pending; 31 extern uint32_t nxge_bcopy_thresh; 32 extern uint32_t nxge_dvma_thresh; 33 extern uint32_t nxge_dma_stream_thresh; 34 extern uint32_t nxge_tx_minfree; 35 extern uint32_t nxge_tx_intr_thres; 36 extern uint32_t nxge_tx_max_gathers; 37 extern uint32_t nxge_tx_tiny_pack; 38 extern uint32_t nxge_tx_use_bcopy; 39 extern uint32_t nxge_tx_lb_policy; 40 extern uint32_t nxge_no_tx_lb; 41 extern nxge_tx_mode_t nxge_tx_scheme; 42 43 typedef struct _mac_tx_hint { 44 uint16_t sap; 45 uint16_t vid; 46 void *hash; 47 } mac_tx_hint_t, *p_mac_tx_hint_t; 48 49 int nxge_tx_lb_ring_1(p_mblk_t, uint32_t, p_mac_tx_hint_t); 50 51 int 52 nxge_start(p_nxge_t nxgep, p_tx_ring_t tx_ring_p, p_mblk_t mp) 53 { 54 int status = 0; 55 p_tx_desc_t tx_desc_ring_vp; 56 npi_handle_t npi_desc_handle; 57 nxge_os_dma_handle_t tx_desc_dma_handle; 58 p_tx_desc_t tx_desc_p; 59 p_tx_msg_t tx_msg_ring; 60 p_tx_msg_t tx_msg_p; 61 tx_desc_t tx_desc, *tmp_desc_p; 62 tx_desc_t sop_tx_desc, *sop_tx_desc_p; 63 p_tx_pkt_header_t hdrp; 64 p_tx_pkt_hdr_all_t pkthdrp; 65 uint8_t npads = 0; 66 uint64_t dma_ioaddr; 67 uint32_t dma_flags; 68 int last_bidx; 69 uint8_t *b_rptr; 70 caddr_t kaddr; 71 uint32_t nmblks; 72 uint32_t ngathers; 73 uint32_t clen; 74 int len; 75 uint32_t pkt_len, pack_len, min_len; 76 uint32_t bcopy_thresh; 77 int i, cur_index, sop_index; 78 uint16_t tail_index; 79 boolean_t tail_wrap = B_FALSE; 80 nxge_dma_common_t desc_area; 81 nxge_os_dma_handle_t dma_handle; 82 ddi_dma_cookie_t dma_cookie; 83 npi_handle_t npi_handle; 84 p_mblk_t nmp; 85 p_mblk_t t_mp; 86 uint32_t ncookies; 87 boolean_t good_packet; 88 boolean_t mark_mode = B_FALSE; 89 p_nxge_stats_t statsp; 90 p_nxge_tx_ring_stats_t tdc_stats; 91 t_uscalar_t start_offset = 0; 92 t_uscalar_t stuff_offset = 0; 93 t_uscalar_t end_offset = 0; 94 t_uscalar_t value = 0; 95 t_uscalar_t cksum_flags = 0; 96 boolean_t cksum_on = B_FALSE; 97 uint32_t boff = 0; 98 uint64_t tot_xfer_len = 0, tmp_len = 0; 99 boolean_t header_set = B_FALSE; 100 #ifdef NXGE_DEBUG 101 p_tx_desc_t tx_desc_ring_pp; 102 p_tx_desc_t tx_desc_pp; 103 tx_desc_t *save_desc_p; 104 int dump_len; 105 int sad_len; 106 uint64_t sad; 107 int xfer_len; 108 uint32_t msgsize; 109 #endif 110 111 NXGE_DEBUG_MSG((nxgep, TX_CTL, 112 "==> nxge_start: tx dma channel %d", tx_ring_p->tdc)); 113 NXGE_DEBUG_MSG((nxgep, TX_CTL, 114 "==> nxge_start: Starting tdc %d desc pending %d", 115 tx_ring_p->tdc, tx_ring_p->descs_pending)); 116 117 statsp = nxgep->statsp; 118 119 if (nxgep->statsp->port_stats.lb_mode == nxge_lb_normal) { 120 if (!statsp->mac_stats.link_up) { 121 freemsg(mp); 122 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start: " 123 "link not up or LB mode")); 124 goto nxge_start_fail1; 125 } 126 } 127 128 hcksum_retrieve(mp, NULL, NULL, &start_offset, 129 &stuff_offset, &end_offset, &value, &cksum_flags); 130 if (!NXGE_IS_VLAN_PACKET(mp->b_rptr)) { 131 start_offset += sizeof (ether_header_t); 132 stuff_offset += sizeof (ether_header_t); 133 } else { 134 start_offset += sizeof (struct ether_vlan_header); 135 stuff_offset += sizeof (struct ether_vlan_header); 136 } 137 138 if (cksum_flags & HCK_PARTIALCKSUM) { 139 NXGE_DEBUG_MSG((nxgep, TX_CTL, 140 "==> nxge_start: cksum_flags 0x%x (partial checksum) ", 141 cksum_flags)); 142 cksum_on = B_TRUE; 143 } 144 145 #ifdef NXGE_DEBUG 146 if (tx_ring_p->descs_pending) { 147 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start: " 148 "desc pending %d ", tx_ring_p->descs_pending)); 149 } 150 151 dump_len = (int)(MBLKL(mp)); 152 dump_len = (dump_len > 128) ? 128: dump_len; 153 154 NXGE_DEBUG_MSG((nxgep, TX_CTL, 155 "==> nxge_start: tdc %d: dumping ...: b_rptr $%p " 156 "(Before header reserve: ORIGINAL LEN %d)", 157 tx_ring_p->tdc, 158 mp->b_rptr, 159 dump_len)); 160 161 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start: dump packets " 162 "(IP ORIGINAL b_rptr $%p): %s", mp->b_rptr, 163 nxge_dump_packet((char *)mp->b_rptr, dump_len))); 164 #endif 165 166 MUTEX_ENTER(&tx_ring_p->lock); 167 tdc_stats = tx_ring_p->tdc_stats; 168 mark_mode = (tx_ring_p->descs_pending && 169 ((tx_ring_p->tx_ring_size - tx_ring_p->descs_pending) 170 < nxge_tx_minfree)); 171 172 NXGE_DEBUG_MSG((nxgep, TX_CTL, 173 "TX Descriptor ring is channel %d mark mode %d", 174 tx_ring_p->tdc, mark_mode)); 175 176 if (!nxge_txdma_reclaim(nxgep, tx_ring_p, nxge_tx_minfree)) { 177 NXGE_DEBUG_MSG((nxgep, TX_CTL, 178 "TX Descriptor ring is full: channel %d", 179 tx_ring_p->tdc)); 180 cas32((uint32_t *)&tx_ring_p->queueing, 0, 1); 181 tdc_stats->tx_no_desc++; 182 MUTEX_EXIT(&tx_ring_p->lock); 183 if (nxgep->resched_needed && !nxgep->resched_running) { 184 nxgep->resched_running = B_TRUE; 185 ddi_trigger_softintr(nxgep->resched_id); 186 } 187 status = 1; 188 goto nxge_start_fail1; 189 } 190 191 nmp = mp; 192 i = sop_index = tx_ring_p->wr_index; 193 nmblks = 0; 194 ngathers = 0; 195 pkt_len = 0; 196 pack_len = 0; 197 clen = 0; 198 last_bidx = -1; 199 good_packet = B_TRUE; 200 201 desc_area = tx_ring_p->tdc_desc; 202 npi_handle = desc_area.npi_handle; 203 npi_desc_handle.regh = (nxge_os_acc_handle_t) 204 DMA_COMMON_ACC_HANDLE(desc_area); 205 tx_desc_ring_vp = (p_tx_desc_t)DMA_COMMON_VPTR(desc_area); 206 #ifdef NXGE_DEBUG 207 tx_desc_ring_pp = (p_tx_desc_t)DMA_COMMON_IOADDR(desc_area); 208 #endif 209 tx_desc_dma_handle = (nxge_os_dma_handle_t) 210 DMA_COMMON_HANDLE(desc_area); 211 tx_msg_ring = tx_ring_p->tx_msg_ring; 212 213 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start: wr_index %d i %d", 214 sop_index, i)); 215 216 #ifdef NXGE_DEBUG 217 msgsize = msgdsize(nmp); 218 NXGE_DEBUG_MSG((nxgep, TX_CTL, 219 "==> nxge_start(1): wr_index %d i %d msgdsize %d", 220 sop_index, i, msgsize)); 221 #endif 222 /* 223 * The first 16 bytes of the premapped buffer are reserved 224 * for header. No padding will be used. 225 */ 226 pkt_len = pack_len = boff = TX_PKT_HEADER_SIZE; 227 if (nxge_tx_use_bcopy && (nxgep->niu_type != N2_NIU)) { 228 bcopy_thresh = (nxge_bcopy_thresh - TX_PKT_HEADER_SIZE); 229 } else { 230 bcopy_thresh = (TX_BCOPY_SIZE - TX_PKT_HEADER_SIZE); 231 } 232 while (nmp) { 233 good_packet = B_TRUE; 234 b_rptr = nmp->b_rptr; 235 len = MBLKL(nmp); 236 if (len <= 0) { 237 nmp = nmp->b_cont; 238 continue; 239 } 240 nmblks++; 241 242 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start(1): nmblks %d " 243 "len %d pkt_len %d pack_len %d", 244 nmblks, len, pkt_len, pack_len)); 245 /* 246 * Hardware limits the transfer length to 4K for NIU and 247 * 4076 (TX_MAX_TRANSFER_LENGTH) for Neptune. But we just 248 * use TX_MAX_TRANSFER_LENGTH as the limit for both. 249 * If len is longer than the limit, then we break nmp into 250 * two chunks: Make the first chunk equal to the limit and 251 * the second chunk for the remaining data. If the second 252 * chunk is still larger than the limit, then it will be 253 * broken into two in the next pass. 254 */ 255 if (len > TX_MAX_TRANSFER_LENGTH - TX_PKT_HEADER_SIZE) { 256 t_mp = dupb(nmp); 257 nmp->b_wptr = nmp->b_rptr + 258 (TX_MAX_TRANSFER_LENGTH - TX_PKT_HEADER_SIZE); 259 t_mp->b_rptr = nmp->b_wptr; 260 t_mp->b_cont = nmp->b_cont; 261 nmp->b_cont = t_mp; 262 len = MBLKL(nmp); 263 } 264 265 tx_desc.value = 0; 266 tx_desc_p = &tx_desc_ring_vp[i]; 267 #ifdef NXGE_DEBUG 268 tx_desc_pp = &tx_desc_ring_pp[i]; 269 #endif 270 tx_msg_p = &tx_msg_ring[i]; 271 #if defined(__i386) 272 npi_desc_handle.regp = (uint32_t)tx_desc_p; 273 #else 274 npi_desc_handle.regp = (uint64_t)tx_desc_p; 275 #endif 276 if (!header_set && 277 ((!nxge_tx_use_bcopy && (len > TX_BCOPY_SIZE)) || 278 (len >= bcopy_thresh))) { 279 header_set = B_TRUE; 280 bcopy_thresh += TX_PKT_HEADER_SIZE; 281 boff = 0; 282 pack_len = 0; 283 kaddr = (caddr_t)DMA_COMMON_VPTR(tx_msg_p->buf_dma); 284 hdrp = (p_tx_pkt_header_t)kaddr; 285 clen = pkt_len; 286 dma_handle = tx_msg_p->buf_dma_handle; 287 dma_ioaddr = DMA_COMMON_IOADDR(tx_msg_p->buf_dma); 288 (void) ddi_dma_sync(dma_handle, 289 i * nxge_bcopy_thresh, nxge_bcopy_thresh, 290 DDI_DMA_SYNC_FORDEV); 291 292 tx_msg_p->flags.dma_type = USE_BCOPY; 293 goto nxge_start_control_header_only; 294 } 295 296 pkt_len += len; 297 pack_len += len; 298 299 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start(3): " 300 "desc entry %d " 301 "DESC IOADDR $%p " 302 "desc_vp $%p tx_desc_p $%p " 303 "desc_pp $%p tx_desc_pp $%p " 304 "len %d pkt_len %d pack_len %d", 305 i, 306 DMA_COMMON_IOADDR(desc_area), 307 tx_desc_ring_vp, tx_desc_p, 308 tx_desc_ring_pp, tx_desc_pp, 309 len, pkt_len, pack_len)); 310 311 if (len < bcopy_thresh) { 312 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start(4): " 313 "USE BCOPY: ")); 314 if (nxge_tx_tiny_pack) { 315 uint32_t blst = 316 TXDMA_DESC_NEXT_INDEX(i, -1, 317 tx_ring_p->tx_wrap_mask); 318 NXGE_DEBUG_MSG((nxgep, TX_CTL, 319 "==> nxge_start(5): pack")); 320 if ((pack_len <= bcopy_thresh) && 321 (last_bidx == blst)) { 322 NXGE_DEBUG_MSG((nxgep, TX_CTL, 323 "==> nxge_start: pack(6) " 324 "(pkt_len %d pack_len %d)", 325 pkt_len, pack_len)); 326 i = blst; 327 tx_desc_p = &tx_desc_ring_vp[i]; 328 #ifdef NXGE_DEBUG 329 tx_desc_pp = &tx_desc_ring_pp[i]; 330 #endif 331 tx_msg_p = &tx_msg_ring[i]; 332 boff = pack_len - len; 333 ngathers--; 334 } else if (pack_len > bcopy_thresh && 335 header_set) { 336 pack_len = len; 337 boff = 0; 338 bcopy_thresh = nxge_bcopy_thresh; 339 NXGE_DEBUG_MSG((nxgep, TX_CTL, 340 "==> nxge_start(7): > max NEW " 341 "bcopy thresh %d " 342 "pkt_len %d pack_len %d(next)", 343 bcopy_thresh, 344 pkt_len, pack_len)); 345 } 346 last_bidx = i; 347 } 348 kaddr = (caddr_t)DMA_COMMON_VPTR(tx_msg_p->buf_dma); 349 if ((boff == TX_PKT_HEADER_SIZE) && (nmblks == 1)) { 350 hdrp = (p_tx_pkt_header_t)kaddr; 351 header_set = B_TRUE; 352 NXGE_DEBUG_MSG((nxgep, TX_CTL, 353 "==> nxge_start(7_x2): " 354 "pkt_len %d pack_len %d (new hdrp $%p)", 355 pkt_len, pack_len, hdrp)); 356 } 357 tx_msg_p->flags.dma_type = USE_BCOPY; 358 kaddr += boff; 359 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start(8): " 360 "USE BCOPY: before bcopy " 361 "DESC IOADDR $%p entry %d " 362 "bcopy packets %d " 363 "bcopy kaddr $%p " 364 "bcopy ioaddr (SAD) $%p " 365 "bcopy clen %d " 366 "bcopy boff %d", 367 DMA_COMMON_IOADDR(desc_area), i, 368 tdc_stats->tx_hdr_pkts, 369 kaddr, 370 dma_ioaddr, 371 clen, 372 boff)); 373 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start: " 374 "1USE BCOPY: ")); 375 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start: " 376 "2USE BCOPY: ")); 377 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start: " 378 "last USE BCOPY: copy from b_rptr $%p " 379 "to KADDR $%p (len %d offset %d", 380 b_rptr, kaddr, len, boff)); 381 382 bcopy(b_rptr, kaddr, len); 383 384 #ifdef NXGE_DEBUG 385 dump_len = (len > 128) ? 128: len; 386 NXGE_DEBUG_MSG((nxgep, TX_CTL, 387 "==> nxge_start: dump packets " 388 "(After BCOPY len %d)" 389 "(b_rptr $%p): %s", len, nmp->b_rptr, 390 nxge_dump_packet((char *)nmp->b_rptr, 391 dump_len))); 392 #endif 393 394 dma_handle = tx_msg_p->buf_dma_handle; 395 dma_ioaddr = DMA_COMMON_IOADDR(tx_msg_p->buf_dma); 396 (void) ddi_dma_sync(dma_handle, 397 i * nxge_bcopy_thresh, nxge_bcopy_thresh, 398 DDI_DMA_SYNC_FORDEV); 399 clen = len + boff; 400 tdc_stats->tx_hdr_pkts++; 401 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start(9): " 402 "USE BCOPY: " 403 "DESC IOADDR $%p entry %d " 404 "bcopy packets %d " 405 "bcopy kaddr $%p " 406 "bcopy ioaddr (SAD) $%p " 407 "bcopy clen %d " 408 "bcopy boff %d", 409 DMA_COMMON_IOADDR(desc_area), 410 i, 411 tdc_stats->tx_hdr_pkts, 412 kaddr, 413 dma_ioaddr, 414 clen, 415 boff)); 416 } else { 417 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start(12): " 418 "USE DVMA: len %d", len)); 419 tx_msg_p->flags.dma_type = USE_DMA; 420 dma_flags = DDI_DMA_WRITE; 421 if (len < nxge_dma_stream_thresh) { 422 dma_flags |= DDI_DMA_CONSISTENT; 423 } else { 424 dma_flags |= DDI_DMA_STREAMING; 425 } 426 427 dma_handle = tx_msg_p->dma_handle; 428 status = ddi_dma_addr_bind_handle(dma_handle, NULL, 429 (caddr_t)b_rptr, len, dma_flags, 430 DDI_DMA_DONTWAIT, NULL, 431 &dma_cookie, &ncookies); 432 if (status == DDI_DMA_MAPPED) { 433 dma_ioaddr = dma_cookie.dmac_laddress; 434 len = (int)dma_cookie.dmac_size; 435 clen = (uint32_t)dma_cookie.dmac_size; 436 NXGE_DEBUG_MSG((nxgep, TX_CTL, 437 "==> nxge_start(12_1): " 438 "USE DVMA: len %d clen %d " 439 "ngathers %d", 440 len, clen, 441 ngathers)); 442 #if defined(__i386) 443 npi_desc_handle.regp = (uint32_t)tx_desc_p; 444 #else 445 npi_desc_handle.regp = (uint64_t)tx_desc_p; 446 #endif 447 while (ncookies > 1) { 448 ngathers++; 449 /* 450 * this is the fix for multiple 451 * cookies, which are basicaly 452 * a descriptor entry, we don't set 453 * SOP bit as well as related fields 454 */ 455 456 (void) npi_txdma_desc_gather_set( 457 npi_desc_handle, 458 &tx_desc, 459 (ngathers -1), 460 mark_mode, 461 ngathers, 462 dma_ioaddr, 463 clen); 464 465 tx_msg_p->tx_msg_size = clen; 466 NXGE_DEBUG_MSG((nxgep, TX_CTL, 467 "==> nxge_start: DMA " 468 "ncookie %d " 469 "ngathers %d " 470 "dma_ioaddr $%p len %d" 471 "desc $%p descp $%p (%d)", 472 ncookies, 473 ngathers, 474 dma_ioaddr, clen, 475 *tx_desc_p, tx_desc_p, i)); 476 477 ddi_dma_nextcookie(dma_handle, 478 &dma_cookie); 479 dma_ioaddr = 480 dma_cookie.dmac_laddress; 481 482 len = (int)dma_cookie.dmac_size; 483 clen = (uint32_t)dma_cookie.dmac_size; 484 NXGE_DEBUG_MSG((nxgep, TX_CTL, 485 "==> nxge_start(12_2): " 486 "USE DVMA: len %d clen %d ", 487 len, clen)); 488 489 i = TXDMA_DESC_NEXT_INDEX(i, 1, 490 tx_ring_p->tx_wrap_mask); 491 tx_desc_p = &tx_desc_ring_vp[i]; 492 493 npi_desc_handle.regp = 494 #if defined(__i386) 495 (uint32_t)tx_desc_p; 496 #else 497 (uint64_t)tx_desc_p; 498 #endif 499 tx_msg_p = &tx_msg_ring[i]; 500 tx_msg_p->flags.dma_type = USE_NONE; 501 tx_desc.value = 0; 502 503 ncookies--; 504 } 505 tdc_stats->tx_ddi_pkts++; 506 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start:" 507 "DMA: ddi packets %d", 508 tdc_stats->tx_ddi_pkts)); 509 } else { 510 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 511 "dma mapping failed for %d " 512 "bytes addr $%p flags %x (%d)", 513 len, b_rptr, status, status)); 514 good_packet = B_FALSE; 515 tdc_stats->tx_dma_bind_fail++; 516 tx_msg_p->flags.dma_type = USE_NONE; 517 goto nxge_start_fail2; 518 } 519 } /* ddi dvma */ 520 521 nmp = nmp->b_cont; 522 nxge_start_control_header_only: 523 #if defined(__i386) 524 npi_desc_handle.regp = (uint32_t)tx_desc_p; 525 #else 526 npi_desc_handle.regp = (uint64_t)tx_desc_p; 527 #endif 528 ngathers++; 529 530 if (ngathers == 1) { 531 #ifdef NXGE_DEBUG 532 save_desc_p = &sop_tx_desc; 533 #endif 534 sop_tx_desc_p = &sop_tx_desc; 535 sop_tx_desc_p->value = 0; 536 sop_tx_desc_p->bits.hdw.tr_len = clen; 537 sop_tx_desc_p->bits.hdw.sad = dma_ioaddr >> 32; 538 sop_tx_desc_p->bits.ldw.sad = dma_ioaddr & 0xffffffff; 539 } else { 540 #ifdef NXGE_DEBUG 541 save_desc_p = &tx_desc; 542 #endif 543 tmp_desc_p = &tx_desc; 544 tmp_desc_p->value = 0; 545 tmp_desc_p->bits.hdw.tr_len = clen; 546 tmp_desc_p->bits.hdw.sad = dma_ioaddr >> 32; 547 tmp_desc_p->bits.ldw.sad = dma_ioaddr & 0xffffffff; 548 549 tx_desc_p->value = tmp_desc_p->value; 550 } 551 552 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start(13): " 553 "Desc_entry %d ngathers %d " 554 "desc_vp $%p tx_desc_p $%p " 555 "len %d clen %d pkt_len %d pack_len %d nmblks %d " 556 "dma_ioaddr (SAD) $%p mark %d", 557 i, ngathers, 558 tx_desc_ring_vp, tx_desc_p, 559 len, clen, pkt_len, pack_len, nmblks, 560 dma_ioaddr, mark_mode)); 561 562 #ifdef NXGE_DEBUG 563 npi_desc_handle.nxgep = nxgep; 564 npi_desc_handle.function.function = nxgep->function_num; 565 npi_desc_handle.function.instance = nxgep->instance; 566 sad = (save_desc_p->value & TX_PKT_DESC_SAD_MASK); 567 xfer_len = ((save_desc_p->value & TX_PKT_DESC_TR_LEN_MASK) >> 568 TX_PKT_DESC_TR_LEN_SHIFT); 569 570 571 NXGE_DEBUG_MSG((nxgep, TX_CTL, "\n\t: value 0x%llx\n" 572 "\t\tsad $%p\ttr_len %d len %d\tnptrs %d\t" 573 "mark %d sop %d\n", 574 save_desc_p->value, 575 sad, 576 save_desc_p->bits.hdw.tr_len, 577 xfer_len, 578 save_desc_p->bits.hdw.num_ptr, 579 save_desc_p->bits.hdw.mark, 580 save_desc_p->bits.hdw.sop)); 581 582 npi_txdma_dump_desc_one(npi_desc_handle, NULL, i); 583 #endif 584 585 tx_msg_p->tx_msg_size = clen; 586 i = TXDMA_DESC_NEXT_INDEX(i, 1, tx_ring_p->tx_wrap_mask); 587 if (ngathers > nxge_tx_max_gathers) { 588 good_packet = B_FALSE; 589 hcksum_retrieve(mp, NULL, NULL, &start_offset, 590 &stuff_offset, &end_offset, &value, 591 &cksum_flags); 592 593 NXGE_DEBUG_MSG((NULL, TX_CTL, 594 "==> nxge_start(14): pull msg - " 595 "len %d pkt_len %d ngathers %d", 596 len, pkt_len, ngathers)); 597 /* Pull all message blocks from b_cont */ 598 if ((msgpullup(mp, -1)) == NULL) { 599 goto nxge_start_fail2; 600 } 601 goto nxge_start_fail2; 602 } 603 } /* while (nmp) */ 604 605 tx_msg_p->tx_message = mp; 606 tx_desc_p = &tx_desc_ring_vp[sop_index]; 607 #if defined(__i386) 608 npi_desc_handle.regp = (uint32_t)tx_desc_p; 609 #else 610 npi_desc_handle.regp = (uint64_t)tx_desc_p; 611 #endif 612 613 pkthdrp = (p_tx_pkt_hdr_all_t)hdrp; 614 pkthdrp->reserved = 0; 615 hdrp->value = 0; 616 (void) nxge_fill_tx_hdr(mp, B_FALSE, cksum_on, 617 (pkt_len - TX_PKT_HEADER_SIZE), npads, pkthdrp); 618 619 if (pkt_len > NXGE_MTU_DEFAULT_MAX) { 620 tdc_stats->tx_jumbo_pkts++; 621 } 622 623 min_len = (nxgep->msg_min + TX_PKT_HEADER_SIZE + (npads * 2)); 624 if (pkt_len < min_len) { 625 /* Assume we use bcopy to premapped buffers */ 626 kaddr = (caddr_t)DMA_COMMON_VPTR(tx_msg_p->buf_dma); 627 NXGE_DEBUG_MSG((NULL, TX_CTL, 628 "==> nxge_start(14-1): < (msg_min + 16)" 629 "len %d pkt_len %d min_len %d bzero %d ngathers %d", 630 len, pkt_len, min_len, (min_len - pkt_len), ngathers)); 631 bzero((kaddr + pkt_len), (min_len - pkt_len)); 632 pkt_len = tx_msg_p->tx_msg_size = min_len; 633 634 sop_tx_desc_p->bits.hdw.tr_len = min_len; 635 636 NXGE_MEM_PIO_WRITE64(npi_desc_handle, sop_tx_desc_p->value); 637 tx_desc_p->value = sop_tx_desc_p->value; 638 639 NXGE_DEBUG_MSG((NULL, TX_CTL, 640 "==> nxge_start(14-2): < msg_min - " 641 "len %d pkt_len %d min_len %d ngathers %d", 642 len, pkt_len, min_len, ngathers)); 643 } 644 645 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start: cksum_flags 0x%x ", 646 cksum_flags)); 647 if (cksum_flags & HCK_PARTIALCKSUM) { 648 NXGE_DEBUG_MSG((nxgep, TX_CTL, 649 "==> nxge_start: cksum_flags 0x%x (partial checksum) ", 650 cksum_flags)); 651 cksum_on = B_TRUE; 652 NXGE_DEBUG_MSG((nxgep, TX_CTL, 653 "==> nxge_start: from IP cksum_flags 0x%x " 654 "(partial checksum) " 655 "start_offset %d stuff_offset %d", 656 cksum_flags, start_offset, stuff_offset)); 657 tmp_len = (uint64_t)(start_offset >> 1); 658 hdrp->value |= (tmp_len << TX_PKT_HEADER_L4START_SHIFT); 659 tmp_len = (uint64_t)(stuff_offset >> 1); 660 hdrp->value |= (tmp_len << TX_PKT_HEADER_L4STUFF_SHIFT); 661 662 NXGE_DEBUG_MSG((nxgep, TX_CTL, 663 "==> nxge_start: from IP cksum_flags 0x%x " 664 "(partial checksum) " 665 "after SHIFT start_offset %d stuff_offset %d", 666 cksum_flags, start_offset, stuff_offset)); 667 } 668 { 669 uint64_t tmp_len; 670 671 /* pkt_len already includes 16 + paddings!! */ 672 /* Update the control header length */ 673 tot_xfer_len = (pkt_len - TX_PKT_HEADER_SIZE); 674 tmp_len = hdrp->value | 675 (tot_xfer_len << TX_PKT_HEADER_TOT_XFER_LEN_SHIFT); 676 677 NXGE_DEBUG_MSG((nxgep, TX_CTL, 678 "==> nxge_start(15_x1): setting SOP " 679 "tot_xfer_len 0x%llx (%d) pkt_len %d tmp_len " 680 "0x%llx hdrp->value 0x%llx", 681 tot_xfer_len, tot_xfer_len, pkt_len, 682 tmp_len, hdrp->value)); 683 #if defined(_BIG_ENDIAN) 684 hdrp->value = ddi_swap64(tmp_len); 685 #else 686 hdrp->value = tmp_len; 687 #endif 688 NXGE_DEBUG_MSG((nxgep, 689 TX_CTL, "==> nxge_start(15_x2): setting SOP " 690 "after SWAP: tot_xfer_len 0x%llx pkt_len %d " 691 "tmp_len 0x%llx hdrp->value 0x%llx", 692 tot_xfer_len, pkt_len, 693 tmp_len, hdrp->value)); 694 } 695 696 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start(15): setting SOP " 697 "wr_index %d " 698 "tot_xfer_len (%d) pkt_len %d npads %d", 699 sop_index, 700 tot_xfer_len, pkt_len, 701 npads)); 702 703 sop_tx_desc_p->bits.hdw.sop = 1; 704 sop_tx_desc_p->bits.hdw.mark = mark_mode; 705 sop_tx_desc_p->bits.hdw.num_ptr = ngathers; 706 707 NXGE_MEM_PIO_WRITE64(npi_desc_handle, sop_tx_desc_p->value); 708 709 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start(16): set SOP done")); 710 711 #ifdef NXGE_DEBUG 712 npi_desc_handle.nxgep = nxgep; 713 npi_desc_handle.function.function = nxgep->function_num; 714 npi_desc_handle.function.instance = nxgep->instance; 715 716 NXGE_DEBUG_MSG((nxgep, TX_CTL, "\n\t: value 0x%llx\n" 717 "\t\tsad $%p\ttr_len %d len %d\tnptrs %d\tmark %d sop %d\n", 718 save_desc_p->value, 719 sad, 720 save_desc_p->bits.hdw.tr_len, 721 xfer_len, 722 save_desc_p->bits.hdw.num_ptr, 723 save_desc_p->bits.hdw.mark, 724 save_desc_p->bits.hdw.sop)); 725 (void) npi_txdma_dump_desc_one(npi_desc_handle, NULL, sop_index); 726 727 dump_len = (pkt_len > 128) ? 128: pkt_len; 728 NXGE_DEBUG_MSG((nxgep, TX_CTL, 729 "==> nxge_start: dump packets(17) (after sop set, len " 730 " (len/dump_len/pkt_len/tot_xfer_len) %d/%d/%d/%d):\n" 731 "ptr $%p: %s", len, dump_len, pkt_len, tot_xfer_len, 732 (char *)hdrp, 733 nxge_dump_packet((char *)hdrp, dump_len))); 734 NXGE_DEBUG_MSG((nxgep, TX_CTL, 735 "==> nxge_start(18): TX desc sync: sop_index %d", 736 sop_index)); 737 #endif 738 739 if ((ngathers == 1) || tx_ring_p->wr_index < i) { 740 (void) ddi_dma_sync(tx_desc_dma_handle, 741 sop_index * sizeof (tx_desc_t), 742 ngathers * sizeof (tx_desc_t), 743 DDI_DMA_SYNC_FORDEV); 744 745 NXGE_DEBUG_MSG((nxgep, TX_CTL, "nxge_start(19): sync 1 " 746 "cs_off = 0x%02X cs_s_off = 0x%02X " 747 "pkt_len %d ngathers %d sop_index %d\n", 748 stuff_offset, start_offset, 749 pkt_len, ngathers, sop_index)); 750 } else { /* more than one descriptor and wrap around */ 751 uint32_t nsdescs = tx_ring_p->tx_ring_size - sop_index; 752 (void) ddi_dma_sync(tx_desc_dma_handle, 753 sop_index * sizeof (tx_desc_t), 754 nsdescs * sizeof (tx_desc_t), 755 DDI_DMA_SYNC_FORDEV); 756 NXGE_DEBUG_MSG((nxgep, TX_CTL, "nxge_start(20): sync 1 " 757 "cs_off = 0x%02X cs_s_off = 0x%02X " 758 "pkt_len %d ngathers %d sop_index %d\n", 759 stuff_offset, start_offset, 760 pkt_len, ngathers, sop_index)); 761 762 (void) ddi_dma_sync(tx_desc_dma_handle, 763 0, 764 (ngathers - nsdescs) * sizeof (tx_desc_t), 765 DDI_DMA_SYNC_FORDEV); 766 NXGE_DEBUG_MSG((nxgep, TX_CTL, "nxge_start(21): sync 2 " 767 "cs_off = 0x%02X cs_s_off = 0x%02X " 768 "pkt_len %d ngathers %d sop_index %d\n", 769 stuff_offset, start_offset, 770 pkt_len, ngathers, sop_index)); 771 } 772 773 tail_index = tx_ring_p->wr_index; 774 tail_wrap = tx_ring_p->wr_index_wrap; 775 776 tx_ring_p->wr_index = i; 777 if (tx_ring_p->wr_index <= tail_index) { 778 tx_ring_p->wr_index_wrap = ((tail_wrap == B_TRUE) ? 779 B_FALSE : B_TRUE); 780 } 781 782 tx_ring_p->descs_pending += ngathers; 783 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start: TX kick: " 784 "channel %d wr_index %d wrap %d ngathers %d desc_pend %d", 785 tx_ring_p->tdc, 786 tx_ring_p->wr_index, 787 tx_ring_p->wr_index_wrap, 788 ngathers, 789 tx_ring_p->descs_pending)); 790 791 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start: TX KICKING: ")); 792 793 { 794 tx_ring_kick_t kick; 795 796 kick.value = 0; 797 kick.bits.ldw.wrap = tx_ring_p->wr_index_wrap; 798 kick.bits.ldw.tail = (uint16_t)tx_ring_p->wr_index; 799 800 /* Kick start the Transmit kick register */ 801 TXDMA_REG_WRITE64(NXGE_DEV_NPI_HANDLE(nxgep), 802 TX_RING_KICK_REG, 803 (uint8_t)tx_ring_p->tdc, 804 kick.value); 805 } 806 807 tdc_stats->tx_starts++; 808 809 MUTEX_EXIT(&tx_ring_p->lock); 810 811 NXGE_DEBUG_MSG((nxgep, TX_CTL, "<== nxge_start")); 812 813 return (status); 814 815 nxge_start_fail2: 816 if (good_packet == B_FALSE) { 817 cur_index = sop_index; 818 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start: clean up")); 819 for (i = 0; i < ngathers; i++) { 820 tx_desc_p = &tx_desc_ring_vp[cur_index]; 821 #if defined(__i386) 822 npi_handle.regp = (uint32_t)tx_desc_p; 823 #else 824 npi_handle.regp = (uint64_t)tx_desc_p; 825 #endif 826 tx_msg_p = &tx_msg_ring[cur_index]; 827 (void) npi_txdma_desc_set_zero(npi_handle, 1); 828 if (tx_msg_p->flags.dma_type == USE_DVMA) { 829 NXGE_DEBUG_MSG((nxgep, TX_CTL, 830 "tx_desc_p = %X index = %d", 831 tx_desc_p, tx_ring_p->rd_index)); 832 (void) dvma_unload( 833 tx_msg_p->dvma_handle, 834 0, -1); 835 tx_msg_p->dvma_handle = NULL; 836 if (tx_ring_p->dvma_wr_index == 837 tx_ring_p->dvma_wrap_mask) 838 tx_ring_p->dvma_wr_index = 0; 839 else 840 tx_ring_p->dvma_wr_index++; 841 tx_ring_p->dvma_pending--; 842 } else if (tx_msg_p->flags.dma_type == 843 USE_DMA) { 844 if (ddi_dma_unbind_handle( 845 tx_msg_p->dma_handle)) 846 cmn_err(CE_WARN, "!nxge_start: " 847 "ddi_dma_unbind_handle failed"); 848 } 849 tx_msg_p->flags.dma_type = USE_NONE; 850 cur_index = TXDMA_DESC_NEXT_INDEX(cur_index, 1, 851 tx_ring_p->tx_wrap_mask); 852 853 } 854 855 nxgep->resched_needed = B_TRUE; 856 } 857 858 MUTEX_EXIT(&tx_ring_p->lock); 859 860 nxge_start_fail1: 861 /* Add FMA to check the access handle nxge_hregh */ 862 863 NXGE_DEBUG_MSG((nxgep, TX_CTL, "<== nxge_start")); 864 865 return (status); 866 } 867 868 int 869 nxge_serial_tx(mblk_t *mp, void *arg) 870 { 871 p_tx_ring_t tx_ring_p = (p_tx_ring_t)arg; 872 p_nxge_t nxgep = tx_ring_p->nxgep; 873 874 return (nxge_start(nxgep, tx_ring_p, mp)); 875 } 876 877 boolean_t 878 nxge_send(p_nxge_t nxgep, mblk_t *mp, p_mac_tx_hint_t hp) 879 { 880 p_tx_ring_t *tx_rings; 881 uint8_t ring_index; 882 p_tx_ring_t tx_ring_p; 883 884 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_send")); 885 886 ASSERT(mp->b_next == NULL); 887 888 ring_index = nxge_tx_lb_ring_1(mp, nxgep->max_tdcs, hp); 889 tx_rings = nxgep->tx_rings->rings; 890 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_tx_msg: tx_rings $%p", 891 tx_rings)); 892 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_tx_msg: max_tdcs %d " 893 "ring_index %d", nxgep->max_tdcs, ring_index)); 894 895 switch (nxge_tx_scheme) { 896 case NXGE_USE_START: 897 if (nxge_start(nxgep, tx_rings[ring_index], mp)) { 898 NXGE_DEBUG_MSG((nxgep, TX_CTL, "<== nxge_send: failed " 899 "ring index %d", ring_index)); 900 return (B_FALSE); 901 } 902 break; 903 904 case NXGE_USE_SERIAL: 905 default: 906 tx_ring_p = tx_rings[ring_index]; 907 nxge_serialize_enter(tx_ring_p->serial, mp); 908 break; 909 } 910 911 NXGE_DEBUG_MSG((nxgep, TX_CTL, "<== nxge_send: ring index %d", 912 ring_index)); 913 914 return (B_TRUE); 915 } 916 917 /* 918 * nxge_m_tx() - send a chain of packets 919 */ 920 mblk_t * 921 nxge_m_tx(void *arg, mblk_t *mp) 922 { 923 p_nxge_t nxgep = (p_nxge_t)arg; 924 mblk_t *next; 925 mac_tx_hint_t hint; 926 927 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 928 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 929 "==> nxge_m_tx: hardware not initialized")); 930 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 931 "<== nxge_m_tx")); 932 return (mp); 933 } 934 935 hint.hash = NULL; 936 hint.vid = 0; 937 hint.sap = 0; 938 939 while (mp != NULL) { 940 next = mp->b_next; 941 mp->b_next = NULL; 942 943 /* 944 * Until Nemo tx resource works, the mac driver 945 * does the load balancing based on TCP port, 946 * or CPU. For debugging, we use a system 947 * configurable parameter. 948 */ 949 if (!nxge_send(nxgep, mp, &hint)) { 950 mp->b_next = next; 951 break; 952 } 953 954 mp = next; 955 } 956 957 return (mp); 958 } 959 960 int 961 nxge_tx_lb_ring_1(p_mblk_t mp, uint32_t maxtdcs, p_mac_tx_hint_t hp) 962 { 963 uint8_t ring_index = 0; 964 uint8_t *tcp_port; 965 p_mblk_t nmp; 966 size_t mblk_len; 967 size_t iph_len; 968 size_t hdrs_size; 969 uint8_t hdrs_buf[sizeof (struct ether_header) + 970 IP_MAX_HDR_LENGTH + sizeof (uint32_t)]; 971 /* 972 * allocate space big enough to cover 973 * the max ip header length and the first 974 * 4 bytes of the TCP/IP header. 975 */ 976 977 boolean_t qos = B_FALSE; 978 979 NXGE_DEBUG_MSG((NULL, TX_CTL, "==> nxge_tx_lb_ring")); 980 981 if (hp->vid) { 982 qos = B_TRUE; 983 } 984 switch (nxge_tx_lb_policy) { 985 case NXGE_TX_LB_TCPUDP: /* default IPv4 TCP/UDP */ 986 default: 987 tcp_port = mp->b_rptr; 988 if (!nxge_no_tx_lb && !qos && 989 (ntohs(((p_ether_header_t)tcp_port)->ether_type) 990 == ETHERTYPE_IP)) { 991 nmp = mp; 992 mblk_len = MBLKL(nmp); 993 tcp_port = NULL; 994 if (mblk_len > sizeof (struct ether_header) + 995 sizeof (uint8_t)) { 996 tcp_port = nmp->b_rptr + 997 sizeof (struct ether_header); 998 mblk_len -= sizeof (struct ether_header); 999 iph_len = ((*tcp_port) & 0x0f) << 2; 1000 if (mblk_len > (iph_len + sizeof (uint32_t))) { 1001 tcp_port = nmp->b_rptr; 1002 } else { 1003 tcp_port = NULL; 1004 } 1005 } 1006 if (tcp_port == NULL) { 1007 hdrs_size = 0; 1008 ((p_ether_header_t)hdrs_buf)->ether_type = 0; 1009 while ((nmp) && (hdrs_size < 1010 sizeof (hdrs_buf))) { 1011 mblk_len = MBLKL(nmp); 1012 if (mblk_len >= 1013 (sizeof (hdrs_buf) - hdrs_size)) 1014 mblk_len = sizeof (hdrs_buf) - 1015 hdrs_size; 1016 bcopy(nmp->b_rptr, 1017 &hdrs_buf[hdrs_size], mblk_len); 1018 hdrs_size += mblk_len; 1019 nmp = nmp->b_cont; 1020 } 1021 tcp_port = hdrs_buf; 1022 } 1023 tcp_port += sizeof (ether_header_t); 1024 if (!(tcp_port[6] & 0x3f) && !(tcp_port[7] & 0xff)) { 1025 switch (tcp_port[9]) { 1026 case IPPROTO_TCP: 1027 case IPPROTO_UDP: 1028 case IPPROTO_ESP: 1029 tcp_port += ((*tcp_port) & 0x0f) << 2; 1030 ring_index = 1031 ((tcp_port[0] ^ 1032 tcp_port[1] ^ 1033 tcp_port[2] ^ 1034 tcp_port[3]) % maxtdcs); 1035 break; 1036 1037 case IPPROTO_AH: 1038 /* SPI starts at the 4th byte */ 1039 tcp_port += ((*tcp_port) & 0x0f) << 2; 1040 ring_index = 1041 ((tcp_port[4] ^ 1042 tcp_port[5] ^ 1043 tcp_port[6] ^ 1044 tcp_port[7]) % maxtdcs); 1045 break; 1046 1047 default: 1048 ring_index = tcp_port[19] % maxtdcs; 1049 break; 1050 } 1051 } else { /* fragmented packet */ 1052 ring_index = tcp_port[19] % maxtdcs; 1053 } 1054 } else { 1055 ring_index = mp->b_band % maxtdcs; 1056 } 1057 break; 1058 1059 case NXGE_TX_LB_HASH: 1060 if (hp->hash) { 1061 #if defined(__i386) 1062 ring_index = ((uint32_t)(hp->hash) % maxtdcs); 1063 #else 1064 ring_index = ((uint64_t)(hp->hash) % maxtdcs); 1065 #endif 1066 } else { 1067 ring_index = mp->b_band % maxtdcs; 1068 } 1069 break; 1070 1071 case NXGE_TX_LB_DEST_MAC: /* Use destination MAC address */ 1072 tcp_port = mp->b_rptr; 1073 ring_index = tcp_port[5] % maxtdcs; 1074 break; 1075 } 1076 1077 NXGE_DEBUG_MSG((NULL, TX_CTL, "<== nxge_tx_lb_ring")); 1078 1079 return (ring_index); 1080 } 1081 1082 uint_t 1083 nxge_reschedule(caddr_t arg) 1084 { 1085 p_nxge_t nxgep; 1086 1087 nxgep = (p_nxge_t)arg; 1088 1089 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_reschedule")); 1090 1091 if (nxgep->nxge_mac_state == NXGE_MAC_STARTED && 1092 nxgep->resched_needed) { 1093 mac_tx_update(nxgep->mach); 1094 nxgep->resched_needed = B_FALSE; 1095 nxgep->resched_running = B_FALSE; 1096 } 1097 1098 NXGE_DEBUG_MSG((NULL, TX_CTL, "<== nxge_reschedule")); 1099 return (DDI_INTR_CLAIMED); 1100 } 1101