1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/nxge/nxge_impl.h> 29 #include <sys/nxge/nxge_rxdma.h> 30 31 #define NXGE_ACTUAL_RDCGRP(nxgep, rdcgrp) \ 32 (rdcgrp + nxgep->pt_config.hw_config.start_rdc_grpid) 33 #define NXGE_ACTUAL_RDC(nxgep, rdc) \ 34 (rdc + nxgep->pt_config.hw_config.start_rdc) 35 36 /* 37 * Globals: tunable parameters (/etc/system or adb) 38 * 39 */ 40 extern uint32_t nxge_rbr_size; 41 extern uint32_t nxge_rcr_size; 42 extern uint32_t nxge_rbr_spare_size; 43 44 extern uint32_t nxge_mblks_pending; 45 46 /* 47 * Tunable to reduce the amount of time spent in the 48 * ISR doing Rx Processing. 49 */ 50 extern uint32_t nxge_max_rx_pkts; 51 boolean_t nxge_jumbo_enable; 52 53 /* 54 * Tunables to manage the receive buffer blocks. 55 * 56 * nxge_rx_threshold_hi: copy all buffers. 57 * nxge_rx_bcopy_size_type: receive buffer block size type. 58 * nxge_rx_threshold_lo: copy only up to tunable block size type. 59 */ 60 extern nxge_rxbuf_threshold_t nxge_rx_threshold_hi; 61 extern nxge_rxbuf_type_t nxge_rx_buf_size_type; 62 extern nxge_rxbuf_threshold_t nxge_rx_threshold_lo; 63 64 static nxge_status_t nxge_map_rxdma(p_nxge_t); 65 static void nxge_unmap_rxdma(p_nxge_t); 66 67 static nxge_status_t nxge_rxdma_hw_start_common(p_nxge_t); 68 static void nxge_rxdma_hw_stop_common(p_nxge_t); 69 70 static nxge_status_t nxge_rxdma_hw_start(p_nxge_t); 71 static void nxge_rxdma_hw_stop(p_nxge_t); 72 73 static nxge_status_t nxge_map_rxdma_channel(p_nxge_t, uint16_t, 74 p_nxge_dma_common_t *, p_rx_rbr_ring_t *, 75 uint32_t, 76 p_nxge_dma_common_t *, p_rx_rcr_ring_t *, 77 p_rx_mbox_t *); 78 static void nxge_unmap_rxdma_channel(p_nxge_t, uint16_t, 79 p_rx_rbr_ring_t, p_rx_rcr_ring_t, p_rx_mbox_t); 80 81 static nxge_status_t nxge_map_rxdma_channel_cfg_ring(p_nxge_t, 82 uint16_t, 83 p_nxge_dma_common_t *, p_rx_rbr_ring_t *, 84 p_rx_rcr_ring_t *, p_rx_mbox_t *); 85 static void nxge_unmap_rxdma_channel_cfg_ring(p_nxge_t, 86 p_rx_rcr_ring_t, p_rx_mbox_t); 87 88 static nxge_status_t nxge_map_rxdma_channel_buf_ring(p_nxge_t, 89 uint16_t, 90 p_nxge_dma_common_t *, 91 p_rx_rbr_ring_t *, uint32_t); 92 static void nxge_unmap_rxdma_channel_buf_ring(p_nxge_t, 93 p_rx_rbr_ring_t); 94 95 static nxge_status_t nxge_rxdma_start_channel(p_nxge_t, uint16_t, 96 p_rx_rbr_ring_t, p_rx_rcr_ring_t, p_rx_mbox_t); 97 static nxge_status_t nxge_rxdma_stop_channel(p_nxge_t, uint16_t); 98 99 mblk_t * 100 nxge_rx_pkts(p_nxge_t, uint_t, p_nxge_ldv_t, 101 p_rx_rcr_ring_t *, rx_dma_ctl_stat_t); 102 103 static void nxge_receive_packet(p_nxge_t, 104 p_rx_rcr_ring_t, 105 p_rcr_entry_t, 106 boolean_t *, 107 mblk_t **, mblk_t **); 108 109 nxge_status_t nxge_disable_rxdma_channel(p_nxge_t, uint16_t); 110 111 static p_rx_msg_t nxge_allocb(size_t, uint32_t, p_nxge_dma_common_t); 112 static void nxge_freeb(p_rx_msg_t); 113 static void nxge_rx_pkts_vring(p_nxge_t, uint_t, 114 p_nxge_ldv_t, rx_dma_ctl_stat_t); 115 static nxge_status_t nxge_rx_err_evnts(p_nxge_t, uint_t, 116 p_nxge_ldv_t, rx_dma_ctl_stat_t); 117 118 static nxge_status_t nxge_rxdma_handle_port_errors(p_nxge_t, 119 uint32_t, uint32_t); 120 121 static nxge_status_t nxge_rxbuf_index_info_init(p_nxge_t, 122 p_rx_rbr_ring_t); 123 124 125 static nxge_status_t 126 nxge_rxdma_fatal_err_recover(p_nxge_t, uint16_t); 127 128 nxge_status_t 129 nxge_rx_port_fatal_err_recover(p_nxge_t); 130 131 nxge_status_t 132 nxge_init_rxdma_channels(p_nxge_t nxgep) 133 { 134 nxge_status_t status = NXGE_OK; 135 136 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_init_rxdma_channels")); 137 138 status = nxge_map_rxdma(nxgep); 139 if (status != NXGE_OK) { 140 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 141 "<== nxge_init_rxdma: status 0x%x", status)); 142 return (status); 143 } 144 145 status = nxge_rxdma_hw_start_common(nxgep); 146 if (status != NXGE_OK) { 147 nxge_unmap_rxdma(nxgep); 148 } 149 150 status = nxge_rxdma_hw_start(nxgep); 151 if (status != NXGE_OK) { 152 nxge_unmap_rxdma(nxgep); 153 } 154 155 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 156 "<== nxge_init_rxdma_channels: status 0x%x", status)); 157 158 return (status); 159 } 160 161 void 162 nxge_uninit_rxdma_channels(p_nxge_t nxgep) 163 { 164 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_uninit_rxdma_channels")); 165 166 nxge_rxdma_hw_stop(nxgep); 167 nxge_rxdma_hw_stop_common(nxgep); 168 nxge_unmap_rxdma(nxgep); 169 170 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 171 "<== nxge_uinit_rxdma_channels")); 172 } 173 174 nxge_status_t 175 nxge_reset_rxdma_channel(p_nxge_t nxgep, uint16_t channel) 176 { 177 npi_handle_t handle; 178 npi_status_t rs = NPI_SUCCESS; 179 nxge_status_t status = NXGE_OK; 180 181 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_reset_rxdma_channel")); 182 183 handle = NXGE_DEV_NPI_HANDLE(nxgep); 184 rs = npi_rxdma_cfg_rdc_reset(handle, channel); 185 186 if (rs != NPI_SUCCESS) { 187 status = NXGE_ERROR | rs; 188 } 189 190 return (status); 191 } 192 193 void 194 nxge_rxdma_regs_dump_channels(p_nxge_t nxgep) 195 { 196 int i, ndmas; 197 uint16_t channel; 198 p_rx_rbr_rings_t rx_rbr_rings; 199 p_rx_rbr_ring_t *rbr_rings; 200 npi_handle_t handle; 201 202 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_regs_dump_channels")); 203 204 handle = NXGE_DEV_NPI_HANDLE(nxgep); 205 (void) npi_rxdma_dump_fzc_regs(handle); 206 207 rx_rbr_rings = nxgep->rx_rbr_rings; 208 if (rx_rbr_rings == NULL) { 209 NXGE_DEBUG_MSG((nxgep, RX_CTL, 210 "<== nxge_rxdma_regs_dump_channels: " 211 "NULL ring pointer")); 212 return; 213 } 214 if (rx_rbr_rings->rbr_rings == NULL) { 215 NXGE_DEBUG_MSG((nxgep, RX_CTL, 216 "<== nxge_rxdma_regs_dump_channels: " 217 " NULL rbr rings pointer")); 218 return; 219 } 220 221 ndmas = rx_rbr_rings->ndmas; 222 if (!ndmas) { 223 NXGE_DEBUG_MSG((nxgep, RX_CTL, 224 "<== nxge_rxdma_regs_dump_channels: no channel")); 225 return; 226 } 227 228 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 229 "==> nxge_rxdma_regs_dump_channels (ndmas %d)", ndmas)); 230 231 rbr_rings = rx_rbr_rings->rbr_rings; 232 for (i = 0; i < ndmas; i++) { 233 if (rbr_rings == NULL || rbr_rings[i] == NULL) { 234 continue; 235 } 236 channel = rbr_rings[i]->rdc; 237 (void) nxge_dump_rxdma_channel(nxgep, channel); 238 } 239 240 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_regs_dump")); 241 242 } 243 244 nxge_status_t 245 nxge_dump_rxdma_channel(p_nxge_t nxgep, uint8_t channel) 246 { 247 npi_handle_t handle; 248 npi_status_t rs = NPI_SUCCESS; 249 nxge_status_t status = NXGE_OK; 250 251 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_dump_rxdma_channel")); 252 253 handle = NXGE_DEV_NPI_HANDLE(nxgep); 254 rs = npi_rxdma_dump_rdc_regs(handle, channel); 255 256 if (rs != NPI_SUCCESS) { 257 status = NXGE_ERROR | rs; 258 } 259 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_dump_rxdma_channel")); 260 return (status); 261 } 262 263 nxge_status_t 264 nxge_init_rxdma_channel_event_mask(p_nxge_t nxgep, uint16_t channel, 265 p_rx_dma_ent_msk_t mask_p) 266 { 267 npi_handle_t handle; 268 npi_status_t rs = NPI_SUCCESS; 269 nxge_status_t status = NXGE_OK; 270 271 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 272 "<== nxge_init_rxdma_channel_event_mask")); 273 274 handle = NXGE_DEV_NPI_HANDLE(nxgep); 275 rs = npi_rxdma_event_mask(handle, OP_SET, channel, mask_p); 276 if (rs != NPI_SUCCESS) { 277 status = NXGE_ERROR | rs; 278 } 279 280 return (status); 281 } 282 283 nxge_status_t 284 nxge_init_rxdma_channel_cntl_stat(p_nxge_t nxgep, uint16_t channel, 285 p_rx_dma_ctl_stat_t cs_p) 286 { 287 npi_handle_t handle; 288 npi_status_t rs = NPI_SUCCESS; 289 nxge_status_t status = NXGE_OK; 290 291 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 292 "<== nxge_init_rxdma_channel_cntl_stat")); 293 294 handle = NXGE_DEV_NPI_HANDLE(nxgep); 295 rs = npi_rxdma_control_status(handle, OP_SET, channel, cs_p); 296 297 if (rs != NPI_SUCCESS) { 298 status = NXGE_ERROR | rs; 299 } 300 301 return (status); 302 } 303 304 nxge_status_t 305 nxge_rxdma_cfg_rdcgrp_default_rdc(p_nxge_t nxgep, uint8_t rdcgrp, 306 uint8_t rdc) 307 { 308 npi_handle_t handle; 309 npi_status_t rs = NPI_SUCCESS; 310 p_nxge_dma_pt_cfg_t p_dma_cfgp; 311 p_nxge_rdc_grp_t rdc_grp_p; 312 uint8_t actual_rdcgrp, actual_rdc; 313 314 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 315 " ==> nxge_rxdma_cfg_rdcgrp_default_rdc")); 316 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 317 318 handle = NXGE_DEV_NPI_HANDLE(nxgep); 319 320 rdc_grp_p = &p_dma_cfgp->rdc_grps[rdcgrp]; 321 rdc_grp_p->rdc[0] = rdc; 322 323 actual_rdcgrp = NXGE_ACTUAL_RDCGRP(nxgep, rdcgrp); 324 actual_rdc = NXGE_ACTUAL_RDC(nxgep, rdc); 325 326 rs = npi_rxdma_cfg_rdc_table_default_rdc(handle, actual_rdcgrp, 327 actual_rdc); 328 329 if (rs != NPI_SUCCESS) { 330 return (NXGE_ERROR | rs); 331 } 332 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 333 " <== nxge_rxdma_cfg_rdcgrp_default_rdc")); 334 return (NXGE_OK); 335 } 336 337 nxge_status_t 338 nxge_rxdma_cfg_port_default_rdc(p_nxge_t nxgep, uint8_t port, uint8_t rdc) 339 { 340 npi_handle_t handle; 341 342 uint8_t actual_rdc; 343 npi_status_t rs = NPI_SUCCESS; 344 345 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 346 " ==> nxge_rxdma_cfg_port_default_rdc")); 347 348 handle = NXGE_DEV_NPI_HANDLE(nxgep); 349 actual_rdc = NXGE_ACTUAL_RDC(nxgep, rdc); 350 rs = npi_rxdma_cfg_default_port_rdc(handle, port, actual_rdc); 351 352 353 if (rs != NPI_SUCCESS) { 354 return (NXGE_ERROR | rs); 355 } 356 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 357 " <== nxge_rxdma_cfg_port_default_rdc")); 358 359 return (NXGE_OK); 360 } 361 362 nxge_status_t 363 nxge_rxdma_cfg_rcr_threshold(p_nxge_t nxgep, uint8_t channel, 364 uint16_t pkts) 365 { 366 npi_status_t rs = NPI_SUCCESS; 367 npi_handle_t handle; 368 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 369 " ==> nxge_rxdma_cfg_rcr_threshold")); 370 handle = NXGE_DEV_NPI_HANDLE(nxgep); 371 372 rs = npi_rxdma_cfg_rdc_rcr_threshold(handle, channel, pkts); 373 374 if (rs != NPI_SUCCESS) { 375 return (NXGE_ERROR | rs); 376 } 377 NXGE_DEBUG_MSG((nxgep, RX2_CTL, " <== nxge_rxdma_cfg_rcr_threshold")); 378 return (NXGE_OK); 379 } 380 381 nxge_status_t 382 nxge_rxdma_cfg_rcr_timeout(p_nxge_t nxgep, uint8_t channel, 383 uint16_t tout, uint8_t enable) 384 { 385 npi_status_t rs = NPI_SUCCESS; 386 npi_handle_t handle; 387 NXGE_DEBUG_MSG((nxgep, RX2_CTL, " ==> nxge_rxdma_cfg_rcr_timeout")); 388 handle = NXGE_DEV_NPI_HANDLE(nxgep); 389 if (enable == 0) { 390 rs = npi_rxdma_cfg_rdc_rcr_timeout_disable(handle, channel); 391 } else { 392 rs = npi_rxdma_cfg_rdc_rcr_timeout(handle, channel, 393 tout); 394 } 395 396 if (rs != NPI_SUCCESS) { 397 return (NXGE_ERROR | rs); 398 } 399 NXGE_DEBUG_MSG((nxgep, RX2_CTL, " <== nxge_rxdma_cfg_rcr_timeout")); 400 return (NXGE_OK); 401 } 402 403 nxge_status_t 404 nxge_enable_rxdma_channel(p_nxge_t nxgep, uint16_t channel, 405 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p) 406 { 407 npi_handle_t handle; 408 rdc_desc_cfg_t rdc_desc; 409 p_rcrcfig_b_t cfgb_p; 410 npi_status_t rs = NPI_SUCCESS; 411 412 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel")); 413 handle = NXGE_DEV_NPI_HANDLE(nxgep); 414 /* 415 * Use configuration data composed at init time. 416 * Write to hardware the receive ring configurations. 417 */ 418 rdc_desc.mbox_enable = 1; 419 rdc_desc.mbox_addr = mbox_p->mbox_addr; 420 NXGE_DEBUG_MSG((nxgep, RX_CTL, 421 "==> nxge_enable_rxdma_channel: mboxp $%p($%p)", 422 mbox_p->mbox_addr, rdc_desc.mbox_addr)); 423 424 rdc_desc.rbr_len = rbr_p->rbb_max; 425 rdc_desc.rbr_addr = rbr_p->rbr_addr; 426 427 switch (nxgep->rx_bksize_code) { 428 case RBR_BKSIZE_4K: 429 rdc_desc.page_size = SIZE_4KB; 430 break; 431 case RBR_BKSIZE_8K: 432 rdc_desc.page_size = SIZE_8KB; 433 break; 434 case RBR_BKSIZE_16K: 435 rdc_desc.page_size = SIZE_16KB; 436 break; 437 case RBR_BKSIZE_32K: 438 rdc_desc.page_size = SIZE_32KB; 439 break; 440 } 441 442 rdc_desc.size0 = rbr_p->npi_pkt_buf_size0; 443 rdc_desc.valid0 = 1; 444 445 rdc_desc.size1 = rbr_p->npi_pkt_buf_size1; 446 rdc_desc.valid1 = 1; 447 448 rdc_desc.size2 = rbr_p->npi_pkt_buf_size2; 449 rdc_desc.valid2 = 1; 450 451 rdc_desc.full_hdr = rcr_p->full_hdr_flag; 452 rdc_desc.offset = rcr_p->sw_priv_hdr_len; 453 454 rdc_desc.rcr_len = rcr_p->comp_size; 455 rdc_desc.rcr_addr = rcr_p->rcr_addr; 456 457 cfgb_p = &(rcr_p->rcr_cfgb); 458 rdc_desc.rcr_threshold = cfgb_p->bits.ldw.pthres; 459 rdc_desc.rcr_timeout = cfgb_p->bits.ldw.timeout; 460 rdc_desc.rcr_timeout_enable = cfgb_p->bits.ldw.entout; 461 462 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel: " 463 "rbr_len qlen %d pagesize code %d rcr_len %d", 464 rdc_desc.rbr_len, rdc_desc.page_size, rdc_desc.rcr_len)); 465 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel: " 466 "size 0 %d size 1 %d size 2 %d", 467 rbr_p->npi_pkt_buf_size0, rbr_p->npi_pkt_buf_size1, 468 rbr_p->npi_pkt_buf_size2)); 469 470 rs = npi_rxdma_cfg_rdc_ring(handle, rbr_p->rdc, &rdc_desc); 471 if (rs != NPI_SUCCESS) { 472 return (NXGE_ERROR | rs); 473 } 474 475 /* 476 * Enable the timeout and threshold. 477 */ 478 rs = npi_rxdma_cfg_rdc_rcr_threshold(handle, channel, 479 rdc_desc.rcr_threshold); 480 if (rs != NPI_SUCCESS) { 481 return (NXGE_ERROR | rs); 482 } 483 484 rs = npi_rxdma_cfg_rdc_rcr_timeout(handle, channel, 485 rdc_desc.rcr_timeout); 486 if (rs != NPI_SUCCESS) { 487 return (NXGE_ERROR | rs); 488 } 489 490 /* Enable the DMA */ 491 rs = npi_rxdma_cfg_rdc_enable(handle, channel); 492 if (rs != NPI_SUCCESS) { 493 return (NXGE_ERROR | rs); 494 } 495 496 /* Kick the DMA engine. */ 497 npi_rxdma_rdc_rbr_kick(handle, channel, rbr_p->rbb_max); 498 /* Clear the rbr empty bit */ 499 (void) npi_rxdma_channel_rbr_empty_clear(handle, channel); 500 501 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_enable_rxdma_channel")); 502 503 return (NXGE_OK); 504 } 505 506 nxge_status_t 507 nxge_disable_rxdma_channel(p_nxge_t nxgep, uint16_t channel) 508 { 509 npi_handle_t handle; 510 npi_status_t rs = NPI_SUCCESS; 511 512 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_disable_rxdma_channel")); 513 handle = NXGE_DEV_NPI_HANDLE(nxgep); 514 515 /* disable the DMA */ 516 rs = npi_rxdma_cfg_rdc_disable(handle, channel); 517 if (rs != NPI_SUCCESS) { 518 NXGE_DEBUG_MSG((nxgep, RX_CTL, 519 "<== nxge_disable_rxdma_channel:failed (0x%x)", 520 rs)); 521 return (NXGE_ERROR | rs); 522 } 523 524 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_disable_rxdma_channel")); 525 return (NXGE_OK); 526 } 527 528 nxge_status_t 529 nxge_rxdma_channel_rcrflush(p_nxge_t nxgep, uint8_t channel) 530 { 531 npi_handle_t handle; 532 nxge_status_t status = NXGE_OK; 533 534 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 535 "<== nxge_init_rxdma_channel_rcrflush")); 536 537 handle = NXGE_DEV_NPI_HANDLE(nxgep); 538 npi_rxdma_rdc_rcr_flush(handle, channel); 539 540 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 541 "<== nxge_init_rxdma_channel_rcrflsh")); 542 return (status); 543 544 } 545 546 #define MID_INDEX(l, r) ((r + l + 1) >> 1) 547 548 #define TO_LEFT -1 549 #define TO_RIGHT 1 550 #define BOTH_RIGHT (TO_RIGHT + TO_RIGHT) 551 #define BOTH_LEFT (TO_LEFT + TO_LEFT) 552 #define IN_MIDDLE (TO_RIGHT + TO_LEFT) 553 #define NO_HINT 0xffffffff 554 555 /*ARGSUSED*/ 556 nxge_status_t 557 nxge_rxbuf_pp_to_vp(p_nxge_t nxgep, p_rx_rbr_ring_t rbr_p, 558 uint8_t pktbufsz_type, uint64_t *pkt_buf_addr_pp, 559 uint64_t **pkt_buf_addr_p, uint32_t *bufoffset, uint32_t *msg_index) 560 { 561 int bufsize; 562 uint64_t pktbuf_pp; 563 uint64_t dvma_addr; 564 rxring_info_t *ring_info; 565 int base_side, end_side; 566 int r_index, l_index, anchor_index; 567 int found, search_done; 568 uint32_t offset, chunk_size, block_size, page_size_mask; 569 uint32_t chunk_index, block_index, total_index; 570 int max_iterations, iteration; 571 rxbuf_index_info_t *bufinfo; 572 573 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> nxge_rxbuf_pp_to_vp")); 574 575 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 576 "==> nxge_rxbuf_pp_to_vp: buf_pp $%p btype %d", 577 pkt_buf_addr_pp, 578 pktbufsz_type)); 579 #if defined(__i386) 580 pktbuf_pp = (uint64_t)(uint32_t)pkt_buf_addr_pp; 581 #else 582 pktbuf_pp = (uint64_t)pkt_buf_addr_pp; 583 #endif 584 585 switch (pktbufsz_type) { 586 case 0: 587 bufsize = rbr_p->pkt_buf_size0; 588 break; 589 case 1: 590 bufsize = rbr_p->pkt_buf_size1; 591 break; 592 case 2: 593 bufsize = rbr_p->pkt_buf_size2; 594 break; 595 case RCR_SINGLE_BLOCK: 596 bufsize = 0; 597 anchor_index = 0; 598 break; 599 default: 600 return (NXGE_ERROR); 601 } 602 603 if (rbr_p->num_blocks == 1) { 604 anchor_index = 0; 605 ring_info = rbr_p->ring_info; 606 bufinfo = (rxbuf_index_info_t *)ring_info->buffer; 607 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 608 "==> nxge_rxbuf_pp_to_vp: (found, 1 block) " 609 "buf_pp $%p btype %d anchor_index %d " 610 "bufinfo $%p", 611 pkt_buf_addr_pp, 612 pktbufsz_type, 613 anchor_index, 614 bufinfo)); 615 616 goto found_index; 617 } 618 619 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 620 "==> nxge_rxbuf_pp_to_vp: " 621 "buf_pp $%p btype %d anchor_index %d", 622 pkt_buf_addr_pp, 623 pktbufsz_type, 624 anchor_index)); 625 626 ring_info = rbr_p->ring_info; 627 found = B_FALSE; 628 bufinfo = (rxbuf_index_info_t *)ring_info->buffer; 629 iteration = 0; 630 max_iterations = ring_info->max_iterations; 631 /* 632 * First check if this block has been seen 633 * recently. This is indicated by a hint which 634 * is initialized when the first buffer of the block 635 * is seen. The hint is reset when the last buffer of 636 * the block has been processed. 637 * As three block sizes are supported, three hints 638 * are kept. The idea behind the hints is that once 639 * the hardware uses a block for a buffer of that 640 * size, it will use it exclusively for that size 641 * and will use it until it is exhausted. It is assumed 642 * that there would a single block being used for the same 643 * buffer sizes at any given time. 644 */ 645 if (ring_info->hint[pktbufsz_type] != NO_HINT) { 646 anchor_index = ring_info->hint[pktbufsz_type]; 647 dvma_addr = bufinfo[anchor_index].dvma_addr; 648 chunk_size = bufinfo[anchor_index].buf_size; 649 if ((pktbuf_pp >= dvma_addr) && 650 (pktbuf_pp < (dvma_addr + chunk_size))) { 651 found = B_TRUE; 652 /* 653 * check if this is the last buffer in the block 654 * If so, then reset the hint for the size; 655 */ 656 657 if ((pktbuf_pp + bufsize) >= (dvma_addr + chunk_size)) 658 ring_info->hint[pktbufsz_type] = NO_HINT; 659 } 660 } 661 662 if (found == B_FALSE) { 663 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 664 "==> nxge_rxbuf_pp_to_vp: (!found)" 665 "buf_pp $%p btype %d anchor_index %d", 666 pkt_buf_addr_pp, 667 pktbufsz_type, 668 anchor_index)); 669 670 /* 671 * This is the first buffer of the block of this 672 * size. Need to search the whole information 673 * array. 674 * the search algorithm uses a binary tree search 675 * algorithm. It assumes that the information is 676 * already sorted with increasing order 677 * info[0] < info[1] < info[2] .... < info[n-1] 678 * where n is the size of the information array 679 */ 680 r_index = rbr_p->num_blocks - 1; 681 l_index = 0; 682 search_done = B_FALSE; 683 anchor_index = MID_INDEX(r_index, l_index); 684 while (search_done == B_FALSE) { 685 if ((r_index == l_index) || 686 (iteration >= max_iterations)) 687 search_done = B_TRUE; 688 end_side = TO_RIGHT; /* to the right */ 689 base_side = TO_LEFT; /* to the left */ 690 /* read the DVMA address information and sort it */ 691 dvma_addr = bufinfo[anchor_index].dvma_addr; 692 chunk_size = bufinfo[anchor_index].buf_size; 693 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 694 "==> nxge_rxbuf_pp_to_vp: (searching)" 695 "buf_pp $%p btype %d " 696 "anchor_index %d chunk_size %d dvmaaddr $%p", 697 pkt_buf_addr_pp, 698 pktbufsz_type, 699 anchor_index, 700 chunk_size, 701 dvma_addr)); 702 703 if (pktbuf_pp >= dvma_addr) 704 base_side = TO_RIGHT; /* to the right */ 705 if (pktbuf_pp < (dvma_addr + chunk_size)) 706 end_side = TO_LEFT; /* to the left */ 707 708 switch (base_side + end_side) { 709 case IN_MIDDLE: 710 /* found */ 711 found = B_TRUE; 712 search_done = B_TRUE; 713 if ((pktbuf_pp + bufsize) < 714 (dvma_addr + chunk_size)) 715 ring_info->hint[pktbufsz_type] = 716 bufinfo[anchor_index].buf_index; 717 break; 718 case BOTH_RIGHT: 719 /* not found: go to the right */ 720 l_index = anchor_index + 1; 721 anchor_index = 722 MID_INDEX(r_index, l_index); 723 break; 724 725 case BOTH_LEFT: 726 /* not found: go to the left */ 727 r_index = anchor_index - 1; 728 anchor_index = MID_INDEX(r_index, 729 l_index); 730 break; 731 default: /* should not come here */ 732 return (NXGE_ERROR); 733 } 734 iteration++; 735 } 736 737 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 738 "==> nxge_rxbuf_pp_to_vp: (search done)" 739 "buf_pp $%p btype %d anchor_index %d", 740 pkt_buf_addr_pp, 741 pktbufsz_type, 742 anchor_index)); 743 } 744 745 if (found == B_FALSE) { 746 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 747 "==> nxge_rxbuf_pp_to_vp: (search failed)" 748 "buf_pp $%p btype %d anchor_index %d", 749 pkt_buf_addr_pp, 750 pktbufsz_type, 751 anchor_index)); 752 return (NXGE_ERROR); 753 } 754 755 found_index: 756 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 757 "==> nxge_rxbuf_pp_to_vp: (FOUND1)" 758 "buf_pp $%p btype %d bufsize %d anchor_index %d", 759 pkt_buf_addr_pp, 760 pktbufsz_type, 761 bufsize, 762 anchor_index)); 763 764 /* index of the first block in this chunk */ 765 chunk_index = bufinfo[anchor_index].start_index; 766 dvma_addr = bufinfo[anchor_index].dvma_addr; 767 page_size_mask = ring_info->block_size_mask; 768 769 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 770 "==> nxge_rxbuf_pp_to_vp: (FOUND3), get chunk)" 771 "buf_pp $%p btype %d bufsize %d " 772 "anchor_index %d chunk_index %d dvma $%p", 773 pkt_buf_addr_pp, 774 pktbufsz_type, 775 bufsize, 776 anchor_index, 777 chunk_index, 778 dvma_addr)); 779 780 offset = pktbuf_pp - dvma_addr; /* offset within the chunk */ 781 block_size = rbr_p->block_size; /* System block(page) size */ 782 783 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 784 "==> nxge_rxbuf_pp_to_vp: (FOUND4), get chunk)" 785 "buf_pp $%p btype %d bufsize %d " 786 "anchor_index %d chunk_index %d dvma $%p " 787 "offset %d block_size %d", 788 pkt_buf_addr_pp, 789 pktbufsz_type, 790 bufsize, 791 anchor_index, 792 chunk_index, 793 dvma_addr, 794 offset, 795 block_size)); 796 797 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> getting total index")); 798 799 block_index = (offset / block_size); /* index within chunk */ 800 total_index = chunk_index + block_index; 801 802 803 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 804 "==> nxge_rxbuf_pp_to_vp: " 805 "total_index %d dvma_addr $%p " 806 "offset %d block_size %d " 807 "block_index %d ", 808 total_index, dvma_addr, 809 offset, block_size, 810 block_index)); 811 #if defined(__i386) 812 *pkt_buf_addr_p = (uint64_t *)((uint32_t)bufinfo[anchor_index].kaddr + 813 (uint32_t)offset); 814 #else 815 *pkt_buf_addr_p = (uint64_t *)((uint64_t)bufinfo[anchor_index].kaddr + 816 (uint64_t)offset); 817 #endif 818 819 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 820 "==> nxge_rxbuf_pp_to_vp: " 821 "total_index %d dvma_addr $%p " 822 "offset %d block_size %d " 823 "block_index %d " 824 "*pkt_buf_addr_p $%p", 825 total_index, dvma_addr, 826 offset, block_size, 827 block_index, 828 *pkt_buf_addr_p)); 829 830 831 *msg_index = total_index; 832 *bufoffset = (offset & page_size_mask); 833 834 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 835 "==> nxge_rxbuf_pp_to_vp: get msg index: " 836 "msg_index %d bufoffset_index %d", 837 *msg_index, 838 *bufoffset)); 839 840 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "<== nxge_rxbuf_pp_to_vp")); 841 842 return (NXGE_OK); 843 } 844 845 /* 846 * used by quick sort (qsort) function 847 * to perform comparison 848 */ 849 static int 850 nxge_sort_compare(const void *p1, const void *p2) 851 { 852 853 rxbuf_index_info_t *a, *b; 854 855 a = (rxbuf_index_info_t *)p1; 856 b = (rxbuf_index_info_t *)p2; 857 858 if (a->dvma_addr > b->dvma_addr) 859 return (1); 860 if (a->dvma_addr < b->dvma_addr) 861 return (-1); 862 return (0); 863 } 864 865 866 867 /* 868 * grabbed this sort implementation from common/syscall/avl.c 869 * 870 */ 871 /* 872 * Generic shellsort, from K&R (1st ed, p 58.), somewhat modified. 873 * v = Ptr to array/vector of objs 874 * n = # objs in the array 875 * s = size of each obj (must be multiples of a word size) 876 * f = ptr to function to compare two objs 877 * returns (-1 = less than, 0 = equal, 1 = greater than 878 */ 879 void 880 nxge_ksort(caddr_t v, int n, int s, int (*f)()) 881 { 882 int g, i, j, ii; 883 unsigned int *p1, *p2; 884 unsigned int tmp; 885 886 /* No work to do */ 887 if (v == NULL || n <= 1) 888 return; 889 /* Sanity check on arguments */ 890 ASSERT(((uintptr_t)v & 0x3) == 0 && (s & 0x3) == 0); 891 ASSERT(s > 0); 892 893 for (g = n / 2; g > 0; g /= 2) { 894 for (i = g; i < n; i++) { 895 for (j = i - g; j >= 0 && 896 (*f)(v + j * s, v + (j + g) * s) == 1; 897 j -= g) { 898 p1 = (unsigned *)(v + j * s); 899 p2 = (unsigned *)(v + (j + g) * s); 900 for (ii = 0; ii < s / 4; ii++) { 901 tmp = *p1; 902 *p1++ = *p2; 903 *p2++ = tmp; 904 } 905 } 906 } 907 } 908 } 909 910 /* 911 * Initialize data structures required for rxdma 912 * buffer dvma->vmem address lookup 913 */ 914 /*ARGSUSED*/ 915 static nxge_status_t 916 nxge_rxbuf_index_info_init(p_nxge_t nxgep, p_rx_rbr_ring_t rbrp) 917 { 918 919 int index; 920 rxring_info_t *ring_info; 921 int max_iteration = 0, max_index = 0; 922 923 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_rxbuf_index_info_init")); 924 925 ring_info = rbrp->ring_info; 926 ring_info->hint[0] = NO_HINT; 927 ring_info->hint[1] = NO_HINT; 928 ring_info->hint[2] = NO_HINT; 929 max_index = rbrp->num_blocks; 930 931 /* read the DVMA address information and sort it */ 932 /* do init of the information array */ 933 934 935 NXGE_DEBUG_MSG((nxgep, DMA2_CTL, 936 " nxge_rxbuf_index_info_init Sort ptrs")); 937 938 /* sort the array */ 939 nxge_ksort((void *)ring_info->buffer, max_index, 940 sizeof (rxbuf_index_info_t), nxge_sort_compare); 941 942 943 944 for (index = 0; index < max_index; index++) { 945 NXGE_DEBUG_MSG((nxgep, DMA2_CTL, 946 " nxge_rxbuf_index_info_init: sorted chunk %d " 947 " ioaddr $%p kaddr $%p size %x", 948 index, ring_info->buffer[index].dvma_addr, 949 ring_info->buffer[index].kaddr, 950 ring_info->buffer[index].buf_size)); 951 } 952 953 max_iteration = 0; 954 while (max_index >= (1ULL << max_iteration)) 955 max_iteration++; 956 ring_info->max_iterations = max_iteration + 1; 957 NXGE_DEBUG_MSG((nxgep, DMA2_CTL, 958 " nxge_rxbuf_index_info_init Find max iter %d", 959 ring_info->max_iterations)); 960 961 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxbuf_index_info_init")); 962 return (NXGE_OK); 963 } 964 965 /* ARGSUSED */ 966 void 967 nxge_dump_rcr_entry(p_nxge_t nxgep, p_rcr_entry_t entry_p) 968 { 969 #ifdef NXGE_DEBUG 970 971 uint32_t bptr; 972 uint64_t pp; 973 974 bptr = entry_p->bits.hdw.pkt_buf_addr; 975 976 NXGE_DEBUG_MSG((nxgep, RX_CTL, 977 "\trcr entry $%p " 978 "\trcr entry 0x%0llx " 979 "\trcr entry 0x%08x " 980 "\trcr entry 0x%08x " 981 "\tvalue 0x%0llx\n" 982 "\tmulti = %d\n" 983 "\tpkt_type = 0x%x\n" 984 "\tzero_copy = %d\n" 985 "\tnoport = %d\n" 986 "\tpromis = %d\n" 987 "\terror = 0x%04x\n" 988 "\tdcf_err = 0x%01x\n" 989 "\tl2_len = %d\n" 990 "\tpktbufsize = %d\n" 991 "\tpkt_buf_addr = $%p\n" 992 "\tpkt_buf_addr (<< 6) = $%p\n", 993 entry_p, 994 *(int64_t *)entry_p, 995 *(int32_t *)entry_p, 996 *(int32_t *)((char *)entry_p + 32), 997 entry_p->value, 998 entry_p->bits.hdw.multi, 999 entry_p->bits.hdw.pkt_type, 1000 entry_p->bits.hdw.zero_copy, 1001 entry_p->bits.hdw.noport, 1002 entry_p->bits.hdw.promis, 1003 entry_p->bits.hdw.error, 1004 entry_p->bits.hdw.dcf_err, 1005 entry_p->bits.hdw.l2_len, 1006 entry_p->bits.hdw.pktbufsz, 1007 bptr, 1008 entry_p->bits.ldw.pkt_buf_addr)); 1009 1010 pp = (entry_p->value & RCR_PKT_BUF_ADDR_MASK) << 1011 RCR_PKT_BUF_ADDR_SHIFT; 1012 1013 NXGE_DEBUG_MSG((nxgep, RX_CTL, "rcr pp 0x%llx l2 len %d", 1014 pp, (*(int64_t *)entry_p >> 40) & 0x3fff)); 1015 #endif 1016 } 1017 1018 void 1019 nxge_rxdma_regs_dump(p_nxge_t nxgep, int rdc) 1020 { 1021 npi_handle_t handle; 1022 rbr_stat_t rbr_stat; 1023 addr44_t hd_addr; 1024 addr44_t tail_addr; 1025 uint16_t qlen; 1026 1027 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1028 "==> nxge_rxdma_regs_dump: rdc channel %d", rdc)); 1029 1030 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1031 1032 /* RBR head */ 1033 hd_addr.addr = 0; 1034 (void) npi_rxdma_rdc_rbr_head_get(handle, rdc, &hd_addr); 1035 #if defined(__i386) 1036 printf("nxge_rxdma_regs_dump: got hdptr $%p \n", 1037 (void *)(uint32_t)hd_addr.addr); 1038 #else 1039 printf("nxge_rxdma_regs_dump: got hdptr $%p \n", 1040 (void *)hd_addr.addr); 1041 #endif 1042 1043 /* RBR stats */ 1044 (void) npi_rxdma_rdc_rbr_stat_get(handle, rdc, &rbr_stat); 1045 printf("nxge_rxdma_regs_dump: rbr len %d \n", rbr_stat.bits.ldw.qlen); 1046 1047 /* RCR tail */ 1048 tail_addr.addr = 0; 1049 (void) npi_rxdma_rdc_rcr_tail_get(handle, rdc, &tail_addr); 1050 #if defined(__i386) 1051 printf("nxge_rxdma_regs_dump: got tail ptr $%p \n", 1052 (void *)(uint32_t)tail_addr.addr); 1053 #else 1054 printf("nxge_rxdma_regs_dump: got tail ptr $%p \n", 1055 (void *)tail_addr.addr); 1056 #endif 1057 1058 /* RCR qlen */ 1059 (void) npi_rxdma_rdc_rcr_qlen_get(handle, rdc, &qlen); 1060 printf("nxge_rxdma_regs_dump: rcr len %x \n", qlen); 1061 1062 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1063 "<== nxge_rxdma_regs_dump: rdc rdc %d", rdc)); 1064 } 1065 1066 void 1067 nxge_rxdma_stop(p_nxge_t nxgep) 1068 { 1069 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop")); 1070 1071 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 1072 (void) nxge_rx_mac_disable(nxgep); 1073 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP); 1074 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_stop")); 1075 } 1076 1077 void 1078 nxge_rxdma_stop_reinit(p_nxge_t nxgep) 1079 { 1080 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop_reinit")); 1081 1082 (void) nxge_rxdma_stop(nxgep); 1083 (void) nxge_uninit_rxdma_channels(nxgep); 1084 (void) nxge_init_rxdma_channels(nxgep); 1085 1086 #ifndef AXIS_DEBUG_LB 1087 (void) nxge_xcvr_init(nxgep); 1088 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 1089 #endif 1090 (void) nxge_rx_mac_enable(nxgep); 1091 1092 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_stop_reinit")); 1093 } 1094 1095 nxge_status_t 1096 nxge_rxdma_hw_mode(p_nxge_t nxgep, boolean_t enable) 1097 { 1098 int i, ndmas; 1099 uint16_t channel; 1100 p_rx_rbr_rings_t rx_rbr_rings; 1101 p_rx_rbr_ring_t *rbr_rings; 1102 npi_handle_t handle; 1103 npi_status_t rs = NPI_SUCCESS; 1104 nxge_status_t status = NXGE_OK; 1105 1106 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1107 "==> nxge_rxdma_hw_mode: mode %d", enable)); 1108 1109 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 1110 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1111 "<== nxge_rxdma_mode: not initialized")); 1112 return (NXGE_ERROR); 1113 } 1114 1115 rx_rbr_rings = nxgep->rx_rbr_rings; 1116 if (rx_rbr_rings == NULL) { 1117 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1118 "<== nxge_rxdma_mode: NULL ring pointer")); 1119 return (NXGE_ERROR); 1120 } 1121 if (rx_rbr_rings->rbr_rings == NULL) { 1122 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1123 "<== nxge_rxdma_mode: NULL rbr rings pointer")); 1124 return (NXGE_ERROR); 1125 } 1126 1127 ndmas = rx_rbr_rings->ndmas; 1128 if (!ndmas) { 1129 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1130 "<== nxge_rxdma_mode: no channel")); 1131 return (NXGE_ERROR); 1132 } 1133 1134 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1135 "==> nxge_rxdma_mode (ndmas %d)", ndmas)); 1136 1137 rbr_rings = rx_rbr_rings->rbr_rings; 1138 1139 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1140 for (i = 0; i < ndmas; i++) { 1141 if (rbr_rings == NULL || rbr_rings[i] == NULL) { 1142 continue; 1143 } 1144 channel = rbr_rings[i]->rdc; 1145 if (enable) { 1146 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1147 "==> nxge_rxdma_hw_mode: channel %d (enable)", 1148 channel)); 1149 rs = npi_rxdma_cfg_rdc_enable(handle, channel); 1150 } else { 1151 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1152 "==> nxge_rxdma_hw_mode: channel %d (disable)", 1153 channel)); 1154 rs = npi_rxdma_cfg_rdc_disable(handle, channel); 1155 } 1156 } 1157 1158 status = ((rs == NPI_SUCCESS) ? NXGE_OK : NXGE_ERROR | rs); 1159 1160 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1161 "<== nxge_rxdma_hw_mode: status 0x%x", status)); 1162 1163 return (status); 1164 } 1165 1166 void 1167 nxge_rxdma_enable_channel(p_nxge_t nxgep, uint16_t channel) 1168 { 1169 npi_handle_t handle; 1170 1171 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 1172 "==> nxge_rxdma_enable_channel: channel %d", channel)); 1173 1174 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1175 (void) npi_rxdma_cfg_rdc_enable(handle, channel); 1176 1177 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxdma_enable_channel")); 1178 } 1179 1180 void 1181 nxge_rxdma_disable_channel(p_nxge_t nxgep, uint16_t channel) 1182 { 1183 npi_handle_t handle; 1184 1185 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 1186 "==> nxge_rxdma_disable_channel: channel %d", channel)); 1187 1188 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1189 (void) npi_rxdma_cfg_rdc_disable(handle, channel); 1190 1191 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxdma_disable_channel")); 1192 } 1193 1194 void 1195 nxge_hw_start_rx(p_nxge_t nxgep) 1196 { 1197 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_start_rx")); 1198 1199 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_START); 1200 (void) nxge_rx_mac_enable(nxgep); 1201 1202 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_start_rx")); 1203 } 1204 1205 /*ARGSUSED*/ 1206 void 1207 nxge_fixup_rxdma_rings(p_nxge_t nxgep) 1208 { 1209 int i, ndmas; 1210 uint16_t rdc; 1211 p_rx_rbr_rings_t rx_rbr_rings; 1212 p_rx_rbr_ring_t *rbr_rings; 1213 p_rx_rcr_rings_t rx_rcr_rings; 1214 1215 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_fixup_rxdma_rings")); 1216 1217 rx_rbr_rings = nxgep->rx_rbr_rings; 1218 if (rx_rbr_rings == NULL) { 1219 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1220 "<== nxge_fixup_rxdma_rings: NULL ring pointer")); 1221 return; 1222 } 1223 ndmas = rx_rbr_rings->ndmas; 1224 if (!ndmas) { 1225 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1226 "<== nxge_fixup_rxdma_rings: no channel")); 1227 return; 1228 } 1229 1230 rx_rcr_rings = nxgep->rx_rcr_rings; 1231 if (rx_rcr_rings == NULL) { 1232 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1233 "<== nxge_fixup_rxdma_rings: NULL ring pointer")); 1234 return; 1235 } 1236 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1237 "==> nxge_fixup_rxdma_rings (ndmas %d)", ndmas)); 1238 1239 nxge_rxdma_hw_stop(nxgep); 1240 1241 rbr_rings = rx_rbr_rings->rbr_rings; 1242 for (i = 0; i < ndmas; i++) { 1243 rdc = rbr_rings[i]->rdc; 1244 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1245 "==> nxge_fixup_rxdma_rings: channel %d " 1246 "ring $%px", rdc, rbr_rings[i])); 1247 (void) nxge_rxdma_fixup_channel(nxgep, rdc, i); 1248 } 1249 1250 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_fixup_rxdma_rings")); 1251 } 1252 1253 void 1254 nxge_rxdma_fix_channel(p_nxge_t nxgep, uint16_t channel) 1255 { 1256 int i; 1257 1258 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_fix_channel")); 1259 i = nxge_rxdma_get_ring_index(nxgep, channel); 1260 if (i < 0) { 1261 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1262 "<== nxge_rxdma_fix_channel: no entry found")); 1263 return; 1264 } 1265 1266 nxge_rxdma_fixup_channel(nxgep, channel, i); 1267 1268 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_txdma_fix_channel")); 1269 } 1270 1271 void 1272 nxge_rxdma_fixup_channel(p_nxge_t nxgep, uint16_t channel, int entry) 1273 { 1274 int ndmas; 1275 p_rx_rbr_rings_t rx_rbr_rings; 1276 p_rx_rbr_ring_t *rbr_rings; 1277 p_rx_rcr_rings_t rx_rcr_rings; 1278 p_rx_rcr_ring_t *rcr_rings; 1279 p_rx_mbox_areas_t rx_mbox_areas_p; 1280 p_rx_mbox_t *rx_mbox_p; 1281 p_nxge_dma_pool_t dma_buf_poolp; 1282 p_nxge_dma_pool_t dma_cntl_poolp; 1283 p_rx_rbr_ring_t rbrp; 1284 p_rx_rcr_ring_t rcrp; 1285 p_rx_mbox_t mboxp; 1286 p_nxge_dma_common_t dmap; 1287 nxge_status_t status = NXGE_OK; 1288 1289 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_fixup_channel")); 1290 1291 (void) nxge_rxdma_stop_channel(nxgep, channel); 1292 1293 dma_buf_poolp = nxgep->rx_buf_pool_p; 1294 dma_cntl_poolp = nxgep->rx_cntl_pool_p; 1295 1296 if (!dma_buf_poolp->buf_allocated || !dma_cntl_poolp->buf_allocated) { 1297 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1298 "<== nxge_rxdma_fixup_channel: buf not allocated")); 1299 return; 1300 } 1301 1302 ndmas = dma_buf_poolp->ndmas; 1303 if (!ndmas) { 1304 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1305 "<== nxge_rxdma_fixup_channel: no dma allocated")); 1306 return; 1307 } 1308 1309 rx_rbr_rings = nxgep->rx_rbr_rings; 1310 rx_rcr_rings = nxgep->rx_rcr_rings; 1311 rbr_rings = rx_rbr_rings->rbr_rings; 1312 rcr_rings = rx_rcr_rings->rcr_rings; 1313 rx_mbox_areas_p = nxgep->rx_mbox_areas_p; 1314 rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 1315 1316 /* Reinitialize the receive block and completion rings */ 1317 rbrp = (p_rx_rbr_ring_t)rbr_rings[entry], 1318 rcrp = (p_rx_rcr_ring_t)rcr_rings[entry], 1319 mboxp = (p_rx_mbox_t)rx_mbox_p[entry]; 1320 1321 1322 rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 1323 rbrp->rbr_rd_index = 0; 1324 rcrp->comp_rd_index = 0; 1325 rcrp->comp_wt_index = 0; 1326 1327 dmap = (p_nxge_dma_common_t)&rcrp->rcr_desc; 1328 bzero((caddr_t)dmap->kaddrp, dmap->alength); 1329 1330 status = nxge_rxdma_start_channel(nxgep, channel, 1331 rbrp, rcrp, mboxp); 1332 if (status != NXGE_OK) { 1333 goto nxge_rxdma_fixup_channel_fail; 1334 } 1335 if (status != NXGE_OK) { 1336 goto nxge_rxdma_fixup_channel_fail; 1337 } 1338 1339 nxge_rxdma_fixup_channel_fail: 1340 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1341 "==> nxge_rxdma_fixup_channel: failed (0x%08x)", status)); 1342 1343 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_fixup_channel")); 1344 } 1345 1346 int 1347 nxge_rxdma_get_ring_index(p_nxge_t nxgep, uint16_t channel) 1348 { 1349 int i, ndmas; 1350 uint16_t rdc; 1351 p_rx_rbr_rings_t rx_rbr_rings; 1352 p_rx_rbr_ring_t *rbr_rings; 1353 1354 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1355 "==> nxge_rxdma_get_ring_index: channel %d", channel)); 1356 1357 rx_rbr_rings = nxgep->rx_rbr_rings; 1358 if (rx_rbr_rings == NULL) { 1359 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1360 "<== nxge_rxdma_get_ring_index: NULL ring pointer")); 1361 return (-1); 1362 } 1363 ndmas = rx_rbr_rings->ndmas; 1364 if (!ndmas) { 1365 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1366 "<== nxge_rxdma_get_ring_index: no channel")); 1367 return (-1); 1368 } 1369 1370 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1371 "==> nxge_rxdma_get_ring_index (ndmas %d)", ndmas)); 1372 1373 rbr_rings = rx_rbr_rings->rbr_rings; 1374 for (i = 0; i < ndmas; i++) { 1375 rdc = rbr_rings[i]->rdc; 1376 if (channel == rdc) { 1377 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1378 "==> nxge_rxdma_get_rbr_ring: " 1379 "channel %d (index %d) " 1380 "ring %d", channel, i, 1381 rbr_rings[i])); 1382 return (i); 1383 } 1384 } 1385 1386 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1387 "<== nxge_rxdma_get_rbr_ring_index: not found")); 1388 1389 return (-1); 1390 } 1391 1392 p_rx_rbr_ring_t 1393 nxge_rxdma_get_rbr_ring(p_nxge_t nxgep, uint16_t channel) 1394 { 1395 int i, ndmas; 1396 uint16_t rdc; 1397 p_rx_rbr_rings_t rx_rbr_rings; 1398 p_rx_rbr_ring_t *rbr_rings; 1399 1400 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1401 "==> nxge_rxdma_get_rbr_ring: channel %d", channel)); 1402 1403 rx_rbr_rings = nxgep->rx_rbr_rings; 1404 if (rx_rbr_rings == NULL) { 1405 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1406 "<== nxge_rxdma_get_rbr_ring: NULL ring pointer")); 1407 return (NULL); 1408 } 1409 ndmas = rx_rbr_rings->ndmas; 1410 if (!ndmas) { 1411 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1412 "<== nxge_rxdma_get_rbr_ring: no channel")); 1413 return (NULL); 1414 } 1415 1416 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1417 "==> nxge_rxdma_get_ring (ndmas %d)", ndmas)); 1418 1419 rbr_rings = rx_rbr_rings->rbr_rings; 1420 for (i = 0; i < ndmas; i++) { 1421 rdc = rbr_rings[i]->rdc; 1422 if (channel == rdc) { 1423 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1424 "==> nxge_rxdma_get_rbr_ring: channel %d " 1425 "ring $%p", channel, rbr_rings[i])); 1426 return (rbr_rings[i]); 1427 } 1428 } 1429 1430 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1431 "<== nxge_rxdma_get_rbr_ring: not found")); 1432 1433 return (NULL); 1434 } 1435 1436 p_rx_rcr_ring_t 1437 nxge_rxdma_get_rcr_ring(p_nxge_t nxgep, uint16_t channel) 1438 { 1439 int i, ndmas; 1440 uint16_t rdc; 1441 p_rx_rcr_rings_t rx_rcr_rings; 1442 p_rx_rcr_ring_t *rcr_rings; 1443 1444 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1445 "==> nxge_rxdma_get_rcr_ring: channel %d", channel)); 1446 1447 rx_rcr_rings = nxgep->rx_rcr_rings; 1448 if (rx_rcr_rings == NULL) { 1449 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1450 "<== nxge_rxdma_get_rcr_ring: NULL ring pointer")); 1451 return (NULL); 1452 } 1453 ndmas = rx_rcr_rings->ndmas; 1454 if (!ndmas) { 1455 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1456 "<== nxge_rxdma_get_rcr_ring: no channel")); 1457 return (NULL); 1458 } 1459 1460 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1461 "==> nxge_rxdma_get_rcr_ring (ndmas %d)", ndmas)); 1462 1463 rcr_rings = rx_rcr_rings->rcr_rings; 1464 for (i = 0; i < ndmas; i++) { 1465 rdc = rcr_rings[i]->rdc; 1466 if (channel == rdc) { 1467 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1468 "==> nxge_rxdma_get_rcr_ring: channel %d " 1469 "ring $%p", channel, rcr_rings[i])); 1470 return (rcr_rings[i]); 1471 } 1472 } 1473 1474 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1475 "<== nxge_rxdma_get_rcr_ring: not found")); 1476 1477 return (NULL); 1478 } 1479 1480 /* 1481 * Static functions start here. 1482 */ 1483 static p_rx_msg_t 1484 nxge_allocb(size_t size, uint32_t pri, p_nxge_dma_common_t dmabuf_p) 1485 { 1486 p_rx_msg_t nxge_mp = NULL; 1487 p_nxge_dma_common_t dmamsg_p; 1488 uchar_t *buffer; 1489 1490 nxge_mp = KMEM_ZALLOC(sizeof (rx_msg_t), KM_NOSLEEP); 1491 if (nxge_mp == NULL) { 1492 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 1493 "Allocation of a rx msg failed.")); 1494 goto nxge_allocb_exit; 1495 } 1496 1497 nxge_mp->use_buf_pool = B_FALSE; 1498 if (dmabuf_p) { 1499 nxge_mp->use_buf_pool = B_TRUE; 1500 dmamsg_p = (p_nxge_dma_common_t)&nxge_mp->buf_dma; 1501 *dmamsg_p = *dmabuf_p; 1502 dmamsg_p->nblocks = 1; 1503 dmamsg_p->block_size = size; 1504 dmamsg_p->alength = size; 1505 buffer = (uchar_t *)dmabuf_p->kaddrp; 1506 1507 dmabuf_p->kaddrp = (void *) 1508 ((char *)dmabuf_p->kaddrp + size); 1509 dmabuf_p->ioaddr_pp = (void *) 1510 ((char *)dmabuf_p->ioaddr_pp + size); 1511 dmabuf_p->alength -= size; 1512 dmabuf_p->offset += size; 1513 dmabuf_p->dma_cookie.dmac_laddress += size; 1514 dmabuf_p->dma_cookie.dmac_size -= size; 1515 1516 } else { 1517 buffer = KMEM_ALLOC(size, KM_NOSLEEP); 1518 if (buffer == NULL) { 1519 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 1520 "Allocation of a receive page failed.")); 1521 goto nxge_allocb_fail1; 1522 } 1523 } 1524 1525 nxge_mp->rx_mblk_p = desballoc(buffer, size, pri, &nxge_mp->freeb); 1526 if (nxge_mp->rx_mblk_p == NULL) { 1527 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, "desballoc failed.")); 1528 goto nxge_allocb_fail2; 1529 } 1530 1531 nxge_mp->buffer = buffer; 1532 nxge_mp->block_size = size; 1533 nxge_mp->freeb.free_func = (void (*)())nxge_freeb; 1534 nxge_mp->freeb.free_arg = (caddr_t)nxge_mp; 1535 nxge_mp->ref_cnt = 1; 1536 nxge_mp->free = B_TRUE; 1537 nxge_mp->rx_use_bcopy = B_FALSE; 1538 1539 atomic_inc_32(&nxge_mblks_pending); 1540 1541 goto nxge_allocb_exit; 1542 1543 nxge_allocb_fail2: 1544 if (!nxge_mp->use_buf_pool) { 1545 KMEM_FREE(buffer, size); 1546 } 1547 1548 nxge_allocb_fail1: 1549 KMEM_FREE(nxge_mp, sizeof (rx_msg_t)); 1550 nxge_mp = NULL; 1551 1552 nxge_allocb_exit: 1553 return (nxge_mp); 1554 } 1555 1556 p_mblk_t 1557 nxge_dupb(p_rx_msg_t nxge_mp, uint_t offset, size_t size) 1558 { 1559 p_mblk_t mp; 1560 1561 NXGE_DEBUG_MSG((NULL, MEM_CTL, "==> nxge_dupb")); 1562 NXGE_DEBUG_MSG((NULL, MEM_CTL, "nxge_mp = $%p " 1563 "offset = 0x%08X " 1564 "size = 0x%08X", 1565 nxge_mp, offset, size)); 1566 1567 mp = desballoc(&nxge_mp->buffer[offset], size, 1568 0, &nxge_mp->freeb); 1569 if (mp == NULL) { 1570 NXGE_DEBUG_MSG((NULL, RX_CTL, "desballoc failed")); 1571 goto nxge_dupb_exit; 1572 } 1573 atomic_inc_32(&nxge_mp->ref_cnt); 1574 atomic_inc_32(&nxge_mblks_pending); 1575 1576 1577 nxge_dupb_exit: 1578 NXGE_DEBUG_MSG((NULL, MEM_CTL, "<== nxge_dupb mp = $%p", 1579 nxge_mp)); 1580 return (mp); 1581 } 1582 1583 p_mblk_t 1584 nxge_dupb_bcopy(p_rx_msg_t nxge_mp, uint_t offset, size_t size) 1585 { 1586 p_mblk_t mp; 1587 uchar_t *dp; 1588 1589 mp = allocb(size + NXGE_RXBUF_EXTRA, 0); 1590 if (mp == NULL) { 1591 NXGE_DEBUG_MSG((NULL, RX_CTL, "desballoc failed")); 1592 goto nxge_dupb_bcopy_exit; 1593 } 1594 dp = mp->b_rptr = mp->b_rptr + NXGE_RXBUF_EXTRA; 1595 bcopy((void *)&nxge_mp->buffer[offset], dp, size); 1596 mp->b_wptr = dp + size; 1597 1598 nxge_dupb_bcopy_exit: 1599 NXGE_DEBUG_MSG((NULL, MEM_CTL, "<== nxge_dupb mp = $%p", 1600 nxge_mp)); 1601 return (mp); 1602 } 1603 1604 void nxge_post_page(p_nxge_t nxgep, p_rx_rbr_ring_t rx_rbr_p, 1605 p_rx_msg_t rx_msg_p); 1606 1607 void 1608 nxge_post_page(p_nxge_t nxgep, p_rx_rbr_ring_t rx_rbr_p, p_rx_msg_t rx_msg_p) 1609 { 1610 1611 npi_handle_t handle; 1612 1613 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_post_page")); 1614 1615 /* Reuse this buffer */ 1616 rx_msg_p->free = B_FALSE; 1617 rx_msg_p->cur_usage_cnt = 0; 1618 rx_msg_p->max_usage_cnt = 0; 1619 rx_msg_p->pkt_buf_size = 0; 1620 1621 if (rx_rbr_p->rbr_use_bcopy) { 1622 rx_msg_p->rx_use_bcopy = B_FALSE; 1623 atomic_dec_32(&rx_rbr_p->rbr_consumed); 1624 } 1625 1626 /* 1627 * Get the rbr header pointer and its offset index. 1628 */ 1629 MUTEX_ENTER(&rx_rbr_p->post_lock); 1630 1631 1632 rx_rbr_p->rbr_wr_index = ((rx_rbr_p->rbr_wr_index + 1) & 1633 rx_rbr_p->rbr_wrap_mask); 1634 rx_rbr_p->rbr_desc_vp[rx_rbr_p->rbr_wr_index] = rx_msg_p->shifted_addr; 1635 MUTEX_EXIT(&rx_rbr_p->post_lock); 1636 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1637 npi_rxdma_rdc_rbr_kick(handle, rx_rbr_p->rdc, 1); 1638 1639 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1640 "<== nxge_post_page (channel %d post_next_index %d)", 1641 rx_rbr_p->rdc, rx_rbr_p->rbr_wr_index)); 1642 1643 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_post_page")); 1644 } 1645 1646 void 1647 nxge_freeb(p_rx_msg_t rx_msg_p) 1648 { 1649 size_t size; 1650 uchar_t *buffer = NULL; 1651 int ref_cnt; 1652 boolean_t free_state = B_FALSE; 1653 1654 rx_rbr_ring_t *ring = rx_msg_p->rx_rbr_p; 1655 1656 NXGE_DEBUG_MSG((NULL, MEM2_CTL, "==> nxge_freeb")); 1657 NXGE_DEBUG_MSG((NULL, MEM2_CTL, 1658 "nxge_freeb:rx_msg_p = $%p (block pending %d)", 1659 rx_msg_p, nxge_mblks_pending)); 1660 1661 atomic_dec_32(&nxge_mblks_pending); 1662 /* 1663 * First we need to get the free state, then 1664 * atomic decrement the reference count to prevent 1665 * the race condition with the interrupt thread that 1666 * is processing a loaned up buffer block. 1667 */ 1668 free_state = rx_msg_p->free; 1669 ref_cnt = atomic_add_32_nv(&rx_msg_p->ref_cnt, -1); 1670 if (!ref_cnt) { 1671 buffer = rx_msg_p->buffer; 1672 size = rx_msg_p->block_size; 1673 NXGE_DEBUG_MSG((NULL, MEM2_CTL, "nxge_freeb: " 1674 "will free: rx_msg_p = $%p (block pending %d)", 1675 rx_msg_p, nxge_mblks_pending)); 1676 1677 if (!rx_msg_p->use_buf_pool) { 1678 KMEM_FREE(buffer, size); 1679 } 1680 1681 KMEM_FREE(rx_msg_p, sizeof (rx_msg_t)); 1682 1683 /* Decrement the receive buffer ring's reference count, too. */ 1684 atomic_dec_32(&ring->rbr_ref_cnt); 1685 1686 /* 1687 * Free the receive buffer ring, iff 1688 * 1. all the receive buffers have been freed 1689 * 2. and we are in the proper state (that is, 1690 * we are not UNMAPPING). 1691 */ 1692 if (ring->rbr_ref_cnt == 0 && 1693 ring->rbr_state == RBR_UNMAPPED) { 1694 KMEM_FREE(ring, sizeof (*ring)); 1695 } 1696 return; 1697 } 1698 1699 /* 1700 * Repost buffer. 1701 */ 1702 if (free_state && (ref_cnt == 1)) { 1703 NXGE_DEBUG_MSG((NULL, RX_CTL, 1704 "nxge_freeb: post page $%p:", rx_msg_p)); 1705 if (ring->rbr_state == RBR_POSTING) 1706 nxge_post_page(rx_msg_p->nxgep, ring, rx_msg_p); 1707 } 1708 1709 NXGE_DEBUG_MSG((NULL, MEM2_CTL, "<== nxge_freeb")); 1710 } 1711 1712 uint_t 1713 nxge_rx_intr(void *arg1, void *arg2) 1714 { 1715 p_nxge_ldv_t ldvp = (p_nxge_ldv_t)arg1; 1716 p_nxge_t nxgep = (p_nxge_t)arg2; 1717 p_nxge_ldg_t ldgp; 1718 uint8_t channel; 1719 npi_handle_t handle; 1720 rx_dma_ctl_stat_t cs; 1721 1722 #ifdef NXGE_DEBUG 1723 rxdma_cfig1_t cfg; 1724 #endif 1725 uint_t serviced = DDI_INTR_UNCLAIMED; 1726 1727 if (ldvp == NULL) { 1728 NXGE_DEBUG_MSG((NULL, INT_CTL, 1729 "<== nxge_rx_intr: arg2 $%p arg1 $%p", 1730 nxgep, ldvp)); 1731 1732 return (DDI_INTR_CLAIMED); 1733 } 1734 1735 if (arg2 == NULL || (void *)ldvp->nxgep != arg2) { 1736 nxgep = ldvp->nxgep; 1737 } 1738 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1739 "==> nxge_rx_intr: arg2 $%p arg1 $%p", 1740 nxgep, ldvp)); 1741 1742 /* 1743 * This interrupt handler is for a specific 1744 * receive dma channel. 1745 */ 1746 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1747 /* 1748 * Get the control and status for this channel. 1749 */ 1750 channel = ldvp->channel; 1751 ldgp = ldvp->ldgp; 1752 RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, channel, &cs.value); 1753 1754 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_intr:channel %d " 1755 "cs 0x%016llx rcrto 0x%x rcrthres %x", 1756 channel, 1757 cs.value, 1758 cs.bits.hdw.rcrto, 1759 cs.bits.hdw.rcrthres)); 1760 1761 nxge_rx_pkts_vring(nxgep, ldvp->vdma_index, ldvp, cs); 1762 serviced = DDI_INTR_CLAIMED; 1763 1764 /* error events. */ 1765 if (cs.value & RX_DMA_CTL_STAT_ERROR) { 1766 (void) nxge_rx_err_evnts(nxgep, ldvp->vdma_index, ldvp, cs); 1767 } 1768 1769 nxge_intr_exit: 1770 1771 1772 /* 1773 * Enable the mailbox update interrupt if we want 1774 * to use mailbox. We probably don't need to use 1775 * mailbox as it only saves us one pio read. 1776 * Also write 1 to rcrthres and rcrto to clear 1777 * these two edge triggered bits. 1778 */ 1779 1780 cs.value &= RX_DMA_CTL_STAT_WR1C; 1781 cs.bits.hdw.mex = 1; 1782 RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, channel, 1783 cs.value); 1784 1785 /* 1786 * Rearm this logical group if this is a single device 1787 * group. 1788 */ 1789 if (ldgp->nldvs == 1) { 1790 ldgimgm_t mgm; 1791 mgm.value = 0; 1792 mgm.bits.ldw.arm = 1; 1793 mgm.bits.ldw.timer = ldgp->ldg_timer; 1794 NXGE_REG_WR64(handle, 1795 LDGIMGN_REG + LDSV_OFFSET(ldgp->ldg), 1796 mgm.value); 1797 } 1798 1799 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rx_intr: serviced %d", 1800 serviced)); 1801 return (serviced); 1802 } 1803 1804 /* 1805 * Process the packets received in the specified logical device 1806 * and pass up a chain of message blocks to the upper layer. 1807 */ 1808 static void 1809 nxge_rx_pkts_vring(p_nxge_t nxgep, uint_t vindex, p_nxge_ldv_t ldvp, 1810 rx_dma_ctl_stat_t cs) 1811 { 1812 p_mblk_t mp; 1813 p_rx_rcr_ring_t rcrp; 1814 1815 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts_vring")); 1816 if ((mp = nxge_rx_pkts(nxgep, vindex, ldvp, &rcrp, cs)) == NULL) { 1817 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1818 "<== nxge_rx_pkts_vring: no mp")); 1819 return; 1820 } 1821 1822 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts_vring: $%p", 1823 mp)); 1824 1825 #ifdef NXGE_DEBUG 1826 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1827 "==> nxge_rx_pkts_vring:calling mac_rx " 1828 "LEN %d mp $%p mp->b_cont $%p mp->b_next $%p rcrp $%p " 1829 "mac_handle $%p", 1830 mp->b_wptr - mp->b_rptr, 1831 mp, mp->b_cont, mp->b_next, 1832 rcrp, rcrp->rcr_mac_handle)); 1833 1834 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1835 "==> nxge_rx_pkts_vring: dump packets " 1836 "(mp $%p b_rptr $%p b_wptr $%p):\n %s", 1837 mp, 1838 mp->b_rptr, 1839 mp->b_wptr, 1840 nxge_dump_packet((char *)mp->b_rptr, 1841 mp->b_wptr - mp->b_rptr))); 1842 if (mp->b_cont) { 1843 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1844 "==> nxge_rx_pkts_vring: dump b_cont packets " 1845 "(mp->b_cont $%p b_rptr $%p b_wptr $%p):\n %s", 1846 mp->b_cont, 1847 mp->b_cont->b_rptr, 1848 mp->b_cont->b_wptr, 1849 nxge_dump_packet((char *)mp->b_cont->b_rptr, 1850 mp->b_cont->b_wptr - mp->b_cont->b_rptr))); 1851 } 1852 if (mp->b_next) { 1853 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1854 "==> nxge_rx_pkts_vring: dump next packets " 1855 "(b_rptr $%p): %s", 1856 mp->b_next->b_rptr, 1857 nxge_dump_packet((char *)mp->b_next->b_rptr, 1858 mp->b_next->b_wptr - mp->b_next->b_rptr))); 1859 } 1860 #endif 1861 1862 mac_rx(nxgep->mach, rcrp->rcr_mac_handle, mp); 1863 } 1864 1865 1866 /* 1867 * This routine is the main packet receive processing function. 1868 * It gets the packet type, error code, and buffer related 1869 * information from the receive completion entry. 1870 * How many completion entries to process is based on the number of packets 1871 * queued by the hardware, a hardware maintained tail pointer 1872 * and a configurable receive packet count. 1873 * 1874 * A chain of message blocks will be created as result of processing 1875 * the completion entries. This chain of message blocks will be returned and 1876 * a hardware control status register will be updated with the number of 1877 * packets were removed from the hardware queue. 1878 * 1879 */ 1880 mblk_t * 1881 nxge_rx_pkts(p_nxge_t nxgep, uint_t vindex, p_nxge_ldv_t ldvp, 1882 p_rx_rcr_ring_t *rcrp, rx_dma_ctl_stat_t cs) 1883 { 1884 npi_handle_t handle; 1885 uint8_t channel; 1886 p_rx_rcr_rings_t rx_rcr_rings; 1887 p_rx_rcr_ring_t rcr_p; 1888 uint32_t comp_rd_index; 1889 p_rcr_entry_t rcr_desc_rd_head_p; 1890 p_rcr_entry_t rcr_desc_rd_head_pp; 1891 p_mblk_t nmp, mp_cont, head_mp, *tail_mp; 1892 uint16_t qlen, nrcr_read, npkt_read; 1893 uint32_t qlen_hw; 1894 boolean_t multi; 1895 rcrcfig_b_t rcr_cfg_b; 1896 #if defined(_BIG_ENDIAN) 1897 npi_status_t rs = NPI_SUCCESS; 1898 #endif 1899 1900 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts:vindex %d " 1901 "channel %d", vindex, ldvp->channel)); 1902 1903 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 1904 return (NULL); 1905 } 1906 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1907 rx_rcr_rings = nxgep->rx_rcr_rings; 1908 rcr_p = rx_rcr_rings->rcr_rings[vindex]; 1909 channel = rcr_p->rdc; 1910 if (channel != ldvp->channel) { 1911 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts:index %d " 1912 "channel %d, and rcr channel %d not matched.", 1913 vindex, ldvp->channel, channel)); 1914 return (NULL); 1915 } 1916 1917 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1918 "==> nxge_rx_pkts: START: rcr channel %d " 1919 "head_p $%p head_pp $%p index %d ", 1920 channel, rcr_p->rcr_desc_rd_head_p, 1921 rcr_p->rcr_desc_rd_head_pp, 1922 rcr_p->comp_rd_index)); 1923 1924 1925 #if !defined(_BIG_ENDIAN) 1926 qlen = RXDMA_REG_READ32(handle, RCRSTAT_A_REG, channel) & 0xffff; 1927 #else 1928 rs = npi_rxdma_rdc_rcr_qlen_get(handle, channel, &qlen); 1929 if (rs != NPI_SUCCESS) { 1930 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts:index %d " 1931 "channel %d, get qlen failed 0x%08x", 1932 vindex, ldvp->channel, rs)); 1933 return (NULL); 1934 } 1935 #endif 1936 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts:rcr channel %d " 1937 "qlen %d", channel, qlen)); 1938 1939 1940 1941 if (!qlen) { 1942 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1943 "==> nxge_rx_pkts:rcr channel %d " 1944 "qlen %d (no pkts)", channel, qlen)); 1945 1946 return (NULL); 1947 } 1948 1949 comp_rd_index = rcr_p->comp_rd_index; 1950 1951 rcr_desc_rd_head_p = rcr_p->rcr_desc_rd_head_p; 1952 rcr_desc_rd_head_pp = rcr_p->rcr_desc_rd_head_pp; 1953 nrcr_read = npkt_read = 0; 1954 1955 /* 1956 * Number of packets queued 1957 * (The jumbo or multi packet will be counted as only one 1958 * packets and it may take up more than one completion entry). 1959 */ 1960 qlen_hw = (qlen < nxge_max_rx_pkts) ? 1961 qlen : nxge_max_rx_pkts; 1962 head_mp = NULL; 1963 tail_mp = &head_mp; 1964 nmp = mp_cont = NULL; 1965 multi = B_FALSE; 1966 1967 while (qlen_hw) { 1968 1969 #ifdef NXGE_DEBUG 1970 nxge_dump_rcr_entry(nxgep, rcr_desc_rd_head_p); 1971 #endif 1972 /* 1973 * Process one completion ring entry. 1974 */ 1975 nxge_receive_packet(nxgep, 1976 rcr_p, rcr_desc_rd_head_p, &multi, &nmp, &mp_cont); 1977 1978 /* 1979 * message chaining modes 1980 */ 1981 if (nmp) { 1982 nmp->b_next = NULL; 1983 if (!multi && !mp_cont) { /* frame fits a partition */ 1984 *tail_mp = nmp; 1985 tail_mp = &nmp->b_next; 1986 nmp = NULL; 1987 } else if (multi && !mp_cont) { /* first segment */ 1988 *tail_mp = nmp; 1989 tail_mp = &nmp->b_cont; 1990 } else if (multi && mp_cont) { /* mid of multi segs */ 1991 *tail_mp = mp_cont; 1992 tail_mp = &mp_cont->b_cont; 1993 } else if (!multi && mp_cont) { /* last segment */ 1994 *tail_mp = mp_cont; 1995 tail_mp = &nmp->b_next; 1996 nmp = NULL; 1997 } 1998 } 1999 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2000 "==> nxge_rx_pkts: loop: rcr channel %d " 2001 "before updating: multi %d " 2002 "nrcr_read %d " 2003 "npk read %d " 2004 "head_pp $%p index %d ", 2005 channel, 2006 multi, 2007 nrcr_read, npkt_read, rcr_desc_rd_head_pp, 2008 comp_rd_index)); 2009 2010 if (!multi) { 2011 qlen_hw--; 2012 npkt_read++; 2013 } 2014 2015 /* 2016 * Update the next read entry. 2017 */ 2018 comp_rd_index = NEXT_ENTRY(comp_rd_index, 2019 rcr_p->comp_wrap_mask); 2020 2021 rcr_desc_rd_head_p = NEXT_ENTRY_PTR(rcr_desc_rd_head_p, 2022 rcr_p->rcr_desc_first_p, 2023 rcr_p->rcr_desc_last_p); 2024 2025 nrcr_read++; 2026 2027 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2028 "<== nxge_rx_pkts: (SAM, process one packet) " 2029 "nrcr_read %d", 2030 nrcr_read)); 2031 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2032 "==> nxge_rx_pkts: loop: rcr channel %d " 2033 "multi %d " 2034 "nrcr_read %d " 2035 "npk read %d " 2036 "head_pp $%p index %d ", 2037 channel, 2038 multi, 2039 nrcr_read, npkt_read, rcr_desc_rd_head_pp, 2040 comp_rd_index)); 2041 2042 } 2043 2044 rcr_p->rcr_desc_rd_head_pp = rcr_desc_rd_head_pp; 2045 rcr_p->comp_rd_index = comp_rd_index; 2046 rcr_p->rcr_desc_rd_head_p = rcr_desc_rd_head_p; 2047 2048 if ((nxgep->intr_timeout != rcr_p->intr_timeout) || 2049 (nxgep->intr_threshold != rcr_p->intr_threshold)) { 2050 rcr_p->intr_timeout = nxgep->intr_timeout; 2051 rcr_p->intr_threshold = nxgep->intr_threshold; 2052 rcr_cfg_b.value = 0x0ULL; 2053 if (rcr_p->intr_timeout) 2054 rcr_cfg_b.bits.ldw.entout = 1; 2055 rcr_cfg_b.bits.ldw.timeout = rcr_p->intr_timeout; 2056 rcr_cfg_b.bits.ldw.pthres = rcr_p->intr_threshold; 2057 RXDMA_REG_WRITE64(handle, RCRCFIG_B_REG, 2058 channel, rcr_cfg_b.value); 2059 } 2060 2061 cs.bits.ldw.pktread = npkt_read; 2062 cs.bits.ldw.ptrread = nrcr_read; 2063 RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, 2064 channel, cs.value); 2065 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2066 "==> nxge_rx_pkts: EXIT: rcr channel %d " 2067 "head_pp $%p index %016llx ", 2068 channel, 2069 rcr_p->rcr_desc_rd_head_pp, 2070 rcr_p->comp_rd_index)); 2071 /* 2072 * Update RCR buffer pointer read and number of packets 2073 * read. 2074 */ 2075 2076 *rcrp = rcr_p; 2077 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rx_pkts")); 2078 return (head_mp); 2079 } 2080 2081 void 2082 nxge_receive_packet(p_nxge_t nxgep, 2083 p_rx_rcr_ring_t rcr_p, p_rcr_entry_t rcr_desc_rd_head_p, 2084 boolean_t *multi_p, mblk_t **mp, mblk_t **mp_cont) 2085 { 2086 p_mblk_t nmp = NULL; 2087 uint64_t multi; 2088 uint64_t dcf_err; 2089 uint8_t channel; 2090 2091 boolean_t first_entry = B_TRUE; 2092 boolean_t is_tcp_udp = B_FALSE; 2093 boolean_t buffer_free = B_FALSE; 2094 boolean_t error_send_up = B_FALSE; 2095 uint8_t error_type; 2096 uint16_t l2_len; 2097 uint16_t skip_len; 2098 uint8_t pktbufsz_type; 2099 uint64_t rcr_entry; 2100 uint64_t *pkt_buf_addr_pp; 2101 uint64_t *pkt_buf_addr_p; 2102 uint32_t buf_offset; 2103 uint32_t bsize; 2104 uint32_t error_disp_cnt; 2105 uint32_t msg_index; 2106 p_rx_rbr_ring_t rx_rbr_p; 2107 p_rx_msg_t *rx_msg_ring_p; 2108 p_rx_msg_t rx_msg_p; 2109 uint16_t sw_offset_bytes = 0, hdr_size = 0; 2110 nxge_status_t status = NXGE_OK; 2111 boolean_t is_valid = B_FALSE; 2112 p_nxge_rx_ring_stats_t rdc_stats; 2113 uint32_t bytes_read; 2114 uint64_t pkt_type; 2115 uint64_t frag; 2116 #ifdef NXGE_DEBUG 2117 int dump_len; 2118 #endif 2119 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> nxge_receive_packet")); 2120 first_entry = (*mp == NULL) ? B_TRUE : B_FALSE; 2121 2122 rcr_entry = *((uint64_t *)rcr_desc_rd_head_p); 2123 2124 multi = (rcr_entry & RCR_MULTI_MASK); 2125 dcf_err = (rcr_entry & RCR_DCF_ERROR_MASK); 2126 pkt_type = (rcr_entry & RCR_PKT_TYPE_MASK); 2127 2128 error_type = ((rcr_entry & RCR_ERROR_MASK) >> RCR_ERROR_SHIFT); 2129 frag = (rcr_entry & RCR_FRAG_MASK); 2130 2131 l2_len = ((rcr_entry & RCR_L2_LEN_MASK) >> RCR_L2_LEN_SHIFT); 2132 2133 pktbufsz_type = ((rcr_entry & RCR_PKTBUFSZ_MASK) >> 2134 RCR_PKTBUFSZ_SHIFT); 2135 #if defined(__i386) 2136 pkt_buf_addr_pp = (uint64_t *)(uint32_t)((rcr_entry & 2137 RCR_PKT_BUF_ADDR_MASK) << RCR_PKT_BUF_ADDR_SHIFT); 2138 #else 2139 pkt_buf_addr_pp = (uint64_t *)((rcr_entry & RCR_PKT_BUF_ADDR_MASK) << 2140 RCR_PKT_BUF_ADDR_SHIFT); 2141 #endif 2142 2143 channel = rcr_p->rdc; 2144 2145 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2146 "==> nxge_receive_packet: entryp $%p entry 0x%0llx " 2147 "pkt_buf_addr_pp $%p l2_len %d multi 0x%llx " 2148 "error_type 0x%x pkt_type 0x%x " 2149 "pktbufsz_type %d ", 2150 rcr_desc_rd_head_p, 2151 rcr_entry, pkt_buf_addr_pp, l2_len, 2152 multi, 2153 error_type, 2154 pkt_type, 2155 pktbufsz_type)); 2156 2157 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2158 "==> nxge_receive_packet: entryp $%p entry 0x%0llx " 2159 "pkt_buf_addr_pp $%p l2_len %d multi 0x%llx " 2160 "error_type 0x%x pkt_type 0x%x ", rcr_desc_rd_head_p, 2161 rcr_entry, pkt_buf_addr_pp, l2_len, 2162 multi, 2163 error_type, 2164 pkt_type)); 2165 2166 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2167 "==> (rbr) nxge_receive_packet: entry 0x%0llx " 2168 "full pkt_buf_addr_pp $%p l2_len %d", 2169 rcr_entry, pkt_buf_addr_pp, l2_len)); 2170 2171 /* get the stats ptr */ 2172 rdc_stats = rcr_p->rdc_stats; 2173 2174 if (!l2_len) { 2175 2176 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2177 "<== nxge_receive_packet: failed: l2 length is 0.")); 2178 return; 2179 } 2180 2181 /* Hardware sends us 4 bytes of CRC as no stripping is done. */ 2182 l2_len -= ETHERFCSL; 2183 2184 /* shift 6 bits to get the full io address */ 2185 #if defined(__i386) 2186 pkt_buf_addr_pp = (uint64_t *)((uint32_t)pkt_buf_addr_pp << 2187 RCR_PKT_BUF_ADDR_SHIFT_FULL); 2188 #else 2189 pkt_buf_addr_pp = (uint64_t *)((uint64_t)pkt_buf_addr_pp << 2190 RCR_PKT_BUF_ADDR_SHIFT_FULL); 2191 #endif 2192 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2193 "==> (rbr) nxge_receive_packet: entry 0x%0llx " 2194 "full pkt_buf_addr_pp $%p l2_len %d", 2195 rcr_entry, pkt_buf_addr_pp, l2_len)); 2196 2197 rx_rbr_p = rcr_p->rx_rbr_p; 2198 rx_msg_ring_p = rx_rbr_p->rx_msg_ring; 2199 2200 if (first_entry) { 2201 hdr_size = (rcr_p->full_hdr_flag ? RXDMA_HDR_SIZE_FULL : 2202 RXDMA_HDR_SIZE_DEFAULT); 2203 2204 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2205 "==> nxge_receive_packet: first entry 0x%016llx " 2206 "pkt_buf_addr_pp $%p l2_len %d hdr %d", 2207 rcr_entry, pkt_buf_addr_pp, l2_len, 2208 hdr_size)); 2209 } 2210 2211 MUTEX_ENTER(&rcr_p->lock); 2212 MUTEX_ENTER(&rx_rbr_p->lock); 2213 2214 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2215 "==> (rbr 1) nxge_receive_packet: entry 0x%0llx " 2216 "full pkt_buf_addr_pp $%p l2_len %d", 2217 rcr_entry, pkt_buf_addr_pp, l2_len)); 2218 2219 /* 2220 * Packet buffer address in the completion entry points 2221 * to the starting buffer address (offset 0). 2222 * Use the starting buffer address to locate the corresponding 2223 * kernel address. 2224 */ 2225 status = nxge_rxbuf_pp_to_vp(nxgep, rx_rbr_p, 2226 pktbufsz_type, pkt_buf_addr_pp, &pkt_buf_addr_p, 2227 &buf_offset, 2228 &msg_index); 2229 2230 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2231 "==> (rbr 2) nxge_receive_packet: entry 0x%0llx " 2232 "full pkt_buf_addr_pp $%p l2_len %d", 2233 rcr_entry, pkt_buf_addr_pp, l2_len)); 2234 2235 if (status != NXGE_OK) { 2236 MUTEX_EXIT(&rx_rbr_p->lock); 2237 MUTEX_EXIT(&rcr_p->lock); 2238 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2239 "<== nxge_receive_packet: found vaddr failed %d", 2240 status)); 2241 return; 2242 } 2243 2244 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2245 "==> (rbr 3) nxge_receive_packet: entry 0x%0llx " 2246 "full pkt_buf_addr_pp $%p l2_len %d", 2247 rcr_entry, pkt_buf_addr_pp, l2_len)); 2248 2249 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2250 "==> (rbr 4 msgindex %d) nxge_receive_packet: entry 0x%0llx " 2251 "full pkt_buf_addr_pp $%p l2_len %d", 2252 msg_index, rcr_entry, pkt_buf_addr_pp, l2_len)); 2253 2254 rx_msg_p = rx_msg_ring_p[msg_index]; 2255 2256 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2257 "==> (rbr 4 msgindex %d) nxge_receive_packet: entry 0x%0llx " 2258 "full pkt_buf_addr_pp $%p l2_len %d", 2259 msg_index, rcr_entry, pkt_buf_addr_pp, l2_len)); 2260 2261 switch (pktbufsz_type) { 2262 case RCR_PKTBUFSZ_0: 2263 bsize = rx_rbr_p->pkt_buf_size0_bytes; 2264 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2265 "==> nxge_receive_packet: 0 buf %d", bsize)); 2266 break; 2267 case RCR_PKTBUFSZ_1: 2268 bsize = rx_rbr_p->pkt_buf_size1_bytes; 2269 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2270 "==> nxge_receive_packet: 1 buf %d", bsize)); 2271 break; 2272 case RCR_PKTBUFSZ_2: 2273 bsize = rx_rbr_p->pkt_buf_size2_bytes; 2274 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2275 "==> nxge_receive_packet: 2 buf %d", bsize)); 2276 break; 2277 case RCR_SINGLE_BLOCK: 2278 bsize = rx_msg_p->block_size; 2279 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2280 "==> nxge_receive_packet: single %d", bsize)); 2281 2282 break; 2283 default: 2284 MUTEX_EXIT(&rx_rbr_p->lock); 2285 MUTEX_EXIT(&rcr_p->lock); 2286 return; 2287 } 2288 2289 DMA_COMMON_SYNC_OFFSET(rx_msg_p->buf_dma, 2290 (buf_offset + sw_offset_bytes), 2291 (hdr_size + l2_len), 2292 DDI_DMA_SYNC_FORCPU); 2293 2294 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2295 "==> nxge_receive_packet: after first dump:usage count")); 2296 2297 if (rx_msg_p->cur_usage_cnt == 0) { 2298 if (rx_rbr_p->rbr_use_bcopy) { 2299 atomic_inc_32(&rx_rbr_p->rbr_consumed); 2300 if (rx_rbr_p->rbr_consumed < 2301 rx_rbr_p->rbr_threshold_hi) { 2302 if (rx_rbr_p->rbr_threshold_lo == 0 || 2303 ((rx_rbr_p->rbr_consumed >= 2304 rx_rbr_p->rbr_threshold_lo) && 2305 (rx_rbr_p->rbr_bufsize_type >= 2306 pktbufsz_type))) { 2307 rx_msg_p->rx_use_bcopy = B_TRUE; 2308 } 2309 } else { 2310 rx_msg_p->rx_use_bcopy = B_TRUE; 2311 } 2312 } 2313 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2314 "==> nxge_receive_packet: buf %d (new block) ", 2315 bsize)); 2316 2317 rx_msg_p->pkt_buf_size_code = pktbufsz_type; 2318 rx_msg_p->pkt_buf_size = bsize; 2319 rx_msg_p->cur_usage_cnt = 1; 2320 if (pktbufsz_type == RCR_SINGLE_BLOCK) { 2321 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2322 "==> nxge_receive_packet: buf %d " 2323 "(single block) ", 2324 bsize)); 2325 /* 2326 * Buffer can be reused once the free function 2327 * is called. 2328 */ 2329 rx_msg_p->max_usage_cnt = 1; 2330 buffer_free = B_TRUE; 2331 } else { 2332 rx_msg_p->max_usage_cnt = rx_msg_p->block_size/bsize; 2333 if (rx_msg_p->max_usage_cnt == 1) { 2334 buffer_free = B_TRUE; 2335 } 2336 } 2337 } else { 2338 rx_msg_p->cur_usage_cnt++; 2339 if (rx_msg_p->cur_usage_cnt == rx_msg_p->max_usage_cnt) { 2340 buffer_free = B_TRUE; 2341 } 2342 } 2343 2344 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2345 "msgbuf index = %d l2len %d bytes usage %d max_usage %d ", 2346 msg_index, l2_len, 2347 rx_msg_p->cur_usage_cnt, rx_msg_p->max_usage_cnt)); 2348 2349 if ((error_type) || (dcf_err)) { 2350 rdc_stats->ierrors++; 2351 if (dcf_err) { 2352 rdc_stats->dcf_err++; 2353 #ifdef NXGE_DEBUG 2354 if (!rdc_stats->dcf_err) { 2355 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2356 "nxge_receive_packet: channel %d dcf_err rcr" 2357 " 0x%llx", channel, rcr_entry)); 2358 } 2359 #endif 2360 NXGE_FM_REPORT_ERROR(nxgep, nxgep->mac.portnum, NULL, 2361 NXGE_FM_EREPORT_RDMC_DCF_ERR); 2362 } else { 2363 /* Update error stats */ 2364 error_disp_cnt = NXGE_ERROR_SHOW_MAX; 2365 rdc_stats->errlog.compl_err_type = error_type; 2366 2367 switch (error_type) { 2368 /* 2369 * Do not send FMA ereport for RCR_L2_ERROR and 2370 * RCR_L4_CSUM_ERROR because most likely they indicate 2371 * back pressure rather than HW failures. 2372 */ 2373 case RCR_L2_ERROR: 2374 rdc_stats->l2_err++; 2375 if (rdc_stats->l2_err < 2376 error_disp_cnt) { 2377 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2378 " nxge_receive_packet:" 2379 " channel %d RCR L2_ERROR", 2380 channel)); 2381 } 2382 break; 2383 case RCR_L4_CSUM_ERROR: 2384 error_send_up = B_TRUE; 2385 rdc_stats->l4_cksum_err++; 2386 if (rdc_stats->l4_cksum_err < 2387 error_disp_cnt) { 2388 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2389 " nxge_receive_packet:" 2390 " channel %d" 2391 " RCR L4_CSUM_ERROR", channel)); 2392 } 2393 break; 2394 /* 2395 * Do not send FMA ereport for RCR_FFLP_SOFT_ERROR and 2396 * RCR_ZCP_SOFT_ERROR because they reflect the same 2397 * FFLP and ZCP errors that have been reported by 2398 * nxge_fflp.c and nxge_zcp.c. 2399 */ 2400 case RCR_FFLP_SOFT_ERROR: 2401 error_send_up = B_TRUE; 2402 rdc_stats->fflp_soft_err++; 2403 if (rdc_stats->fflp_soft_err < 2404 error_disp_cnt) { 2405 NXGE_ERROR_MSG((nxgep, 2406 NXGE_ERR_CTL, 2407 " nxge_receive_packet:" 2408 " channel %d" 2409 " RCR FFLP_SOFT_ERROR", channel)); 2410 } 2411 break; 2412 case RCR_ZCP_SOFT_ERROR: 2413 error_send_up = B_TRUE; 2414 rdc_stats->fflp_soft_err++; 2415 if (rdc_stats->zcp_soft_err < 2416 error_disp_cnt) 2417 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2418 " nxge_receive_packet: Channel %d" 2419 " RCR ZCP_SOFT_ERROR", channel)); 2420 break; 2421 default: 2422 rdc_stats->rcr_unknown_err++; 2423 if (rdc_stats->rcr_unknown_err 2424 < error_disp_cnt) { 2425 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2426 " nxge_receive_packet: Channel %d" 2427 " RCR entry 0x%llx error 0x%x", 2428 rcr_entry, channel, error_type)); 2429 } 2430 break; 2431 } 2432 } 2433 2434 /* 2435 * Update and repost buffer block if max usage 2436 * count is reached. 2437 */ 2438 if (error_send_up == B_FALSE) { 2439 atomic_inc_32(&rx_msg_p->ref_cnt); 2440 atomic_inc_32(&nxge_mblks_pending); 2441 if (buffer_free == B_TRUE) { 2442 rx_msg_p->free = B_TRUE; 2443 } 2444 2445 MUTEX_EXIT(&rx_rbr_p->lock); 2446 MUTEX_EXIT(&rcr_p->lock); 2447 nxge_freeb(rx_msg_p); 2448 return; 2449 } 2450 } 2451 2452 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2453 "==> nxge_receive_packet: DMA sync second ")); 2454 2455 bytes_read = rcr_p->rcvd_pkt_bytes; 2456 skip_len = sw_offset_bytes + hdr_size; 2457 if (!rx_msg_p->rx_use_bcopy) { 2458 /* 2459 * For loaned up buffers, the driver reference count 2460 * will be incremented first and then the free state. 2461 */ 2462 if ((nmp = nxge_dupb(rx_msg_p, buf_offset, bsize)) != NULL) { 2463 if (first_entry) { 2464 nmp->b_rptr = &nmp->b_rptr[skip_len]; 2465 if (l2_len < bsize - skip_len) { 2466 nmp->b_wptr = &nmp->b_rptr[l2_len]; 2467 } else { 2468 nmp->b_wptr = &nmp->b_rptr[bsize 2469 - skip_len]; 2470 } 2471 } else { 2472 if (l2_len - bytes_read < bsize) { 2473 nmp->b_wptr = 2474 &nmp->b_rptr[l2_len - bytes_read]; 2475 } else { 2476 nmp->b_wptr = &nmp->b_rptr[bsize]; 2477 } 2478 } 2479 } 2480 } else { 2481 if (first_entry) { 2482 nmp = nxge_dupb_bcopy(rx_msg_p, buf_offset + skip_len, 2483 l2_len < bsize - skip_len ? 2484 l2_len : bsize - skip_len); 2485 } else { 2486 nmp = nxge_dupb_bcopy(rx_msg_p, buf_offset, 2487 l2_len - bytes_read < bsize ? 2488 l2_len - bytes_read : bsize); 2489 } 2490 } 2491 if (nmp != NULL) { 2492 if (first_entry) 2493 bytes_read = nmp->b_wptr - nmp->b_rptr; 2494 else 2495 bytes_read += nmp->b_wptr - nmp->b_rptr; 2496 2497 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2498 "==> nxge_receive_packet after dupb: " 2499 "rbr consumed %d " 2500 "pktbufsz_type %d " 2501 "nmp $%p rptr $%p wptr $%p " 2502 "buf_offset %d bzise %d l2_len %d skip_len %d", 2503 rx_rbr_p->rbr_consumed, 2504 pktbufsz_type, 2505 nmp, nmp->b_rptr, nmp->b_wptr, 2506 buf_offset, bsize, l2_len, skip_len)); 2507 } else { 2508 cmn_err(CE_WARN, "!nxge_receive_packet: " 2509 "update stats (error)"); 2510 atomic_inc_32(&rx_msg_p->ref_cnt); 2511 atomic_inc_32(&nxge_mblks_pending); 2512 if (buffer_free == B_TRUE) { 2513 rx_msg_p->free = B_TRUE; 2514 } 2515 MUTEX_EXIT(&rx_rbr_p->lock); 2516 MUTEX_EXIT(&rcr_p->lock); 2517 nxge_freeb(rx_msg_p); 2518 return; 2519 } 2520 2521 if (buffer_free == B_TRUE) { 2522 rx_msg_p->free = B_TRUE; 2523 } 2524 /* 2525 * ERROR, FRAG and PKT_TYPE are only reported 2526 * in the first entry. 2527 * If a packet is not fragmented and no error bit is set, then 2528 * L4 checksum is OK. 2529 */ 2530 is_valid = (nmp != NULL); 2531 if (first_entry) { 2532 rdc_stats->ipackets++; /* count only 1st seg for jumbo */ 2533 rdc_stats->ibytes += skip_len + l2_len < bsize ? 2534 l2_len : bsize; 2535 } else { 2536 rdc_stats->ibytes += l2_len - bytes_read < bsize ? 2537 l2_len - bytes_read : bsize; 2538 } 2539 2540 rcr_p->rcvd_pkt_bytes = bytes_read; 2541 2542 MUTEX_EXIT(&rx_rbr_p->lock); 2543 MUTEX_EXIT(&rcr_p->lock); 2544 2545 if (rx_msg_p->free && rx_msg_p->rx_use_bcopy) { 2546 atomic_inc_32(&rx_msg_p->ref_cnt); 2547 atomic_inc_32(&nxge_mblks_pending); 2548 nxge_freeb(rx_msg_p); 2549 } 2550 2551 if (is_valid) { 2552 nmp->b_cont = NULL; 2553 if (first_entry) { 2554 *mp = nmp; 2555 *mp_cont = NULL; 2556 } else { 2557 *mp_cont = nmp; 2558 } 2559 } 2560 2561 /* 2562 * Update stats and hardware checksuming. 2563 */ 2564 if (is_valid && !multi) { 2565 2566 is_tcp_udp = ((pkt_type == RCR_PKT_IS_TCP || 2567 pkt_type == RCR_PKT_IS_UDP) ? 2568 B_TRUE: B_FALSE); 2569 2570 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_receive_packet: " 2571 "is_valid 0x%x multi 0x%llx pkt %d frag %d error %d", 2572 is_valid, multi, is_tcp_udp, frag, error_type)); 2573 2574 if (is_tcp_udp && !frag && !error_type) { 2575 (void) hcksum_assoc(nmp, NULL, NULL, 0, 0, 0, 0, 2576 HCK_FULLCKSUM_OK | HCK_FULLCKSUM, 0); 2577 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2578 "==> nxge_receive_packet: Full tcp/udp cksum " 2579 "is_valid 0x%x multi 0x%llx pkt %d frag %d " 2580 "error %d", 2581 is_valid, multi, is_tcp_udp, frag, error_type)); 2582 } 2583 } 2584 2585 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2586 "==> nxge_receive_packet: *mp 0x%016llx", *mp)); 2587 2588 *multi_p = (multi == RCR_MULTI_MASK); 2589 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_receive_packet: " 2590 "multi %d nmp 0x%016llx *mp 0x%016llx *mp_cont 0x%016llx", 2591 *multi_p, nmp, *mp, *mp_cont)); 2592 } 2593 2594 /*ARGSUSED*/ 2595 static nxge_status_t 2596 nxge_rx_err_evnts(p_nxge_t nxgep, uint_t index, p_nxge_ldv_t ldvp, 2597 rx_dma_ctl_stat_t cs) 2598 { 2599 p_nxge_rx_ring_stats_t rdc_stats; 2600 npi_handle_t handle; 2601 npi_status_t rs; 2602 boolean_t rxchan_fatal = B_FALSE; 2603 boolean_t rxport_fatal = B_FALSE; 2604 uint8_t channel; 2605 uint8_t portn; 2606 nxge_status_t status = NXGE_OK; 2607 uint32_t error_disp_cnt = NXGE_ERROR_SHOW_MAX; 2608 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_rx_err_evnts")); 2609 2610 handle = NXGE_DEV_NPI_HANDLE(nxgep); 2611 channel = ldvp->channel; 2612 portn = nxgep->mac.portnum; 2613 rdc_stats = &nxgep->statsp->rdc_stats[ldvp->vdma_index]; 2614 2615 if (cs.bits.hdw.rbr_tmout) { 2616 rdc_stats->rx_rbr_tmout++; 2617 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2618 NXGE_FM_EREPORT_RDMC_RBR_TMOUT); 2619 rxchan_fatal = B_TRUE; 2620 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2621 "==> nxge_rx_err_evnts: rx_rbr_timeout")); 2622 } 2623 if (cs.bits.hdw.rsp_cnt_err) { 2624 rdc_stats->rsp_cnt_err++; 2625 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2626 NXGE_FM_EREPORT_RDMC_RSP_CNT_ERR); 2627 rxchan_fatal = B_TRUE; 2628 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2629 "==> nxge_rx_err_evnts(channel %d): " 2630 "rsp_cnt_err", channel)); 2631 } 2632 if (cs.bits.hdw.byte_en_bus) { 2633 rdc_stats->byte_en_bus++; 2634 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2635 NXGE_FM_EREPORT_RDMC_BYTE_EN_BUS); 2636 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2637 "==> nxge_rx_err_evnts(channel %d): " 2638 "fatal error: byte_en_bus", channel)); 2639 rxchan_fatal = B_TRUE; 2640 } 2641 if (cs.bits.hdw.rsp_dat_err) { 2642 rdc_stats->rsp_dat_err++; 2643 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2644 NXGE_FM_EREPORT_RDMC_RSP_DAT_ERR); 2645 rxchan_fatal = B_TRUE; 2646 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2647 "==> nxge_rx_err_evnts(channel %d): " 2648 "fatal error: rsp_dat_err", channel)); 2649 } 2650 if (cs.bits.hdw.rcr_ack_err) { 2651 rdc_stats->rcr_ack_err++; 2652 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2653 NXGE_FM_EREPORT_RDMC_RCR_ACK_ERR); 2654 rxchan_fatal = B_TRUE; 2655 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2656 "==> nxge_rx_err_evnts(channel %d): " 2657 "fatal error: rcr_ack_err", channel)); 2658 } 2659 if (cs.bits.hdw.dc_fifo_err) { 2660 rdc_stats->dc_fifo_err++; 2661 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2662 NXGE_FM_EREPORT_RDMC_DC_FIFO_ERR); 2663 /* This is not a fatal error! */ 2664 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2665 "==> nxge_rx_err_evnts(channel %d): " 2666 "dc_fifo_err", channel)); 2667 rxport_fatal = B_TRUE; 2668 } 2669 if ((cs.bits.hdw.rcr_sha_par) || (cs.bits.hdw.rbr_pre_par)) { 2670 if ((rs = npi_rxdma_ring_perr_stat_get(handle, 2671 &rdc_stats->errlog.pre_par, 2672 &rdc_stats->errlog.sha_par)) 2673 != NPI_SUCCESS) { 2674 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2675 "==> nxge_rx_err_evnts(channel %d): " 2676 "rcr_sha_par: get perr", channel)); 2677 return (NXGE_ERROR | rs); 2678 } 2679 if (cs.bits.hdw.rcr_sha_par) { 2680 rdc_stats->rcr_sha_par++; 2681 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2682 NXGE_FM_EREPORT_RDMC_RCR_SHA_PAR); 2683 rxchan_fatal = B_TRUE; 2684 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2685 "==> nxge_rx_err_evnts(channel %d): " 2686 "fatal error: rcr_sha_par", channel)); 2687 } 2688 if (cs.bits.hdw.rbr_pre_par) { 2689 rdc_stats->rbr_pre_par++; 2690 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2691 NXGE_FM_EREPORT_RDMC_RBR_PRE_PAR); 2692 rxchan_fatal = B_TRUE; 2693 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2694 "==> nxge_rx_err_evnts(channel %d): " 2695 "fatal error: rbr_pre_par", channel)); 2696 } 2697 } 2698 if (cs.bits.hdw.port_drop_pkt) { 2699 rdc_stats->port_drop_pkt++; 2700 if (rdc_stats->port_drop_pkt < error_disp_cnt) 2701 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2702 "==> nxge_rx_err_evnts (channel %d): " 2703 "port_drop_pkt", channel)); 2704 } 2705 if (cs.bits.hdw.wred_drop) { 2706 rdc_stats->wred_drop++; 2707 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 2708 "==> nxge_rx_err_evnts(channel %d): " 2709 "wred_drop", channel)); 2710 } 2711 if (cs.bits.hdw.rbr_pre_empty) { 2712 rdc_stats->rbr_pre_empty++; 2713 if (rdc_stats->rbr_pre_empty < error_disp_cnt) 2714 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2715 "==> nxge_rx_err_evnts(channel %d): " 2716 "rbr_pre_empty", channel)); 2717 } 2718 if (cs.bits.hdw.rcr_shadow_full) { 2719 rdc_stats->rcr_shadow_full++; 2720 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2721 "==> nxge_rx_err_evnts(channel %d): " 2722 "rcr_shadow_full", channel)); 2723 } 2724 if (cs.bits.hdw.config_err) { 2725 rdc_stats->config_err++; 2726 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2727 NXGE_FM_EREPORT_RDMC_CONFIG_ERR); 2728 rxchan_fatal = B_TRUE; 2729 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2730 "==> nxge_rx_err_evnts(channel %d): " 2731 "config error", channel)); 2732 } 2733 if (cs.bits.hdw.rcrincon) { 2734 rdc_stats->rcrincon++; 2735 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2736 NXGE_FM_EREPORT_RDMC_RCRINCON); 2737 rxchan_fatal = B_TRUE; 2738 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2739 "==> nxge_rx_err_evnts(channel %d): " 2740 "fatal error: rcrincon error", channel)); 2741 } 2742 if (cs.bits.hdw.rcrfull) { 2743 rdc_stats->rcrfull++; 2744 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2745 NXGE_FM_EREPORT_RDMC_RCRFULL); 2746 rxchan_fatal = B_TRUE; 2747 if (rdc_stats->rcrfull < error_disp_cnt) 2748 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2749 "==> nxge_rx_err_evnts(channel %d): " 2750 "fatal error: rcrfull error", channel)); 2751 } 2752 if (cs.bits.hdw.rbr_empty) { 2753 rdc_stats->rbr_empty++; 2754 if (rdc_stats->rbr_empty < error_disp_cnt) 2755 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2756 "==> nxge_rx_err_evnts(channel %d): " 2757 "rbr empty error", channel)); 2758 } 2759 if (cs.bits.hdw.rbrfull) { 2760 rdc_stats->rbrfull++; 2761 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2762 NXGE_FM_EREPORT_RDMC_RBRFULL); 2763 rxchan_fatal = B_TRUE; 2764 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2765 "==> nxge_rx_err_evnts(channel %d): " 2766 "fatal error: rbr_full error", channel)); 2767 } 2768 if (cs.bits.hdw.rbrlogpage) { 2769 rdc_stats->rbrlogpage++; 2770 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2771 NXGE_FM_EREPORT_RDMC_RBRLOGPAGE); 2772 rxchan_fatal = B_TRUE; 2773 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2774 "==> nxge_rx_err_evnts(channel %d): " 2775 "fatal error: rbr logical page error", channel)); 2776 } 2777 if (cs.bits.hdw.cfiglogpage) { 2778 rdc_stats->cfiglogpage++; 2779 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2780 NXGE_FM_EREPORT_RDMC_CFIGLOGPAGE); 2781 rxchan_fatal = B_TRUE; 2782 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2783 "==> nxge_rx_err_evnts(channel %d): " 2784 "fatal error: cfig logical page error", channel)); 2785 } 2786 2787 if (rxport_fatal) { 2788 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2789 " nxge_rx_err_evnts: " 2790 " fatal error on Port #%d\n", 2791 portn)); 2792 status = nxge_ipp_fatal_err_recover(nxgep); 2793 if (status == NXGE_OK) { 2794 FM_SERVICE_RESTORED(nxgep); 2795 } 2796 } 2797 2798 if (rxchan_fatal) { 2799 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2800 " nxge_rx_err_evnts: " 2801 " fatal error on Channel #%d\n", 2802 channel)); 2803 status = nxge_rxdma_fatal_err_recover(nxgep, channel); 2804 if (status == NXGE_OK) { 2805 FM_SERVICE_RESTORED(nxgep); 2806 } 2807 } 2808 2809 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "<== nxge_rx_err_evnts")); 2810 2811 return (status); 2812 } 2813 2814 static nxge_status_t 2815 nxge_map_rxdma(p_nxge_t nxgep) 2816 { 2817 int i, ndmas; 2818 uint16_t channel; 2819 p_rx_rbr_rings_t rx_rbr_rings; 2820 p_rx_rbr_ring_t *rbr_rings; 2821 p_rx_rcr_rings_t rx_rcr_rings; 2822 p_rx_rcr_ring_t *rcr_rings; 2823 p_rx_mbox_areas_t rx_mbox_areas_p; 2824 p_rx_mbox_t *rx_mbox_p; 2825 p_nxge_dma_pool_t dma_buf_poolp; 2826 p_nxge_dma_pool_t dma_cntl_poolp; 2827 p_nxge_dma_common_t *dma_buf_p; 2828 p_nxge_dma_common_t *dma_cntl_p; 2829 uint32_t *num_chunks; 2830 nxge_status_t status = NXGE_OK; 2831 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2832 p_nxge_dma_common_t t_dma_buf_p; 2833 p_nxge_dma_common_t t_dma_cntl_p; 2834 #endif 2835 2836 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_map_rxdma")); 2837 2838 dma_buf_poolp = nxgep->rx_buf_pool_p; 2839 dma_cntl_poolp = nxgep->rx_cntl_pool_p; 2840 2841 if (!dma_buf_poolp->buf_allocated || !dma_cntl_poolp->buf_allocated) { 2842 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2843 "<== nxge_map_rxdma: buf not allocated")); 2844 return (NXGE_ERROR); 2845 } 2846 2847 ndmas = dma_buf_poolp->ndmas; 2848 if (!ndmas) { 2849 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2850 "<== nxge_map_rxdma: no dma allocated")); 2851 return (NXGE_ERROR); 2852 } 2853 2854 num_chunks = dma_buf_poolp->num_chunks; 2855 dma_buf_p = dma_buf_poolp->dma_buf_pool_p; 2856 dma_cntl_p = dma_cntl_poolp->dma_buf_pool_p; 2857 2858 rx_rbr_rings = (p_rx_rbr_rings_t) 2859 KMEM_ZALLOC(sizeof (rx_rbr_rings_t), KM_SLEEP); 2860 rbr_rings = (p_rx_rbr_ring_t *) 2861 KMEM_ZALLOC(sizeof (p_rx_rbr_ring_t) * ndmas, KM_SLEEP); 2862 rx_rcr_rings = (p_rx_rcr_rings_t) 2863 KMEM_ZALLOC(sizeof (rx_rcr_rings_t), KM_SLEEP); 2864 rcr_rings = (p_rx_rcr_ring_t *) 2865 KMEM_ZALLOC(sizeof (p_rx_rcr_ring_t) * ndmas, KM_SLEEP); 2866 rx_mbox_areas_p = (p_rx_mbox_areas_t) 2867 KMEM_ZALLOC(sizeof (rx_mbox_areas_t), KM_SLEEP); 2868 rx_mbox_p = (p_rx_mbox_t *) 2869 KMEM_ZALLOC(sizeof (p_rx_mbox_t) * ndmas, KM_SLEEP); 2870 2871 /* 2872 * Timeout should be set based on the system clock divider. 2873 * The following timeout value of 1 assumes that the 2874 * granularity (1000) is 3 microseconds running at 300MHz. 2875 */ 2876 2877 nxgep->intr_threshold = RXDMA_RCR_PTHRES_DEFAULT; 2878 nxgep->intr_timeout = RXDMA_RCR_TO_DEFAULT; 2879 2880 /* 2881 * Map descriptors from the buffer polls for each dam channel. 2882 */ 2883 for (i = 0; i < ndmas; i++) { 2884 /* 2885 * Set up and prepare buffer blocks, descriptors 2886 * and mailbox. 2887 */ 2888 channel = ((p_nxge_dma_common_t)dma_buf_p[i])->dma_channel; 2889 status = nxge_map_rxdma_channel(nxgep, channel, 2890 (p_nxge_dma_common_t *)&dma_buf_p[i], 2891 (p_rx_rbr_ring_t *)&rbr_rings[i], 2892 num_chunks[i], 2893 (p_nxge_dma_common_t *)&dma_cntl_p[i], 2894 (p_rx_rcr_ring_t *)&rcr_rings[i], 2895 (p_rx_mbox_t *)&rx_mbox_p[i]); 2896 if (status != NXGE_OK) { 2897 goto nxge_map_rxdma_fail1; 2898 } 2899 rbr_rings[i]->index = (uint16_t)i; 2900 rcr_rings[i]->index = (uint16_t)i; 2901 rcr_rings[i]->rdc_stats = &nxgep->statsp->rdc_stats[i]; 2902 2903 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2904 if (nxgep->niu_type == N2_NIU && NXGE_DMA_BLOCK == 1) { 2905 rbr_rings[i]->hv_set = B_FALSE; 2906 t_dma_buf_p = (p_nxge_dma_common_t)dma_buf_p[i]; 2907 t_dma_cntl_p = 2908 (p_nxge_dma_common_t)dma_cntl_p[i]; 2909 2910 rbr_rings[i]->hv_rx_buf_base_ioaddr_pp = 2911 (uint64_t)t_dma_buf_p->orig_ioaddr_pp; 2912 rbr_rings[i]->hv_rx_buf_ioaddr_size = 2913 (uint64_t)t_dma_buf_p->orig_alength; 2914 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2915 "==> nxge_map_rxdma_channel: " 2916 "channel %d " 2917 "data buf base io $%p ($%p) " 2918 "size 0x%llx (%d 0x%x)", 2919 channel, 2920 rbr_rings[i]->hv_rx_buf_base_ioaddr_pp, 2921 t_dma_cntl_p->ioaddr_pp, 2922 rbr_rings[i]->hv_rx_buf_ioaddr_size, 2923 t_dma_buf_p->orig_alength, 2924 t_dma_buf_p->orig_alength)); 2925 2926 rbr_rings[i]->hv_rx_cntl_base_ioaddr_pp = 2927 (uint64_t)t_dma_cntl_p->orig_ioaddr_pp; 2928 rbr_rings[i]->hv_rx_cntl_ioaddr_size = 2929 (uint64_t)t_dma_cntl_p->orig_alength; 2930 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2931 "==> nxge_map_rxdma_channel: " 2932 "channel %d " 2933 "cntl base io $%p ($%p) " 2934 "size 0x%llx (%d 0x%x)", 2935 channel, 2936 rbr_rings[i]->hv_rx_cntl_base_ioaddr_pp, 2937 t_dma_cntl_p->ioaddr_pp, 2938 rbr_rings[i]->hv_rx_cntl_ioaddr_size, 2939 t_dma_cntl_p->orig_alength, 2940 t_dma_cntl_p->orig_alength)); 2941 } 2942 2943 #endif /* sun4v and NIU_LP_WORKAROUND */ 2944 } 2945 2946 rx_rbr_rings->ndmas = rx_rcr_rings->ndmas = ndmas; 2947 rx_rbr_rings->rbr_rings = rbr_rings; 2948 nxgep->rx_rbr_rings = rx_rbr_rings; 2949 rx_rcr_rings->rcr_rings = rcr_rings; 2950 nxgep->rx_rcr_rings = rx_rcr_rings; 2951 2952 rx_mbox_areas_p->rxmbox_areas = rx_mbox_p; 2953 nxgep->rx_mbox_areas_p = rx_mbox_areas_p; 2954 2955 goto nxge_map_rxdma_exit; 2956 2957 nxge_map_rxdma_fail1: 2958 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2959 "==> nxge_map_rxdma: unmap rbr,rcr " 2960 "(status 0x%x channel %d i %d)", 2961 status, channel, i)); 2962 i--; 2963 for (; i >= 0; i--) { 2964 channel = ((p_nxge_dma_common_t)dma_buf_p[i])->dma_channel; 2965 nxge_unmap_rxdma_channel(nxgep, channel, 2966 rbr_rings[i], 2967 rcr_rings[i], 2968 rx_mbox_p[i]); 2969 } 2970 2971 KMEM_FREE(rbr_rings, sizeof (p_rx_rbr_ring_t) * ndmas); 2972 KMEM_FREE(rx_rbr_rings, sizeof (rx_rbr_rings_t)); 2973 KMEM_FREE(rcr_rings, sizeof (p_rx_rcr_ring_t) * ndmas); 2974 KMEM_FREE(rx_rcr_rings, sizeof (rx_rcr_rings_t)); 2975 KMEM_FREE(rx_mbox_p, sizeof (p_rx_mbox_t) * ndmas); 2976 KMEM_FREE(rx_mbox_areas_p, sizeof (rx_mbox_areas_t)); 2977 2978 nxge_map_rxdma_exit: 2979 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2980 "<== nxge_map_rxdma: " 2981 "(status 0x%x channel %d)", 2982 status, channel)); 2983 2984 return (status); 2985 } 2986 2987 static void 2988 nxge_unmap_rxdma(p_nxge_t nxgep) 2989 { 2990 int i, ndmas; 2991 uint16_t channel; 2992 p_rx_rbr_rings_t rx_rbr_rings; 2993 p_rx_rbr_ring_t *rbr_rings; 2994 p_rx_rcr_rings_t rx_rcr_rings; 2995 p_rx_rcr_ring_t *rcr_rings; 2996 p_rx_mbox_areas_t rx_mbox_areas_p; 2997 p_rx_mbox_t *rx_mbox_p; 2998 p_nxge_dma_pool_t dma_buf_poolp; 2999 p_nxge_dma_pool_t dma_cntl_poolp; 3000 p_nxge_dma_common_t *dma_buf_p; 3001 3002 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_unmap_rxdma")); 3003 3004 dma_buf_poolp = nxgep->rx_buf_pool_p; 3005 dma_cntl_poolp = nxgep->rx_cntl_pool_p; 3006 3007 if (!dma_buf_poolp->buf_allocated || !dma_cntl_poolp->buf_allocated) { 3008 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3009 "<== nxge_unmap_rxdma: NULL buf pointers")); 3010 return; 3011 } 3012 3013 rx_rbr_rings = nxgep->rx_rbr_rings; 3014 rx_rcr_rings = nxgep->rx_rcr_rings; 3015 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 3016 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3017 "<== nxge_unmap_rxdma: NULL ring pointers")); 3018 return; 3019 } 3020 ndmas = rx_rbr_rings->ndmas; 3021 if (!ndmas) { 3022 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3023 "<== nxge_unmap_rxdma: no channel")); 3024 return; 3025 } 3026 3027 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3028 "==> nxge_unmap_rxdma (ndmas %d)", ndmas)); 3029 rbr_rings = rx_rbr_rings->rbr_rings; 3030 rcr_rings = rx_rcr_rings->rcr_rings; 3031 rx_mbox_areas_p = nxgep->rx_mbox_areas_p; 3032 rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 3033 dma_buf_p = dma_buf_poolp->dma_buf_pool_p; 3034 3035 for (i = 0; i < ndmas; i++) { 3036 channel = ((p_nxge_dma_common_t)dma_buf_p[i])->dma_channel; 3037 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3038 "==> nxge_unmap_rxdma (ndmas %d) channel %d", 3039 ndmas, channel)); 3040 (void) nxge_unmap_rxdma_channel(nxgep, channel, 3041 (p_rx_rbr_ring_t)rbr_rings[i], 3042 (p_rx_rcr_ring_t)rcr_rings[i], 3043 (p_rx_mbox_t)rx_mbox_p[i]); 3044 } 3045 3046 KMEM_FREE(rx_rbr_rings, sizeof (rx_rbr_rings_t)); 3047 KMEM_FREE(rbr_rings, sizeof (p_rx_rbr_ring_t) * ndmas); 3048 KMEM_FREE(rx_rcr_rings, sizeof (rx_rcr_rings_t)); 3049 KMEM_FREE(rcr_rings, sizeof (p_rx_rcr_ring_t) * ndmas); 3050 KMEM_FREE(rx_mbox_areas_p, sizeof (rx_mbox_areas_t)); 3051 KMEM_FREE(rx_mbox_p, sizeof (p_rx_mbox_t) * ndmas); 3052 3053 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3054 "<== nxge_unmap_rxdma")); 3055 } 3056 3057 nxge_status_t 3058 nxge_map_rxdma_channel(p_nxge_t nxgep, uint16_t channel, 3059 p_nxge_dma_common_t *dma_buf_p, p_rx_rbr_ring_t *rbr_p, 3060 uint32_t num_chunks, 3061 p_nxge_dma_common_t *dma_cntl_p, p_rx_rcr_ring_t *rcr_p, 3062 p_rx_mbox_t *rx_mbox_p) 3063 { 3064 int status = NXGE_OK; 3065 3066 /* 3067 * Set up and prepare buffer blocks, descriptors 3068 * and mailbox. 3069 */ 3070 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3071 "==> nxge_map_rxdma_channel (channel %d)", channel)); 3072 /* 3073 * Receive buffer blocks 3074 */ 3075 status = nxge_map_rxdma_channel_buf_ring(nxgep, channel, 3076 dma_buf_p, rbr_p, num_chunks); 3077 if (status != NXGE_OK) { 3078 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3079 "==> nxge_map_rxdma_channel (channel %d): " 3080 "map buffer failed 0x%x", channel, status)); 3081 goto nxge_map_rxdma_channel_exit; 3082 } 3083 3084 /* 3085 * Receive block ring, completion ring and mailbox. 3086 */ 3087 status = nxge_map_rxdma_channel_cfg_ring(nxgep, channel, 3088 dma_cntl_p, rbr_p, rcr_p, rx_mbox_p); 3089 if (status != NXGE_OK) { 3090 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3091 "==> nxge_map_rxdma_channel (channel %d): " 3092 "map config failed 0x%x", channel, status)); 3093 goto nxge_map_rxdma_channel_fail2; 3094 } 3095 3096 goto nxge_map_rxdma_channel_exit; 3097 3098 nxge_map_rxdma_channel_fail3: 3099 /* Free rbr, rcr */ 3100 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3101 "==> nxge_map_rxdma_channel: free rbr/rcr " 3102 "(status 0x%x channel %d)", 3103 status, channel)); 3104 nxge_unmap_rxdma_channel_cfg_ring(nxgep, 3105 *rcr_p, *rx_mbox_p); 3106 3107 nxge_map_rxdma_channel_fail2: 3108 /* Free buffer blocks */ 3109 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3110 "==> nxge_map_rxdma_channel: free rx buffers" 3111 "(nxgep 0x%x status 0x%x channel %d)", 3112 nxgep, status, channel)); 3113 nxge_unmap_rxdma_channel_buf_ring(nxgep, *rbr_p); 3114 3115 status = NXGE_ERROR; 3116 3117 nxge_map_rxdma_channel_exit: 3118 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3119 "<== nxge_map_rxdma_channel: " 3120 "(nxgep 0x%x status 0x%x channel %d)", 3121 nxgep, status, channel)); 3122 3123 return (status); 3124 } 3125 3126 /*ARGSUSED*/ 3127 static void 3128 nxge_unmap_rxdma_channel(p_nxge_t nxgep, uint16_t channel, 3129 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p) 3130 { 3131 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3132 "==> nxge_unmap_rxdma_channel (channel %d)", channel)); 3133 3134 /* 3135 * unmap receive block ring, completion ring and mailbox. 3136 */ 3137 (void) nxge_unmap_rxdma_channel_cfg_ring(nxgep, 3138 rcr_p, rx_mbox_p); 3139 3140 /* unmap buffer blocks */ 3141 (void) nxge_unmap_rxdma_channel_buf_ring(nxgep, rbr_p); 3142 3143 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_unmap_rxdma_channel")); 3144 } 3145 3146 /*ARGSUSED*/ 3147 static nxge_status_t 3148 nxge_map_rxdma_channel_cfg_ring(p_nxge_t nxgep, uint16_t dma_channel, 3149 p_nxge_dma_common_t *dma_cntl_p, p_rx_rbr_ring_t *rbr_p, 3150 p_rx_rcr_ring_t *rcr_p, p_rx_mbox_t *rx_mbox_p) 3151 { 3152 p_rx_rbr_ring_t rbrp; 3153 p_rx_rcr_ring_t rcrp; 3154 p_rx_mbox_t mboxp; 3155 p_nxge_dma_common_t cntl_dmap; 3156 p_nxge_dma_common_t dmap; 3157 p_rx_msg_t *rx_msg_ring; 3158 p_rx_msg_t rx_msg_p; 3159 p_rbr_cfig_a_t rcfga_p; 3160 p_rbr_cfig_b_t rcfgb_p; 3161 p_rcrcfig_a_t cfga_p; 3162 p_rcrcfig_b_t cfgb_p; 3163 p_rxdma_cfig1_t cfig1_p; 3164 p_rxdma_cfig2_t cfig2_p; 3165 p_rbr_kick_t kick_p; 3166 uint32_t dmaaddrp; 3167 uint32_t *rbr_vaddrp; 3168 uint32_t bkaddr; 3169 nxge_status_t status = NXGE_OK; 3170 int i; 3171 uint32_t nxge_port_rcr_size; 3172 3173 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3174 "==> nxge_map_rxdma_channel_cfg_ring")); 3175 3176 cntl_dmap = *dma_cntl_p; 3177 3178 /* Map in the receive block ring */ 3179 rbrp = *rbr_p; 3180 dmap = (p_nxge_dma_common_t)&rbrp->rbr_desc; 3181 nxge_setup_dma_common(dmap, cntl_dmap, rbrp->rbb_max, 4); 3182 /* 3183 * Zero out buffer block ring descriptors. 3184 */ 3185 bzero((caddr_t)dmap->kaddrp, dmap->alength); 3186 3187 rcfga_p = &(rbrp->rbr_cfga); 3188 rcfgb_p = &(rbrp->rbr_cfgb); 3189 kick_p = &(rbrp->rbr_kick); 3190 rcfga_p->value = 0; 3191 rcfgb_p->value = 0; 3192 kick_p->value = 0; 3193 rbrp->rbr_addr = dmap->dma_cookie.dmac_laddress; 3194 rcfga_p->value = (rbrp->rbr_addr & 3195 (RBR_CFIG_A_STDADDR_MASK | 3196 RBR_CFIG_A_STDADDR_BASE_MASK)); 3197 rcfga_p->value |= ((uint64_t)rbrp->rbb_max << RBR_CFIG_A_LEN_SHIFT); 3198 3199 rcfgb_p->bits.ldw.bufsz0 = rbrp->pkt_buf_size0; 3200 rcfgb_p->bits.ldw.vld0 = 1; 3201 rcfgb_p->bits.ldw.bufsz1 = rbrp->pkt_buf_size1; 3202 rcfgb_p->bits.ldw.vld1 = 1; 3203 rcfgb_p->bits.ldw.bufsz2 = rbrp->pkt_buf_size2; 3204 rcfgb_p->bits.ldw.vld2 = 1; 3205 rcfgb_p->bits.ldw.bksize = nxgep->rx_bksize_code; 3206 3207 /* 3208 * For each buffer block, enter receive block address to the ring. 3209 */ 3210 rbr_vaddrp = (uint32_t *)dmap->kaddrp; 3211 rbrp->rbr_desc_vp = (uint32_t *)dmap->kaddrp; 3212 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3213 "==> nxge_map_rxdma_channel_cfg_ring: channel %d " 3214 "rbr_vaddrp $%p", dma_channel, rbr_vaddrp)); 3215 3216 rx_msg_ring = rbrp->rx_msg_ring; 3217 for (i = 0; i < rbrp->tnblocks; i++) { 3218 rx_msg_p = rx_msg_ring[i]; 3219 rx_msg_p->nxgep = nxgep; 3220 rx_msg_p->rx_rbr_p = rbrp; 3221 bkaddr = (uint32_t) 3222 ((rx_msg_p->buf_dma.dma_cookie.dmac_laddress 3223 >> RBR_BKADDR_SHIFT)); 3224 rx_msg_p->free = B_FALSE; 3225 rx_msg_p->max_usage_cnt = 0xbaddcafe; 3226 3227 *rbr_vaddrp++ = bkaddr; 3228 } 3229 3230 kick_p->bits.ldw.bkadd = rbrp->rbb_max; 3231 rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 3232 3233 rbrp->rbr_rd_index = 0; 3234 3235 rbrp->rbr_consumed = 0; 3236 rbrp->rbr_use_bcopy = B_TRUE; 3237 rbrp->rbr_bufsize_type = RCR_PKTBUFSZ_0; 3238 /* 3239 * Do bcopy on packets greater than bcopy size once 3240 * the lo threshold is reached. 3241 * This lo threshold should be less than the hi threshold. 3242 * 3243 * Do bcopy on every packet once the hi threshold is reached. 3244 */ 3245 if (nxge_rx_threshold_lo >= nxge_rx_threshold_hi) { 3246 /* default it to use hi */ 3247 nxge_rx_threshold_lo = nxge_rx_threshold_hi; 3248 } 3249 3250 if (nxge_rx_buf_size_type > NXGE_RBR_TYPE2) { 3251 nxge_rx_buf_size_type = NXGE_RBR_TYPE2; 3252 } 3253 rbrp->rbr_bufsize_type = nxge_rx_buf_size_type; 3254 3255 switch (nxge_rx_threshold_hi) { 3256 default: 3257 case NXGE_RX_COPY_NONE: 3258 /* Do not do bcopy at all */ 3259 rbrp->rbr_use_bcopy = B_FALSE; 3260 rbrp->rbr_threshold_hi = rbrp->rbb_max; 3261 break; 3262 3263 case NXGE_RX_COPY_1: 3264 case NXGE_RX_COPY_2: 3265 case NXGE_RX_COPY_3: 3266 case NXGE_RX_COPY_4: 3267 case NXGE_RX_COPY_5: 3268 case NXGE_RX_COPY_6: 3269 case NXGE_RX_COPY_7: 3270 rbrp->rbr_threshold_hi = 3271 rbrp->rbb_max * 3272 (nxge_rx_threshold_hi)/NXGE_RX_BCOPY_SCALE; 3273 break; 3274 3275 case NXGE_RX_COPY_ALL: 3276 rbrp->rbr_threshold_hi = 0; 3277 break; 3278 } 3279 3280 switch (nxge_rx_threshold_lo) { 3281 default: 3282 case NXGE_RX_COPY_NONE: 3283 /* Do not do bcopy at all */ 3284 if (rbrp->rbr_use_bcopy) { 3285 rbrp->rbr_use_bcopy = B_FALSE; 3286 } 3287 rbrp->rbr_threshold_lo = rbrp->rbb_max; 3288 break; 3289 3290 case NXGE_RX_COPY_1: 3291 case NXGE_RX_COPY_2: 3292 case NXGE_RX_COPY_3: 3293 case NXGE_RX_COPY_4: 3294 case NXGE_RX_COPY_5: 3295 case NXGE_RX_COPY_6: 3296 case NXGE_RX_COPY_7: 3297 rbrp->rbr_threshold_lo = 3298 rbrp->rbb_max * 3299 (nxge_rx_threshold_lo)/NXGE_RX_BCOPY_SCALE; 3300 break; 3301 3302 case NXGE_RX_COPY_ALL: 3303 rbrp->rbr_threshold_lo = 0; 3304 break; 3305 } 3306 3307 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3308 "nxge_map_rxdma_channel_cfg_ring: channel %d " 3309 "rbb_max %d " 3310 "rbrp->rbr_bufsize_type %d " 3311 "rbb_threshold_hi %d " 3312 "rbb_threshold_lo %d", 3313 dma_channel, 3314 rbrp->rbb_max, 3315 rbrp->rbr_bufsize_type, 3316 rbrp->rbr_threshold_hi, 3317 rbrp->rbr_threshold_lo)); 3318 3319 rbrp->page_valid.value = 0; 3320 rbrp->page_mask_1.value = rbrp->page_mask_2.value = 0; 3321 rbrp->page_value_1.value = rbrp->page_value_2.value = 0; 3322 rbrp->page_reloc_1.value = rbrp->page_reloc_2.value = 0; 3323 rbrp->page_hdl.value = 0; 3324 3325 rbrp->page_valid.bits.ldw.page0 = 1; 3326 rbrp->page_valid.bits.ldw.page1 = 1; 3327 3328 /* Map in the receive completion ring */ 3329 rcrp = (p_rx_rcr_ring_t) 3330 KMEM_ZALLOC(sizeof (rx_rcr_ring_t), KM_SLEEP); 3331 rcrp->rdc = dma_channel; 3332 3333 nxge_port_rcr_size = nxgep->nxge_port_rcr_size; 3334 rcrp->comp_size = nxge_port_rcr_size; 3335 rcrp->comp_wrap_mask = nxge_port_rcr_size - 1; 3336 3337 rcrp->max_receive_pkts = nxge_max_rx_pkts; 3338 3339 dmap = (p_nxge_dma_common_t)&rcrp->rcr_desc; 3340 nxge_setup_dma_common(dmap, cntl_dmap, rcrp->comp_size, 3341 sizeof (rcr_entry_t)); 3342 rcrp->comp_rd_index = 0; 3343 rcrp->comp_wt_index = 0; 3344 rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p = 3345 (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc); 3346 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 3347 #if defined(__i386) 3348 (p_rcr_entry_t)(uint32_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 3349 #else 3350 (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 3351 #endif 3352 3353 rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p + 3354 (nxge_port_rcr_size - 1); 3355 rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp + 3356 (nxge_port_rcr_size - 1); 3357 3358 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3359 "==> nxge_map_rxdma_channel_cfg_ring: " 3360 "channel %d " 3361 "rbr_vaddrp $%p " 3362 "rcr_desc_rd_head_p $%p " 3363 "rcr_desc_rd_head_pp $%p " 3364 "rcr_desc_rd_last_p $%p " 3365 "rcr_desc_rd_last_pp $%p ", 3366 dma_channel, 3367 rbr_vaddrp, 3368 rcrp->rcr_desc_rd_head_p, 3369 rcrp->rcr_desc_rd_head_pp, 3370 rcrp->rcr_desc_last_p, 3371 rcrp->rcr_desc_last_pp)); 3372 3373 /* 3374 * Zero out buffer block ring descriptors. 3375 */ 3376 bzero((caddr_t)dmap->kaddrp, dmap->alength); 3377 rcrp->intr_timeout = nxgep->intr_timeout; 3378 rcrp->intr_threshold = nxgep->intr_threshold; 3379 rcrp->full_hdr_flag = B_FALSE; 3380 rcrp->sw_priv_hdr_len = 0; 3381 3382 cfga_p = &(rcrp->rcr_cfga); 3383 cfgb_p = &(rcrp->rcr_cfgb); 3384 cfga_p->value = 0; 3385 cfgb_p->value = 0; 3386 rcrp->rcr_addr = dmap->dma_cookie.dmac_laddress; 3387 cfga_p->value = (rcrp->rcr_addr & 3388 (RCRCFIG_A_STADDR_MASK | 3389 RCRCFIG_A_STADDR_BASE_MASK)); 3390 3391 rcfga_p->value |= ((uint64_t)rcrp->comp_size << 3392 RCRCFIG_A_LEN_SHIF); 3393 3394 /* 3395 * Timeout should be set based on the system clock divider. 3396 * The following timeout value of 1 assumes that the 3397 * granularity (1000) is 3 microseconds running at 300MHz. 3398 */ 3399 cfgb_p->bits.ldw.pthres = rcrp->intr_threshold; 3400 cfgb_p->bits.ldw.timeout = rcrp->intr_timeout; 3401 cfgb_p->bits.ldw.entout = 1; 3402 3403 /* Map in the mailbox */ 3404 mboxp = (p_rx_mbox_t) 3405 KMEM_ZALLOC(sizeof (rx_mbox_t), KM_SLEEP); 3406 dmap = (p_nxge_dma_common_t)&mboxp->rx_mbox; 3407 nxge_setup_dma_common(dmap, cntl_dmap, 1, sizeof (rxdma_mailbox_t)); 3408 cfig1_p = (p_rxdma_cfig1_t)&mboxp->rx_cfg1; 3409 cfig2_p = (p_rxdma_cfig2_t)&mboxp->rx_cfg2; 3410 cfig1_p->value = cfig2_p->value = 0; 3411 3412 mboxp->mbox_addr = dmap->dma_cookie.dmac_laddress; 3413 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3414 "==> nxge_map_rxdma_channel_cfg_ring: " 3415 "channel %d cfg1 0x%016llx cfig2 0x%016llx cookie 0x%016llx", 3416 dma_channel, cfig1_p->value, cfig2_p->value, 3417 mboxp->mbox_addr)); 3418 3419 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress >> 32 3420 & 0xfff); 3421 cfig1_p->bits.ldw.mbaddr_h = dmaaddrp; 3422 3423 3424 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress & 0xffffffff); 3425 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress & 3426 RXDMA_CFIG2_MBADDR_L_MASK); 3427 3428 cfig2_p->bits.ldw.mbaddr = (dmaaddrp >> RXDMA_CFIG2_MBADDR_L_SHIFT); 3429 3430 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3431 "==> nxge_map_rxdma_channel_cfg_ring: " 3432 "channel %d damaddrp $%p " 3433 "cfg1 0x%016llx cfig2 0x%016llx", 3434 dma_channel, dmaaddrp, 3435 cfig1_p->value, cfig2_p->value)); 3436 3437 cfig2_p->bits.ldw.full_hdr = rcrp->full_hdr_flag; 3438 cfig2_p->bits.ldw.offset = rcrp->sw_priv_hdr_len; 3439 3440 rbrp->rx_rcr_p = rcrp; 3441 rcrp->rx_rbr_p = rbrp; 3442 *rcr_p = rcrp; 3443 *rx_mbox_p = mboxp; 3444 3445 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3446 "<== nxge_map_rxdma_channel_cfg_ring status 0x%08x", status)); 3447 3448 return (status); 3449 } 3450 3451 /*ARGSUSED*/ 3452 static void 3453 nxge_unmap_rxdma_channel_cfg_ring(p_nxge_t nxgep, 3454 p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p) 3455 { 3456 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3457 "==> nxge_unmap_rxdma_channel_cfg_ring: channel %d", 3458 rcr_p->rdc)); 3459 3460 KMEM_FREE(rcr_p, sizeof (rx_rcr_ring_t)); 3461 KMEM_FREE(rx_mbox_p, sizeof (rx_mbox_t)); 3462 3463 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3464 "<== nxge_unmap_rxdma_channel_cfg_ring")); 3465 } 3466 3467 static nxge_status_t 3468 nxge_map_rxdma_channel_buf_ring(p_nxge_t nxgep, uint16_t channel, 3469 p_nxge_dma_common_t *dma_buf_p, 3470 p_rx_rbr_ring_t *rbr_p, uint32_t num_chunks) 3471 { 3472 p_rx_rbr_ring_t rbrp; 3473 p_nxge_dma_common_t dma_bufp, tmp_bufp; 3474 p_rx_msg_t *rx_msg_ring; 3475 p_rx_msg_t rx_msg_p; 3476 p_mblk_t mblk_p; 3477 3478 rxring_info_t *ring_info; 3479 nxge_status_t status = NXGE_OK; 3480 int i, j, index; 3481 uint32_t size, bsize, nblocks, nmsgs; 3482 3483 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3484 "==> nxge_map_rxdma_channel_buf_ring: channel %d", 3485 channel)); 3486 3487 dma_bufp = tmp_bufp = *dma_buf_p; 3488 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3489 " nxge_map_rxdma_channel_buf_ring: channel %d to map %d " 3490 "chunks bufp 0x%016llx", 3491 channel, num_chunks, dma_bufp)); 3492 3493 nmsgs = 0; 3494 for (i = 0; i < num_chunks; i++, tmp_bufp++) { 3495 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3496 "==> nxge_map_rxdma_channel_buf_ring: channel %d " 3497 "bufp 0x%016llx nblocks %d nmsgs %d", 3498 channel, tmp_bufp, tmp_bufp->nblocks, nmsgs)); 3499 nmsgs += tmp_bufp->nblocks; 3500 } 3501 if (!nmsgs) { 3502 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3503 "<== nxge_map_rxdma_channel_buf_ring: channel %d " 3504 "no msg blocks", 3505 channel)); 3506 status = NXGE_ERROR; 3507 goto nxge_map_rxdma_channel_buf_ring_exit; 3508 } 3509 3510 rbrp = (p_rx_rbr_ring_t)KMEM_ZALLOC(sizeof (*rbrp), KM_SLEEP); 3511 3512 size = nmsgs * sizeof (p_rx_msg_t); 3513 rx_msg_ring = KMEM_ZALLOC(size, KM_SLEEP); 3514 ring_info = (rxring_info_t *)KMEM_ZALLOC(sizeof (rxring_info_t), 3515 KM_SLEEP); 3516 3517 MUTEX_INIT(&rbrp->lock, NULL, MUTEX_DRIVER, 3518 (void *)nxgep->interrupt_cookie); 3519 MUTEX_INIT(&rbrp->post_lock, NULL, MUTEX_DRIVER, 3520 (void *)nxgep->interrupt_cookie); 3521 rbrp->rdc = channel; 3522 rbrp->num_blocks = num_chunks; 3523 rbrp->tnblocks = nmsgs; 3524 rbrp->rbb_max = nmsgs; 3525 rbrp->rbr_max_size = nmsgs; 3526 rbrp->rbr_wrap_mask = (rbrp->rbb_max - 1); 3527 3528 /* 3529 * Buffer sizes suggested by NIU architect. 3530 * 256, 512 and 2K. 3531 */ 3532 3533 rbrp->pkt_buf_size0 = RBR_BUFSZ0_256B; 3534 rbrp->pkt_buf_size0_bytes = RBR_BUFSZ0_256_BYTES; 3535 rbrp->npi_pkt_buf_size0 = SIZE_256B; 3536 3537 rbrp->pkt_buf_size1 = RBR_BUFSZ1_1K; 3538 rbrp->pkt_buf_size1_bytes = RBR_BUFSZ1_1K_BYTES; 3539 rbrp->npi_pkt_buf_size1 = SIZE_1KB; 3540 3541 rbrp->block_size = nxgep->rx_default_block_size; 3542 3543 if (!nxge_jumbo_enable && !nxgep->param_arr[param_accept_jumbo].value) { 3544 rbrp->pkt_buf_size2 = RBR_BUFSZ2_2K; 3545 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_2K_BYTES; 3546 rbrp->npi_pkt_buf_size2 = SIZE_2KB; 3547 } else { 3548 if (rbrp->block_size >= 0x2000) { 3549 rbrp->pkt_buf_size2 = RBR_BUFSZ2_8K; 3550 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_8K_BYTES; 3551 rbrp->npi_pkt_buf_size2 = SIZE_8KB; 3552 } else { 3553 rbrp->pkt_buf_size2 = RBR_BUFSZ2_4K; 3554 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_4K_BYTES; 3555 rbrp->npi_pkt_buf_size2 = SIZE_4KB; 3556 } 3557 } 3558 3559 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3560 "==> nxge_map_rxdma_channel_buf_ring: channel %d " 3561 "actual rbr max %d rbb_max %d nmsgs %d " 3562 "rbrp->block_size %d default_block_size %d " 3563 "(config nxge_rbr_size %d nxge_rbr_spare_size %d)", 3564 channel, rbrp->rbr_max_size, rbrp->rbb_max, nmsgs, 3565 rbrp->block_size, nxgep->rx_default_block_size, 3566 nxge_rbr_size, nxge_rbr_spare_size)); 3567 3568 /* Map in buffers from the buffer pool. */ 3569 index = 0; 3570 for (i = 0; i < rbrp->num_blocks; i++, dma_bufp++) { 3571 bsize = dma_bufp->block_size; 3572 nblocks = dma_bufp->nblocks; 3573 #if defined(__i386) 3574 ring_info->buffer[i].dvma_addr = (uint32_t)dma_bufp->ioaddr_pp; 3575 #else 3576 ring_info->buffer[i].dvma_addr = (uint64_t)dma_bufp->ioaddr_pp; 3577 #endif 3578 ring_info->buffer[i].buf_index = i; 3579 ring_info->buffer[i].buf_size = dma_bufp->alength; 3580 ring_info->buffer[i].start_index = index; 3581 #if defined(__i386) 3582 ring_info->buffer[i].kaddr = (uint32_t)dma_bufp->kaddrp; 3583 #else 3584 ring_info->buffer[i].kaddr = (uint64_t)dma_bufp->kaddrp; 3585 #endif 3586 3587 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3588 " nxge_map_rxdma_channel_buf_ring: map channel %d " 3589 "chunk %d" 3590 " nblocks %d chunk_size %x block_size 0x%x " 3591 "dma_bufp $%p", channel, i, 3592 dma_bufp->nblocks, ring_info->buffer[i].buf_size, bsize, 3593 dma_bufp)); 3594 3595 for (j = 0; j < nblocks; j++) { 3596 if ((rx_msg_p = nxge_allocb(bsize, BPRI_LO, 3597 dma_bufp)) == NULL) { 3598 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3599 "allocb failed (index %d i %d j %d)", 3600 index, i, j)); 3601 goto nxge_map_rxdma_channel_buf_ring_fail1; 3602 } 3603 rx_msg_ring[index] = rx_msg_p; 3604 rx_msg_p->block_index = index; 3605 rx_msg_p->shifted_addr = (uint32_t) 3606 ((rx_msg_p->buf_dma.dma_cookie.dmac_laddress >> 3607 RBR_BKADDR_SHIFT)); 3608 3609 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3610 "index %d j %d rx_msg_p $%p mblk %p", 3611 index, j, rx_msg_p, rx_msg_p->rx_mblk_p)); 3612 3613 mblk_p = rx_msg_p->rx_mblk_p; 3614 mblk_p->b_wptr = mblk_p->b_rptr + bsize; 3615 3616 rbrp->rbr_ref_cnt++; 3617 index++; 3618 rx_msg_p->buf_dma.dma_channel = channel; 3619 } 3620 } 3621 if (i < rbrp->num_blocks) { 3622 goto nxge_map_rxdma_channel_buf_ring_fail1; 3623 } 3624 3625 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3626 "nxge_map_rxdma_channel_buf_ring: done buf init " 3627 "channel %d msg block entries %d", 3628 channel, index)); 3629 ring_info->block_size_mask = bsize - 1; 3630 rbrp->rx_msg_ring = rx_msg_ring; 3631 rbrp->dma_bufp = dma_buf_p; 3632 rbrp->ring_info = ring_info; 3633 3634 status = nxge_rxbuf_index_info_init(nxgep, rbrp); 3635 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3636 " nxge_map_rxdma_channel_buf_ring: " 3637 "channel %d done buf info init", channel)); 3638 3639 /* 3640 * Finally, permit nxge_freeb() to call nxge_post_page(). 3641 */ 3642 rbrp->rbr_state = RBR_POSTING; 3643 3644 *rbr_p = rbrp; 3645 goto nxge_map_rxdma_channel_buf_ring_exit; 3646 3647 nxge_map_rxdma_channel_buf_ring_fail1: 3648 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3649 " nxge_map_rxdma_channel_buf_ring: failed channel (0x%x)", 3650 channel, status)); 3651 3652 index--; 3653 for (; index >= 0; index--) { 3654 rx_msg_p = rx_msg_ring[index]; 3655 if (rx_msg_p != NULL) { 3656 freeb(rx_msg_p->rx_mblk_p); 3657 rx_msg_ring[index] = NULL; 3658 } 3659 } 3660 nxge_map_rxdma_channel_buf_ring_fail: 3661 MUTEX_DESTROY(&rbrp->post_lock); 3662 MUTEX_DESTROY(&rbrp->lock); 3663 KMEM_FREE(ring_info, sizeof (rxring_info_t)); 3664 KMEM_FREE(rx_msg_ring, size); 3665 KMEM_FREE(rbrp, sizeof (rx_rbr_ring_t)); 3666 3667 status = NXGE_ERROR; 3668 3669 nxge_map_rxdma_channel_buf_ring_exit: 3670 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3671 "<== nxge_map_rxdma_channel_buf_ring status 0x%08x", status)); 3672 3673 return (status); 3674 } 3675 3676 /*ARGSUSED*/ 3677 static void 3678 nxge_unmap_rxdma_channel_buf_ring(p_nxge_t nxgep, 3679 p_rx_rbr_ring_t rbr_p) 3680 { 3681 p_rx_msg_t *rx_msg_ring; 3682 p_rx_msg_t rx_msg_p; 3683 rxring_info_t *ring_info; 3684 int i; 3685 uint32_t size; 3686 #ifdef NXGE_DEBUG 3687 int num_chunks; 3688 #endif 3689 3690 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3691 "==> nxge_unmap_rxdma_channel_buf_ring")); 3692 if (rbr_p == NULL) { 3693 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3694 "<== nxge_unmap_rxdma_channel_buf_ring: NULL rbrp")); 3695 return; 3696 } 3697 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3698 "==> nxge_unmap_rxdma_channel_buf_ring: channel %d", 3699 rbr_p->rdc)); 3700 3701 rx_msg_ring = rbr_p->rx_msg_ring; 3702 ring_info = rbr_p->ring_info; 3703 3704 if (rx_msg_ring == NULL || ring_info == NULL) { 3705 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3706 "<== nxge_unmap_rxdma_channel_buf_ring: " 3707 "rx_msg_ring $%p ring_info $%p", 3708 rx_msg_p, ring_info)); 3709 return; 3710 } 3711 3712 #ifdef NXGE_DEBUG 3713 num_chunks = rbr_p->num_blocks; 3714 #endif 3715 size = rbr_p->tnblocks * sizeof (p_rx_msg_t); 3716 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3717 " nxge_unmap_rxdma_channel_buf_ring: channel %d chunks %d " 3718 "tnblocks %d (max %d) size ptrs %d ", 3719 rbr_p->rdc, num_chunks, 3720 rbr_p->tnblocks, rbr_p->rbr_max_size, size)); 3721 3722 for (i = 0; i < rbr_p->tnblocks; i++) { 3723 rx_msg_p = rx_msg_ring[i]; 3724 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3725 " nxge_unmap_rxdma_channel_buf_ring: " 3726 "rx_msg_p $%p", 3727 rx_msg_p)); 3728 if (rx_msg_p != NULL) { 3729 freeb(rx_msg_p->rx_mblk_p); 3730 rx_msg_ring[i] = NULL; 3731 } 3732 } 3733 3734 /* 3735 * We no longer may use the mutex <post_lock>. By setting 3736 * <rbr_state> to anything but POSTING, we prevent 3737 * nxge_post_page() from accessing a dead mutex. 3738 */ 3739 rbr_p->rbr_state = RBR_UNMAPPING; 3740 MUTEX_DESTROY(&rbr_p->post_lock); 3741 3742 MUTEX_DESTROY(&rbr_p->lock); 3743 KMEM_FREE(ring_info, sizeof (rxring_info_t)); 3744 KMEM_FREE(rx_msg_ring, size); 3745 3746 if (rbr_p->rbr_ref_cnt == 0) { 3747 /* This is the normal state of affairs. */ 3748 KMEM_FREE(rbr_p, sizeof (*rbr_p)); 3749 } else { 3750 /* 3751 * Some of our buffers are still being used. 3752 * Therefore, tell nxge_freeb() this ring is 3753 * unmapped, so it may free <rbr_p> for us. 3754 */ 3755 rbr_p->rbr_state = RBR_UNMAPPED; 3756 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3757 "unmap_rxdma_buf_ring: %d %s outstanding.", 3758 rbr_p->rbr_ref_cnt, 3759 rbr_p->rbr_ref_cnt == 1 ? "msg" : "msgs")); 3760 } 3761 3762 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3763 "<== nxge_unmap_rxdma_channel_buf_ring")); 3764 } 3765 3766 static nxge_status_t 3767 nxge_rxdma_hw_start_common(p_nxge_t nxgep) 3768 { 3769 nxge_status_t status = NXGE_OK; 3770 3771 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start_common")); 3772 3773 /* 3774 * Load the sharable parameters by writing to the 3775 * function zero control registers. These FZC registers 3776 * should be initialized only once for the entire chip. 3777 */ 3778 (void) nxge_init_fzc_rx_common(nxgep); 3779 3780 /* 3781 * Initialize the RXDMA port specific FZC control configurations. 3782 * These FZC registers are pertaining to each port. 3783 */ 3784 (void) nxge_init_fzc_rxdma_port(nxgep); 3785 3786 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start_common")); 3787 3788 return (status); 3789 } 3790 3791 /*ARGSUSED*/ 3792 static void 3793 nxge_rxdma_hw_stop_common(p_nxge_t nxgep) 3794 { 3795 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_stop_common")); 3796 3797 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_stop_common")); 3798 } 3799 3800 static nxge_status_t 3801 nxge_rxdma_hw_start(p_nxge_t nxgep) 3802 { 3803 int i, ndmas; 3804 uint16_t channel; 3805 p_rx_rbr_rings_t rx_rbr_rings; 3806 p_rx_rbr_ring_t *rbr_rings; 3807 p_rx_rcr_rings_t rx_rcr_rings; 3808 p_rx_rcr_ring_t *rcr_rings; 3809 p_rx_mbox_areas_t rx_mbox_areas_p; 3810 p_rx_mbox_t *rx_mbox_p; 3811 nxge_status_t status = NXGE_OK; 3812 3813 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start")); 3814 3815 rx_rbr_rings = nxgep->rx_rbr_rings; 3816 rx_rcr_rings = nxgep->rx_rcr_rings; 3817 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 3818 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3819 "<== nxge_rxdma_hw_start: NULL ring pointers")); 3820 return (NXGE_ERROR); 3821 } 3822 ndmas = rx_rbr_rings->ndmas; 3823 if (ndmas == 0) { 3824 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3825 "<== nxge_rxdma_hw_start: no dma channel allocated")); 3826 return (NXGE_ERROR); 3827 } 3828 3829 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3830 "==> nxge_rxdma_hw_start (ndmas %d)", ndmas)); 3831 3832 rbr_rings = rx_rbr_rings->rbr_rings; 3833 rcr_rings = rx_rcr_rings->rcr_rings; 3834 rx_mbox_areas_p = nxgep->rx_mbox_areas_p; 3835 if (rx_mbox_areas_p) { 3836 rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 3837 } 3838 3839 for (i = 0; i < ndmas; i++) { 3840 channel = rbr_rings[i]->rdc; 3841 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3842 "==> nxge_rxdma_hw_start (ndmas %d) channel %d", 3843 ndmas, channel)); 3844 status = nxge_rxdma_start_channel(nxgep, channel, 3845 (p_rx_rbr_ring_t)rbr_rings[i], 3846 (p_rx_rcr_ring_t)rcr_rings[i], 3847 (p_rx_mbox_t)rx_mbox_p[i]); 3848 if (status != NXGE_OK) { 3849 goto nxge_rxdma_hw_start_fail1; 3850 } 3851 } 3852 3853 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start: " 3854 "rx_rbr_rings 0x%016llx rings 0x%016llx", 3855 rx_rbr_rings, rx_rcr_rings)); 3856 3857 goto nxge_rxdma_hw_start_exit; 3858 3859 nxge_rxdma_hw_start_fail1: 3860 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3861 "==> nxge_rxdma_hw_start: disable " 3862 "(status 0x%x channel %d i %d)", status, channel, i)); 3863 for (; i >= 0; i--) { 3864 channel = rbr_rings[i]->rdc; 3865 (void) nxge_rxdma_stop_channel(nxgep, channel); 3866 } 3867 3868 nxge_rxdma_hw_start_exit: 3869 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3870 "==> nxge_rxdma_hw_start: (status 0x%x)", status)); 3871 3872 return (status); 3873 } 3874 3875 static void 3876 nxge_rxdma_hw_stop(p_nxge_t nxgep) 3877 { 3878 int i, ndmas; 3879 uint16_t channel; 3880 p_rx_rbr_rings_t rx_rbr_rings; 3881 p_rx_rbr_ring_t *rbr_rings; 3882 p_rx_rcr_rings_t rx_rcr_rings; 3883 3884 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_stop")); 3885 3886 rx_rbr_rings = nxgep->rx_rbr_rings; 3887 rx_rcr_rings = nxgep->rx_rcr_rings; 3888 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 3889 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3890 "<== nxge_rxdma_hw_stop: NULL ring pointers")); 3891 return; 3892 } 3893 ndmas = rx_rbr_rings->ndmas; 3894 if (!ndmas) { 3895 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3896 "<== nxge_rxdma_hw_stop: no dma channel allocated")); 3897 return; 3898 } 3899 3900 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3901 "==> nxge_rxdma_hw_stop (ndmas %d)", ndmas)); 3902 3903 rbr_rings = rx_rbr_rings->rbr_rings; 3904 3905 for (i = 0; i < ndmas; i++) { 3906 channel = rbr_rings[i]->rdc; 3907 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3908 "==> nxge_rxdma_hw_stop (ndmas %d) channel %d", 3909 ndmas, channel)); 3910 (void) nxge_rxdma_stop_channel(nxgep, channel); 3911 } 3912 3913 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_stop: " 3914 "rx_rbr_rings 0x%016llx rings 0x%016llx", 3915 rx_rbr_rings, rx_rcr_rings)); 3916 3917 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_rxdma_hw_stop")); 3918 } 3919 3920 3921 static nxge_status_t 3922 nxge_rxdma_start_channel(p_nxge_t nxgep, uint16_t channel, 3923 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p) 3924 3925 { 3926 npi_handle_t handle; 3927 npi_status_t rs = NPI_SUCCESS; 3928 rx_dma_ctl_stat_t cs; 3929 rx_dma_ent_msk_t ent_mask; 3930 nxge_status_t status = NXGE_OK; 3931 3932 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel")); 3933 3934 handle = NXGE_DEV_NPI_HANDLE(nxgep); 3935 3936 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "nxge_rxdma_start_channel: " 3937 "npi handle addr $%p acc $%p", 3938 nxgep->npi_handle.regp, nxgep->npi_handle.regh)); 3939 3940 /* Reset RXDMA channel */ 3941 rs = npi_rxdma_cfg_rdc_reset(handle, channel); 3942 if (rs != NPI_SUCCESS) { 3943 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3944 "==> nxge_rxdma_start_channel: " 3945 "reset rxdma failed (0x%08x channel %d)", 3946 status, channel)); 3947 return (NXGE_ERROR | rs); 3948 } 3949 3950 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3951 "==> nxge_rxdma_start_channel: reset done: channel %d", 3952 channel)); 3953 3954 /* 3955 * Initialize the RXDMA channel specific FZC control 3956 * configurations. These FZC registers are pertaining 3957 * to each RX channel (logical pages). 3958 */ 3959 status = nxge_init_fzc_rxdma_channel(nxgep, 3960 channel, rbr_p, rcr_p, mbox_p); 3961 if (status != NXGE_OK) { 3962 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3963 "==> nxge_rxdma_start_channel: " 3964 "init fzc rxdma failed (0x%08x channel %d)", 3965 status, channel)); 3966 return (status); 3967 } 3968 3969 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3970 "==> nxge_rxdma_start_channel: fzc done")); 3971 3972 /* 3973 * Zero out the shadow and prefetch ram. 3974 */ 3975 3976 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 3977 "ram done")); 3978 3979 /* Set up the interrupt event masks. */ 3980 ent_mask.value = 0; 3981 ent_mask.value |= RX_DMA_ENT_MSK_RBREMPTY_MASK; 3982 rs = npi_rxdma_event_mask(handle, OP_SET, channel, 3983 &ent_mask); 3984 if (rs != NPI_SUCCESS) { 3985 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3986 "==> nxge_rxdma_start_channel: " 3987 "init rxdma event masks failed (0x%08x channel %d)", 3988 status, channel)); 3989 return (NXGE_ERROR | rs); 3990 } 3991 3992 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 3993 "event done: channel %d (mask 0x%016llx)", 3994 channel, ent_mask.value)); 3995 3996 /* Initialize the receive DMA control and status register */ 3997 cs.value = 0; 3998 cs.bits.hdw.mex = 1; 3999 cs.bits.hdw.rcrthres = 1; 4000 cs.bits.hdw.rcrto = 1; 4001 cs.bits.hdw.rbr_empty = 1; 4002 status = nxge_init_rxdma_channel_cntl_stat(nxgep, channel, &cs); 4003 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 4004 "channel %d rx_dma_cntl_stat 0x%0016llx", channel, cs.value)); 4005 if (status != NXGE_OK) { 4006 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4007 "==> nxge_rxdma_start_channel: " 4008 "init rxdma control register failed (0x%08x channel %d", 4009 status, channel)); 4010 return (status); 4011 } 4012 4013 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 4014 "control done - channel %d cs 0x%016llx", channel, cs.value)); 4015 4016 /* 4017 * Load RXDMA descriptors, buffers, mailbox, 4018 * initialise the receive DMA channels and 4019 * enable each DMA channel. 4020 */ 4021 status = nxge_enable_rxdma_channel(nxgep, 4022 channel, rbr_p, rcr_p, mbox_p); 4023 4024 if (status != NXGE_OK) { 4025 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4026 " nxge_rxdma_start_channel: " 4027 " init enable rxdma failed (0x%08x channel %d)", 4028 status, channel)); 4029 return (status); 4030 } 4031 4032 ent_mask.value = 0; 4033 ent_mask.value |= (RX_DMA_ENT_MSK_WRED_DROP_MASK | 4034 RX_DMA_ENT_MSK_PTDROP_PKT_MASK); 4035 rs = npi_rxdma_event_mask(handle, OP_SET, channel, 4036 &ent_mask); 4037 if (rs != NPI_SUCCESS) { 4038 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4039 "==> nxge_rxdma_start_channel: " 4040 "init rxdma event masks failed (0x%08x channel %d)", 4041 status, channel)); 4042 return (NXGE_ERROR | rs); 4043 } 4044 4045 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 4046 "control done - channel %d cs 0x%016llx", channel, cs.value)); 4047 4048 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4049 "==> nxge_rxdma_start_channel: enable done")); 4050 4051 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_rxdma_start_channel")); 4052 4053 return (NXGE_OK); 4054 } 4055 4056 static nxge_status_t 4057 nxge_rxdma_stop_channel(p_nxge_t nxgep, uint16_t channel) 4058 { 4059 npi_handle_t handle; 4060 npi_status_t rs = NPI_SUCCESS; 4061 rx_dma_ctl_stat_t cs; 4062 rx_dma_ent_msk_t ent_mask; 4063 nxge_status_t status = NXGE_OK; 4064 4065 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop_channel")); 4066 4067 handle = NXGE_DEV_NPI_HANDLE(nxgep); 4068 4069 NXGE_DEBUG_MSG((nxgep, RX_CTL, "nxge_rxdma_stop_channel: " 4070 "npi handle addr $%p acc $%p", 4071 nxgep->npi_handle.regp, nxgep->npi_handle.regh)); 4072 4073 /* Reset RXDMA channel */ 4074 rs = npi_rxdma_cfg_rdc_reset(handle, channel); 4075 if (rs != NPI_SUCCESS) { 4076 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4077 " nxge_rxdma_stop_channel: " 4078 " reset rxdma failed (0x%08x channel %d)", 4079 rs, channel)); 4080 return (NXGE_ERROR | rs); 4081 } 4082 4083 NXGE_DEBUG_MSG((nxgep, RX_CTL, 4084 "==> nxge_rxdma_stop_channel: reset done")); 4085 4086 /* Set up the interrupt event masks. */ 4087 ent_mask.value = RX_DMA_ENT_MSK_ALL; 4088 rs = npi_rxdma_event_mask(handle, OP_SET, channel, 4089 &ent_mask); 4090 if (rs != NPI_SUCCESS) { 4091 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4092 "==> nxge_rxdma_stop_channel: " 4093 "set rxdma event masks failed (0x%08x channel %d)", 4094 rs, channel)); 4095 return (NXGE_ERROR | rs); 4096 } 4097 4098 NXGE_DEBUG_MSG((nxgep, RX_CTL, 4099 "==> nxge_rxdma_stop_channel: event done")); 4100 4101 /* Initialize the receive DMA control and status register */ 4102 cs.value = 0; 4103 status = nxge_init_rxdma_channel_cntl_stat(nxgep, channel, 4104 &cs); 4105 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop_channel: control " 4106 " to default (all 0s) 0x%08x", cs.value)); 4107 if (status != NXGE_OK) { 4108 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4109 " nxge_rxdma_stop_channel: init rxdma" 4110 " control register failed (0x%08x channel %d", 4111 status, channel)); 4112 return (status); 4113 } 4114 4115 NXGE_DEBUG_MSG((nxgep, RX_CTL, 4116 "==> nxge_rxdma_stop_channel: control done")); 4117 4118 /* disable dma channel */ 4119 status = nxge_disable_rxdma_channel(nxgep, channel); 4120 4121 if (status != NXGE_OK) { 4122 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4123 " nxge_rxdma_stop_channel: " 4124 " init enable rxdma failed (0x%08x channel %d)", 4125 status, channel)); 4126 return (status); 4127 } 4128 4129 NXGE_DEBUG_MSG((nxgep, 4130 RX_CTL, "==> nxge_rxdma_stop_channel: disable done")); 4131 4132 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_stop_channel")); 4133 4134 return (NXGE_OK); 4135 } 4136 4137 nxge_status_t 4138 nxge_rxdma_handle_sys_errors(p_nxge_t nxgep) 4139 { 4140 npi_handle_t handle; 4141 p_nxge_rdc_sys_stats_t statsp; 4142 rx_ctl_dat_fifo_stat_t stat; 4143 uint32_t zcp_err_status; 4144 uint32_t ipp_err_status; 4145 nxge_status_t status = NXGE_OK; 4146 npi_status_t rs = NPI_SUCCESS; 4147 boolean_t my_err = B_FALSE; 4148 4149 handle = nxgep->npi_handle; 4150 statsp = (p_nxge_rdc_sys_stats_t)&nxgep->statsp->rdc_sys_stats; 4151 4152 rs = npi_rxdma_rxctl_fifo_error_intr_get(handle, &stat); 4153 4154 if (rs != NPI_SUCCESS) 4155 return (NXGE_ERROR | rs); 4156 4157 if (stat.bits.ldw.id_mismatch) { 4158 statsp->id_mismatch++; 4159 NXGE_FM_REPORT_ERROR(nxgep, nxgep->mac.portnum, NULL, 4160 NXGE_FM_EREPORT_RDMC_ID_MISMATCH); 4161 /* Global fatal error encountered */ 4162 } 4163 4164 if ((stat.bits.ldw.zcp_eop_err) || (stat.bits.ldw.ipp_eop_err)) { 4165 switch (nxgep->mac.portnum) { 4166 case 0: 4167 if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT0) || 4168 (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT0)) { 4169 my_err = B_TRUE; 4170 zcp_err_status = stat.bits.ldw.zcp_eop_err; 4171 ipp_err_status = stat.bits.ldw.ipp_eop_err; 4172 } 4173 break; 4174 case 1: 4175 if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT1) || 4176 (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT1)) { 4177 my_err = B_TRUE; 4178 zcp_err_status = stat.bits.ldw.zcp_eop_err; 4179 ipp_err_status = stat.bits.ldw.ipp_eop_err; 4180 } 4181 break; 4182 case 2: 4183 if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT2) || 4184 (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT2)) { 4185 my_err = B_TRUE; 4186 zcp_err_status = stat.bits.ldw.zcp_eop_err; 4187 ipp_err_status = stat.bits.ldw.ipp_eop_err; 4188 } 4189 break; 4190 case 3: 4191 if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT3) || 4192 (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT3)) { 4193 my_err = B_TRUE; 4194 zcp_err_status = stat.bits.ldw.zcp_eop_err; 4195 ipp_err_status = stat.bits.ldw.ipp_eop_err; 4196 } 4197 break; 4198 default: 4199 return (NXGE_ERROR); 4200 } 4201 } 4202 4203 if (my_err) { 4204 status = nxge_rxdma_handle_port_errors(nxgep, ipp_err_status, 4205 zcp_err_status); 4206 if (status != NXGE_OK) 4207 return (status); 4208 } 4209 4210 return (NXGE_OK); 4211 } 4212 4213 static nxge_status_t 4214 nxge_rxdma_handle_port_errors(p_nxge_t nxgep, uint32_t ipp_status, 4215 uint32_t zcp_status) 4216 { 4217 boolean_t rxport_fatal = B_FALSE; 4218 p_nxge_rdc_sys_stats_t statsp; 4219 nxge_status_t status = NXGE_OK; 4220 uint8_t portn; 4221 4222 portn = nxgep->mac.portnum; 4223 statsp = (p_nxge_rdc_sys_stats_t)&nxgep->statsp->rdc_sys_stats; 4224 4225 if (ipp_status & (0x1 << portn)) { 4226 statsp->ipp_eop_err++; 4227 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 4228 NXGE_FM_EREPORT_RDMC_IPP_EOP_ERR); 4229 rxport_fatal = B_TRUE; 4230 } 4231 4232 if (zcp_status & (0x1 << portn)) { 4233 statsp->zcp_eop_err++; 4234 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 4235 NXGE_FM_EREPORT_RDMC_ZCP_EOP_ERR); 4236 rxport_fatal = B_TRUE; 4237 } 4238 4239 if (rxport_fatal) { 4240 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4241 " nxge_rxdma_handle_port_error: " 4242 " fatal error on Port #%d\n", 4243 portn)); 4244 status = nxge_rx_port_fatal_err_recover(nxgep); 4245 if (status == NXGE_OK) { 4246 FM_SERVICE_RESTORED(nxgep); 4247 } 4248 } 4249 4250 return (status); 4251 } 4252 4253 static nxge_status_t 4254 nxge_rxdma_fatal_err_recover(p_nxge_t nxgep, uint16_t channel) 4255 { 4256 npi_handle_t handle; 4257 npi_status_t rs = NPI_SUCCESS; 4258 nxge_status_t status = NXGE_OK; 4259 p_rx_rbr_ring_t rbrp; 4260 p_rx_rcr_ring_t rcrp; 4261 p_rx_mbox_t mboxp; 4262 rx_dma_ent_msk_t ent_mask; 4263 p_nxge_dma_common_t dmap; 4264 int ring_idx; 4265 uint32_t ref_cnt; 4266 p_rx_msg_t rx_msg_p; 4267 int i; 4268 uint32_t nxge_port_rcr_size; 4269 4270 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_fatal_err_recover")); 4271 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4272 "Recovering from RxDMAChannel#%d error...", channel)); 4273 4274 /* 4275 * Stop the dma channel waits for the stop done. 4276 * If the stop done bit is not set, then create 4277 * an error. 4278 */ 4279 4280 handle = NXGE_DEV_NPI_HANDLE(nxgep); 4281 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Rx DMA stop...")); 4282 4283 ring_idx = nxge_rxdma_get_ring_index(nxgep, channel); 4284 rbrp = (p_rx_rbr_ring_t)nxgep->rx_rbr_rings->rbr_rings[ring_idx]; 4285 rcrp = (p_rx_rcr_ring_t)nxgep->rx_rcr_rings->rcr_rings[ring_idx]; 4286 4287 MUTEX_ENTER(&rcrp->lock); 4288 MUTEX_ENTER(&rbrp->lock); 4289 MUTEX_ENTER(&rbrp->post_lock); 4290 4291 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Disable RxDMA channel...")); 4292 4293 rs = npi_rxdma_cfg_rdc_disable(handle, channel); 4294 if (rs != NPI_SUCCESS) { 4295 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4296 "nxge_disable_rxdma_channel:failed")); 4297 goto fail; 4298 } 4299 4300 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Disable RxDMA interrupt...")); 4301 4302 /* Disable interrupt */ 4303 ent_mask.value = RX_DMA_ENT_MSK_ALL; 4304 rs = npi_rxdma_event_mask(handle, OP_SET, channel, &ent_mask); 4305 if (rs != NPI_SUCCESS) { 4306 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4307 "nxge_rxdma_stop_channel: " 4308 "set rxdma event masks failed (channel %d)", 4309 channel)); 4310 } 4311 4312 NXGE_DEBUG_MSG((nxgep, RX_CTL, "RxDMA channel reset...")); 4313 4314 /* Reset RXDMA channel */ 4315 rs = npi_rxdma_cfg_rdc_reset(handle, channel); 4316 if (rs != NPI_SUCCESS) { 4317 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4318 "nxge_rxdma_fatal_err_recover: " 4319 " reset rxdma failed (channel %d)", channel)); 4320 goto fail; 4321 } 4322 4323 nxge_port_rcr_size = nxgep->nxge_port_rcr_size; 4324 4325 mboxp = 4326 (p_rx_mbox_t)nxgep->rx_mbox_areas_p->rxmbox_areas[ring_idx]; 4327 4328 rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 4329 rbrp->rbr_rd_index = 0; 4330 4331 rcrp->comp_rd_index = 0; 4332 rcrp->comp_wt_index = 0; 4333 rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p = 4334 (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc); 4335 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 4336 #if defined(__i386) 4337 (p_rcr_entry_t)(uint32_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 4338 #else 4339 (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 4340 #endif 4341 4342 rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p + 4343 (nxge_port_rcr_size - 1); 4344 rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp + 4345 (nxge_port_rcr_size - 1); 4346 4347 dmap = (p_nxge_dma_common_t)&rcrp->rcr_desc; 4348 bzero((caddr_t)dmap->kaddrp, dmap->alength); 4349 4350 cmn_err(CE_NOTE, "!rbr entries = %d\n", rbrp->rbr_max_size); 4351 4352 for (i = 0; i < rbrp->rbr_max_size; i++) { 4353 rx_msg_p = rbrp->rx_msg_ring[i]; 4354 ref_cnt = rx_msg_p->ref_cnt; 4355 if (ref_cnt != 1) { 4356 if (rx_msg_p->cur_usage_cnt != 4357 rx_msg_p->max_usage_cnt) { 4358 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4359 "buf[%d]: cur_usage_cnt = %d " 4360 "max_usage_cnt = %d\n", i, 4361 rx_msg_p->cur_usage_cnt, 4362 rx_msg_p->max_usage_cnt)); 4363 } else { 4364 /* Buffer can be re-posted */ 4365 rx_msg_p->free = B_TRUE; 4366 rx_msg_p->cur_usage_cnt = 0; 4367 rx_msg_p->max_usage_cnt = 0xbaddcafe; 4368 rx_msg_p->pkt_buf_size = 0; 4369 } 4370 } 4371 } 4372 4373 NXGE_DEBUG_MSG((nxgep, RX_CTL, "RxDMA channel re-start...")); 4374 4375 status = nxge_rxdma_start_channel(nxgep, channel, rbrp, rcrp, mboxp); 4376 if (status != NXGE_OK) { 4377 goto fail; 4378 } 4379 4380 MUTEX_EXIT(&rbrp->post_lock); 4381 MUTEX_EXIT(&rbrp->lock); 4382 MUTEX_EXIT(&rcrp->lock); 4383 4384 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4385 "Recovery Successful, RxDMAChannel#%d Restored", 4386 channel)); 4387 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_fatal_err_recover")); 4388 4389 return (NXGE_OK); 4390 fail: 4391 MUTEX_EXIT(&rbrp->post_lock); 4392 MUTEX_EXIT(&rbrp->lock); 4393 MUTEX_EXIT(&rcrp->lock); 4394 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Recovery failed")); 4395 4396 return (NXGE_ERROR | rs); 4397 } 4398 4399 nxge_status_t 4400 nxge_rx_port_fatal_err_recover(p_nxge_t nxgep) 4401 { 4402 nxge_status_t status = NXGE_OK; 4403 p_nxge_dma_common_t *dma_buf_p; 4404 uint16_t channel; 4405 int ndmas; 4406 int i; 4407 4408 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rx_port_fatal_err_recover")); 4409 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4410 "Recovering from RxPort error...")); 4411 /* Disable RxMAC */ 4412 4413 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Disable RxMAC...\n")); 4414 if (nxge_rx_mac_disable(nxgep) != NXGE_OK) 4415 goto fail; 4416 4417 NXGE_DELAY(1000); 4418 4419 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Stop all RxDMA channels...")); 4420 4421 ndmas = nxgep->rx_buf_pool_p->ndmas; 4422 dma_buf_p = nxgep->rx_buf_pool_p->dma_buf_pool_p; 4423 4424 for (i = 0; i < ndmas; i++) { 4425 channel = ((p_nxge_dma_common_t)dma_buf_p[i])->dma_channel; 4426 if (nxge_rxdma_fatal_err_recover(nxgep, channel) != NXGE_OK) { 4427 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4428 "Could not recover channel %d", 4429 channel)); 4430 } 4431 } 4432 4433 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Reset IPP...")); 4434 4435 /* Reset IPP */ 4436 if (nxge_ipp_reset(nxgep) != NXGE_OK) { 4437 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4438 "nxge_rx_port_fatal_err_recover: " 4439 "Failed to reset IPP")); 4440 goto fail; 4441 } 4442 4443 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Reset RxMAC...")); 4444 4445 /* Reset RxMAC */ 4446 if (nxge_rx_mac_reset(nxgep) != NXGE_OK) { 4447 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4448 "nxge_rx_port_fatal_err_recover: " 4449 "Failed to reset RxMAC")); 4450 goto fail; 4451 } 4452 4453 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Re-initialize IPP...")); 4454 4455 /* Re-Initialize IPP */ 4456 if (nxge_ipp_init(nxgep) != NXGE_OK) { 4457 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4458 "nxge_rx_port_fatal_err_recover: " 4459 "Failed to init IPP")); 4460 goto fail; 4461 } 4462 4463 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Re-initialize RxMAC...")); 4464 4465 /* Re-Initialize RxMAC */ 4466 if ((status = nxge_rx_mac_init(nxgep)) != NXGE_OK) { 4467 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4468 "nxge_rx_port_fatal_err_recover: " 4469 "Failed to reset RxMAC")); 4470 goto fail; 4471 } 4472 4473 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Re-enable RxMAC...")); 4474 4475 /* Re-enable RxMAC */ 4476 if ((status = nxge_rx_mac_enable(nxgep)) != NXGE_OK) { 4477 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4478 "nxge_rx_port_fatal_err_recover: " 4479 "Failed to enable RxMAC")); 4480 goto fail; 4481 } 4482 4483 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4484 "Recovery Successful, RxPort Restored")); 4485 4486 return (NXGE_OK); 4487 fail: 4488 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Recovery failed")); 4489 return (status); 4490 } 4491 4492 void 4493 nxge_rxdma_inject_err(p_nxge_t nxgep, uint32_t err_id, uint8_t chan) 4494 { 4495 rx_dma_ctl_stat_t cs; 4496 rx_ctl_dat_fifo_stat_t cdfs; 4497 4498 switch (err_id) { 4499 case NXGE_FM_EREPORT_RDMC_RCR_ACK_ERR: 4500 case NXGE_FM_EREPORT_RDMC_DC_FIFO_ERR: 4501 case NXGE_FM_EREPORT_RDMC_RCR_SHA_PAR: 4502 case NXGE_FM_EREPORT_RDMC_RBR_PRE_PAR: 4503 case NXGE_FM_EREPORT_RDMC_RBR_TMOUT: 4504 case NXGE_FM_EREPORT_RDMC_RSP_CNT_ERR: 4505 case NXGE_FM_EREPORT_RDMC_BYTE_EN_BUS: 4506 case NXGE_FM_EREPORT_RDMC_RSP_DAT_ERR: 4507 case NXGE_FM_EREPORT_RDMC_RCRINCON: 4508 case NXGE_FM_EREPORT_RDMC_RCRFULL: 4509 case NXGE_FM_EREPORT_RDMC_RBRFULL: 4510 case NXGE_FM_EREPORT_RDMC_RBRLOGPAGE: 4511 case NXGE_FM_EREPORT_RDMC_CFIGLOGPAGE: 4512 case NXGE_FM_EREPORT_RDMC_CONFIG_ERR: 4513 RXDMA_REG_READ64(nxgep->npi_handle, RX_DMA_CTL_STAT_DBG_REG, 4514 chan, &cs.value); 4515 if (err_id == NXGE_FM_EREPORT_RDMC_RCR_ACK_ERR) 4516 cs.bits.hdw.rcr_ack_err = 1; 4517 else if (err_id == NXGE_FM_EREPORT_RDMC_DC_FIFO_ERR) 4518 cs.bits.hdw.dc_fifo_err = 1; 4519 else if (err_id == NXGE_FM_EREPORT_RDMC_RCR_SHA_PAR) 4520 cs.bits.hdw.rcr_sha_par = 1; 4521 else if (err_id == NXGE_FM_EREPORT_RDMC_RBR_PRE_PAR) 4522 cs.bits.hdw.rbr_pre_par = 1; 4523 else if (err_id == NXGE_FM_EREPORT_RDMC_RBR_TMOUT) 4524 cs.bits.hdw.rbr_tmout = 1; 4525 else if (err_id == NXGE_FM_EREPORT_RDMC_RSP_CNT_ERR) 4526 cs.bits.hdw.rsp_cnt_err = 1; 4527 else if (err_id == NXGE_FM_EREPORT_RDMC_BYTE_EN_BUS) 4528 cs.bits.hdw.byte_en_bus = 1; 4529 else if (err_id == NXGE_FM_EREPORT_RDMC_RSP_DAT_ERR) 4530 cs.bits.hdw.rsp_dat_err = 1; 4531 else if (err_id == NXGE_FM_EREPORT_RDMC_CONFIG_ERR) 4532 cs.bits.hdw.config_err = 1; 4533 else if (err_id == NXGE_FM_EREPORT_RDMC_RCRINCON) 4534 cs.bits.hdw.rcrincon = 1; 4535 else if (err_id == NXGE_FM_EREPORT_RDMC_RCRFULL) 4536 cs.bits.hdw.rcrfull = 1; 4537 else if (err_id == NXGE_FM_EREPORT_RDMC_RBRFULL) 4538 cs.bits.hdw.rbrfull = 1; 4539 else if (err_id == NXGE_FM_EREPORT_RDMC_RBRLOGPAGE) 4540 cs.bits.hdw.rbrlogpage = 1; 4541 else if (err_id == NXGE_FM_EREPORT_RDMC_CFIGLOGPAGE) 4542 cs.bits.hdw.cfiglogpage = 1; 4543 #if defined(__i386) 4544 cmn_err(CE_NOTE, "!Write 0x%llx to RX_DMA_CTL_STAT_DBG_REG\n", 4545 cs.value); 4546 #else 4547 cmn_err(CE_NOTE, "!Write 0x%lx to RX_DMA_CTL_STAT_DBG_REG\n", 4548 cs.value); 4549 #endif 4550 RXDMA_REG_WRITE64(nxgep->npi_handle, RX_DMA_CTL_STAT_DBG_REG, 4551 chan, cs.value); 4552 break; 4553 case NXGE_FM_EREPORT_RDMC_ID_MISMATCH: 4554 case NXGE_FM_EREPORT_RDMC_ZCP_EOP_ERR: 4555 case NXGE_FM_EREPORT_RDMC_IPP_EOP_ERR: 4556 cdfs.value = 0; 4557 if (err_id == NXGE_FM_EREPORT_RDMC_ID_MISMATCH) 4558 cdfs.bits.ldw.id_mismatch = (1 << nxgep->mac.portnum); 4559 else if (err_id == NXGE_FM_EREPORT_RDMC_ZCP_EOP_ERR) 4560 cdfs.bits.ldw.zcp_eop_err = (1 << nxgep->mac.portnum); 4561 else if (err_id == NXGE_FM_EREPORT_RDMC_IPP_EOP_ERR) 4562 cdfs.bits.ldw.ipp_eop_err = (1 << nxgep->mac.portnum); 4563 #if defined(__i386) 4564 cmn_err(CE_NOTE, 4565 "!Write 0x%llx to RX_CTL_DAT_FIFO_STAT_DBG_REG\n", 4566 cdfs.value); 4567 #else 4568 cmn_err(CE_NOTE, 4569 "!Write 0x%lx to RX_CTL_DAT_FIFO_STAT_DBG_REG\n", 4570 cdfs.value); 4571 #endif 4572 RXDMA_REG_WRITE64(nxgep->npi_handle, 4573 RX_CTL_DAT_FIFO_STAT_DBG_REG, chan, cdfs.value); 4574 break; 4575 case NXGE_FM_EREPORT_RDMC_DCF_ERR: 4576 break; 4577 case NXGE_FM_EREPORT_RDMC_RCR_ERR: 4578 break; 4579 } 4580 } 4581