1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <sys/nxge/nxge_impl.h> 27 #include <sys/nxge/nxge_rxdma.h> 28 #include <sys/nxge/nxge_hio.h> 29 30 #if !defined(_BIG_ENDIAN) 31 #include <npi_rx_rd32.h> 32 #endif 33 #include <npi_rx_rd64.h> 34 #include <npi_rx_wr64.h> 35 36 #define NXGE_ACTUAL_RDCGRP(nxgep, rdcgrp) \ 37 (rdcgrp + nxgep->pt_config.hw_config.def_mac_rxdma_grpid) 38 #define NXGE_ACTUAL_RDC(nxgep, rdc) \ 39 (rdc + nxgep->pt_config.hw_config.start_rdc) 40 41 /* 42 * Globals: tunable parameters (/etc/system or adb) 43 * 44 */ 45 extern uint32_t nxge_rbr_size; 46 extern uint32_t nxge_rcr_size; 47 extern uint32_t nxge_rbr_spare_size; 48 49 extern uint32_t nxge_mblks_pending; 50 51 /* 52 * Tunable to reduce the amount of time spent in the 53 * ISR doing Rx Processing. 54 */ 55 extern uint32_t nxge_max_rx_pkts; 56 57 /* 58 * Tunables to manage the receive buffer blocks. 59 * 60 * nxge_rx_threshold_hi: copy all buffers. 61 * nxge_rx_bcopy_size_type: receive buffer block size type. 62 * nxge_rx_threshold_lo: copy only up to tunable block size type. 63 */ 64 extern nxge_rxbuf_threshold_t nxge_rx_threshold_hi; 65 extern nxge_rxbuf_type_t nxge_rx_buf_size_type; 66 extern nxge_rxbuf_threshold_t nxge_rx_threshold_lo; 67 68 extern uint32_t nxge_cksum_offload; 69 70 static nxge_status_t nxge_map_rxdma(p_nxge_t, int); 71 static void nxge_unmap_rxdma(p_nxge_t, int); 72 73 static nxge_status_t nxge_rxdma_hw_start_common(p_nxge_t); 74 75 static nxge_status_t nxge_rxdma_hw_start(p_nxge_t, int); 76 static void nxge_rxdma_hw_stop(p_nxge_t, int); 77 78 static nxge_status_t nxge_map_rxdma_channel(p_nxge_t, uint16_t, 79 p_nxge_dma_common_t *, p_rx_rbr_ring_t *, 80 uint32_t, 81 p_nxge_dma_common_t *, p_rx_rcr_ring_t *, 82 p_rx_mbox_t *); 83 static void nxge_unmap_rxdma_channel(p_nxge_t, uint16_t, 84 p_rx_rbr_ring_t, p_rx_rcr_ring_t, p_rx_mbox_t); 85 86 static nxge_status_t nxge_map_rxdma_channel_cfg_ring(p_nxge_t, 87 uint16_t, 88 p_nxge_dma_common_t *, p_rx_rbr_ring_t *, 89 p_rx_rcr_ring_t *, p_rx_mbox_t *); 90 static void nxge_unmap_rxdma_channel_cfg_ring(p_nxge_t, 91 p_rx_rcr_ring_t, p_rx_mbox_t); 92 93 static nxge_status_t nxge_map_rxdma_channel_buf_ring(p_nxge_t, 94 uint16_t, 95 p_nxge_dma_common_t *, 96 p_rx_rbr_ring_t *, uint32_t); 97 static void nxge_unmap_rxdma_channel_buf_ring(p_nxge_t, 98 p_rx_rbr_ring_t); 99 100 static nxge_status_t nxge_rxdma_start_channel(p_nxge_t, uint16_t, 101 p_rx_rbr_ring_t, p_rx_rcr_ring_t, p_rx_mbox_t); 102 static nxge_status_t nxge_rxdma_stop_channel(p_nxge_t, uint16_t); 103 104 static mblk_t * 105 nxge_rx_pkts(p_nxge_t, p_rx_rcr_ring_t, rx_dma_ctl_stat_t, int); 106 107 static void nxge_receive_packet(p_nxge_t, 108 p_rx_rcr_ring_t, 109 p_rcr_entry_t, 110 boolean_t *, 111 mblk_t **, mblk_t **); 112 113 nxge_status_t nxge_disable_rxdma_channel(p_nxge_t, uint16_t); 114 115 static p_rx_msg_t nxge_allocb(size_t, uint32_t, p_nxge_dma_common_t); 116 static void nxge_freeb(p_rx_msg_t); 117 static nxge_status_t nxge_rx_err_evnts(p_nxge_t, int, rx_dma_ctl_stat_t); 118 119 static nxge_status_t nxge_rxdma_handle_port_errors(p_nxge_t, 120 uint32_t, uint32_t); 121 122 static nxge_status_t nxge_rxbuf_index_info_init(p_nxge_t, 123 p_rx_rbr_ring_t); 124 125 126 static nxge_status_t 127 nxge_rxdma_fatal_err_recover(p_nxge_t, uint16_t); 128 129 nxge_status_t 130 nxge_rx_port_fatal_err_recover(p_nxge_t); 131 132 static void nxge_rxdma_databuf_free(p_rx_rbr_ring_t); 133 134 nxge_status_t 135 nxge_init_rxdma_channels(p_nxge_t nxgep) 136 { 137 nxge_grp_set_t *set = &nxgep->rx_set; 138 int i, count, channel; 139 nxge_grp_t *group; 140 dc_map_t map; 141 int dev_gindex; 142 143 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_init_rxdma_channels")); 144 145 if (!isLDOMguest(nxgep)) { 146 if (nxge_rxdma_hw_start_common(nxgep) != NXGE_OK) { 147 cmn_err(CE_NOTE, "hw_start_common"); 148 return (NXGE_ERROR); 149 } 150 } 151 152 /* 153 * NXGE_LOGICAL_GROUP_MAX > NXGE_MAX_RDC_GROUPS (8) 154 * We only have 8 hardware RDC tables, but we may have 155 * up to 16 logical (software-defined) groups of RDCS, 156 * if we make use of layer 3 & 4 hardware classification. 157 */ 158 for (i = 0, count = 0; i < NXGE_LOGICAL_GROUP_MAX; i++) { 159 if ((1 << i) & set->lg.map) { 160 group = set->group[i]; 161 dev_gindex = 162 nxgep->pt_config.hw_config.def_mac_rxdma_grpid + i; 163 map = nxgep->pt_config.rdc_grps[dev_gindex].map; 164 for (channel = 0; channel < NXGE_MAX_RDCS; channel++) { 165 if ((1 << channel) & map) { 166 if ((nxge_grp_dc_add(nxgep, 167 group, VP_BOUND_RX, channel))) 168 goto init_rxdma_channels_exit; 169 } 170 } 171 } 172 if (++count == set->lg.count) 173 break; 174 } 175 176 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_init_rxdma_channels")); 177 return (NXGE_OK); 178 179 init_rxdma_channels_exit: 180 for (i = 0, count = 0; i < NXGE_LOGICAL_GROUP_MAX; i++) { 181 if ((1 << i) & set->lg.map) { 182 group = set->group[i]; 183 dev_gindex = 184 nxgep->pt_config.hw_config.def_mac_rxdma_grpid + i; 185 map = nxgep->pt_config.rdc_grps[dev_gindex].map; 186 for (channel = 0; channel < NXGE_MAX_RDCS; channel++) { 187 if ((1 << channel) & map) { 188 nxge_grp_dc_remove(nxgep, 189 VP_BOUND_RX, channel); 190 } 191 } 192 } 193 if (++count == set->lg.count) 194 break; 195 } 196 197 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_init_rxdma_channels")); 198 return (NXGE_ERROR); 199 } 200 201 nxge_status_t 202 nxge_init_rxdma_channel(p_nxge_t nxge, int channel) 203 { 204 nxge_status_t status; 205 206 NXGE_DEBUG_MSG((nxge, MEM2_CTL, "==> nxge_init_rxdma_channel")); 207 208 status = nxge_map_rxdma(nxge, channel); 209 if (status != NXGE_OK) { 210 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, 211 "<== nxge_init_rxdma: status 0x%x", status)); 212 return (status); 213 } 214 215 #if defined(sun4v) 216 if (isLDOMguest(nxge)) { 217 /* set rcr_ring */ 218 p_rx_rcr_ring_t ring = nxge->rx_rcr_rings->rcr_rings[channel]; 219 220 status = nxge_hio_rxdma_bind_intr(nxge, ring, channel); 221 if (status != NXGE_OK) { 222 nxge_unmap_rxdma(nxge, channel); 223 return (status); 224 } 225 } 226 #endif 227 228 status = nxge_rxdma_hw_start(nxge, channel); 229 if (status != NXGE_OK) { 230 nxge_unmap_rxdma(nxge, channel); 231 } 232 233 if (!nxge->statsp->rdc_ksp[channel]) 234 nxge_setup_rdc_kstats(nxge, channel); 235 236 NXGE_DEBUG_MSG((nxge, MEM2_CTL, 237 "<== nxge_init_rxdma_channel: status 0x%x", status)); 238 239 return (status); 240 } 241 242 void 243 nxge_uninit_rxdma_channels(p_nxge_t nxgep) 244 { 245 nxge_grp_set_t *set = &nxgep->rx_set; 246 int rdc; 247 248 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_uninit_rxdma_channels")); 249 250 if (set->owned.map == 0) { 251 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 252 "nxge_uninit_rxdma_channels: no channels")); 253 return; 254 } 255 256 for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 257 if ((1 << rdc) & set->owned.map) { 258 nxge_grp_dc_remove(nxgep, VP_BOUND_RX, rdc); 259 } 260 } 261 262 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_uninit_rxdma_channels")); 263 } 264 265 void 266 nxge_uninit_rxdma_channel(p_nxge_t nxgep, int channel) 267 { 268 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_uninit_rxdma_channel")); 269 270 if (nxgep->statsp->rdc_ksp[channel]) { 271 kstat_delete(nxgep->statsp->rdc_ksp[channel]); 272 nxgep->statsp->rdc_ksp[channel] = 0; 273 } 274 275 nxge_rxdma_hw_stop(nxgep, channel); 276 nxge_unmap_rxdma(nxgep, channel); 277 278 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_uinit_rxdma_channel")); 279 } 280 281 nxge_status_t 282 nxge_reset_rxdma_channel(p_nxge_t nxgep, uint16_t channel) 283 { 284 npi_handle_t handle; 285 npi_status_t rs = NPI_SUCCESS; 286 nxge_status_t status = NXGE_OK; 287 288 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_reset_rxdma_channel")); 289 290 handle = NXGE_DEV_NPI_HANDLE(nxgep); 291 rs = npi_rxdma_cfg_rdc_reset(handle, channel); 292 293 if (rs != NPI_SUCCESS) { 294 status = NXGE_ERROR | rs; 295 } 296 297 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_reset_rxdma_channel")); 298 299 return (status); 300 } 301 302 void 303 nxge_rxdma_regs_dump_channels(p_nxge_t nxgep) 304 { 305 nxge_grp_set_t *set = &nxgep->rx_set; 306 int rdc; 307 308 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_regs_dump_channels")); 309 310 if (!isLDOMguest(nxgep)) { 311 npi_handle_t handle = NXGE_DEV_NPI_HANDLE(nxgep); 312 (void) npi_rxdma_dump_fzc_regs(handle); 313 } 314 315 if (nxgep->rx_rbr_rings == 0 || nxgep->rx_rbr_rings->rbr_rings == 0) { 316 NXGE_DEBUG_MSG((nxgep, TX_CTL, 317 "nxge_rxdma_regs_dump_channels: " 318 "NULL ring pointer(s)")); 319 return; 320 } 321 322 if (set->owned.map == 0) { 323 NXGE_DEBUG_MSG((nxgep, RX_CTL, 324 "nxge_rxdma_regs_dump_channels: no channels")); 325 return; 326 } 327 328 for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 329 if ((1 << rdc) & set->owned.map) { 330 rx_rbr_ring_t *ring = 331 nxgep->rx_rbr_rings->rbr_rings[rdc]; 332 if (ring) { 333 (void) nxge_dump_rxdma_channel(nxgep, rdc); 334 } 335 } 336 } 337 338 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_regs_dump")); 339 } 340 341 nxge_status_t 342 nxge_dump_rxdma_channel(p_nxge_t nxgep, uint8_t channel) 343 { 344 npi_handle_t handle; 345 npi_status_t rs = NPI_SUCCESS; 346 nxge_status_t status = NXGE_OK; 347 348 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_dump_rxdma_channel")); 349 350 handle = NXGE_DEV_NPI_HANDLE(nxgep); 351 rs = npi_rxdma_dump_rdc_regs(handle, channel); 352 353 if (rs != NPI_SUCCESS) { 354 status = NXGE_ERROR | rs; 355 } 356 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_dump_rxdma_channel")); 357 return (status); 358 } 359 360 nxge_status_t 361 nxge_init_rxdma_channel_event_mask(p_nxge_t nxgep, uint16_t channel, 362 p_rx_dma_ent_msk_t mask_p) 363 { 364 npi_handle_t handle; 365 npi_status_t rs = NPI_SUCCESS; 366 nxge_status_t status = NXGE_OK; 367 368 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 369 "<== nxge_init_rxdma_channel_event_mask")); 370 371 handle = NXGE_DEV_NPI_HANDLE(nxgep); 372 rs = npi_rxdma_event_mask(handle, OP_SET, channel, mask_p); 373 if (rs != NPI_SUCCESS) { 374 status = NXGE_ERROR | rs; 375 } 376 377 return (status); 378 } 379 380 nxge_status_t 381 nxge_init_rxdma_channel_cntl_stat(p_nxge_t nxgep, uint16_t channel, 382 p_rx_dma_ctl_stat_t cs_p) 383 { 384 npi_handle_t handle; 385 npi_status_t rs = NPI_SUCCESS; 386 nxge_status_t status = NXGE_OK; 387 388 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 389 "<== nxge_init_rxdma_channel_cntl_stat")); 390 391 handle = NXGE_DEV_NPI_HANDLE(nxgep); 392 rs = npi_rxdma_control_status(handle, OP_SET, channel, cs_p); 393 394 if (rs != NPI_SUCCESS) { 395 status = NXGE_ERROR | rs; 396 } 397 398 return (status); 399 } 400 401 /* 402 * nxge_rxdma_cfg_rdcgrp_default_rdc 403 * 404 * Set the default RDC for an RDC Group (Table) 405 * 406 * Arguments: 407 * nxgep 408 * rdcgrp The group to modify 409 * rdc The new default RDC. 410 * 411 * Notes: 412 * 413 * NPI/NXGE function calls: 414 * npi_rxdma_cfg_rdc_table_default_rdc() 415 * 416 * Registers accessed: 417 * RDC_TBL_REG: FZC_ZCP + 0x10000 418 * 419 * Context: 420 * Service domain 421 */ 422 nxge_status_t 423 nxge_rxdma_cfg_rdcgrp_default_rdc( 424 p_nxge_t nxgep, 425 uint8_t rdcgrp, 426 uint8_t rdc) 427 { 428 npi_handle_t handle; 429 npi_status_t rs = NPI_SUCCESS; 430 p_nxge_dma_pt_cfg_t p_dma_cfgp; 431 p_nxge_rdc_grp_t rdc_grp_p; 432 uint8_t actual_rdcgrp, actual_rdc; 433 434 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 435 " ==> nxge_rxdma_cfg_rdcgrp_default_rdc")); 436 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 437 438 handle = NXGE_DEV_NPI_HANDLE(nxgep); 439 440 /* 441 * This has to be rewritten. Do we even allow this anymore? 442 */ 443 rdc_grp_p = &p_dma_cfgp->rdc_grps[rdcgrp]; 444 RDC_MAP_IN(rdc_grp_p->map, rdc); 445 rdc_grp_p->def_rdc = rdc; 446 447 actual_rdcgrp = NXGE_ACTUAL_RDCGRP(nxgep, rdcgrp); 448 actual_rdc = NXGE_ACTUAL_RDC(nxgep, rdc); 449 450 rs = npi_rxdma_cfg_rdc_table_default_rdc( 451 handle, actual_rdcgrp, actual_rdc); 452 453 if (rs != NPI_SUCCESS) { 454 return (NXGE_ERROR | rs); 455 } 456 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 457 " <== nxge_rxdma_cfg_rdcgrp_default_rdc")); 458 return (NXGE_OK); 459 } 460 461 nxge_status_t 462 nxge_rxdma_cfg_port_default_rdc(p_nxge_t nxgep, uint8_t port, uint8_t rdc) 463 { 464 npi_handle_t handle; 465 466 uint8_t actual_rdc; 467 npi_status_t rs = NPI_SUCCESS; 468 469 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 470 " ==> nxge_rxdma_cfg_port_default_rdc")); 471 472 handle = NXGE_DEV_NPI_HANDLE(nxgep); 473 actual_rdc = rdc; /* XXX Hack! */ 474 rs = npi_rxdma_cfg_default_port_rdc(handle, port, actual_rdc); 475 476 477 if (rs != NPI_SUCCESS) { 478 return (NXGE_ERROR | rs); 479 } 480 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 481 " <== nxge_rxdma_cfg_port_default_rdc")); 482 483 return (NXGE_OK); 484 } 485 486 nxge_status_t 487 nxge_rxdma_cfg_rcr_threshold(p_nxge_t nxgep, uint8_t channel, 488 uint16_t pkts) 489 { 490 npi_status_t rs = NPI_SUCCESS; 491 npi_handle_t handle; 492 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 493 " ==> nxge_rxdma_cfg_rcr_threshold")); 494 handle = NXGE_DEV_NPI_HANDLE(nxgep); 495 496 rs = npi_rxdma_cfg_rdc_rcr_threshold(handle, channel, pkts); 497 498 if (rs != NPI_SUCCESS) { 499 return (NXGE_ERROR | rs); 500 } 501 NXGE_DEBUG_MSG((nxgep, RX2_CTL, " <== nxge_rxdma_cfg_rcr_threshold")); 502 return (NXGE_OK); 503 } 504 505 nxge_status_t 506 nxge_rxdma_cfg_rcr_timeout(p_nxge_t nxgep, uint8_t channel, 507 uint16_t tout, uint8_t enable) 508 { 509 npi_status_t rs = NPI_SUCCESS; 510 npi_handle_t handle; 511 NXGE_DEBUG_MSG((nxgep, RX2_CTL, " ==> nxge_rxdma_cfg_rcr_timeout")); 512 handle = NXGE_DEV_NPI_HANDLE(nxgep); 513 if (enable == 0) { 514 rs = npi_rxdma_cfg_rdc_rcr_timeout_disable(handle, channel); 515 } else { 516 rs = npi_rxdma_cfg_rdc_rcr_timeout(handle, channel, 517 tout); 518 } 519 520 if (rs != NPI_SUCCESS) { 521 return (NXGE_ERROR | rs); 522 } 523 NXGE_DEBUG_MSG((nxgep, RX2_CTL, " <== nxge_rxdma_cfg_rcr_timeout")); 524 return (NXGE_OK); 525 } 526 527 nxge_status_t 528 nxge_enable_rxdma_channel(p_nxge_t nxgep, uint16_t channel, 529 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p) 530 { 531 npi_handle_t handle; 532 rdc_desc_cfg_t rdc_desc; 533 p_rcrcfig_b_t cfgb_p; 534 npi_status_t rs = NPI_SUCCESS; 535 536 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel")); 537 handle = NXGE_DEV_NPI_HANDLE(nxgep); 538 /* 539 * Use configuration data composed at init time. 540 * Write to hardware the receive ring configurations. 541 */ 542 rdc_desc.mbox_enable = 1; 543 rdc_desc.mbox_addr = mbox_p->mbox_addr; 544 NXGE_DEBUG_MSG((nxgep, RX_CTL, 545 "==> nxge_enable_rxdma_channel: mboxp $%p($%p)", 546 mbox_p->mbox_addr, rdc_desc.mbox_addr)); 547 548 rdc_desc.rbr_len = rbr_p->rbb_max; 549 rdc_desc.rbr_addr = rbr_p->rbr_addr; 550 551 switch (nxgep->rx_bksize_code) { 552 case RBR_BKSIZE_4K: 553 rdc_desc.page_size = SIZE_4KB; 554 break; 555 case RBR_BKSIZE_8K: 556 rdc_desc.page_size = SIZE_8KB; 557 break; 558 case RBR_BKSIZE_16K: 559 rdc_desc.page_size = SIZE_16KB; 560 break; 561 case RBR_BKSIZE_32K: 562 rdc_desc.page_size = SIZE_32KB; 563 break; 564 } 565 566 rdc_desc.size0 = rbr_p->npi_pkt_buf_size0; 567 rdc_desc.valid0 = 1; 568 569 rdc_desc.size1 = rbr_p->npi_pkt_buf_size1; 570 rdc_desc.valid1 = 1; 571 572 rdc_desc.size2 = rbr_p->npi_pkt_buf_size2; 573 rdc_desc.valid2 = 1; 574 575 rdc_desc.full_hdr = rcr_p->full_hdr_flag; 576 rdc_desc.offset = rcr_p->sw_priv_hdr_len; 577 578 rdc_desc.rcr_len = rcr_p->comp_size; 579 rdc_desc.rcr_addr = rcr_p->rcr_addr; 580 581 cfgb_p = &(rcr_p->rcr_cfgb); 582 rdc_desc.rcr_threshold = cfgb_p->bits.ldw.pthres; 583 /* For now, disable this timeout in a guest domain. */ 584 if (isLDOMguest(nxgep)) { 585 rdc_desc.rcr_timeout = 0; 586 rdc_desc.rcr_timeout_enable = 0; 587 } else { 588 rdc_desc.rcr_timeout = cfgb_p->bits.ldw.timeout; 589 rdc_desc.rcr_timeout_enable = cfgb_p->bits.ldw.entout; 590 } 591 592 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel: " 593 "rbr_len qlen %d pagesize code %d rcr_len %d", 594 rdc_desc.rbr_len, rdc_desc.page_size, rdc_desc.rcr_len)); 595 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel: " 596 "size 0 %d size 1 %d size 2 %d", 597 rbr_p->npi_pkt_buf_size0, rbr_p->npi_pkt_buf_size1, 598 rbr_p->npi_pkt_buf_size2)); 599 600 rs = npi_rxdma_cfg_rdc_ring(handle, rbr_p->rdc, &rdc_desc); 601 if (rs != NPI_SUCCESS) { 602 return (NXGE_ERROR | rs); 603 } 604 605 /* 606 * Enable the timeout and threshold. 607 */ 608 rs = npi_rxdma_cfg_rdc_rcr_threshold(handle, channel, 609 rdc_desc.rcr_threshold); 610 if (rs != NPI_SUCCESS) { 611 return (NXGE_ERROR | rs); 612 } 613 614 rs = npi_rxdma_cfg_rdc_rcr_timeout(handle, channel, 615 rdc_desc.rcr_timeout); 616 if (rs != NPI_SUCCESS) { 617 return (NXGE_ERROR | rs); 618 } 619 620 if (!isLDOMguest(nxgep)) { 621 /* Enable the DMA */ 622 rs = npi_rxdma_cfg_rdc_enable(handle, channel); 623 if (rs != NPI_SUCCESS) { 624 return (NXGE_ERROR | rs); 625 } 626 } 627 628 /* Kick the DMA engine. */ 629 npi_rxdma_rdc_rbr_kick(handle, channel, rbr_p->rbb_max); 630 631 if (!isLDOMguest(nxgep)) { 632 /* Clear the rbr empty bit */ 633 (void) npi_rxdma_channel_rbr_empty_clear(handle, channel); 634 } 635 636 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_enable_rxdma_channel")); 637 638 return (NXGE_OK); 639 } 640 641 nxge_status_t 642 nxge_disable_rxdma_channel(p_nxge_t nxgep, uint16_t channel) 643 { 644 npi_handle_t handle; 645 npi_status_t rs = NPI_SUCCESS; 646 647 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_disable_rxdma_channel")); 648 handle = NXGE_DEV_NPI_HANDLE(nxgep); 649 650 /* disable the DMA */ 651 rs = npi_rxdma_cfg_rdc_disable(handle, channel); 652 if (rs != NPI_SUCCESS) { 653 NXGE_DEBUG_MSG((nxgep, RX_CTL, 654 "<== nxge_disable_rxdma_channel:failed (0x%x)", 655 rs)); 656 return (NXGE_ERROR | rs); 657 } 658 659 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_disable_rxdma_channel")); 660 return (NXGE_OK); 661 } 662 663 nxge_status_t 664 nxge_rxdma_channel_rcrflush(p_nxge_t nxgep, uint8_t channel) 665 { 666 npi_handle_t handle; 667 nxge_status_t status = NXGE_OK; 668 669 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 670 "<== nxge_init_rxdma_channel_rcrflush")); 671 672 handle = NXGE_DEV_NPI_HANDLE(nxgep); 673 npi_rxdma_rdc_rcr_flush(handle, channel); 674 675 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 676 "<== nxge_init_rxdma_channel_rcrflsh")); 677 return (status); 678 679 } 680 681 #define MID_INDEX(l, r) ((r + l + 1) >> 1) 682 683 #define TO_LEFT -1 684 #define TO_RIGHT 1 685 #define BOTH_RIGHT (TO_RIGHT + TO_RIGHT) 686 #define BOTH_LEFT (TO_LEFT + TO_LEFT) 687 #define IN_MIDDLE (TO_RIGHT + TO_LEFT) 688 #define NO_HINT 0xffffffff 689 690 /*ARGSUSED*/ 691 nxge_status_t 692 nxge_rxbuf_pp_to_vp(p_nxge_t nxgep, p_rx_rbr_ring_t rbr_p, 693 uint8_t pktbufsz_type, uint64_t *pkt_buf_addr_pp, 694 uint64_t **pkt_buf_addr_p, uint32_t *bufoffset, uint32_t *msg_index) 695 { 696 int bufsize; 697 uint64_t pktbuf_pp; 698 uint64_t dvma_addr; 699 rxring_info_t *ring_info; 700 int base_side, end_side; 701 int r_index, l_index, anchor_index; 702 int found, search_done; 703 uint32_t offset, chunk_size, block_size, page_size_mask; 704 uint32_t chunk_index, block_index, total_index; 705 int max_iterations, iteration; 706 rxbuf_index_info_t *bufinfo; 707 708 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> nxge_rxbuf_pp_to_vp")); 709 710 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 711 "==> nxge_rxbuf_pp_to_vp: buf_pp $%p btype %d", 712 pkt_buf_addr_pp, 713 pktbufsz_type)); 714 #if defined(__i386) 715 pktbuf_pp = (uint64_t)(uint32_t)pkt_buf_addr_pp; 716 #else 717 pktbuf_pp = (uint64_t)pkt_buf_addr_pp; 718 #endif 719 720 switch (pktbufsz_type) { 721 case 0: 722 bufsize = rbr_p->pkt_buf_size0; 723 break; 724 case 1: 725 bufsize = rbr_p->pkt_buf_size1; 726 break; 727 case 2: 728 bufsize = rbr_p->pkt_buf_size2; 729 break; 730 case RCR_SINGLE_BLOCK: 731 bufsize = 0; 732 anchor_index = 0; 733 break; 734 default: 735 return (NXGE_ERROR); 736 } 737 738 if (rbr_p->num_blocks == 1) { 739 anchor_index = 0; 740 ring_info = rbr_p->ring_info; 741 bufinfo = (rxbuf_index_info_t *)ring_info->buffer; 742 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 743 "==> nxge_rxbuf_pp_to_vp: (found, 1 block) " 744 "buf_pp $%p btype %d anchor_index %d " 745 "bufinfo $%p", 746 pkt_buf_addr_pp, 747 pktbufsz_type, 748 anchor_index, 749 bufinfo)); 750 751 goto found_index; 752 } 753 754 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 755 "==> nxge_rxbuf_pp_to_vp: " 756 "buf_pp $%p btype %d anchor_index %d", 757 pkt_buf_addr_pp, 758 pktbufsz_type, 759 anchor_index)); 760 761 ring_info = rbr_p->ring_info; 762 found = B_FALSE; 763 bufinfo = (rxbuf_index_info_t *)ring_info->buffer; 764 iteration = 0; 765 max_iterations = ring_info->max_iterations; 766 /* 767 * First check if this block has been seen 768 * recently. This is indicated by a hint which 769 * is initialized when the first buffer of the block 770 * is seen. The hint is reset when the last buffer of 771 * the block has been processed. 772 * As three block sizes are supported, three hints 773 * are kept. The idea behind the hints is that once 774 * the hardware uses a block for a buffer of that 775 * size, it will use it exclusively for that size 776 * and will use it until it is exhausted. It is assumed 777 * that there would a single block being used for the same 778 * buffer sizes at any given time. 779 */ 780 if (ring_info->hint[pktbufsz_type] != NO_HINT) { 781 anchor_index = ring_info->hint[pktbufsz_type]; 782 dvma_addr = bufinfo[anchor_index].dvma_addr; 783 chunk_size = bufinfo[anchor_index].buf_size; 784 if ((pktbuf_pp >= dvma_addr) && 785 (pktbuf_pp < (dvma_addr + chunk_size))) { 786 found = B_TRUE; 787 /* 788 * check if this is the last buffer in the block 789 * If so, then reset the hint for the size; 790 */ 791 792 if ((pktbuf_pp + bufsize) >= (dvma_addr + chunk_size)) 793 ring_info->hint[pktbufsz_type] = NO_HINT; 794 } 795 } 796 797 if (found == B_FALSE) { 798 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 799 "==> nxge_rxbuf_pp_to_vp: (!found)" 800 "buf_pp $%p btype %d anchor_index %d", 801 pkt_buf_addr_pp, 802 pktbufsz_type, 803 anchor_index)); 804 805 /* 806 * This is the first buffer of the block of this 807 * size. Need to search the whole information 808 * array. 809 * the search algorithm uses a binary tree search 810 * algorithm. It assumes that the information is 811 * already sorted with increasing order 812 * info[0] < info[1] < info[2] .... < info[n-1] 813 * where n is the size of the information array 814 */ 815 r_index = rbr_p->num_blocks - 1; 816 l_index = 0; 817 search_done = B_FALSE; 818 anchor_index = MID_INDEX(r_index, l_index); 819 while (search_done == B_FALSE) { 820 if ((r_index == l_index) || 821 (iteration >= max_iterations)) 822 search_done = B_TRUE; 823 end_side = TO_RIGHT; /* to the right */ 824 base_side = TO_LEFT; /* to the left */ 825 /* read the DVMA address information and sort it */ 826 dvma_addr = bufinfo[anchor_index].dvma_addr; 827 chunk_size = bufinfo[anchor_index].buf_size; 828 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 829 "==> nxge_rxbuf_pp_to_vp: (searching)" 830 "buf_pp $%p btype %d " 831 "anchor_index %d chunk_size %d dvmaaddr $%p", 832 pkt_buf_addr_pp, 833 pktbufsz_type, 834 anchor_index, 835 chunk_size, 836 dvma_addr)); 837 838 if (pktbuf_pp >= dvma_addr) 839 base_side = TO_RIGHT; /* to the right */ 840 if (pktbuf_pp < (dvma_addr + chunk_size)) 841 end_side = TO_LEFT; /* to the left */ 842 843 switch (base_side + end_side) { 844 case IN_MIDDLE: 845 /* found */ 846 found = B_TRUE; 847 search_done = B_TRUE; 848 if ((pktbuf_pp + bufsize) < 849 (dvma_addr + chunk_size)) 850 ring_info->hint[pktbufsz_type] = 851 bufinfo[anchor_index].buf_index; 852 break; 853 case BOTH_RIGHT: 854 /* not found: go to the right */ 855 l_index = anchor_index + 1; 856 anchor_index = MID_INDEX(r_index, l_index); 857 break; 858 859 case BOTH_LEFT: 860 /* not found: go to the left */ 861 r_index = anchor_index - 1; 862 anchor_index = MID_INDEX(r_index, l_index); 863 break; 864 default: /* should not come here */ 865 return (NXGE_ERROR); 866 } 867 iteration++; 868 } 869 870 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 871 "==> nxge_rxbuf_pp_to_vp: (search done)" 872 "buf_pp $%p btype %d anchor_index %d", 873 pkt_buf_addr_pp, 874 pktbufsz_type, 875 anchor_index)); 876 } 877 878 if (found == B_FALSE) { 879 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 880 "==> nxge_rxbuf_pp_to_vp: (search failed)" 881 "buf_pp $%p btype %d anchor_index %d", 882 pkt_buf_addr_pp, 883 pktbufsz_type, 884 anchor_index)); 885 return (NXGE_ERROR); 886 } 887 888 found_index: 889 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 890 "==> nxge_rxbuf_pp_to_vp: (FOUND1)" 891 "buf_pp $%p btype %d bufsize %d anchor_index %d", 892 pkt_buf_addr_pp, 893 pktbufsz_type, 894 bufsize, 895 anchor_index)); 896 897 /* index of the first block in this chunk */ 898 chunk_index = bufinfo[anchor_index].start_index; 899 dvma_addr = bufinfo[anchor_index].dvma_addr; 900 page_size_mask = ring_info->block_size_mask; 901 902 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 903 "==> nxge_rxbuf_pp_to_vp: (FOUND3), get chunk)" 904 "buf_pp $%p btype %d bufsize %d " 905 "anchor_index %d chunk_index %d dvma $%p", 906 pkt_buf_addr_pp, 907 pktbufsz_type, 908 bufsize, 909 anchor_index, 910 chunk_index, 911 dvma_addr)); 912 913 offset = pktbuf_pp - dvma_addr; /* offset within the chunk */ 914 block_size = rbr_p->block_size; /* System block(page) size */ 915 916 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 917 "==> nxge_rxbuf_pp_to_vp: (FOUND4), get chunk)" 918 "buf_pp $%p btype %d bufsize %d " 919 "anchor_index %d chunk_index %d dvma $%p " 920 "offset %d block_size %d", 921 pkt_buf_addr_pp, 922 pktbufsz_type, 923 bufsize, 924 anchor_index, 925 chunk_index, 926 dvma_addr, 927 offset, 928 block_size)); 929 930 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> getting total index")); 931 932 block_index = (offset / block_size); /* index within chunk */ 933 total_index = chunk_index + block_index; 934 935 936 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 937 "==> nxge_rxbuf_pp_to_vp: " 938 "total_index %d dvma_addr $%p " 939 "offset %d block_size %d " 940 "block_index %d ", 941 total_index, dvma_addr, 942 offset, block_size, 943 block_index)); 944 #if defined(__i386) 945 *pkt_buf_addr_p = (uint64_t *)((uint32_t)bufinfo[anchor_index].kaddr + 946 (uint32_t)offset); 947 #else 948 *pkt_buf_addr_p = (uint64_t *)((uint64_t)bufinfo[anchor_index].kaddr + 949 (uint64_t)offset); 950 #endif 951 952 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 953 "==> nxge_rxbuf_pp_to_vp: " 954 "total_index %d dvma_addr $%p " 955 "offset %d block_size %d " 956 "block_index %d " 957 "*pkt_buf_addr_p $%p", 958 total_index, dvma_addr, 959 offset, block_size, 960 block_index, 961 *pkt_buf_addr_p)); 962 963 964 *msg_index = total_index; 965 *bufoffset = (offset & page_size_mask); 966 967 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 968 "==> nxge_rxbuf_pp_to_vp: get msg index: " 969 "msg_index %d bufoffset_index %d", 970 *msg_index, 971 *bufoffset)); 972 973 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "<== nxge_rxbuf_pp_to_vp")); 974 975 return (NXGE_OK); 976 } 977 978 /* 979 * used by quick sort (qsort) function 980 * to perform comparison 981 */ 982 static int 983 nxge_sort_compare(const void *p1, const void *p2) 984 { 985 986 rxbuf_index_info_t *a, *b; 987 988 a = (rxbuf_index_info_t *)p1; 989 b = (rxbuf_index_info_t *)p2; 990 991 if (a->dvma_addr > b->dvma_addr) 992 return (1); 993 if (a->dvma_addr < b->dvma_addr) 994 return (-1); 995 return (0); 996 } 997 998 999 1000 /* 1001 * grabbed this sort implementation from common/syscall/avl.c 1002 * 1003 */ 1004 /* 1005 * Generic shellsort, from K&R (1st ed, p 58.), somewhat modified. 1006 * v = Ptr to array/vector of objs 1007 * n = # objs in the array 1008 * s = size of each obj (must be multiples of a word size) 1009 * f = ptr to function to compare two objs 1010 * returns (-1 = less than, 0 = equal, 1 = greater than 1011 */ 1012 void 1013 nxge_ksort(caddr_t v, int n, int s, int (*f)()) 1014 { 1015 int g, i, j, ii; 1016 unsigned int *p1, *p2; 1017 unsigned int tmp; 1018 1019 /* No work to do */ 1020 if (v == NULL || n <= 1) 1021 return; 1022 /* Sanity check on arguments */ 1023 ASSERT(((uintptr_t)v & 0x3) == 0 && (s & 0x3) == 0); 1024 ASSERT(s > 0); 1025 1026 for (g = n / 2; g > 0; g /= 2) { 1027 for (i = g; i < n; i++) { 1028 for (j = i - g; j >= 0 && 1029 (*f)(v + j * s, v + (j + g) * s) == 1; 1030 j -= g) { 1031 p1 = (unsigned *)(v + j * s); 1032 p2 = (unsigned *)(v + (j + g) * s); 1033 for (ii = 0; ii < s / 4; ii++) { 1034 tmp = *p1; 1035 *p1++ = *p2; 1036 *p2++ = tmp; 1037 } 1038 } 1039 } 1040 } 1041 } 1042 1043 /* 1044 * Initialize data structures required for rxdma 1045 * buffer dvma->vmem address lookup 1046 */ 1047 /*ARGSUSED*/ 1048 static nxge_status_t 1049 nxge_rxbuf_index_info_init(p_nxge_t nxgep, p_rx_rbr_ring_t rbrp) 1050 { 1051 1052 int index; 1053 rxring_info_t *ring_info; 1054 int max_iteration = 0, max_index = 0; 1055 1056 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_rxbuf_index_info_init")); 1057 1058 ring_info = rbrp->ring_info; 1059 ring_info->hint[0] = NO_HINT; 1060 ring_info->hint[1] = NO_HINT; 1061 ring_info->hint[2] = NO_HINT; 1062 max_index = rbrp->num_blocks; 1063 1064 /* read the DVMA address information and sort it */ 1065 /* do init of the information array */ 1066 1067 1068 NXGE_DEBUG_MSG((nxgep, DMA2_CTL, 1069 " nxge_rxbuf_index_info_init Sort ptrs")); 1070 1071 /* sort the array */ 1072 nxge_ksort((void *)ring_info->buffer, max_index, 1073 sizeof (rxbuf_index_info_t), nxge_sort_compare); 1074 1075 1076 1077 for (index = 0; index < max_index; index++) { 1078 NXGE_DEBUG_MSG((nxgep, DMA2_CTL, 1079 " nxge_rxbuf_index_info_init: sorted chunk %d " 1080 " ioaddr $%p kaddr $%p size %x", 1081 index, ring_info->buffer[index].dvma_addr, 1082 ring_info->buffer[index].kaddr, 1083 ring_info->buffer[index].buf_size)); 1084 } 1085 1086 max_iteration = 0; 1087 while (max_index >= (1ULL << max_iteration)) 1088 max_iteration++; 1089 ring_info->max_iterations = max_iteration + 1; 1090 NXGE_DEBUG_MSG((nxgep, DMA2_CTL, 1091 " nxge_rxbuf_index_info_init Find max iter %d", 1092 ring_info->max_iterations)); 1093 1094 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxbuf_index_info_init")); 1095 return (NXGE_OK); 1096 } 1097 1098 /* ARGSUSED */ 1099 void 1100 nxge_dump_rcr_entry(p_nxge_t nxgep, p_rcr_entry_t entry_p) 1101 { 1102 #ifdef NXGE_DEBUG 1103 1104 uint32_t bptr; 1105 uint64_t pp; 1106 1107 bptr = entry_p->bits.hdw.pkt_buf_addr; 1108 1109 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1110 "\trcr entry $%p " 1111 "\trcr entry 0x%0llx " 1112 "\trcr entry 0x%08x " 1113 "\trcr entry 0x%08x " 1114 "\tvalue 0x%0llx\n" 1115 "\tmulti = %d\n" 1116 "\tpkt_type = 0x%x\n" 1117 "\tzero_copy = %d\n" 1118 "\tnoport = %d\n" 1119 "\tpromis = %d\n" 1120 "\terror = 0x%04x\n" 1121 "\tdcf_err = 0x%01x\n" 1122 "\tl2_len = %d\n" 1123 "\tpktbufsize = %d\n" 1124 "\tpkt_buf_addr = $%p\n" 1125 "\tpkt_buf_addr (<< 6) = $%p\n", 1126 entry_p, 1127 *(int64_t *)entry_p, 1128 *(int32_t *)entry_p, 1129 *(int32_t *)((char *)entry_p + 32), 1130 entry_p->value, 1131 entry_p->bits.hdw.multi, 1132 entry_p->bits.hdw.pkt_type, 1133 entry_p->bits.hdw.zero_copy, 1134 entry_p->bits.hdw.noport, 1135 entry_p->bits.hdw.promis, 1136 entry_p->bits.hdw.error, 1137 entry_p->bits.hdw.dcf_err, 1138 entry_p->bits.hdw.l2_len, 1139 entry_p->bits.hdw.pktbufsz, 1140 bptr, 1141 entry_p->bits.ldw.pkt_buf_addr)); 1142 1143 pp = (entry_p->value & RCR_PKT_BUF_ADDR_MASK) << 1144 RCR_PKT_BUF_ADDR_SHIFT; 1145 1146 NXGE_DEBUG_MSG((nxgep, RX_CTL, "rcr pp 0x%llx l2 len %d", 1147 pp, (*(int64_t *)entry_p >> 40) & 0x3fff)); 1148 #endif 1149 } 1150 1151 void 1152 nxge_rxdma_regs_dump(p_nxge_t nxgep, int rdc) 1153 { 1154 npi_handle_t handle; 1155 rbr_stat_t rbr_stat; 1156 addr44_t hd_addr; 1157 addr44_t tail_addr; 1158 uint16_t qlen; 1159 1160 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1161 "==> nxge_rxdma_regs_dump: rdc channel %d", rdc)); 1162 1163 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1164 1165 /* RBR head */ 1166 hd_addr.addr = 0; 1167 (void) npi_rxdma_rdc_rbr_head_get(handle, rdc, &hd_addr); 1168 #if defined(__i386) 1169 printf("nxge_rxdma_regs_dump: got hdptr $%p \n", 1170 (void *)(uint32_t)hd_addr.addr); 1171 #else 1172 printf("nxge_rxdma_regs_dump: got hdptr $%p \n", 1173 (void *)hd_addr.addr); 1174 #endif 1175 1176 /* RBR stats */ 1177 (void) npi_rxdma_rdc_rbr_stat_get(handle, rdc, &rbr_stat); 1178 printf("nxge_rxdma_regs_dump: rbr len %d \n", rbr_stat.bits.ldw.qlen); 1179 1180 /* RCR tail */ 1181 tail_addr.addr = 0; 1182 (void) npi_rxdma_rdc_rcr_tail_get(handle, rdc, &tail_addr); 1183 #if defined(__i386) 1184 printf("nxge_rxdma_regs_dump: got tail ptr $%p \n", 1185 (void *)(uint32_t)tail_addr.addr); 1186 #else 1187 printf("nxge_rxdma_regs_dump: got tail ptr $%p \n", 1188 (void *)tail_addr.addr); 1189 #endif 1190 1191 /* RCR qlen */ 1192 (void) npi_rxdma_rdc_rcr_qlen_get(handle, rdc, &qlen); 1193 printf("nxge_rxdma_regs_dump: rcr len %x \n", qlen); 1194 1195 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1196 "<== nxge_rxdma_regs_dump: rdc rdc %d", rdc)); 1197 } 1198 1199 nxge_status_t 1200 nxge_rxdma_hw_mode(p_nxge_t nxgep, boolean_t enable) 1201 { 1202 nxge_grp_set_t *set = &nxgep->rx_set; 1203 nxge_status_t status; 1204 npi_status_t rs; 1205 int rdc; 1206 1207 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1208 "==> nxge_rxdma_hw_mode: mode %d", enable)); 1209 1210 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 1211 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1212 "<== nxge_rxdma_mode: not initialized")); 1213 return (NXGE_ERROR); 1214 } 1215 1216 if (nxgep->rx_rbr_rings == 0 || nxgep->rx_rbr_rings->rbr_rings == 0) { 1217 NXGE_DEBUG_MSG((nxgep, TX_CTL, 1218 "<== nxge_tx_port_fatal_err_recover: " 1219 "NULL ring pointer(s)")); 1220 return (NXGE_ERROR); 1221 } 1222 1223 if (set->owned.map == 0) { 1224 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1225 "nxge_rxdma_regs_dump_channels: no channels")); 1226 return (NULL); 1227 } 1228 1229 for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 1230 if ((1 << rdc) & set->owned.map) { 1231 rx_rbr_ring_t *ring = 1232 nxgep->rx_rbr_rings->rbr_rings[rdc]; 1233 npi_handle_t handle = NXGE_DEV_NPI_HANDLE(nxgep); 1234 if (ring) { 1235 if (enable) { 1236 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1237 "==> nxge_rxdma_hw_mode: " 1238 "channel %d (enable)", rdc)); 1239 rs = npi_rxdma_cfg_rdc_enable 1240 (handle, rdc); 1241 } else { 1242 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1243 "==> nxge_rxdma_hw_mode: " 1244 "channel %d disable)", rdc)); 1245 rs = npi_rxdma_cfg_rdc_disable 1246 (handle, rdc); 1247 } 1248 } 1249 } 1250 } 1251 1252 status = ((rs == NPI_SUCCESS) ? NXGE_OK : NXGE_ERROR | rs); 1253 1254 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1255 "<== nxge_rxdma_hw_mode: status 0x%x", status)); 1256 1257 return (status); 1258 } 1259 1260 void 1261 nxge_rxdma_enable_channel(p_nxge_t nxgep, uint16_t channel) 1262 { 1263 npi_handle_t handle; 1264 1265 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 1266 "==> nxge_rxdma_enable_channel: channel %d", channel)); 1267 1268 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1269 (void) npi_rxdma_cfg_rdc_enable(handle, channel); 1270 1271 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxdma_enable_channel")); 1272 } 1273 1274 void 1275 nxge_rxdma_disable_channel(p_nxge_t nxgep, uint16_t channel) 1276 { 1277 npi_handle_t handle; 1278 1279 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 1280 "==> nxge_rxdma_disable_channel: channel %d", channel)); 1281 1282 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1283 (void) npi_rxdma_cfg_rdc_disable(handle, channel); 1284 1285 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxdma_disable_channel")); 1286 } 1287 1288 void 1289 nxge_hw_start_rx(p_nxge_t nxgep) 1290 { 1291 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_start_rx")); 1292 1293 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_START); 1294 (void) nxge_rx_mac_enable(nxgep); 1295 1296 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_start_rx")); 1297 } 1298 1299 /*ARGSUSED*/ 1300 void 1301 nxge_fixup_rxdma_rings(p_nxge_t nxgep) 1302 { 1303 nxge_grp_set_t *set = &nxgep->rx_set; 1304 int rdc; 1305 1306 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_fixup_rxdma_rings")); 1307 1308 if (nxgep->rx_rbr_rings == 0 || nxgep->rx_rbr_rings->rbr_rings == 0) { 1309 NXGE_DEBUG_MSG((nxgep, TX_CTL, 1310 "<== nxge_tx_port_fatal_err_recover: " 1311 "NULL ring pointer(s)")); 1312 return; 1313 } 1314 1315 if (set->owned.map == 0) { 1316 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1317 "nxge_rxdma_regs_dump_channels: no channels")); 1318 return; 1319 } 1320 1321 for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 1322 if ((1 << rdc) & set->owned.map) { 1323 rx_rbr_ring_t *ring = 1324 nxgep->rx_rbr_rings->rbr_rings[rdc]; 1325 if (ring) { 1326 nxge_rxdma_hw_stop(nxgep, rdc); 1327 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1328 "==> nxge_fixup_rxdma_rings: " 1329 "channel %d ring $%px", 1330 rdc, ring)); 1331 (void) nxge_rxdma_fix_channel(nxgep, rdc); 1332 } 1333 } 1334 } 1335 1336 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_fixup_rxdma_rings")); 1337 } 1338 1339 void 1340 nxge_rxdma_fix_channel(p_nxge_t nxgep, uint16_t channel) 1341 { 1342 int ndmas; 1343 p_rx_rbr_rings_t rx_rbr_rings; 1344 p_rx_rbr_ring_t *rbr_rings; 1345 p_rx_rcr_rings_t rx_rcr_rings; 1346 p_rx_rcr_ring_t *rcr_rings; 1347 p_rx_mbox_areas_t rx_mbox_areas_p; 1348 p_rx_mbox_t *rx_mbox_p; 1349 p_nxge_dma_pool_t dma_buf_poolp; 1350 p_nxge_dma_pool_t dma_cntl_poolp; 1351 p_rx_rbr_ring_t rbrp; 1352 p_rx_rcr_ring_t rcrp; 1353 p_rx_mbox_t mboxp; 1354 p_nxge_dma_common_t dmap; 1355 nxge_status_t status = NXGE_OK; 1356 1357 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_fix_channel")); 1358 1359 (void) nxge_rxdma_stop_channel(nxgep, channel); 1360 1361 dma_buf_poolp = nxgep->rx_buf_pool_p; 1362 dma_cntl_poolp = nxgep->rx_cntl_pool_p; 1363 1364 if (!dma_buf_poolp->buf_allocated || !dma_cntl_poolp->buf_allocated) { 1365 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1366 "<== nxge_rxdma_fix_channel: buf not allocated")); 1367 return; 1368 } 1369 1370 ndmas = dma_buf_poolp->ndmas; 1371 if (!ndmas) { 1372 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1373 "<== nxge_rxdma_fix_channel: no dma allocated")); 1374 return; 1375 } 1376 1377 rx_rbr_rings = nxgep->rx_rbr_rings; 1378 rx_rcr_rings = nxgep->rx_rcr_rings; 1379 rbr_rings = rx_rbr_rings->rbr_rings; 1380 rcr_rings = rx_rcr_rings->rcr_rings; 1381 rx_mbox_areas_p = nxgep->rx_mbox_areas_p; 1382 rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 1383 1384 /* Reinitialize the receive block and completion rings */ 1385 rbrp = (p_rx_rbr_ring_t)rbr_rings[channel], 1386 rcrp = (p_rx_rcr_ring_t)rcr_rings[channel], 1387 mboxp = (p_rx_mbox_t)rx_mbox_p[channel]; 1388 1389 rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 1390 rbrp->rbr_rd_index = 0; 1391 rcrp->comp_rd_index = 0; 1392 rcrp->comp_wt_index = 0; 1393 1394 dmap = (p_nxge_dma_common_t)&rcrp->rcr_desc; 1395 bzero((caddr_t)dmap->kaddrp, dmap->alength); 1396 1397 status = nxge_rxdma_start_channel(nxgep, channel, 1398 rbrp, rcrp, mboxp); 1399 if (status != NXGE_OK) { 1400 goto nxge_rxdma_fix_channel_fail; 1401 } 1402 1403 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1404 "<== nxge_rxdma_fix_channel: success (0x%08x)", status)); 1405 return; 1406 1407 nxge_rxdma_fix_channel_fail: 1408 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1409 "<== nxge_rxdma_fix_channel: failed (0x%08x)", status)); 1410 } 1411 1412 p_rx_rbr_ring_t 1413 nxge_rxdma_get_rbr_ring(p_nxge_t nxgep, uint16_t channel) 1414 { 1415 nxge_grp_set_t *set = &nxgep->rx_set; 1416 nxge_channel_t rdc; 1417 1418 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1419 "==> nxge_rxdma_get_rbr_ring: channel %d", channel)); 1420 1421 if (nxgep->rx_rbr_rings == 0 || nxgep->rx_rbr_rings->rbr_rings == 0) { 1422 NXGE_DEBUG_MSG((nxgep, TX_CTL, 1423 "<== nxge_rxdma_get_rbr_ring: " 1424 "NULL ring pointer(s)")); 1425 return (NULL); 1426 } 1427 1428 if (set->owned.map == 0) { 1429 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1430 "<== nxge_rxdma_get_rbr_ring: no channels")); 1431 return (NULL); 1432 } 1433 1434 for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 1435 if ((1 << rdc) & set->owned.map) { 1436 rx_rbr_ring_t *ring = 1437 nxgep->rx_rbr_rings->rbr_rings[rdc]; 1438 if (ring) { 1439 if (channel == ring->rdc) { 1440 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1441 "==> nxge_rxdma_get_rbr_ring: " 1442 "channel %d ring $%p", rdc, ring)); 1443 return (ring); 1444 } 1445 } 1446 } 1447 } 1448 1449 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1450 "<== nxge_rxdma_get_rbr_ring: not found")); 1451 1452 return (NULL); 1453 } 1454 1455 p_rx_rcr_ring_t 1456 nxge_rxdma_get_rcr_ring(p_nxge_t nxgep, uint16_t channel) 1457 { 1458 nxge_grp_set_t *set = &nxgep->rx_set; 1459 nxge_channel_t rdc; 1460 1461 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1462 "==> nxge_rxdma_get_rcr_ring: channel %d", channel)); 1463 1464 if (nxgep->rx_rcr_rings == 0 || nxgep->rx_rcr_rings->rcr_rings == 0) { 1465 NXGE_DEBUG_MSG((nxgep, TX_CTL, 1466 "<== nxge_rxdma_get_rcr_ring: " 1467 "NULL ring pointer(s)")); 1468 return (NULL); 1469 } 1470 1471 if (set->owned.map == 0) { 1472 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1473 "<== nxge_rxdma_get_rbr_ring: no channels")); 1474 return (NULL); 1475 } 1476 1477 for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 1478 if ((1 << rdc) & set->owned.map) { 1479 rx_rcr_ring_t *ring = 1480 nxgep->rx_rcr_rings->rcr_rings[rdc]; 1481 if (ring) { 1482 if (channel == ring->rdc) { 1483 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1484 "==> nxge_rxdma_get_rcr_ring: " 1485 "channel %d ring $%p", rdc, ring)); 1486 return (ring); 1487 } 1488 } 1489 } 1490 } 1491 1492 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1493 "<== nxge_rxdma_get_rcr_ring: not found")); 1494 1495 return (NULL); 1496 } 1497 1498 /* 1499 * Static functions start here. 1500 */ 1501 static p_rx_msg_t 1502 nxge_allocb(size_t size, uint32_t pri, p_nxge_dma_common_t dmabuf_p) 1503 { 1504 p_rx_msg_t nxge_mp = NULL; 1505 p_nxge_dma_common_t dmamsg_p; 1506 uchar_t *buffer; 1507 1508 nxge_mp = KMEM_ZALLOC(sizeof (rx_msg_t), KM_NOSLEEP); 1509 if (nxge_mp == NULL) { 1510 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 1511 "Allocation of a rx msg failed.")); 1512 goto nxge_allocb_exit; 1513 } 1514 1515 nxge_mp->use_buf_pool = B_FALSE; 1516 if (dmabuf_p) { 1517 nxge_mp->use_buf_pool = B_TRUE; 1518 dmamsg_p = (p_nxge_dma_common_t)&nxge_mp->buf_dma; 1519 *dmamsg_p = *dmabuf_p; 1520 dmamsg_p->nblocks = 1; 1521 dmamsg_p->block_size = size; 1522 dmamsg_p->alength = size; 1523 buffer = (uchar_t *)dmabuf_p->kaddrp; 1524 1525 dmabuf_p->kaddrp = (void *) 1526 ((char *)dmabuf_p->kaddrp + size); 1527 dmabuf_p->ioaddr_pp = (void *) 1528 ((char *)dmabuf_p->ioaddr_pp + size); 1529 dmabuf_p->alength -= size; 1530 dmabuf_p->offset += size; 1531 dmabuf_p->dma_cookie.dmac_laddress += size; 1532 dmabuf_p->dma_cookie.dmac_size -= size; 1533 1534 } else { 1535 buffer = KMEM_ALLOC(size, KM_NOSLEEP); 1536 if (buffer == NULL) { 1537 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 1538 "Allocation of a receive page failed.")); 1539 goto nxge_allocb_fail1; 1540 } 1541 } 1542 1543 nxge_mp->rx_mblk_p = desballoc(buffer, size, pri, &nxge_mp->freeb); 1544 if (nxge_mp->rx_mblk_p == NULL) { 1545 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, "desballoc failed.")); 1546 goto nxge_allocb_fail2; 1547 } 1548 1549 nxge_mp->buffer = buffer; 1550 nxge_mp->block_size = size; 1551 nxge_mp->freeb.free_func = (void (*)())nxge_freeb; 1552 nxge_mp->freeb.free_arg = (caddr_t)nxge_mp; 1553 nxge_mp->ref_cnt = 1; 1554 nxge_mp->free = B_TRUE; 1555 nxge_mp->rx_use_bcopy = B_FALSE; 1556 1557 atomic_inc_32(&nxge_mblks_pending); 1558 1559 goto nxge_allocb_exit; 1560 1561 nxge_allocb_fail2: 1562 if (!nxge_mp->use_buf_pool) { 1563 KMEM_FREE(buffer, size); 1564 } 1565 1566 nxge_allocb_fail1: 1567 KMEM_FREE(nxge_mp, sizeof (rx_msg_t)); 1568 nxge_mp = NULL; 1569 1570 nxge_allocb_exit: 1571 return (nxge_mp); 1572 } 1573 1574 p_mblk_t 1575 nxge_dupb(p_rx_msg_t nxge_mp, uint_t offset, size_t size) 1576 { 1577 p_mblk_t mp; 1578 1579 NXGE_DEBUG_MSG((NULL, MEM_CTL, "==> nxge_dupb")); 1580 NXGE_DEBUG_MSG((NULL, MEM_CTL, "nxge_mp = $%p " 1581 "offset = 0x%08X " 1582 "size = 0x%08X", 1583 nxge_mp, offset, size)); 1584 1585 mp = desballoc(&nxge_mp->buffer[offset], size, 1586 0, &nxge_mp->freeb); 1587 if (mp == NULL) { 1588 NXGE_DEBUG_MSG((NULL, RX_CTL, "desballoc failed")); 1589 goto nxge_dupb_exit; 1590 } 1591 atomic_inc_32(&nxge_mp->ref_cnt); 1592 1593 1594 nxge_dupb_exit: 1595 NXGE_DEBUG_MSG((NULL, MEM_CTL, "<== nxge_dupb mp = $%p", 1596 nxge_mp)); 1597 return (mp); 1598 } 1599 1600 p_mblk_t 1601 nxge_dupb_bcopy(p_rx_msg_t nxge_mp, uint_t offset, size_t size) 1602 { 1603 p_mblk_t mp; 1604 uchar_t *dp; 1605 1606 mp = allocb(size + NXGE_RXBUF_EXTRA, 0); 1607 if (mp == NULL) { 1608 NXGE_DEBUG_MSG((NULL, RX_CTL, "desballoc failed")); 1609 goto nxge_dupb_bcopy_exit; 1610 } 1611 dp = mp->b_rptr = mp->b_rptr + NXGE_RXBUF_EXTRA; 1612 bcopy((void *)&nxge_mp->buffer[offset], dp, size); 1613 mp->b_wptr = dp + size; 1614 1615 nxge_dupb_bcopy_exit: 1616 NXGE_DEBUG_MSG((NULL, MEM_CTL, "<== nxge_dupb mp = $%p", 1617 nxge_mp)); 1618 return (mp); 1619 } 1620 1621 void nxge_post_page(p_nxge_t nxgep, p_rx_rbr_ring_t rx_rbr_p, 1622 p_rx_msg_t rx_msg_p); 1623 1624 void 1625 nxge_post_page(p_nxge_t nxgep, p_rx_rbr_ring_t rx_rbr_p, p_rx_msg_t rx_msg_p) 1626 { 1627 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_post_page")); 1628 1629 /* Reuse this buffer */ 1630 rx_msg_p->free = B_FALSE; 1631 rx_msg_p->cur_usage_cnt = 0; 1632 rx_msg_p->max_usage_cnt = 0; 1633 rx_msg_p->pkt_buf_size = 0; 1634 1635 if (rx_rbr_p->rbr_use_bcopy) { 1636 rx_msg_p->rx_use_bcopy = B_FALSE; 1637 atomic_dec_32(&rx_rbr_p->rbr_consumed); 1638 } 1639 1640 /* 1641 * Get the rbr header pointer and its offset index. 1642 */ 1643 MUTEX_ENTER(&rx_rbr_p->post_lock); 1644 rx_rbr_p->rbr_wr_index = ((rx_rbr_p->rbr_wr_index + 1) & 1645 rx_rbr_p->rbr_wrap_mask); 1646 rx_rbr_p->rbr_desc_vp[rx_rbr_p->rbr_wr_index] = rx_msg_p->shifted_addr; 1647 MUTEX_EXIT(&rx_rbr_p->post_lock); 1648 npi_rxdma_rdc_rbr_kick(NXGE_DEV_NPI_HANDLE(nxgep), 1649 rx_rbr_p->rdc, 1); 1650 1651 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1652 "<== nxge_post_page (channel %d post_next_index %d)", 1653 rx_rbr_p->rdc, rx_rbr_p->rbr_wr_index)); 1654 1655 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_post_page")); 1656 } 1657 1658 void 1659 nxge_freeb(p_rx_msg_t rx_msg_p) 1660 { 1661 size_t size; 1662 uchar_t *buffer = NULL; 1663 int ref_cnt; 1664 boolean_t free_state = B_FALSE; 1665 1666 rx_rbr_ring_t *ring = rx_msg_p->rx_rbr_p; 1667 1668 NXGE_DEBUG_MSG((NULL, MEM2_CTL, "==> nxge_freeb")); 1669 NXGE_DEBUG_MSG((NULL, MEM2_CTL, 1670 "nxge_freeb:rx_msg_p = $%p (block pending %d)", 1671 rx_msg_p, nxge_mblks_pending)); 1672 1673 /* 1674 * First we need to get the free state, then 1675 * atomic decrement the reference count to prevent 1676 * the race condition with the interrupt thread that 1677 * is processing a loaned up buffer block. 1678 */ 1679 free_state = rx_msg_p->free; 1680 ref_cnt = atomic_add_32_nv(&rx_msg_p->ref_cnt, -1); 1681 if (!ref_cnt) { 1682 atomic_dec_32(&nxge_mblks_pending); 1683 buffer = rx_msg_p->buffer; 1684 size = rx_msg_p->block_size; 1685 NXGE_DEBUG_MSG((NULL, MEM2_CTL, "nxge_freeb: " 1686 "will free: rx_msg_p = $%p (block pending %d)", 1687 rx_msg_p, nxge_mblks_pending)); 1688 1689 if (!rx_msg_p->use_buf_pool) { 1690 KMEM_FREE(buffer, size); 1691 } 1692 1693 KMEM_FREE(rx_msg_p, sizeof (rx_msg_t)); 1694 1695 if (ring) { 1696 /* 1697 * Decrement the receive buffer ring's reference 1698 * count, too. 1699 */ 1700 atomic_dec_32(&ring->rbr_ref_cnt); 1701 1702 /* 1703 * Free the receive buffer ring, if 1704 * 1. all the receive buffers have been freed 1705 * 2. and we are in the proper state (that is, 1706 * we are not UNMAPPING). 1707 */ 1708 if (ring->rbr_ref_cnt == 0 && 1709 ring->rbr_state == RBR_UNMAPPED) { 1710 /* 1711 * Free receive data buffers, 1712 * buffer index information 1713 * (rxring_info) and 1714 * the message block ring. 1715 */ 1716 NXGE_DEBUG_MSG((NULL, RX_CTL, 1717 "nxge_freeb:rx_msg_p = $%p " 1718 "(block pending %d) free buffers", 1719 rx_msg_p, nxge_mblks_pending)); 1720 nxge_rxdma_databuf_free(ring); 1721 if (ring->ring_info) { 1722 KMEM_FREE(ring->ring_info, 1723 sizeof (rxring_info_t)); 1724 } 1725 1726 if (ring->rx_msg_ring) { 1727 KMEM_FREE(ring->rx_msg_ring, 1728 ring->tnblocks * 1729 sizeof (p_rx_msg_t)); 1730 } 1731 KMEM_FREE(ring, sizeof (*ring)); 1732 } 1733 } 1734 return; 1735 } 1736 1737 /* 1738 * Repost buffer. 1739 */ 1740 if (free_state && (ref_cnt == 1) && ring) { 1741 NXGE_DEBUG_MSG((NULL, RX_CTL, 1742 "nxge_freeb: post page $%p:", rx_msg_p)); 1743 if (ring->rbr_state == RBR_POSTING) 1744 nxge_post_page(rx_msg_p->nxgep, ring, rx_msg_p); 1745 } 1746 1747 NXGE_DEBUG_MSG((NULL, MEM2_CTL, "<== nxge_freeb")); 1748 } 1749 1750 uint_t 1751 nxge_rx_intr(void *arg1, void *arg2) 1752 { 1753 p_nxge_ldv_t ldvp = (p_nxge_ldv_t)arg1; 1754 p_nxge_t nxgep = (p_nxge_t)arg2; 1755 p_nxge_ldg_t ldgp; 1756 uint8_t channel; 1757 npi_handle_t handle; 1758 rx_dma_ctl_stat_t cs; 1759 p_rx_rcr_ring_t rcrp; 1760 mblk_t *mp = NULL; 1761 1762 if (ldvp == NULL) { 1763 NXGE_DEBUG_MSG((NULL, INT_CTL, 1764 "<== nxge_rx_intr: arg2 $%p arg1 $%p", 1765 nxgep, ldvp)); 1766 return (DDI_INTR_CLAIMED); 1767 } 1768 1769 if (arg2 == NULL || (void *)ldvp->nxgep != arg2) { 1770 nxgep = ldvp->nxgep; 1771 } 1772 1773 if ((!(nxgep->drv_state & STATE_HW_INITIALIZED)) || 1774 (nxgep->nxge_mac_state != NXGE_MAC_STARTED)) { 1775 NXGE_DEBUG_MSG((nxgep, INT_CTL, 1776 "<== nxge_rx_intr: interface not started or intialized")); 1777 return (DDI_INTR_CLAIMED); 1778 } 1779 1780 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1781 "==> nxge_rx_intr: arg2 $%p arg1 $%p", 1782 nxgep, ldvp)); 1783 1784 /* 1785 * Get the PIO handle. 1786 */ 1787 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1788 1789 /* 1790 * Get the ring to enable us to process packets. 1791 */ 1792 rcrp = nxgep->rx_rcr_rings->rcr_rings[ldvp->vdma_index]; 1793 1794 /* 1795 * The RCR ring lock must be held when packets 1796 * are being processed and the hardware registers are 1797 * being read or written to prevent race condition 1798 * among the interrupt thread, the polling thread 1799 * (will cause fatal errors such as rcrincon bit set) 1800 * and the setting of the poll_flag. 1801 */ 1802 MUTEX_ENTER(&rcrp->lock); 1803 1804 /* 1805 * Get the control and status for this channel. 1806 */ 1807 channel = ldvp->channel; 1808 ldgp = ldvp->ldgp; 1809 1810 if (!isLDOMguest(nxgep) && (!nxgep->rx_channel_started[channel])) { 1811 NXGE_DEBUG_MSG((nxgep, INT_CTL, 1812 "<== nxge_rx_intr: channel is not started")); 1813 1814 /* 1815 * We received an interrupt before the ring is started. 1816 */ 1817 RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, channel, 1818 &cs.value); 1819 cs.value &= RX_DMA_CTL_STAT_WR1C; 1820 cs.bits.hdw.mex = 1; 1821 RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, channel, 1822 cs.value); 1823 1824 /* 1825 * Rearm this logical group if this is a single device 1826 * group. 1827 */ 1828 if (ldgp->nldvs == 1) { 1829 if (isLDOMguest(nxgep)) { 1830 nxge_hio_ldgimgn(nxgep, ldgp); 1831 } else { 1832 ldgimgm_t mgm; 1833 1834 mgm.value = 0; 1835 mgm.bits.ldw.arm = 1; 1836 mgm.bits.ldw.timer = ldgp->ldg_timer; 1837 1838 NXGE_REG_WR64(handle, 1839 LDGIMGN_REG + LDSV_OFFSET(ldgp->ldg), 1840 mgm.value); 1841 } 1842 } 1843 MUTEX_EXIT(&rcrp->lock); 1844 return (DDI_INTR_CLAIMED); 1845 } 1846 1847 ASSERT(rcrp->ldgp == ldgp); 1848 ASSERT(rcrp->ldvp == ldvp); 1849 1850 RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, channel, &cs.value); 1851 1852 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_intr:channel %d " 1853 "cs 0x%016llx rcrto 0x%x rcrthres %x", 1854 channel, 1855 cs.value, 1856 cs.bits.hdw.rcrto, 1857 cs.bits.hdw.rcrthres)); 1858 1859 if (!rcrp->poll_flag) { 1860 mp = nxge_rx_pkts(nxgep, rcrp, cs, -1); 1861 } 1862 1863 /* error events. */ 1864 if (cs.value & RX_DMA_CTL_STAT_ERROR) { 1865 (void) nxge_rx_err_evnts(nxgep, channel, cs); 1866 } 1867 1868 /* 1869 * Enable the mailbox update interrupt if we want 1870 * to use mailbox. We probably don't need to use 1871 * mailbox as it only saves us one pio read. 1872 * Also write 1 to rcrthres and rcrto to clear 1873 * these two edge triggered bits. 1874 */ 1875 cs.value &= RX_DMA_CTL_STAT_WR1C; 1876 cs.bits.hdw.mex = rcrp->poll_flag ? 0 : 1; 1877 RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, channel, 1878 cs.value); 1879 1880 /* 1881 * If the polling mode is enabled, disable the interrupt. 1882 */ 1883 if (rcrp->poll_flag) { 1884 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 1885 "==> nxge_rx_intr: rdc %d ldgp $%p ldvp $%p " 1886 "(disabling interrupts)", channel, ldgp, ldvp)); 1887 1888 /* 1889 * Disarm this logical group if this is a single device 1890 * group. 1891 */ 1892 if (ldgp->nldvs == 1) { 1893 if (isLDOMguest(nxgep)) { 1894 ldgp->arm = B_FALSE; 1895 nxge_hio_ldgimgn(nxgep, ldgp); 1896 } else { 1897 ldgimgm_t mgm; 1898 mgm.value = 0; 1899 mgm.bits.ldw.arm = 0; 1900 NXGE_REG_WR64(handle, 1901 LDGIMGN_REG + LDSV_OFFSET(ldgp->ldg), 1902 mgm.value); 1903 } 1904 } 1905 } else { 1906 /* 1907 * Rearm this logical group if this is a single device 1908 * group. 1909 */ 1910 if (ldgp->nldvs == 1) { 1911 if (isLDOMguest(nxgep)) { 1912 nxge_hio_ldgimgn(nxgep, ldgp); 1913 } else { 1914 ldgimgm_t mgm; 1915 1916 mgm.value = 0; 1917 mgm.bits.ldw.arm = 1; 1918 mgm.bits.ldw.timer = ldgp->ldg_timer; 1919 1920 NXGE_REG_WR64(handle, 1921 LDGIMGN_REG + LDSV_OFFSET(ldgp->ldg), 1922 mgm.value); 1923 } 1924 } 1925 1926 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 1927 "==> nxge_rx_intr: rdc %d ldgp $%p " 1928 "exiting ISR (and call mac_rx_ring)", channel, ldgp)); 1929 } 1930 MUTEX_EXIT(&rcrp->lock); 1931 1932 if (mp != NULL) { 1933 mac_rx_ring(nxgep->mach, rcrp->rcr_mac_handle, mp, 1934 rcrp->rcr_gen_num); 1935 } 1936 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rx_intr: DDI_INTR_CLAIMED")); 1937 return (DDI_INTR_CLAIMED); 1938 } 1939 1940 /* 1941 * This routine is the main packet receive processing function. 1942 * It gets the packet type, error code, and buffer related 1943 * information from the receive completion entry. 1944 * How many completion entries to process is based on the number of packets 1945 * queued by the hardware, a hardware maintained tail pointer 1946 * and a configurable receive packet count. 1947 * 1948 * A chain of message blocks will be created as result of processing 1949 * the completion entries. This chain of message blocks will be returned and 1950 * a hardware control status register will be updated with the number of 1951 * packets were removed from the hardware queue. 1952 * 1953 * The RCR ring lock is held when entering this function. 1954 */ 1955 static mblk_t * 1956 nxge_rx_pkts(p_nxge_t nxgep, p_rx_rcr_ring_t rcr_p, rx_dma_ctl_stat_t cs, 1957 int bytes_to_pickup) 1958 { 1959 npi_handle_t handle; 1960 uint8_t channel; 1961 uint32_t comp_rd_index; 1962 p_rcr_entry_t rcr_desc_rd_head_p; 1963 p_rcr_entry_t rcr_desc_rd_head_pp; 1964 p_mblk_t nmp, mp_cont, head_mp, *tail_mp; 1965 uint16_t qlen, nrcr_read, npkt_read; 1966 uint32_t qlen_hw; 1967 boolean_t multi; 1968 rcrcfig_b_t rcr_cfg_b; 1969 int totallen = 0; 1970 #if defined(_BIG_ENDIAN) 1971 npi_status_t rs = NPI_SUCCESS; 1972 #endif 1973 1974 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, "==> nxge_rx_pkts: " 1975 "channel %d", rcr_p->rdc)); 1976 1977 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 1978 return (NULL); 1979 } 1980 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1981 channel = rcr_p->rdc; 1982 1983 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1984 "==> nxge_rx_pkts: START: rcr channel %d " 1985 "head_p $%p head_pp $%p index %d ", 1986 channel, rcr_p->rcr_desc_rd_head_p, 1987 rcr_p->rcr_desc_rd_head_pp, 1988 rcr_p->comp_rd_index)); 1989 1990 1991 #if !defined(_BIG_ENDIAN) 1992 qlen = RXDMA_REG_READ32(handle, RCRSTAT_A_REG, channel) & 0xffff; 1993 #else 1994 rs = npi_rxdma_rdc_rcr_qlen_get(handle, channel, &qlen); 1995 if (rs != NPI_SUCCESS) { 1996 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts: " 1997 "channel %d, get qlen failed 0x%08x", 1998 channel, rs)); 1999 return (NULL); 2000 } 2001 #endif 2002 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts:rcr channel %d " 2003 "qlen %d", channel, qlen)); 2004 2005 2006 2007 if (!qlen) { 2008 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 2009 "==> nxge_rx_pkts:rcr channel %d " 2010 "qlen %d (no pkts)", channel, qlen)); 2011 2012 return (NULL); 2013 } 2014 2015 comp_rd_index = rcr_p->comp_rd_index; 2016 2017 rcr_desc_rd_head_p = rcr_p->rcr_desc_rd_head_p; 2018 rcr_desc_rd_head_pp = rcr_p->rcr_desc_rd_head_pp; 2019 nrcr_read = npkt_read = 0; 2020 2021 /* 2022 * Number of packets queued 2023 * (The jumbo or multi packet will be counted as only one 2024 * packets and it may take up more than one completion entry). 2025 */ 2026 qlen_hw = (qlen < nxge_max_rx_pkts) ? 2027 qlen : nxge_max_rx_pkts; 2028 head_mp = NULL; 2029 tail_mp = &head_mp; 2030 nmp = mp_cont = NULL; 2031 multi = B_FALSE; 2032 2033 while (qlen_hw) { 2034 2035 #ifdef NXGE_DEBUG 2036 nxge_dump_rcr_entry(nxgep, rcr_desc_rd_head_p); 2037 #endif 2038 /* 2039 * Process one completion ring entry. 2040 */ 2041 nxge_receive_packet(nxgep, 2042 rcr_p, rcr_desc_rd_head_p, &multi, &nmp, &mp_cont); 2043 2044 /* 2045 * message chaining modes 2046 */ 2047 if (nmp) { 2048 nmp->b_next = NULL; 2049 if (!multi && !mp_cont) { /* frame fits a partition */ 2050 *tail_mp = nmp; 2051 tail_mp = &nmp->b_next; 2052 totallen += MBLKL(nmp); 2053 nmp = NULL; 2054 } else if (multi && !mp_cont) { /* first segment */ 2055 *tail_mp = nmp; 2056 tail_mp = &nmp->b_cont; 2057 totallen += MBLKL(nmp); 2058 } else if (multi && mp_cont) { /* mid of multi segs */ 2059 *tail_mp = mp_cont; 2060 tail_mp = &mp_cont->b_cont; 2061 totallen += MBLKL(mp_cont); 2062 } else if (!multi && mp_cont) { /* last segment */ 2063 *tail_mp = mp_cont; 2064 tail_mp = &nmp->b_next; 2065 totallen += MBLKL(mp_cont); 2066 nmp = NULL; 2067 } 2068 } 2069 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2070 "==> nxge_rx_pkts: loop: rcr channel %d " 2071 "before updating: multi %d " 2072 "nrcr_read %d " 2073 "npk read %d " 2074 "head_pp $%p index %d ", 2075 channel, 2076 multi, 2077 nrcr_read, npkt_read, rcr_desc_rd_head_pp, 2078 comp_rd_index)); 2079 2080 if (!multi) { 2081 qlen_hw--; 2082 npkt_read++; 2083 } 2084 2085 /* 2086 * Update the next read entry. 2087 */ 2088 comp_rd_index = NEXT_ENTRY(comp_rd_index, 2089 rcr_p->comp_wrap_mask); 2090 2091 rcr_desc_rd_head_p = NEXT_ENTRY_PTR(rcr_desc_rd_head_p, 2092 rcr_p->rcr_desc_first_p, 2093 rcr_p->rcr_desc_last_p); 2094 2095 nrcr_read++; 2096 2097 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2098 "<== nxge_rx_pkts: (SAM, process one packet) " 2099 "nrcr_read %d", 2100 nrcr_read)); 2101 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2102 "==> nxge_rx_pkts: loop: rcr channel %d " 2103 "multi %d " 2104 "nrcr_read %d " 2105 "npk read %d " 2106 "head_pp $%p index %d ", 2107 channel, 2108 multi, 2109 nrcr_read, npkt_read, rcr_desc_rd_head_pp, 2110 comp_rd_index)); 2111 2112 if ((bytes_to_pickup != -1) && 2113 (totallen >= bytes_to_pickup)) { 2114 break; 2115 } 2116 } 2117 2118 rcr_p->rcr_desc_rd_head_pp = rcr_desc_rd_head_pp; 2119 rcr_p->comp_rd_index = comp_rd_index; 2120 rcr_p->rcr_desc_rd_head_p = rcr_desc_rd_head_p; 2121 if ((nxgep->intr_timeout != rcr_p->intr_timeout) || 2122 (nxgep->intr_threshold != rcr_p->intr_threshold)) { 2123 2124 rcr_p->intr_timeout = (nxgep->intr_timeout < 2125 NXGE_RDC_RCR_TIMEOUT_MIN) ? NXGE_RDC_RCR_TIMEOUT_MIN : 2126 nxgep->intr_timeout; 2127 2128 rcr_p->intr_threshold = (nxgep->intr_threshold < 2129 NXGE_RDC_RCR_THRESHOLD_MIN) ? NXGE_RDC_RCR_THRESHOLD_MIN : 2130 nxgep->intr_threshold; 2131 2132 rcr_cfg_b.value = 0x0ULL; 2133 rcr_cfg_b.bits.ldw.entout = 1; 2134 rcr_cfg_b.bits.ldw.timeout = rcr_p->intr_timeout; 2135 rcr_cfg_b.bits.ldw.pthres = rcr_p->intr_threshold; 2136 2137 RXDMA_REG_WRITE64(handle, RCRCFIG_B_REG, 2138 channel, rcr_cfg_b.value); 2139 } 2140 2141 cs.bits.ldw.pktread = npkt_read; 2142 cs.bits.ldw.ptrread = nrcr_read; 2143 RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, 2144 channel, cs.value); 2145 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2146 "==> nxge_rx_pkts: EXIT: rcr channel %d " 2147 "head_pp $%p index %016llx ", 2148 channel, 2149 rcr_p->rcr_desc_rd_head_pp, 2150 rcr_p->comp_rd_index)); 2151 /* 2152 * Update RCR buffer pointer read and number of packets 2153 * read. 2154 */ 2155 2156 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_rx_pkts: return" 2157 "channel %d", rcr_p->rdc)); 2158 2159 return (head_mp); 2160 } 2161 2162 void 2163 nxge_receive_packet(p_nxge_t nxgep, 2164 p_rx_rcr_ring_t rcr_p, p_rcr_entry_t rcr_desc_rd_head_p, 2165 boolean_t *multi_p, mblk_t **mp, mblk_t **mp_cont) 2166 { 2167 p_mblk_t nmp = NULL; 2168 uint64_t multi; 2169 uint64_t dcf_err; 2170 uint8_t channel; 2171 2172 boolean_t first_entry = B_TRUE; 2173 boolean_t is_tcp_udp = B_FALSE; 2174 boolean_t buffer_free = B_FALSE; 2175 boolean_t error_send_up = B_FALSE; 2176 uint8_t error_type; 2177 uint16_t l2_len; 2178 uint16_t skip_len; 2179 uint8_t pktbufsz_type; 2180 uint64_t rcr_entry; 2181 uint64_t *pkt_buf_addr_pp; 2182 uint64_t *pkt_buf_addr_p; 2183 uint32_t buf_offset; 2184 uint32_t bsize; 2185 uint32_t error_disp_cnt; 2186 uint32_t msg_index; 2187 p_rx_rbr_ring_t rx_rbr_p; 2188 p_rx_msg_t *rx_msg_ring_p; 2189 p_rx_msg_t rx_msg_p; 2190 uint16_t sw_offset_bytes = 0, hdr_size = 0; 2191 nxge_status_t status = NXGE_OK; 2192 boolean_t is_valid = B_FALSE; 2193 p_nxge_rx_ring_stats_t rdc_stats; 2194 uint32_t bytes_read; 2195 uint64_t pkt_type; 2196 uint64_t frag; 2197 boolean_t pkt_too_long_err = B_FALSE; 2198 #ifdef NXGE_DEBUG 2199 int dump_len; 2200 #endif 2201 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> nxge_receive_packet")); 2202 first_entry = (*mp == NULL) ? B_TRUE : B_FALSE; 2203 2204 rcr_entry = *((uint64_t *)rcr_desc_rd_head_p); 2205 2206 multi = (rcr_entry & RCR_MULTI_MASK); 2207 dcf_err = (rcr_entry & RCR_DCF_ERROR_MASK); 2208 pkt_type = (rcr_entry & RCR_PKT_TYPE_MASK); 2209 2210 error_type = ((rcr_entry & RCR_ERROR_MASK) >> RCR_ERROR_SHIFT); 2211 frag = (rcr_entry & RCR_FRAG_MASK); 2212 2213 l2_len = ((rcr_entry & RCR_L2_LEN_MASK) >> RCR_L2_LEN_SHIFT); 2214 2215 pktbufsz_type = ((rcr_entry & RCR_PKTBUFSZ_MASK) >> 2216 RCR_PKTBUFSZ_SHIFT); 2217 #if defined(__i386) 2218 pkt_buf_addr_pp = (uint64_t *)(uint32_t)((rcr_entry & 2219 RCR_PKT_BUF_ADDR_MASK) << RCR_PKT_BUF_ADDR_SHIFT); 2220 #else 2221 pkt_buf_addr_pp = (uint64_t *)((rcr_entry & RCR_PKT_BUF_ADDR_MASK) << 2222 RCR_PKT_BUF_ADDR_SHIFT); 2223 #endif 2224 2225 channel = rcr_p->rdc; 2226 2227 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2228 "==> nxge_receive_packet: entryp $%p entry 0x%0llx " 2229 "pkt_buf_addr_pp $%p l2_len %d multi 0x%llx " 2230 "error_type 0x%x pkt_type 0x%x " 2231 "pktbufsz_type %d ", 2232 rcr_desc_rd_head_p, 2233 rcr_entry, pkt_buf_addr_pp, l2_len, 2234 multi, 2235 error_type, 2236 pkt_type, 2237 pktbufsz_type)); 2238 2239 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2240 "==> nxge_receive_packet: entryp $%p entry 0x%0llx " 2241 "pkt_buf_addr_pp $%p l2_len %d multi 0x%llx " 2242 "error_type 0x%x pkt_type 0x%x ", rcr_desc_rd_head_p, 2243 rcr_entry, pkt_buf_addr_pp, l2_len, 2244 multi, 2245 error_type, 2246 pkt_type)); 2247 2248 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2249 "==> (rbr) nxge_receive_packet: entry 0x%0llx " 2250 "full pkt_buf_addr_pp $%p l2_len %d", 2251 rcr_entry, pkt_buf_addr_pp, l2_len)); 2252 2253 /* get the stats ptr */ 2254 rdc_stats = rcr_p->rdc_stats; 2255 2256 if (!l2_len) { 2257 2258 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2259 "<== nxge_receive_packet: failed: l2 length is 0.")); 2260 return; 2261 } 2262 2263 /* 2264 * Software workaround for BMAC hardware limitation that allows 2265 * maxframe size of 1526, instead of 1522 for non-jumbo and 0x2406 2266 * instead of 0x2400 for jumbo. 2267 */ 2268 if (l2_len > nxgep->mac.maxframesize) { 2269 pkt_too_long_err = B_TRUE; 2270 } 2271 2272 /* Hardware sends us 4 bytes of CRC as no stripping is done. */ 2273 l2_len -= ETHERFCSL; 2274 2275 /* shift 6 bits to get the full io address */ 2276 #if defined(__i386) 2277 pkt_buf_addr_pp = (uint64_t *)((uint32_t)pkt_buf_addr_pp << 2278 RCR_PKT_BUF_ADDR_SHIFT_FULL); 2279 #else 2280 pkt_buf_addr_pp = (uint64_t *)((uint64_t)pkt_buf_addr_pp << 2281 RCR_PKT_BUF_ADDR_SHIFT_FULL); 2282 #endif 2283 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2284 "==> (rbr) nxge_receive_packet: entry 0x%0llx " 2285 "full pkt_buf_addr_pp $%p l2_len %d", 2286 rcr_entry, pkt_buf_addr_pp, l2_len)); 2287 2288 rx_rbr_p = rcr_p->rx_rbr_p; 2289 rx_msg_ring_p = rx_rbr_p->rx_msg_ring; 2290 2291 if (first_entry) { 2292 hdr_size = (rcr_p->full_hdr_flag ? RXDMA_HDR_SIZE_FULL : 2293 RXDMA_HDR_SIZE_DEFAULT); 2294 2295 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2296 "==> nxge_receive_packet: first entry 0x%016llx " 2297 "pkt_buf_addr_pp $%p l2_len %d hdr %d", 2298 rcr_entry, pkt_buf_addr_pp, l2_len, 2299 hdr_size)); 2300 } 2301 2302 MUTEX_ENTER(&rx_rbr_p->lock); 2303 2304 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2305 "==> (rbr 1) nxge_receive_packet: entry 0x%0llx " 2306 "full pkt_buf_addr_pp $%p l2_len %d", 2307 rcr_entry, pkt_buf_addr_pp, l2_len)); 2308 2309 /* 2310 * Packet buffer address in the completion entry points 2311 * to the starting buffer address (offset 0). 2312 * Use the starting buffer address to locate the corresponding 2313 * kernel address. 2314 */ 2315 status = nxge_rxbuf_pp_to_vp(nxgep, rx_rbr_p, 2316 pktbufsz_type, pkt_buf_addr_pp, &pkt_buf_addr_p, 2317 &buf_offset, 2318 &msg_index); 2319 2320 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2321 "==> (rbr 2) nxge_receive_packet: entry 0x%0llx " 2322 "full pkt_buf_addr_pp $%p l2_len %d", 2323 rcr_entry, pkt_buf_addr_pp, l2_len)); 2324 2325 if (status != NXGE_OK) { 2326 MUTEX_EXIT(&rx_rbr_p->lock); 2327 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2328 "<== nxge_receive_packet: found vaddr failed %d", 2329 status)); 2330 return; 2331 } 2332 2333 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2334 "==> (rbr 3) nxge_receive_packet: entry 0x%0llx " 2335 "full pkt_buf_addr_pp $%p l2_len %d", 2336 rcr_entry, pkt_buf_addr_pp, l2_len)); 2337 2338 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2339 "==> (rbr 4 msgindex %d) nxge_receive_packet: entry 0x%0llx " 2340 "full pkt_buf_addr_pp $%p l2_len %d", 2341 msg_index, rcr_entry, pkt_buf_addr_pp, l2_len)); 2342 2343 rx_msg_p = rx_msg_ring_p[msg_index]; 2344 2345 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2346 "==> (rbr 4 msgindex %d) nxge_receive_packet: entry 0x%0llx " 2347 "full pkt_buf_addr_pp $%p l2_len %d", 2348 msg_index, rcr_entry, pkt_buf_addr_pp, l2_len)); 2349 2350 switch (pktbufsz_type) { 2351 case RCR_PKTBUFSZ_0: 2352 bsize = rx_rbr_p->pkt_buf_size0_bytes; 2353 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2354 "==> nxge_receive_packet: 0 buf %d", bsize)); 2355 break; 2356 case RCR_PKTBUFSZ_1: 2357 bsize = rx_rbr_p->pkt_buf_size1_bytes; 2358 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2359 "==> nxge_receive_packet: 1 buf %d", bsize)); 2360 break; 2361 case RCR_PKTBUFSZ_2: 2362 bsize = rx_rbr_p->pkt_buf_size2_bytes; 2363 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2364 "==> nxge_receive_packet: 2 buf %d", bsize)); 2365 break; 2366 case RCR_SINGLE_BLOCK: 2367 bsize = rx_msg_p->block_size; 2368 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2369 "==> nxge_receive_packet: single %d", bsize)); 2370 2371 break; 2372 default: 2373 MUTEX_EXIT(&rx_rbr_p->lock); 2374 return; 2375 } 2376 2377 DMA_COMMON_SYNC_OFFSET(rx_msg_p->buf_dma, 2378 (buf_offset + sw_offset_bytes), 2379 (hdr_size + l2_len), 2380 DDI_DMA_SYNC_FORCPU); 2381 2382 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2383 "==> nxge_receive_packet: after first dump:usage count")); 2384 2385 if (rx_msg_p->cur_usage_cnt == 0) { 2386 if (rx_rbr_p->rbr_use_bcopy) { 2387 atomic_inc_32(&rx_rbr_p->rbr_consumed); 2388 if (rx_rbr_p->rbr_consumed < 2389 rx_rbr_p->rbr_threshold_hi) { 2390 if (rx_rbr_p->rbr_threshold_lo == 0 || 2391 ((rx_rbr_p->rbr_consumed >= 2392 rx_rbr_p->rbr_threshold_lo) && 2393 (rx_rbr_p->rbr_bufsize_type >= 2394 pktbufsz_type))) { 2395 rx_msg_p->rx_use_bcopy = B_TRUE; 2396 } 2397 } else { 2398 rx_msg_p->rx_use_bcopy = B_TRUE; 2399 } 2400 } 2401 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2402 "==> nxge_receive_packet: buf %d (new block) ", 2403 bsize)); 2404 2405 rx_msg_p->pkt_buf_size_code = pktbufsz_type; 2406 rx_msg_p->pkt_buf_size = bsize; 2407 rx_msg_p->cur_usage_cnt = 1; 2408 if (pktbufsz_type == RCR_SINGLE_BLOCK) { 2409 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2410 "==> nxge_receive_packet: buf %d " 2411 "(single block) ", 2412 bsize)); 2413 /* 2414 * Buffer can be reused once the free function 2415 * is called. 2416 */ 2417 rx_msg_p->max_usage_cnt = 1; 2418 buffer_free = B_TRUE; 2419 } else { 2420 rx_msg_p->max_usage_cnt = rx_msg_p->block_size/bsize; 2421 if (rx_msg_p->max_usage_cnt == 1) { 2422 buffer_free = B_TRUE; 2423 } 2424 } 2425 } else { 2426 rx_msg_p->cur_usage_cnt++; 2427 if (rx_msg_p->cur_usage_cnt == rx_msg_p->max_usage_cnt) { 2428 buffer_free = B_TRUE; 2429 } 2430 } 2431 2432 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2433 "msgbuf index = %d l2len %d bytes usage %d max_usage %d ", 2434 msg_index, l2_len, 2435 rx_msg_p->cur_usage_cnt, rx_msg_p->max_usage_cnt)); 2436 2437 if ((error_type) || (dcf_err) || (pkt_too_long_err)) { 2438 rdc_stats->ierrors++; 2439 if (dcf_err) { 2440 rdc_stats->dcf_err++; 2441 #ifdef NXGE_DEBUG 2442 if (!rdc_stats->dcf_err) { 2443 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2444 "nxge_receive_packet: channel %d dcf_err rcr" 2445 " 0x%llx", channel, rcr_entry)); 2446 } 2447 #endif 2448 NXGE_FM_REPORT_ERROR(nxgep, nxgep->mac.portnum, NULL, 2449 NXGE_FM_EREPORT_RDMC_DCF_ERR); 2450 } else if (pkt_too_long_err) { 2451 rdc_stats->pkt_too_long_err++; 2452 NXGE_DEBUG_MSG((nxgep, RX_CTL, " nxge_receive_packet:" 2453 " channel %d packet length [%d] > " 2454 "maxframesize [%d]", channel, l2_len + ETHERFCSL, 2455 nxgep->mac.maxframesize)); 2456 } else { 2457 /* Update error stats */ 2458 error_disp_cnt = NXGE_ERROR_SHOW_MAX; 2459 rdc_stats->errlog.compl_err_type = error_type; 2460 2461 switch (error_type) { 2462 /* 2463 * Do not send FMA ereport for RCR_L2_ERROR and 2464 * RCR_L4_CSUM_ERROR because most likely they indicate 2465 * back pressure rather than HW failures. 2466 */ 2467 case RCR_L2_ERROR: 2468 rdc_stats->l2_err++; 2469 if (rdc_stats->l2_err < 2470 error_disp_cnt) { 2471 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2472 " nxge_receive_packet:" 2473 " channel %d RCR L2_ERROR", 2474 channel)); 2475 } 2476 break; 2477 case RCR_L4_CSUM_ERROR: 2478 error_send_up = B_TRUE; 2479 rdc_stats->l4_cksum_err++; 2480 if (rdc_stats->l4_cksum_err < 2481 error_disp_cnt) { 2482 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2483 " nxge_receive_packet:" 2484 " channel %d" 2485 " RCR L4_CSUM_ERROR", channel)); 2486 } 2487 break; 2488 /* 2489 * Do not send FMA ereport for RCR_FFLP_SOFT_ERROR and 2490 * RCR_ZCP_SOFT_ERROR because they reflect the same 2491 * FFLP and ZCP errors that have been reported by 2492 * nxge_fflp.c and nxge_zcp.c. 2493 */ 2494 case RCR_FFLP_SOFT_ERROR: 2495 error_send_up = B_TRUE; 2496 rdc_stats->fflp_soft_err++; 2497 if (rdc_stats->fflp_soft_err < 2498 error_disp_cnt) { 2499 NXGE_ERROR_MSG((nxgep, 2500 NXGE_ERR_CTL, 2501 " nxge_receive_packet:" 2502 " channel %d" 2503 " RCR FFLP_SOFT_ERROR", channel)); 2504 } 2505 break; 2506 case RCR_ZCP_SOFT_ERROR: 2507 error_send_up = B_TRUE; 2508 rdc_stats->fflp_soft_err++; 2509 if (rdc_stats->zcp_soft_err < 2510 error_disp_cnt) 2511 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2512 " nxge_receive_packet: Channel %d" 2513 " RCR ZCP_SOFT_ERROR", channel)); 2514 break; 2515 default: 2516 rdc_stats->rcr_unknown_err++; 2517 if (rdc_stats->rcr_unknown_err 2518 < error_disp_cnt) { 2519 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2520 " nxge_receive_packet: Channel %d" 2521 " RCR entry 0x%llx error 0x%x", 2522 rcr_entry, channel, error_type)); 2523 } 2524 break; 2525 } 2526 } 2527 2528 /* 2529 * Update and repost buffer block if max usage 2530 * count is reached. 2531 */ 2532 if (error_send_up == B_FALSE) { 2533 atomic_inc_32(&rx_msg_p->ref_cnt); 2534 if (buffer_free == B_TRUE) { 2535 rx_msg_p->free = B_TRUE; 2536 } 2537 2538 MUTEX_EXIT(&rx_rbr_p->lock); 2539 nxge_freeb(rx_msg_p); 2540 return; 2541 } 2542 } 2543 2544 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2545 "==> nxge_receive_packet: DMA sync second ")); 2546 2547 bytes_read = rcr_p->rcvd_pkt_bytes; 2548 skip_len = sw_offset_bytes + hdr_size; 2549 if (!rx_msg_p->rx_use_bcopy) { 2550 /* 2551 * For loaned up buffers, the driver reference count 2552 * will be incremented first and then the free state. 2553 */ 2554 if ((nmp = nxge_dupb(rx_msg_p, buf_offset, bsize)) != NULL) { 2555 if (first_entry) { 2556 nmp->b_rptr = &nmp->b_rptr[skip_len]; 2557 if (l2_len < bsize - skip_len) { 2558 nmp->b_wptr = &nmp->b_rptr[l2_len]; 2559 } else { 2560 nmp->b_wptr = &nmp->b_rptr[bsize 2561 - skip_len]; 2562 } 2563 } else { 2564 if (l2_len - bytes_read < bsize) { 2565 nmp->b_wptr = 2566 &nmp->b_rptr[l2_len - bytes_read]; 2567 } else { 2568 nmp->b_wptr = &nmp->b_rptr[bsize]; 2569 } 2570 } 2571 } 2572 } else { 2573 if (first_entry) { 2574 nmp = nxge_dupb_bcopy(rx_msg_p, buf_offset + skip_len, 2575 l2_len < bsize - skip_len ? 2576 l2_len : bsize - skip_len); 2577 } else { 2578 nmp = nxge_dupb_bcopy(rx_msg_p, buf_offset, 2579 l2_len - bytes_read < bsize ? 2580 l2_len - bytes_read : bsize); 2581 } 2582 } 2583 if (nmp != NULL) { 2584 if (first_entry) { 2585 /* 2586 * Jumbo packets may be received with more than one 2587 * buffer, increment ipackets for the first entry only. 2588 */ 2589 rdc_stats->ipackets++; 2590 2591 /* Update ibytes for kstat. */ 2592 rdc_stats->ibytes += skip_len 2593 + l2_len < bsize ? l2_len : bsize; 2594 /* 2595 * Update the number of bytes read so far for the 2596 * current frame. 2597 */ 2598 bytes_read = nmp->b_wptr - nmp->b_rptr; 2599 } else { 2600 rdc_stats->ibytes += l2_len - bytes_read < bsize ? 2601 l2_len - bytes_read : bsize; 2602 bytes_read += nmp->b_wptr - nmp->b_rptr; 2603 } 2604 2605 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2606 "==> nxge_receive_packet after dupb: " 2607 "rbr consumed %d " 2608 "pktbufsz_type %d " 2609 "nmp $%p rptr $%p wptr $%p " 2610 "buf_offset %d bzise %d l2_len %d skip_len %d", 2611 rx_rbr_p->rbr_consumed, 2612 pktbufsz_type, 2613 nmp, nmp->b_rptr, nmp->b_wptr, 2614 buf_offset, bsize, l2_len, skip_len)); 2615 } else { 2616 cmn_err(CE_WARN, "!nxge_receive_packet: " 2617 "update stats (error)"); 2618 atomic_inc_32(&rx_msg_p->ref_cnt); 2619 if (buffer_free == B_TRUE) { 2620 rx_msg_p->free = B_TRUE; 2621 } 2622 MUTEX_EXIT(&rx_rbr_p->lock); 2623 nxge_freeb(rx_msg_p); 2624 return; 2625 } 2626 2627 if (buffer_free == B_TRUE) { 2628 rx_msg_p->free = B_TRUE; 2629 } 2630 2631 is_valid = (nmp != NULL); 2632 2633 rcr_p->rcvd_pkt_bytes = bytes_read; 2634 2635 MUTEX_EXIT(&rx_rbr_p->lock); 2636 2637 if (rx_msg_p->free && rx_msg_p->rx_use_bcopy) { 2638 atomic_inc_32(&rx_msg_p->ref_cnt); 2639 nxge_freeb(rx_msg_p); 2640 } 2641 2642 if (is_valid) { 2643 nmp->b_cont = NULL; 2644 if (first_entry) { 2645 *mp = nmp; 2646 *mp_cont = NULL; 2647 } else { 2648 *mp_cont = nmp; 2649 } 2650 } 2651 2652 /* 2653 * ERROR, FRAG and PKT_TYPE are only reported in the first entry. 2654 * If a packet is not fragmented and no error bit is set, then 2655 * L4 checksum is OK. 2656 */ 2657 2658 if (is_valid && !multi) { 2659 /* 2660 * If the checksum flag nxge_chksum_offload 2661 * is 1, TCP and UDP packets can be sent 2662 * up with good checksum. If the checksum flag 2663 * is set to 0, checksum reporting will apply to 2664 * TCP packets only (workaround for a hardware bug). 2665 * If the checksum flag nxge_cksum_offload is 2666 * greater than 1, both TCP and UDP packets 2667 * will not be reported its hardware checksum results. 2668 */ 2669 if (nxge_cksum_offload == 1) { 2670 is_tcp_udp = ((pkt_type == RCR_PKT_IS_TCP || 2671 pkt_type == RCR_PKT_IS_UDP) ? 2672 B_TRUE: B_FALSE); 2673 } else if (!nxge_cksum_offload) { 2674 /* TCP checksum only. */ 2675 is_tcp_udp = ((pkt_type == RCR_PKT_IS_TCP) ? 2676 B_TRUE: B_FALSE); 2677 } 2678 2679 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_receive_packet: " 2680 "is_valid 0x%x multi 0x%llx pkt %d frag %d error %d", 2681 is_valid, multi, is_tcp_udp, frag, error_type)); 2682 2683 if (is_tcp_udp && !frag && !error_type) { 2684 (void) hcksum_assoc(nmp, NULL, NULL, 0, 0, 0, 0, 2685 HCK_FULLCKSUM_OK | HCK_FULLCKSUM, 0); 2686 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2687 "==> nxge_receive_packet: Full tcp/udp cksum " 2688 "is_valid 0x%x multi 0x%llx pkt %d frag %d " 2689 "error %d", 2690 is_valid, multi, is_tcp_udp, frag, error_type)); 2691 } 2692 } 2693 2694 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2695 "==> nxge_receive_packet: *mp 0x%016llx", *mp)); 2696 2697 *multi_p = (multi == RCR_MULTI_MASK); 2698 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_receive_packet: " 2699 "multi %d nmp 0x%016llx *mp 0x%016llx *mp_cont 0x%016llx", 2700 *multi_p, nmp, *mp, *mp_cont)); 2701 } 2702 2703 /* 2704 * Enable polling for a ring. Interrupt for the ring is disabled when 2705 * the nxge interrupt comes (see nxge_rx_intr). 2706 */ 2707 int 2708 nxge_enable_poll(void *arg) 2709 { 2710 p_nxge_ring_handle_t ring_handle = (p_nxge_ring_handle_t)arg; 2711 p_rx_rcr_ring_t ringp; 2712 p_nxge_t nxgep; 2713 p_nxge_ldg_t ldgp; 2714 uint32_t channel; 2715 2716 if (ring_handle == NULL) { 2717 ASSERT(ring_handle != NULL); 2718 return (0); 2719 } 2720 2721 nxgep = ring_handle->nxgep; 2722 channel = nxgep->pt_config.hw_config.start_rdc + ring_handle->index; 2723 ringp = nxgep->rx_rcr_rings->rcr_rings[channel]; 2724 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 2725 "==> nxge_enable_poll: rdc %d ", ringp->rdc)); 2726 ldgp = ringp->ldgp; 2727 if (ldgp == NULL) { 2728 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 2729 "==> nxge_enable_poll: rdc %d NULL ldgp: no change", 2730 ringp->rdc)); 2731 return (0); 2732 } 2733 2734 MUTEX_ENTER(&ringp->lock); 2735 /* enable polling */ 2736 if (ringp->poll_flag == 0) { 2737 ringp->poll_flag = 1; 2738 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 2739 "==> nxge_enable_poll: rdc %d set poll flag to 1", 2740 ringp->rdc)); 2741 } 2742 2743 MUTEX_EXIT(&ringp->lock); 2744 return (0); 2745 } 2746 /* 2747 * Disable polling for a ring and enable its interrupt. 2748 */ 2749 int 2750 nxge_disable_poll(void *arg) 2751 { 2752 p_nxge_ring_handle_t ring_handle = (p_nxge_ring_handle_t)arg; 2753 p_rx_rcr_ring_t ringp; 2754 p_nxge_t nxgep; 2755 uint32_t channel; 2756 2757 if (ring_handle == NULL) { 2758 ASSERT(ring_handle != NULL); 2759 return (0); 2760 } 2761 2762 nxgep = ring_handle->nxgep; 2763 channel = nxgep->pt_config.hw_config.start_rdc + ring_handle->index; 2764 ringp = nxgep->rx_rcr_rings->rcr_rings[channel]; 2765 2766 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 2767 "==> nxge_disable_poll: rdc %d poll_flag %d", ringp->rdc)); 2768 2769 MUTEX_ENTER(&ringp->lock); 2770 2771 /* disable polling: enable interrupt */ 2772 if (ringp->poll_flag) { 2773 npi_handle_t handle; 2774 rx_dma_ctl_stat_t cs; 2775 uint8_t channel; 2776 p_nxge_ldg_t ldgp; 2777 2778 /* 2779 * Get the control and status for this channel. 2780 */ 2781 handle = NXGE_DEV_NPI_HANDLE(nxgep); 2782 channel = ringp->rdc; 2783 RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, 2784 channel, &cs.value); 2785 2786 /* 2787 * Enable mailbox update 2788 * Since packets were not read and the hardware uses 2789 * bits pktread and ptrread to update the queue 2790 * length, we need to set both bits to 0. 2791 */ 2792 cs.bits.ldw.pktread = 0; 2793 cs.bits.ldw.ptrread = 0; 2794 cs.bits.hdw.mex = 1; 2795 RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, channel, 2796 cs.value); 2797 2798 /* 2799 * Rearm this logical group if this is a single device 2800 * group. 2801 */ 2802 ldgp = ringp->ldgp; 2803 if (ldgp == NULL) { 2804 ringp->poll_flag = 0; 2805 MUTEX_EXIT(&ringp->lock); 2806 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 2807 "==> nxge_disable_poll: no ldgp rdc %d " 2808 "(still set poll to 0", ringp->rdc)); 2809 return (0); 2810 } 2811 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 2812 "==> nxge_disable_poll: rdc %d ldgp $%p (enable intr)", 2813 ringp->rdc, ldgp)); 2814 if (ldgp->nldvs == 1) { 2815 if (isLDOMguest(nxgep)) { 2816 ldgp->arm = B_TRUE; 2817 nxge_hio_ldgimgn(nxgep, ldgp); 2818 } else { 2819 ldgimgm_t mgm; 2820 mgm.value = 0; 2821 mgm.bits.ldw.arm = 1; 2822 mgm.bits.ldw.timer = ldgp->ldg_timer; 2823 NXGE_REG_WR64(handle, 2824 LDGIMGN_REG + LDSV_OFFSET(ldgp->ldg), 2825 mgm.value); 2826 } 2827 } 2828 ringp->poll_flag = 0; 2829 } 2830 2831 MUTEX_EXIT(&ringp->lock); 2832 return (0); 2833 } 2834 2835 /* 2836 * Poll 'bytes_to_pickup' bytes of message from the rx ring. 2837 */ 2838 mblk_t * 2839 nxge_rx_poll(void *arg, int bytes_to_pickup) 2840 { 2841 p_nxge_ring_handle_t ring_handle = (p_nxge_ring_handle_t)arg; 2842 p_rx_rcr_ring_t rcr_p; 2843 p_nxge_t nxgep; 2844 npi_handle_t handle; 2845 rx_dma_ctl_stat_t cs; 2846 mblk_t *mblk; 2847 p_nxge_ldv_t ldvp; 2848 uint32_t channel; 2849 2850 nxgep = ring_handle->nxgep; 2851 2852 /* 2853 * Get the control and status for this channel. 2854 */ 2855 handle = NXGE_DEV_NPI_HANDLE(nxgep); 2856 channel = nxgep->pt_config.hw_config.start_rdc + ring_handle->index; 2857 rcr_p = nxgep->rx_rcr_rings->rcr_rings[channel]; 2858 MUTEX_ENTER(&rcr_p->lock); 2859 ASSERT(rcr_p->poll_flag == 1); 2860 2861 RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, rcr_p->rdc, &cs.value); 2862 2863 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 2864 "==> nxge_rx_poll: calling nxge_rx_pkts: rdc %d poll_flag %d", 2865 rcr_p->rdc, rcr_p->poll_flag)); 2866 mblk = nxge_rx_pkts(nxgep, rcr_p, cs, bytes_to_pickup); 2867 2868 ldvp = rcr_p->ldvp; 2869 /* error events. */ 2870 if (ldvp && (cs.value & RX_DMA_CTL_STAT_ERROR)) { 2871 (void) nxge_rx_err_evnts(nxgep, ldvp->vdma_index, cs); 2872 } 2873 2874 MUTEX_EXIT(&rcr_p->lock); 2875 2876 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 2877 "<== nxge_rx_poll: rdc %d mblk $%p", rcr_p->rdc, mblk)); 2878 return (mblk); 2879 } 2880 2881 2882 /*ARGSUSED*/ 2883 static nxge_status_t 2884 nxge_rx_err_evnts(p_nxge_t nxgep, int channel, rx_dma_ctl_stat_t cs) 2885 { 2886 p_nxge_rx_ring_stats_t rdc_stats; 2887 npi_handle_t handle; 2888 npi_status_t rs; 2889 boolean_t rxchan_fatal = B_FALSE; 2890 boolean_t rxport_fatal = B_FALSE; 2891 uint8_t portn; 2892 nxge_status_t status = NXGE_OK; 2893 uint32_t error_disp_cnt = NXGE_ERROR_SHOW_MAX; 2894 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_rx_err_evnts")); 2895 2896 handle = NXGE_DEV_NPI_HANDLE(nxgep); 2897 portn = nxgep->mac.portnum; 2898 rdc_stats = &nxgep->statsp->rdc_stats[channel]; 2899 2900 if (cs.bits.hdw.rbr_tmout) { 2901 rdc_stats->rx_rbr_tmout++; 2902 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2903 NXGE_FM_EREPORT_RDMC_RBR_TMOUT); 2904 rxchan_fatal = B_TRUE; 2905 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2906 "==> nxge_rx_err_evnts: rx_rbr_timeout")); 2907 } 2908 if (cs.bits.hdw.rsp_cnt_err) { 2909 rdc_stats->rsp_cnt_err++; 2910 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2911 NXGE_FM_EREPORT_RDMC_RSP_CNT_ERR); 2912 rxchan_fatal = B_TRUE; 2913 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2914 "==> nxge_rx_err_evnts(channel %d): " 2915 "rsp_cnt_err", channel)); 2916 } 2917 if (cs.bits.hdw.byte_en_bus) { 2918 rdc_stats->byte_en_bus++; 2919 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2920 NXGE_FM_EREPORT_RDMC_BYTE_EN_BUS); 2921 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2922 "==> nxge_rx_err_evnts(channel %d): " 2923 "fatal error: byte_en_bus", channel)); 2924 rxchan_fatal = B_TRUE; 2925 } 2926 if (cs.bits.hdw.rsp_dat_err) { 2927 rdc_stats->rsp_dat_err++; 2928 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2929 NXGE_FM_EREPORT_RDMC_RSP_DAT_ERR); 2930 rxchan_fatal = B_TRUE; 2931 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2932 "==> nxge_rx_err_evnts(channel %d): " 2933 "fatal error: rsp_dat_err", channel)); 2934 } 2935 if (cs.bits.hdw.rcr_ack_err) { 2936 rdc_stats->rcr_ack_err++; 2937 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2938 NXGE_FM_EREPORT_RDMC_RCR_ACK_ERR); 2939 rxchan_fatal = B_TRUE; 2940 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2941 "==> nxge_rx_err_evnts(channel %d): " 2942 "fatal error: rcr_ack_err", channel)); 2943 } 2944 if (cs.bits.hdw.dc_fifo_err) { 2945 rdc_stats->dc_fifo_err++; 2946 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2947 NXGE_FM_EREPORT_RDMC_DC_FIFO_ERR); 2948 /* This is not a fatal error! */ 2949 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2950 "==> nxge_rx_err_evnts(channel %d): " 2951 "dc_fifo_err", channel)); 2952 rxport_fatal = B_TRUE; 2953 } 2954 if ((cs.bits.hdw.rcr_sha_par) || (cs.bits.hdw.rbr_pre_par)) { 2955 if ((rs = npi_rxdma_ring_perr_stat_get(handle, 2956 &rdc_stats->errlog.pre_par, 2957 &rdc_stats->errlog.sha_par)) 2958 != NPI_SUCCESS) { 2959 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2960 "==> nxge_rx_err_evnts(channel %d): " 2961 "rcr_sha_par: get perr", channel)); 2962 return (NXGE_ERROR | rs); 2963 } 2964 if (cs.bits.hdw.rcr_sha_par) { 2965 rdc_stats->rcr_sha_par++; 2966 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2967 NXGE_FM_EREPORT_RDMC_RCR_SHA_PAR); 2968 rxchan_fatal = B_TRUE; 2969 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2970 "==> nxge_rx_err_evnts(channel %d): " 2971 "fatal error: rcr_sha_par", channel)); 2972 } 2973 if (cs.bits.hdw.rbr_pre_par) { 2974 rdc_stats->rbr_pre_par++; 2975 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2976 NXGE_FM_EREPORT_RDMC_RBR_PRE_PAR); 2977 rxchan_fatal = B_TRUE; 2978 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2979 "==> nxge_rx_err_evnts(channel %d): " 2980 "fatal error: rbr_pre_par", channel)); 2981 } 2982 } 2983 /* 2984 * The Following 4 status bits are for information, the system 2985 * is running fine. There is no need to send FMA ereports or 2986 * log messages. 2987 */ 2988 if (cs.bits.hdw.port_drop_pkt) { 2989 rdc_stats->port_drop_pkt++; 2990 } 2991 if (cs.bits.hdw.wred_drop) { 2992 rdc_stats->wred_drop++; 2993 } 2994 if (cs.bits.hdw.rbr_pre_empty) { 2995 rdc_stats->rbr_pre_empty++; 2996 } 2997 if (cs.bits.hdw.rcr_shadow_full) { 2998 rdc_stats->rcr_shadow_full++; 2999 } 3000 if (cs.bits.hdw.config_err) { 3001 rdc_stats->config_err++; 3002 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 3003 NXGE_FM_EREPORT_RDMC_CONFIG_ERR); 3004 rxchan_fatal = B_TRUE; 3005 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3006 "==> nxge_rx_err_evnts(channel %d): " 3007 "config error", channel)); 3008 } 3009 if (cs.bits.hdw.rcrincon) { 3010 rdc_stats->rcrincon++; 3011 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 3012 NXGE_FM_EREPORT_RDMC_RCRINCON); 3013 rxchan_fatal = B_TRUE; 3014 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3015 "==> nxge_rx_err_evnts(channel %d): " 3016 "fatal error: rcrincon error", channel)); 3017 } 3018 if (cs.bits.hdw.rcrfull) { 3019 rdc_stats->rcrfull++; 3020 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 3021 NXGE_FM_EREPORT_RDMC_RCRFULL); 3022 rxchan_fatal = B_TRUE; 3023 if (rdc_stats->rcrfull < error_disp_cnt) 3024 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3025 "==> nxge_rx_err_evnts(channel %d): " 3026 "fatal error: rcrfull error", channel)); 3027 } 3028 if (cs.bits.hdw.rbr_empty) { 3029 /* 3030 * This bit is for information, there is no need 3031 * send FMA ereport or log a message. 3032 */ 3033 rdc_stats->rbr_empty++; 3034 } 3035 if (cs.bits.hdw.rbrfull) { 3036 rdc_stats->rbrfull++; 3037 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 3038 NXGE_FM_EREPORT_RDMC_RBRFULL); 3039 rxchan_fatal = B_TRUE; 3040 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3041 "==> nxge_rx_err_evnts(channel %d): " 3042 "fatal error: rbr_full error", channel)); 3043 } 3044 if (cs.bits.hdw.rbrlogpage) { 3045 rdc_stats->rbrlogpage++; 3046 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 3047 NXGE_FM_EREPORT_RDMC_RBRLOGPAGE); 3048 rxchan_fatal = B_TRUE; 3049 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3050 "==> nxge_rx_err_evnts(channel %d): " 3051 "fatal error: rbr logical page error", channel)); 3052 } 3053 if (cs.bits.hdw.cfiglogpage) { 3054 rdc_stats->cfiglogpage++; 3055 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 3056 NXGE_FM_EREPORT_RDMC_CFIGLOGPAGE); 3057 rxchan_fatal = B_TRUE; 3058 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3059 "==> nxge_rx_err_evnts(channel %d): " 3060 "fatal error: cfig logical page error", channel)); 3061 } 3062 3063 if (rxport_fatal) { 3064 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3065 " nxge_rx_err_evnts: fatal error on Port #%d\n", 3066 portn)); 3067 if (isLDOMguest(nxgep)) { 3068 status = NXGE_ERROR; 3069 } else { 3070 status = nxge_ipp_fatal_err_recover(nxgep); 3071 if (status == NXGE_OK) { 3072 FM_SERVICE_RESTORED(nxgep); 3073 } 3074 } 3075 } 3076 3077 if (rxchan_fatal) { 3078 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3079 " nxge_rx_err_evnts: fatal error on Channel #%d\n", 3080 channel)); 3081 if (isLDOMguest(nxgep)) { 3082 status = NXGE_ERROR; 3083 } else { 3084 status = nxge_rxdma_fatal_err_recover(nxgep, channel); 3085 if (status == NXGE_OK) { 3086 FM_SERVICE_RESTORED(nxgep); 3087 } 3088 } 3089 } 3090 3091 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "<== nxge_rx_err_evnts")); 3092 3093 return (status); 3094 } 3095 3096 /* 3097 * nxge_rdc_hvio_setup 3098 * 3099 * This code appears to setup some Hypervisor variables. 3100 * 3101 * Arguments: 3102 * nxgep 3103 * channel 3104 * 3105 * Notes: 3106 * What does NIU_LP_WORKAROUND mean? 3107 * 3108 * NPI/NXGE function calls: 3109 * na 3110 * 3111 * Context: 3112 * Any domain 3113 */ 3114 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 3115 static void 3116 nxge_rdc_hvio_setup( 3117 nxge_t *nxgep, int channel) 3118 { 3119 nxge_dma_common_t *dma_common; 3120 nxge_dma_common_t *dma_control; 3121 rx_rbr_ring_t *ring; 3122 3123 ring = nxgep->rx_rbr_rings->rbr_rings[channel]; 3124 dma_common = nxgep->rx_buf_pool_p->dma_buf_pool_p[channel]; 3125 3126 ring->hv_set = B_FALSE; 3127 3128 ring->hv_rx_buf_base_ioaddr_pp = (uint64_t) 3129 dma_common->orig_ioaddr_pp; 3130 ring->hv_rx_buf_ioaddr_size = (uint64_t) 3131 dma_common->orig_alength; 3132 3133 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_map_rxdma_channel: " 3134 "channel %d data buf base io $%lx ($%p) size 0x%lx (%ld 0x%lx)", 3135 channel, ring->hv_rx_buf_base_ioaddr_pp, 3136 dma_common->ioaddr_pp, ring->hv_rx_buf_ioaddr_size, 3137 dma_common->orig_alength, dma_common->orig_alength)); 3138 3139 dma_control = nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel]; 3140 3141 ring->hv_rx_cntl_base_ioaddr_pp = 3142 (uint64_t)dma_control->orig_ioaddr_pp; 3143 ring->hv_rx_cntl_ioaddr_size = 3144 (uint64_t)dma_control->orig_alength; 3145 3146 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_map_rxdma_channel: " 3147 "channel %d cntl base io $%p ($%p) size 0x%llx (%d 0x%x)", 3148 channel, ring->hv_rx_cntl_base_ioaddr_pp, 3149 dma_control->ioaddr_pp, ring->hv_rx_cntl_ioaddr_size, 3150 dma_control->orig_alength, dma_control->orig_alength)); 3151 } 3152 #endif 3153 3154 /* 3155 * nxge_map_rxdma 3156 * 3157 * Map an RDC into our kernel space. 3158 * 3159 * Arguments: 3160 * nxgep 3161 * channel The channel to map. 3162 * 3163 * Notes: 3164 * 1. Allocate & initialise a memory pool, if necessary. 3165 * 2. Allocate however many receive buffers are required. 3166 * 3. Setup buffers, descriptors, and mailbox. 3167 * 3168 * NPI/NXGE function calls: 3169 * nxge_alloc_rx_mem_pool() 3170 * nxge_alloc_rbb() 3171 * nxge_map_rxdma_channel() 3172 * 3173 * Registers accessed: 3174 * 3175 * Context: 3176 * Any domain 3177 */ 3178 static nxge_status_t 3179 nxge_map_rxdma(p_nxge_t nxgep, int channel) 3180 { 3181 nxge_dma_common_t **data; 3182 nxge_dma_common_t **control; 3183 rx_rbr_ring_t **rbr_ring; 3184 rx_rcr_ring_t **rcr_ring; 3185 rx_mbox_t **mailbox; 3186 uint32_t chunks; 3187 3188 nxge_status_t status; 3189 3190 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_map_rxdma")); 3191 3192 if (!nxgep->rx_buf_pool_p) { 3193 if (nxge_alloc_rx_mem_pool(nxgep) != NXGE_OK) { 3194 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3195 "<== nxge_map_rxdma: buf not allocated")); 3196 return (NXGE_ERROR); 3197 } 3198 } 3199 3200 if (nxge_alloc_rxb(nxgep, channel) != NXGE_OK) 3201 return (NXGE_ERROR); 3202 3203 /* 3204 * Map descriptors from the buffer polls for each dma channel. 3205 */ 3206 3207 /* 3208 * Set up and prepare buffer blocks, descriptors 3209 * and mailbox. 3210 */ 3211 data = &nxgep->rx_buf_pool_p->dma_buf_pool_p[channel]; 3212 rbr_ring = &nxgep->rx_rbr_rings->rbr_rings[channel]; 3213 chunks = nxgep->rx_buf_pool_p->num_chunks[channel]; 3214 3215 control = &nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel]; 3216 rcr_ring = &nxgep->rx_rcr_rings->rcr_rings[channel]; 3217 3218 mailbox = &nxgep->rx_mbox_areas_p->rxmbox_areas[channel]; 3219 3220 status = nxge_map_rxdma_channel(nxgep, channel, data, rbr_ring, 3221 chunks, control, rcr_ring, mailbox); 3222 if (status != NXGE_OK) { 3223 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3224 "==> nxge_map_rxdma: nxge_map_rxdma_channel(%d) " 3225 "returned 0x%x", 3226 channel, status)); 3227 return (status); 3228 } 3229 nxgep->rx_rbr_rings->rbr_rings[channel]->index = (uint16_t)channel; 3230 nxgep->rx_rcr_rings->rcr_rings[channel]->index = (uint16_t)channel; 3231 nxgep->rx_rcr_rings->rcr_rings[channel]->rdc_stats = 3232 &nxgep->statsp->rdc_stats[channel]; 3233 3234 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 3235 if (!isLDOMguest(nxgep)) 3236 nxge_rdc_hvio_setup(nxgep, channel); 3237 #endif 3238 3239 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3240 "<== nxge_map_rxdma: (status 0x%x channel %d)", status, channel)); 3241 3242 return (status); 3243 } 3244 3245 static void 3246 nxge_unmap_rxdma(p_nxge_t nxgep, int channel) 3247 { 3248 rx_rbr_ring_t *rbr_ring; 3249 rx_rcr_ring_t *rcr_ring; 3250 rx_mbox_t *mailbox; 3251 3252 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_unmap_rxdma(%d)", channel)); 3253 3254 if (!nxgep->rx_rbr_rings || !nxgep->rx_rcr_rings || 3255 !nxgep->rx_mbox_areas_p) 3256 return; 3257 3258 rbr_ring = nxgep->rx_rbr_rings->rbr_rings[channel]; 3259 rcr_ring = nxgep->rx_rcr_rings->rcr_rings[channel]; 3260 mailbox = nxgep->rx_mbox_areas_p->rxmbox_areas[channel]; 3261 3262 if (!rbr_ring || !rcr_ring || !mailbox) 3263 return; 3264 3265 (void) nxge_unmap_rxdma_channel( 3266 nxgep, channel, rbr_ring, rcr_ring, mailbox); 3267 3268 nxge_free_rxb(nxgep, channel); 3269 3270 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_unmap_rxdma")); 3271 } 3272 3273 nxge_status_t 3274 nxge_map_rxdma_channel(p_nxge_t nxgep, uint16_t channel, 3275 p_nxge_dma_common_t *dma_buf_p, p_rx_rbr_ring_t *rbr_p, 3276 uint32_t num_chunks, 3277 p_nxge_dma_common_t *dma_cntl_p, p_rx_rcr_ring_t *rcr_p, 3278 p_rx_mbox_t *rx_mbox_p) 3279 { 3280 int status = NXGE_OK; 3281 3282 /* 3283 * Set up and prepare buffer blocks, descriptors 3284 * and mailbox. 3285 */ 3286 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3287 "==> nxge_map_rxdma_channel (channel %d)", channel)); 3288 /* 3289 * Receive buffer blocks 3290 */ 3291 status = nxge_map_rxdma_channel_buf_ring(nxgep, channel, 3292 dma_buf_p, rbr_p, num_chunks); 3293 if (status != NXGE_OK) { 3294 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3295 "==> nxge_map_rxdma_channel (channel %d): " 3296 "map buffer failed 0x%x", channel, status)); 3297 goto nxge_map_rxdma_channel_exit; 3298 } 3299 3300 /* 3301 * Receive block ring, completion ring and mailbox. 3302 */ 3303 status = nxge_map_rxdma_channel_cfg_ring(nxgep, channel, 3304 dma_cntl_p, rbr_p, rcr_p, rx_mbox_p); 3305 if (status != NXGE_OK) { 3306 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3307 "==> nxge_map_rxdma_channel (channel %d): " 3308 "map config failed 0x%x", channel, status)); 3309 goto nxge_map_rxdma_channel_fail2; 3310 } 3311 3312 goto nxge_map_rxdma_channel_exit; 3313 3314 nxge_map_rxdma_channel_fail3: 3315 /* Free rbr, rcr */ 3316 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3317 "==> nxge_map_rxdma_channel: free rbr/rcr " 3318 "(status 0x%x channel %d)", 3319 status, channel)); 3320 nxge_unmap_rxdma_channel_cfg_ring(nxgep, 3321 *rcr_p, *rx_mbox_p); 3322 3323 nxge_map_rxdma_channel_fail2: 3324 /* Free buffer blocks */ 3325 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3326 "==> nxge_map_rxdma_channel: free rx buffers" 3327 "(nxgep 0x%x status 0x%x channel %d)", 3328 nxgep, status, channel)); 3329 nxge_unmap_rxdma_channel_buf_ring(nxgep, *rbr_p); 3330 3331 status = NXGE_ERROR; 3332 3333 nxge_map_rxdma_channel_exit: 3334 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3335 "<== nxge_map_rxdma_channel: " 3336 "(nxgep 0x%x status 0x%x channel %d)", 3337 nxgep, status, channel)); 3338 3339 return (status); 3340 } 3341 3342 /*ARGSUSED*/ 3343 static void 3344 nxge_unmap_rxdma_channel(p_nxge_t nxgep, uint16_t channel, 3345 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p) 3346 { 3347 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3348 "==> nxge_unmap_rxdma_channel (channel %d)", channel)); 3349 3350 /* 3351 * unmap receive block ring, completion ring and mailbox. 3352 */ 3353 (void) nxge_unmap_rxdma_channel_cfg_ring(nxgep, 3354 rcr_p, rx_mbox_p); 3355 3356 /* unmap buffer blocks */ 3357 (void) nxge_unmap_rxdma_channel_buf_ring(nxgep, rbr_p); 3358 3359 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_unmap_rxdma_channel")); 3360 } 3361 3362 /*ARGSUSED*/ 3363 static nxge_status_t 3364 nxge_map_rxdma_channel_cfg_ring(p_nxge_t nxgep, uint16_t dma_channel, 3365 p_nxge_dma_common_t *dma_cntl_p, p_rx_rbr_ring_t *rbr_p, 3366 p_rx_rcr_ring_t *rcr_p, p_rx_mbox_t *rx_mbox_p) 3367 { 3368 p_rx_rbr_ring_t rbrp; 3369 p_rx_rcr_ring_t rcrp; 3370 p_rx_mbox_t mboxp; 3371 p_nxge_dma_common_t cntl_dmap; 3372 p_nxge_dma_common_t dmap; 3373 p_rx_msg_t *rx_msg_ring; 3374 p_rx_msg_t rx_msg_p; 3375 p_rbr_cfig_a_t rcfga_p; 3376 p_rbr_cfig_b_t rcfgb_p; 3377 p_rcrcfig_a_t cfga_p; 3378 p_rcrcfig_b_t cfgb_p; 3379 p_rxdma_cfig1_t cfig1_p; 3380 p_rxdma_cfig2_t cfig2_p; 3381 p_rbr_kick_t kick_p; 3382 uint32_t dmaaddrp; 3383 uint32_t *rbr_vaddrp; 3384 uint32_t bkaddr; 3385 nxge_status_t status = NXGE_OK; 3386 int i; 3387 uint32_t nxge_port_rcr_size; 3388 3389 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3390 "==> nxge_map_rxdma_channel_cfg_ring")); 3391 3392 cntl_dmap = *dma_cntl_p; 3393 3394 /* Map in the receive block ring */ 3395 rbrp = *rbr_p; 3396 dmap = (p_nxge_dma_common_t)&rbrp->rbr_desc; 3397 nxge_setup_dma_common(dmap, cntl_dmap, rbrp->rbb_max, 4); 3398 /* 3399 * Zero out buffer block ring descriptors. 3400 */ 3401 bzero((caddr_t)dmap->kaddrp, dmap->alength); 3402 3403 rcfga_p = &(rbrp->rbr_cfga); 3404 rcfgb_p = &(rbrp->rbr_cfgb); 3405 kick_p = &(rbrp->rbr_kick); 3406 rcfga_p->value = 0; 3407 rcfgb_p->value = 0; 3408 kick_p->value = 0; 3409 rbrp->rbr_addr = dmap->dma_cookie.dmac_laddress; 3410 rcfga_p->value = (rbrp->rbr_addr & 3411 (RBR_CFIG_A_STDADDR_MASK | 3412 RBR_CFIG_A_STDADDR_BASE_MASK)); 3413 rcfga_p->value |= ((uint64_t)rbrp->rbb_max << RBR_CFIG_A_LEN_SHIFT); 3414 3415 rcfgb_p->bits.ldw.bufsz0 = rbrp->pkt_buf_size0; 3416 rcfgb_p->bits.ldw.vld0 = 1; 3417 rcfgb_p->bits.ldw.bufsz1 = rbrp->pkt_buf_size1; 3418 rcfgb_p->bits.ldw.vld1 = 1; 3419 rcfgb_p->bits.ldw.bufsz2 = rbrp->pkt_buf_size2; 3420 rcfgb_p->bits.ldw.vld2 = 1; 3421 rcfgb_p->bits.ldw.bksize = nxgep->rx_bksize_code; 3422 3423 /* 3424 * For each buffer block, enter receive block address to the ring. 3425 */ 3426 rbr_vaddrp = (uint32_t *)dmap->kaddrp; 3427 rbrp->rbr_desc_vp = (uint32_t *)dmap->kaddrp; 3428 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3429 "==> nxge_map_rxdma_channel_cfg_ring: channel %d " 3430 "rbr_vaddrp $%p", dma_channel, rbr_vaddrp)); 3431 3432 rx_msg_ring = rbrp->rx_msg_ring; 3433 for (i = 0; i < rbrp->tnblocks; i++) { 3434 rx_msg_p = rx_msg_ring[i]; 3435 rx_msg_p->nxgep = nxgep; 3436 rx_msg_p->rx_rbr_p = rbrp; 3437 bkaddr = (uint32_t) 3438 ((rx_msg_p->buf_dma.dma_cookie.dmac_laddress 3439 >> RBR_BKADDR_SHIFT)); 3440 rx_msg_p->free = B_FALSE; 3441 rx_msg_p->max_usage_cnt = 0xbaddcafe; 3442 3443 *rbr_vaddrp++ = bkaddr; 3444 } 3445 3446 kick_p->bits.ldw.bkadd = rbrp->rbb_max; 3447 rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 3448 3449 rbrp->rbr_rd_index = 0; 3450 3451 rbrp->rbr_consumed = 0; 3452 rbrp->rbr_use_bcopy = B_TRUE; 3453 rbrp->rbr_bufsize_type = RCR_PKTBUFSZ_0; 3454 /* 3455 * Do bcopy on packets greater than bcopy size once 3456 * the lo threshold is reached. 3457 * This lo threshold should be less than the hi threshold. 3458 * 3459 * Do bcopy on every packet once the hi threshold is reached. 3460 */ 3461 if (nxge_rx_threshold_lo >= nxge_rx_threshold_hi) { 3462 /* default it to use hi */ 3463 nxge_rx_threshold_lo = nxge_rx_threshold_hi; 3464 } 3465 3466 if (nxge_rx_buf_size_type > NXGE_RBR_TYPE2) { 3467 nxge_rx_buf_size_type = NXGE_RBR_TYPE2; 3468 } 3469 rbrp->rbr_bufsize_type = nxge_rx_buf_size_type; 3470 3471 switch (nxge_rx_threshold_hi) { 3472 default: 3473 case NXGE_RX_COPY_NONE: 3474 /* Do not do bcopy at all */ 3475 rbrp->rbr_use_bcopy = B_FALSE; 3476 rbrp->rbr_threshold_hi = rbrp->rbb_max; 3477 break; 3478 3479 case NXGE_RX_COPY_1: 3480 case NXGE_RX_COPY_2: 3481 case NXGE_RX_COPY_3: 3482 case NXGE_RX_COPY_4: 3483 case NXGE_RX_COPY_5: 3484 case NXGE_RX_COPY_6: 3485 case NXGE_RX_COPY_7: 3486 rbrp->rbr_threshold_hi = 3487 rbrp->rbb_max * 3488 (nxge_rx_threshold_hi)/NXGE_RX_BCOPY_SCALE; 3489 break; 3490 3491 case NXGE_RX_COPY_ALL: 3492 rbrp->rbr_threshold_hi = 0; 3493 break; 3494 } 3495 3496 switch (nxge_rx_threshold_lo) { 3497 default: 3498 case NXGE_RX_COPY_NONE: 3499 /* Do not do bcopy at all */ 3500 if (rbrp->rbr_use_bcopy) { 3501 rbrp->rbr_use_bcopy = B_FALSE; 3502 } 3503 rbrp->rbr_threshold_lo = rbrp->rbb_max; 3504 break; 3505 3506 case NXGE_RX_COPY_1: 3507 case NXGE_RX_COPY_2: 3508 case NXGE_RX_COPY_3: 3509 case NXGE_RX_COPY_4: 3510 case NXGE_RX_COPY_5: 3511 case NXGE_RX_COPY_6: 3512 case NXGE_RX_COPY_7: 3513 rbrp->rbr_threshold_lo = 3514 rbrp->rbb_max * 3515 (nxge_rx_threshold_lo)/NXGE_RX_BCOPY_SCALE; 3516 break; 3517 3518 case NXGE_RX_COPY_ALL: 3519 rbrp->rbr_threshold_lo = 0; 3520 break; 3521 } 3522 3523 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3524 "nxge_map_rxdma_channel_cfg_ring: channel %d " 3525 "rbb_max %d " 3526 "rbrp->rbr_bufsize_type %d " 3527 "rbb_threshold_hi %d " 3528 "rbb_threshold_lo %d", 3529 dma_channel, 3530 rbrp->rbb_max, 3531 rbrp->rbr_bufsize_type, 3532 rbrp->rbr_threshold_hi, 3533 rbrp->rbr_threshold_lo)); 3534 3535 rbrp->page_valid.value = 0; 3536 rbrp->page_mask_1.value = rbrp->page_mask_2.value = 0; 3537 rbrp->page_value_1.value = rbrp->page_value_2.value = 0; 3538 rbrp->page_reloc_1.value = rbrp->page_reloc_2.value = 0; 3539 rbrp->page_hdl.value = 0; 3540 3541 rbrp->page_valid.bits.ldw.page0 = 1; 3542 rbrp->page_valid.bits.ldw.page1 = 1; 3543 3544 /* Map in the receive completion ring */ 3545 rcrp = (p_rx_rcr_ring_t) 3546 KMEM_ZALLOC(sizeof (rx_rcr_ring_t), KM_SLEEP); 3547 rcrp->rdc = dma_channel; 3548 3549 nxge_port_rcr_size = nxgep->nxge_port_rcr_size; 3550 rcrp->comp_size = nxge_port_rcr_size; 3551 rcrp->comp_wrap_mask = nxge_port_rcr_size - 1; 3552 3553 rcrp->max_receive_pkts = nxge_max_rx_pkts; 3554 3555 dmap = (p_nxge_dma_common_t)&rcrp->rcr_desc; 3556 nxge_setup_dma_common(dmap, cntl_dmap, rcrp->comp_size, 3557 sizeof (rcr_entry_t)); 3558 rcrp->comp_rd_index = 0; 3559 rcrp->comp_wt_index = 0; 3560 rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p = 3561 (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc); 3562 #if defined(__i386) 3563 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 3564 (p_rcr_entry_t)(uint32_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 3565 #else 3566 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 3567 (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 3568 #endif 3569 3570 rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p + 3571 (nxge_port_rcr_size - 1); 3572 rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp + 3573 (nxge_port_rcr_size - 1); 3574 3575 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3576 "==> nxge_map_rxdma_channel_cfg_ring: " 3577 "channel %d " 3578 "rbr_vaddrp $%p " 3579 "rcr_desc_rd_head_p $%p " 3580 "rcr_desc_rd_head_pp $%p " 3581 "rcr_desc_rd_last_p $%p " 3582 "rcr_desc_rd_last_pp $%p ", 3583 dma_channel, 3584 rbr_vaddrp, 3585 rcrp->rcr_desc_rd_head_p, 3586 rcrp->rcr_desc_rd_head_pp, 3587 rcrp->rcr_desc_last_p, 3588 rcrp->rcr_desc_last_pp)); 3589 3590 /* 3591 * Zero out buffer block ring descriptors. 3592 */ 3593 bzero((caddr_t)dmap->kaddrp, dmap->alength); 3594 3595 rcrp->intr_timeout = (nxgep->intr_timeout < 3596 NXGE_RDC_RCR_TIMEOUT_MIN) ? NXGE_RDC_RCR_TIMEOUT_MIN : 3597 nxgep->intr_timeout; 3598 3599 rcrp->intr_threshold = (nxgep->intr_threshold < 3600 NXGE_RDC_RCR_THRESHOLD_MIN) ? NXGE_RDC_RCR_THRESHOLD_MIN : 3601 nxgep->intr_threshold; 3602 3603 rcrp->full_hdr_flag = B_FALSE; 3604 rcrp->sw_priv_hdr_len = 0; 3605 3606 cfga_p = &(rcrp->rcr_cfga); 3607 cfgb_p = &(rcrp->rcr_cfgb); 3608 cfga_p->value = 0; 3609 cfgb_p->value = 0; 3610 rcrp->rcr_addr = dmap->dma_cookie.dmac_laddress; 3611 cfga_p->value = (rcrp->rcr_addr & 3612 (RCRCFIG_A_STADDR_MASK | 3613 RCRCFIG_A_STADDR_BASE_MASK)); 3614 3615 rcfga_p->value |= ((uint64_t)rcrp->comp_size << 3616 RCRCFIG_A_LEN_SHIF); 3617 3618 /* 3619 * Timeout should be set based on the system clock divider. 3620 * A timeout value of 1 assumes that the 3621 * granularity (1000) is 3 microseconds running at 300MHz. 3622 */ 3623 cfgb_p->bits.ldw.pthres = rcrp->intr_threshold; 3624 cfgb_p->bits.ldw.timeout = rcrp->intr_timeout; 3625 cfgb_p->bits.ldw.entout = 1; 3626 3627 /* Map in the mailbox */ 3628 mboxp = (p_rx_mbox_t) 3629 KMEM_ZALLOC(sizeof (rx_mbox_t), KM_SLEEP); 3630 dmap = (p_nxge_dma_common_t)&mboxp->rx_mbox; 3631 nxge_setup_dma_common(dmap, cntl_dmap, 1, sizeof (rxdma_mailbox_t)); 3632 cfig1_p = (p_rxdma_cfig1_t)&mboxp->rx_cfg1; 3633 cfig2_p = (p_rxdma_cfig2_t)&mboxp->rx_cfg2; 3634 cfig1_p->value = cfig2_p->value = 0; 3635 3636 mboxp->mbox_addr = dmap->dma_cookie.dmac_laddress; 3637 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3638 "==> nxge_map_rxdma_channel_cfg_ring: " 3639 "channel %d cfg1 0x%016llx cfig2 0x%016llx cookie 0x%016llx", 3640 dma_channel, cfig1_p->value, cfig2_p->value, 3641 mboxp->mbox_addr)); 3642 3643 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress >> 32 3644 & 0xfff); 3645 cfig1_p->bits.ldw.mbaddr_h = dmaaddrp; 3646 3647 3648 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress & 0xffffffff); 3649 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress & 3650 RXDMA_CFIG2_MBADDR_L_MASK); 3651 3652 cfig2_p->bits.ldw.mbaddr = (dmaaddrp >> RXDMA_CFIG2_MBADDR_L_SHIFT); 3653 3654 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3655 "==> nxge_map_rxdma_channel_cfg_ring: " 3656 "channel %d damaddrp $%p " 3657 "cfg1 0x%016llx cfig2 0x%016llx", 3658 dma_channel, dmaaddrp, 3659 cfig1_p->value, cfig2_p->value)); 3660 3661 cfig2_p->bits.ldw.full_hdr = rcrp->full_hdr_flag; 3662 cfig2_p->bits.ldw.offset = rcrp->sw_priv_hdr_len; 3663 3664 rbrp->rx_rcr_p = rcrp; 3665 rcrp->rx_rbr_p = rbrp; 3666 *rcr_p = rcrp; 3667 *rx_mbox_p = mboxp; 3668 3669 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3670 "<== nxge_map_rxdma_channel_cfg_ring status 0x%08x", status)); 3671 3672 return (status); 3673 } 3674 3675 /*ARGSUSED*/ 3676 static void 3677 nxge_unmap_rxdma_channel_cfg_ring(p_nxge_t nxgep, 3678 p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p) 3679 { 3680 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3681 "==> nxge_unmap_rxdma_channel_cfg_ring: channel %d", 3682 rcr_p->rdc)); 3683 3684 KMEM_FREE(rcr_p, sizeof (rx_rcr_ring_t)); 3685 KMEM_FREE(rx_mbox_p, sizeof (rx_mbox_t)); 3686 3687 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3688 "<== nxge_unmap_rxdma_channel_cfg_ring")); 3689 } 3690 3691 static nxge_status_t 3692 nxge_map_rxdma_channel_buf_ring(p_nxge_t nxgep, uint16_t channel, 3693 p_nxge_dma_common_t *dma_buf_p, 3694 p_rx_rbr_ring_t *rbr_p, uint32_t num_chunks) 3695 { 3696 p_rx_rbr_ring_t rbrp; 3697 p_nxge_dma_common_t dma_bufp, tmp_bufp; 3698 p_rx_msg_t *rx_msg_ring; 3699 p_rx_msg_t rx_msg_p; 3700 p_mblk_t mblk_p; 3701 3702 rxring_info_t *ring_info; 3703 nxge_status_t status = NXGE_OK; 3704 int i, j, index; 3705 uint32_t size, bsize, nblocks, nmsgs; 3706 3707 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3708 "==> nxge_map_rxdma_channel_buf_ring: channel %d", 3709 channel)); 3710 3711 dma_bufp = tmp_bufp = *dma_buf_p; 3712 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3713 " nxge_map_rxdma_channel_buf_ring: channel %d to map %d " 3714 "chunks bufp 0x%016llx", 3715 channel, num_chunks, dma_bufp)); 3716 3717 nmsgs = 0; 3718 for (i = 0; i < num_chunks; i++, tmp_bufp++) { 3719 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3720 "==> nxge_map_rxdma_channel_buf_ring: channel %d " 3721 "bufp 0x%016llx nblocks %d nmsgs %d", 3722 channel, tmp_bufp, tmp_bufp->nblocks, nmsgs)); 3723 nmsgs += tmp_bufp->nblocks; 3724 } 3725 if (!nmsgs) { 3726 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3727 "<== nxge_map_rxdma_channel_buf_ring: channel %d " 3728 "no msg blocks", 3729 channel)); 3730 status = NXGE_ERROR; 3731 goto nxge_map_rxdma_channel_buf_ring_exit; 3732 } 3733 3734 rbrp = (p_rx_rbr_ring_t)KMEM_ZALLOC(sizeof (*rbrp), KM_SLEEP); 3735 3736 size = nmsgs * sizeof (p_rx_msg_t); 3737 rx_msg_ring = KMEM_ZALLOC(size, KM_SLEEP); 3738 ring_info = (rxring_info_t *)KMEM_ZALLOC(sizeof (rxring_info_t), 3739 KM_SLEEP); 3740 3741 MUTEX_INIT(&rbrp->lock, NULL, MUTEX_DRIVER, 3742 (void *)nxgep->interrupt_cookie); 3743 MUTEX_INIT(&rbrp->post_lock, NULL, MUTEX_DRIVER, 3744 (void *)nxgep->interrupt_cookie); 3745 rbrp->rdc = channel; 3746 rbrp->num_blocks = num_chunks; 3747 rbrp->tnblocks = nmsgs; 3748 rbrp->rbb_max = nmsgs; 3749 rbrp->rbr_max_size = nmsgs; 3750 rbrp->rbr_wrap_mask = (rbrp->rbb_max - 1); 3751 3752 /* 3753 * Buffer sizes suggested by NIU architect. 3754 * 256, 512 and 2K. 3755 */ 3756 3757 rbrp->pkt_buf_size0 = RBR_BUFSZ0_256B; 3758 rbrp->pkt_buf_size0_bytes = RBR_BUFSZ0_256_BYTES; 3759 rbrp->npi_pkt_buf_size0 = SIZE_256B; 3760 3761 rbrp->pkt_buf_size1 = RBR_BUFSZ1_1K; 3762 rbrp->pkt_buf_size1_bytes = RBR_BUFSZ1_1K_BYTES; 3763 rbrp->npi_pkt_buf_size1 = SIZE_1KB; 3764 3765 rbrp->block_size = nxgep->rx_default_block_size; 3766 3767 if (!nxgep->mac.is_jumbo) { 3768 rbrp->pkt_buf_size2 = RBR_BUFSZ2_2K; 3769 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_2K_BYTES; 3770 rbrp->npi_pkt_buf_size2 = SIZE_2KB; 3771 } else { 3772 if (rbrp->block_size >= 0x2000) { 3773 rbrp->pkt_buf_size2 = RBR_BUFSZ2_8K; 3774 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_8K_BYTES; 3775 rbrp->npi_pkt_buf_size2 = SIZE_8KB; 3776 } else { 3777 rbrp->pkt_buf_size2 = RBR_BUFSZ2_4K; 3778 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_4K_BYTES; 3779 rbrp->npi_pkt_buf_size2 = SIZE_4KB; 3780 } 3781 } 3782 3783 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3784 "==> nxge_map_rxdma_channel_buf_ring: channel %d " 3785 "actual rbr max %d rbb_max %d nmsgs %d " 3786 "rbrp->block_size %d default_block_size %d " 3787 "(config nxge_rbr_size %d nxge_rbr_spare_size %d)", 3788 channel, rbrp->rbr_max_size, rbrp->rbb_max, nmsgs, 3789 rbrp->block_size, nxgep->rx_default_block_size, 3790 nxge_rbr_size, nxge_rbr_spare_size)); 3791 3792 /* Map in buffers from the buffer pool. */ 3793 index = 0; 3794 for (i = 0; i < rbrp->num_blocks; i++, dma_bufp++) { 3795 bsize = dma_bufp->block_size; 3796 nblocks = dma_bufp->nblocks; 3797 #if defined(__i386) 3798 ring_info->buffer[i].dvma_addr = (uint32_t)dma_bufp->ioaddr_pp; 3799 #else 3800 ring_info->buffer[i].dvma_addr = (uint64_t)dma_bufp->ioaddr_pp; 3801 #endif 3802 ring_info->buffer[i].buf_index = i; 3803 ring_info->buffer[i].buf_size = dma_bufp->alength; 3804 ring_info->buffer[i].start_index = index; 3805 #if defined(__i386) 3806 ring_info->buffer[i].kaddr = (uint32_t)dma_bufp->kaddrp; 3807 #else 3808 ring_info->buffer[i].kaddr = (uint64_t)dma_bufp->kaddrp; 3809 #endif 3810 3811 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3812 " nxge_map_rxdma_channel_buf_ring: map channel %d " 3813 "chunk %d" 3814 " nblocks %d chunk_size %x block_size 0x%x " 3815 "dma_bufp $%p", channel, i, 3816 dma_bufp->nblocks, ring_info->buffer[i].buf_size, bsize, 3817 dma_bufp)); 3818 3819 for (j = 0; j < nblocks; j++) { 3820 if ((rx_msg_p = nxge_allocb(bsize, BPRI_LO, 3821 dma_bufp)) == NULL) { 3822 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3823 "allocb failed (index %d i %d j %d)", 3824 index, i, j)); 3825 goto nxge_map_rxdma_channel_buf_ring_fail1; 3826 } 3827 rx_msg_ring[index] = rx_msg_p; 3828 rx_msg_p->block_index = index; 3829 rx_msg_p->shifted_addr = (uint32_t) 3830 ((rx_msg_p->buf_dma.dma_cookie.dmac_laddress >> 3831 RBR_BKADDR_SHIFT)); 3832 3833 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3834 "index %d j %d rx_msg_p $%p mblk %p", 3835 index, j, rx_msg_p, rx_msg_p->rx_mblk_p)); 3836 3837 mblk_p = rx_msg_p->rx_mblk_p; 3838 mblk_p->b_wptr = mblk_p->b_rptr + bsize; 3839 3840 rbrp->rbr_ref_cnt++; 3841 index++; 3842 rx_msg_p->buf_dma.dma_channel = channel; 3843 } 3844 3845 rbrp->rbr_alloc_type = DDI_MEM_ALLOC; 3846 if (dma_bufp->contig_alloc_type) { 3847 rbrp->rbr_alloc_type = CONTIG_MEM_ALLOC; 3848 } 3849 3850 if (dma_bufp->kmem_alloc_type) { 3851 rbrp->rbr_alloc_type = KMEM_ALLOC; 3852 } 3853 3854 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3855 " nxge_map_rxdma_channel_buf_ring: map channel %d " 3856 "chunk %d" 3857 " nblocks %d chunk_size %x block_size 0x%x " 3858 "dma_bufp $%p", 3859 channel, i, 3860 dma_bufp->nblocks, ring_info->buffer[i].buf_size, bsize, 3861 dma_bufp)); 3862 } 3863 if (i < rbrp->num_blocks) { 3864 goto nxge_map_rxdma_channel_buf_ring_fail1; 3865 } 3866 3867 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3868 "nxge_map_rxdma_channel_buf_ring: done buf init " 3869 "channel %d msg block entries %d", 3870 channel, index)); 3871 ring_info->block_size_mask = bsize - 1; 3872 rbrp->rx_msg_ring = rx_msg_ring; 3873 rbrp->dma_bufp = dma_buf_p; 3874 rbrp->ring_info = ring_info; 3875 3876 status = nxge_rxbuf_index_info_init(nxgep, rbrp); 3877 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3878 " nxge_map_rxdma_channel_buf_ring: " 3879 "channel %d done buf info init", channel)); 3880 3881 /* 3882 * Finally, permit nxge_freeb() to call nxge_post_page(). 3883 */ 3884 rbrp->rbr_state = RBR_POSTING; 3885 3886 *rbr_p = rbrp; 3887 goto nxge_map_rxdma_channel_buf_ring_exit; 3888 3889 nxge_map_rxdma_channel_buf_ring_fail1: 3890 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3891 " nxge_map_rxdma_channel_buf_ring: failed channel (0x%x)", 3892 channel, status)); 3893 3894 index--; 3895 for (; index >= 0; index--) { 3896 rx_msg_p = rx_msg_ring[index]; 3897 if (rx_msg_p != NULL) { 3898 freeb(rx_msg_p->rx_mblk_p); 3899 rx_msg_ring[index] = NULL; 3900 } 3901 } 3902 nxge_map_rxdma_channel_buf_ring_fail: 3903 MUTEX_DESTROY(&rbrp->post_lock); 3904 MUTEX_DESTROY(&rbrp->lock); 3905 KMEM_FREE(ring_info, sizeof (rxring_info_t)); 3906 KMEM_FREE(rx_msg_ring, size); 3907 KMEM_FREE(rbrp, sizeof (rx_rbr_ring_t)); 3908 3909 status = NXGE_ERROR; 3910 3911 nxge_map_rxdma_channel_buf_ring_exit: 3912 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3913 "<== nxge_map_rxdma_channel_buf_ring status 0x%08x", status)); 3914 3915 return (status); 3916 } 3917 3918 /*ARGSUSED*/ 3919 static void 3920 nxge_unmap_rxdma_channel_buf_ring(p_nxge_t nxgep, 3921 p_rx_rbr_ring_t rbr_p) 3922 { 3923 p_rx_msg_t *rx_msg_ring; 3924 p_rx_msg_t rx_msg_p; 3925 rxring_info_t *ring_info; 3926 int i; 3927 uint32_t size; 3928 #ifdef NXGE_DEBUG 3929 int num_chunks; 3930 #endif 3931 3932 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3933 "==> nxge_unmap_rxdma_channel_buf_ring")); 3934 if (rbr_p == NULL) { 3935 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3936 "<== nxge_unmap_rxdma_channel_buf_ring: NULL rbrp")); 3937 return; 3938 } 3939 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3940 "==> nxge_unmap_rxdma_channel_buf_ring: channel %d", 3941 rbr_p->rdc)); 3942 3943 rx_msg_ring = rbr_p->rx_msg_ring; 3944 ring_info = rbr_p->ring_info; 3945 3946 if (rx_msg_ring == NULL || ring_info == NULL) { 3947 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3948 "<== nxge_unmap_rxdma_channel_buf_ring: " 3949 "rx_msg_ring $%p ring_info $%p", 3950 rx_msg_p, ring_info)); 3951 return; 3952 } 3953 3954 #ifdef NXGE_DEBUG 3955 num_chunks = rbr_p->num_blocks; 3956 #endif 3957 size = rbr_p->tnblocks * sizeof (p_rx_msg_t); 3958 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3959 " nxge_unmap_rxdma_channel_buf_ring: channel %d chunks %d " 3960 "tnblocks %d (max %d) size ptrs %d ", 3961 rbr_p->rdc, num_chunks, 3962 rbr_p->tnblocks, rbr_p->rbr_max_size, size)); 3963 3964 for (i = 0; i < rbr_p->tnblocks; i++) { 3965 rx_msg_p = rx_msg_ring[i]; 3966 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3967 " nxge_unmap_rxdma_channel_buf_ring: " 3968 "rx_msg_p $%p", 3969 rx_msg_p)); 3970 if (rx_msg_p != NULL) { 3971 freeb(rx_msg_p->rx_mblk_p); 3972 rx_msg_ring[i] = NULL; 3973 } 3974 } 3975 3976 /* 3977 * We no longer may use the mutex <post_lock>. By setting 3978 * <rbr_state> to anything but POSTING, we prevent 3979 * nxge_post_page() from accessing a dead mutex. 3980 */ 3981 rbr_p->rbr_state = RBR_UNMAPPING; 3982 MUTEX_DESTROY(&rbr_p->post_lock); 3983 3984 MUTEX_DESTROY(&rbr_p->lock); 3985 3986 if (rbr_p->rbr_ref_cnt == 0) { 3987 /* 3988 * This is the normal state of affairs. 3989 * Need to free the following buffers: 3990 * - data buffers 3991 * - rx_msg ring 3992 * - ring_info 3993 * - rbr ring 3994 */ 3995 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3996 "unmap_rxdma_buf_ring: No outstanding - freeing ")); 3997 nxge_rxdma_databuf_free(rbr_p); 3998 KMEM_FREE(ring_info, sizeof (rxring_info_t)); 3999 KMEM_FREE(rx_msg_ring, size); 4000 KMEM_FREE(rbr_p, sizeof (*rbr_p)); 4001 } else { 4002 /* 4003 * Some of our buffers are still being used. 4004 * Therefore, tell nxge_freeb() this ring is 4005 * unmapped, so it may free <rbr_p> for us. 4006 */ 4007 rbr_p->rbr_state = RBR_UNMAPPED; 4008 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4009 "unmap_rxdma_buf_ring: %d %s outstanding.", 4010 rbr_p->rbr_ref_cnt, 4011 rbr_p->rbr_ref_cnt == 1 ? "msg" : "msgs")); 4012 } 4013 4014 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4015 "<== nxge_unmap_rxdma_channel_buf_ring")); 4016 } 4017 4018 /* 4019 * nxge_rxdma_hw_start_common 4020 * 4021 * Arguments: 4022 * nxgep 4023 * 4024 * Notes: 4025 * 4026 * NPI/NXGE function calls: 4027 * nxge_init_fzc_rx_common(); 4028 * nxge_init_fzc_rxdma_port(); 4029 * 4030 * Registers accessed: 4031 * 4032 * Context: 4033 * Service domain 4034 */ 4035 static nxge_status_t 4036 nxge_rxdma_hw_start_common(p_nxge_t nxgep) 4037 { 4038 nxge_status_t status = NXGE_OK; 4039 4040 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start_common")); 4041 4042 /* 4043 * Load the sharable parameters by writing to the 4044 * function zero control registers. These FZC registers 4045 * should be initialized only once for the entire chip. 4046 */ 4047 (void) nxge_init_fzc_rx_common(nxgep); 4048 4049 /* 4050 * Initialize the RXDMA port specific FZC control configurations. 4051 * These FZC registers are pertaining to each port. 4052 */ 4053 (void) nxge_init_fzc_rxdma_port(nxgep); 4054 4055 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start_common")); 4056 4057 return (status); 4058 } 4059 4060 static nxge_status_t 4061 nxge_rxdma_hw_start(p_nxge_t nxgep, int channel) 4062 { 4063 int i, ndmas; 4064 p_rx_rbr_rings_t rx_rbr_rings; 4065 p_rx_rbr_ring_t *rbr_rings; 4066 p_rx_rcr_rings_t rx_rcr_rings; 4067 p_rx_rcr_ring_t *rcr_rings; 4068 p_rx_mbox_areas_t rx_mbox_areas_p; 4069 p_rx_mbox_t *rx_mbox_p; 4070 nxge_status_t status = NXGE_OK; 4071 4072 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start")); 4073 4074 rx_rbr_rings = nxgep->rx_rbr_rings; 4075 rx_rcr_rings = nxgep->rx_rcr_rings; 4076 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 4077 NXGE_DEBUG_MSG((nxgep, RX_CTL, 4078 "<== nxge_rxdma_hw_start: NULL ring pointers")); 4079 return (NXGE_ERROR); 4080 } 4081 ndmas = rx_rbr_rings->ndmas; 4082 if (ndmas == 0) { 4083 NXGE_DEBUG_MSG((nxgep, RX_CTL, 4084 "<== nxge_rxdma_hw_start: no dma channel allocated")); 4085 return (NXGE_ERROR); 4086 } 4087 4088 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4089 "==> nxge_rxdma_hw_start (ndmas %d)", ndmas)); 4090 4091 rbr_rings = rx_rbr_rings->rbr_rings; 4092 rcr_rings = rx_rcr_rings->rcr_rings; 4093 rx_mbox_areas_p = nxgep->rx_mbox_areas_p; 4094 if (rx_mbox_areas_p) { 4095 rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 4096 } 4097 4098 i = channel; 4099 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4100 "==> nxge_rxdma_hw_start (ndmas %d) channel %d", 4101 ndmas, channel)); 4102 status = nxge_rxdma_start_channel(nxgep, channel, 4103 (p_rx_rbr_ring_t)rbr_rings[i], 4104 (p_rx_rcr_ring_t)rcr_rings[i], 4105 (p_rx_mbox_t)rx_mbox_p[i]); 4106 if (status != NXGE_OK) { 4107 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4108 "==> nxge_rxdma_hw_start: disable " 4109 "(status 0x%x channel %d)", status, channel)); 4110 return (status); 4111 } 4112 4113 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start: " 4114 "rx_rbr_rings 0x%016llx rings 0x%016llx", 4115 rx_rbr_rings, rx_rcr_rings)); 4116 4117 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4118 "==> nxge_rxdma_hw_start: (status 0x%x)", status)); 4119 4120 return (status); 4121 } 4122 4123 static void 4124 nxge_rxdma_hw_stop(p_nxge_t nxgep, int channel) 4125 { 4126 p_rx_rbr_rings_t rx_rbr_rings; 4127 p_rx_rcr_rings_t rx_rcr_rings; 4128 4129 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_stop")); 4130 4131 rx_rbr_rings = nxgep->rx_rbr_rings; 4132 rx_rcr_rings = nxgep->rx_rcr_rings; 4133 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 4134 NXGE_DEBUG_MSG((nxgep, RX_CTL, 4135 "<== nxge_rxdma_hw_stop: NULL ring pointers")); 4136 return; 4137 } 4138 4139 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4140 "==> nxge_rxdma_hw_stop(channel %d)", 4141 channel)); 4142 (void) nxge_rxdma_stop_channel(nxgep, channel); 4143 4144 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_stop: " 4145 "rx_rbr_rings 0x%016llx rings 0x%016llx", 4146 rx_rbr_rings, rx_rcr_rings)); 4147 4148 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_rxdma_hw_stop")); 4149 } 4150 4151 4152 static nxge_status_t 4153 nxge_rxdma_start_channel(p_nxge_t nxgep, uint16_t channel, 4154 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p) 4155 4156 { 4157 npi_handle_t handle; 4158 npi_status_t rs = NPI_SUCCESS; 4159 rx_dma_ctl_stat_t cs; 4160 rx_dma_ent_msk_t ent_mask; 4161 nxge_status_t status = NXGE_OK; 4162 4163 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel")); 4164 4165 handle = NXGE_DEV_NPI_HANDLE(nxgep); 4166 4167 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "nxge_rxdma_start_channel: " 4168 "npi handle addr $%p acc $%p", 4169 nxgep->npi_handle.regp, nxgep->npi_handle.regh)); 4170 4171 /* Reset RXDMA channel, but not if you're a guest. */ 4172 if (!isLDOMguest(nxgep)) { 4173 rs = npi_rxdma_cfg_rdc_reset(handle, channel); 4174 if (rs != NPI_SUCCESS) { 4175 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4176 "==> nxge_init_fzc_rdc: " 4177 "npi_rxdma_cfg_rdc_reset(%d) returned 0x%08x", 4178 channel, rs)); 4179 return (NXGE_ERROR | rs); 4180 } 4181 4182 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4183 "==> nxge_rxdma_start_channel: reset done: channel %d", 4184 channel)); 4185 } 4186 4187 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 4188 if (isLDOMguest(nxgep)) 4189 (void) nxge_rdc_lp_conf(nxgep, channel); 4190 #endif 4191 4192 /* 4193 * Initialize the RXDMA channel specific FZC control 4194 * configurations. These FZC registers are pertaining 4195 * to each RX channel (logical pages). 4196 */ 4197 if (!isLDOMguest(nxgep)) { 4198 status = nxge_init_fzc_rxdma_channel(nxgep, channel); 4199 if (status != NXGE_OK) { 4200 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4201 "==> nxge_rxdma_start_channel: " 4202 "init fzc rxdma failed (0x%08x channel %d)", 4203 status, channel)); 4204 return (status); 4205 } 4206 4207 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4208 "==> nxge_rxdma_start_channel: fzc done")); 4209 } 4210 4211 /* Set up the interrupt event masks. */ 4212 ent_mask.value = 0; 4213 ent_mask.value |= RX_DMA_ENT_MSK_RBREMPTY_MASK; 4214 rs = npi_rxdma_event_mask(handle, OP_SET, channel, 4215 &ent_mask); 4216 if (rs != NPI_SUCCESS) { 4217 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4218 "==> nxge_rxdma_start_channel: " 4219 "init rxdma event masks failed " 4220 "(0x%08x channel %d)", 4221 status, channel)); 4222 return (NXGE_ERROR | rs); 4223 } 4224 4225 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4226 "==> nxge_rxdma_start_channel: " 4227 "event done: channel %d (mask 0x%016llx)", 4228 channel, ent_mask.value)); 4229 4230 /* Initialize the receive DMA control and status register */ 4231 cs.value = 0; 4232 cs.bits.hdw.mex = 1; 4233 cs.bits.hdw.rcrthres = 1; 4234 cs.bits.hdw.rcrto = 1; 4235 cs.bits.hdw.rbr_empty = 1; 4236 status = nxge_init_rxdma_channel_cntl_stat(nxgep, channel, &cs); 4237 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 4238 "channel %d rx_dma_cntl_stat 0x%0016llx", channel, cs.value)); 4239 if (status != NXGE_OK) { 4240 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4241 "==> nxge_rxdma_start_channel: " 4242 "init rxdma control register failed (0x%08x channel %d", 4243 status, channel)); 4244 return (status); 4245 } 4246 4247 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 4248 "control done - channel %d cs 0x%016llx", channel, cs.value)); 4249 4250 /* 4251 * Load RXDMA descriptors, buffers, mailbox, 4252 * initialise the receive DMA channels and 4253 * enable each DMA channel. 4254 */ 4255 status = nxge_enable_rxdma_channel(nxgep, 4256 channel, rbr_p, rcr_p, mbox_p); 4257 4258 if (status != NXGE_OK) { 4259 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4260 " nxge_rxdma_start_channel: " 4261 " enable rxdma failed (0x%08x channel %d)", 4262 status, channel)); 4263 return (status); 4264 } 4265 4266 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4267 "==> nxge_rxdma_start_channel: enabled channel %d")); 4268 4269 if (isLDOMguest(nxgep)) { 4270 /* Add interrupt handler for this channel. */ 4271 if (nxge_hio_intr_add(nxgep, VP_BOUND_RX, channel) 4272 != NXGE_OK) { 4273 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4274 " nxge_rxdma_start_channel: " 4275 " nxge_hio_intr_add failed (0x%08x channel %d)", 4276 status, channel)); 4277 } 4278 } 4279 4280 ent_mask.value = 0; 4281 ent_mask.value |= (RX_DMA_ENT_MSK_WRED_DROP_MASK | 4282 RX_DMA_ENT_MSK_PTDROP_PKT_MASK); 4283 rs = npi_rxdma_event_mask(handle, OP_SET, channel, 4284 &ent_mask); 4285 if (rs != NPI_SUCCESS) { 4286 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4287 "==> nxge_rxdma_start_channel: " 4288 "init rxdma event masks failed (0x%08x channel %d)", 4289 status, channel)); 4290 return (NXGE_ERROR | rs); 4291 } 4292 4293 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 4294 "control done - channel %d cs 0x%016llx", channel, cs.value)); 4295 4296 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_rxdma_start_channel")); 4297 4298 return (NXGE_OK); 4299 } 4300 4301 static nxge_status_t 4302 nxge_rxdma_stop_channel(p_nxge_t nxgep, uint16_t channel) 4303 { 4304 npi_handle_t handle; 4305 npi_status_t rs = NPI_SUCCESS; 4306 rx_dma_ctl_stat_t cs; 4307 rx_dma_ent_msk_t ent_mask; 4308 nxge_status_t status = NXGE_OK; 4309 4310 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop_channel")); 4311 4312 handle = NXGE_DEV_NPI_HANDLE(nxgep); 4313 4314 NXGE_DEBUG_MSG((nxgep, RX_CTL, "nxge_rxdma_stop_channel: " 4315 "npi handle addr $%p acc $%p", 4316 nxgep->npi_handle.regp, nxgep->npi_handle.regh)); 4317 4318 if (!isLDOMguest(nxgep)) { 4319 /* 4320 * Stop RxMAC = A.9.2.6 4321 */ 4322 if (nxge_rx_mac_disable(nxgep) != NXGE_OK) { 4323 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4324 "nxge_rxdma_stop_channel: " 4325 "Failed to disable RxMAC")); 4326 } 4327 4328 /* 4329 * Drain IPP Port = A.9.3.6 4330 */ 4331 (void) nxge_ipp_drain(nxgep); 4332 } 4333 4334 /* Reset RXDMA channel */ 4335 rs = npi_rxdma_cfg_rdc_reset(handle, channel); 4336 if (rs != NPI_SUCCESS) { 4337 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4338 " nxge_rxdma_stop_channel: " 4339 " reset rxdma failed (0x%08x channel %d)", 4340 rs, channel)); 4341 return (NXGE_ERROR | rs); 4342 } 4343 4344 NXGE_DEBUG_MSG((nxgep, RX_CTL, 4345 "==> nxge_rxdma_stop_channel: reset done")); 4346 4347 /* Set up the interrupt event masks. */ 4348 ent_mask.value = RX_DMA_ENT_MSK_ALL; 4349 rs = npi_rxdma_event_mask(handle, OP_SET, channel, 4350 &ent_mask); 4351 if (rs != NPI_SUCCESS) { 4352 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4353 "==> nxge_rxdma_stop_channel: " 4354 "set rxdma event masks failed (0x%08x channel %d)", 4355 rs, channel)); 4356 return (NXGE_ERROR | rs); 4357 } 4358 4359 NXGE_DEBUG_MSG((nxgep, RX_CTL, 4360 "==> nxge_rxdma_stop_channel: event done")); 4361 4362 /* 4363 * Initialize the receive DMA control and status register 4364 */ 4365 cs.value = 0; 4366 status = nxge_init_rxdma_channel_cntl_stat(nxgep, channel, &cs); 4367 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop_channel: control " 4368 " to default (all 0s) 0x%08x", cs.value)); 4369 if (status != NXGE_OK) { 4370 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4371 " nxge_rxdma_stop_channel: init rxdma" 4372 " control register failed (0x%08x channel %d", 4373 status, channel)); 4374 return (status); 4375 } 4376 4377 NXGE_DEBUG_MSG((nxgep, RX_CTL, 4378 "==> nxge_rxdma_stop_channel: control done")); 4379 4380 /* 4381 * Make sure channel is disabled. 4382 */ 4383 status = nxge_disable_rxdma_channel(nxgep, channel); 4384 4385 if (status != NXGE_OK) { 4386 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4387 " nxge_rxdma_stop_channel: " 4388 " init enable rxdma failed (0x%08x channel %d)", 4389 status, channel)); 4390 return (status); 4391 } 4392 4393 if (!isLDOMguest(nxgep)) { 4394 /* 4395 * Enable RxMAC = A.9.2.10 4396 */ 4397 if (nxge_rx_mac_enable(nxgep) != NXGE_OK) { 4398 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4399 "nxge_rxdma_stop_channel: Rx MAC still disabled")); 4400 } 4401 } 4402 4403 NXGE_DEBUG_MSG((nxgep, 4404 RX_CTL, "==> nxge_rxdma_stop_channel: disable done")); 4405 4406 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_stop_channel")); 4407 4408 return (NXGE_OK); 4409 } 4410 4411 nxge_status_t 4412 nxge_rxdma_handle_sys_errors(p_nxge_t nxgep) 4413 { 4414 npi_handle_t handle; 4415 p_nxge_rdc_sys_stats_t statsp; 4416 rx_ctl_dat_fifo_stat_t stat; 4417 uint32_t zcp_err_status; 4418 uint32_t ipp_err_status; 4419 nxge_status_t status = NXGE_OK; 4420 npi_status_t rs = NPI_SUCCESS; 4421 boolean_t my_err = B_FALSE; 4422 4423 handle = nxgep->npi_handle; 4424 statsp = (p_nxge_rdc_sys_stats_t)&nxgep->statsp->rdc_sys_stats; 4425 4426 rs = npi_rxdma_rxctl_fifo_error_intr_get(handle, &stat); 4427 4428 if (rs != NPI_SUCCESS) 4429 return (NXGE_ERROR | rs); 4430 4431 if (stat.bits.ldw.id_mismatch) { 4432 statsp->id_mismatch++; 4433 NXGE_FM_REPORT_ERROR(nxgep, nxgep->mac.portnum, NULL, 4434 NXGE_FM_EREPORT_RDMC_ID_MISMATCH); 4435 /* Global fatal error encountered */ 4436 } 4437 4438 if ((stat.bits.ldw.zcp_eop_err) || (stat.bits.ldw.ipp_eop_err)) { 4439 switch (nxgep->mac.portnum) { 4440 case 0: 4441 if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT0) || 4442 (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT0)) { 4443 my_err = B_TRUE; 4444 zcp_err_status = stat.bits.ldw.zcp_eop_err; 4445 ipp_err_status = stat.bits.ldw.ipp_eop_err; 4446 } 4447 break; 4448 case 1: 4449 if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT1) || 4450 (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT1)) { 4451 my_err = B_TRUE; 4452 zcp_err_status = stat.bits.ldw.zcp_eop_err; 4453 ipp_err_status = stat.bits.ldw.ipp_eop_err; 4454 } 4455 break; 4456 case 2: 4457 if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT2) || 4458 (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT2)) { 4459 my_err = B_TRUE; 4460 zcp_err_status = stat.bits.ldw.zcp_eop_err; 4461 ipp_err_status = stat.bits.ldw.ipp_eop_err; 4462 } 4463 break; 4464 case 3: 4465 if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT3) || 4466 (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT3)) { 4467 my_err = B_TRUE; 4468 zcp_err_status = stat.bits.ldw.zcp_eop_err; 4469 ipp_err_status = stat.bits.ldw.ipp_eop_err; 4470 } 4471 break; 4472 default: 4473 return (NXGE_ERROR); 4474 } 4475 } 4476 4477 if (my_err) { 4478 status = nxge_rxdma_handle_port_errors(nxgep, ipp_err_status, 4479 zcp_err_status); 4480 if (status != NXGE_OK) 4481 return (status); 4482 } 4483 4484 return (NXGE_OK); 4485 } 4486 4487 static nxge_status_t 4488 nxge_rxdma_handle_port_errors(p_nxge_t nxgep, uint32_t ipp_status, 4489 uint32_t zcp_status) 4490 { 4491 boolean_t rxport_fatal = B_FALSE; 4492 p_nxge_rdc_sys_stats_t statsp; 4493 nxge_status_t status = NXGE_OK; 4494 uint8_t portn; 4495 4496 portn = nxgep->mac.portnum; 4497 statsp = (p_nxge_rdc_sys_stats_t)&nxgep->statsp->rdc_sys_stats; 4498 4499 if (ipp_status & (0x1 << portn)) { 4500 statsp->ipp_eop_err++; 4501 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 4502 NXGE_FM_EREPORT_RDMC_IPP_EOP_ERR); 4503 rxport_fatal = B_TRUE; 4504 } 4505 4506 if (zcp_status & (0x1 << portn)) { 4507 statsp->zcp_eop_err++; 4508 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 4509 NXGE_FM_EREPORT_RDMC_ZCP_EOP_ERR); 4510 rxport_fatal = B_TRUE; 4511 } 4512 4513 if (rxport_fatal) { 4514 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4515 " nxge_rxdma_handle_port_error: " 4516 " fatal error on Port #%d\n", 4517 portn)); 4518 status = nxge_rx_port_fatal_err_recover(nxgep); 4519 if (status == NXGE_OK) { 4520 FM_SERVICE_RESTORED(nxgep); 4521 } 4522 } 4523 4524 return (status); 4525 } 4526 4527 static nxge_status_t 4528 nxge_rxdma_fatal_err_recover(p_nxge_t nxgep, uint16_t channel) 4529 { 4530 npi_handle_t handle; 4531 npi_status_t rs = NPI_SUCCESS; 4532 nxge_status_t status = NXGE_OK; 4533 p_rx_rbr_ring_t rbrp; 4534 p_rx_rcr_ring_t rcrp; 4535 p_rx_mbox_t mboxp; 4536 rx_dma_ent_msk_t ent_mask; 4537 p_nxge_dma_common_t dmap; 4538 uint32_t ref_cnt; 4539 p_rx_msg_t rx_msg_p; 4540 int i; 4541 uint32_t nxge_port_rcr_size; 4542 4543 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_fatal_err_recover")); 4544 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4545 "Recovering from RxDMAChannel#%d error...", channel)); 4546 4547 /* 4548 * Stop the dma channel waits for the stop done. 4549 * If the stop done bit is not set, then create 4550 * an error. 4551 */ 4552 4553 handle = NXGE_DEV_NPI_HANDLE(nxgep); 4554 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Rx DMA stop...")); 4555 4556 rbrp = (p_rx_rbr_ring_t)nxgep->rx_rbr_rings->rbr_rings[channel]; 4557 rcrp = (p_rx_rcr_ring_t)nxgep->rx_rcr_rings->rcr_rings[channel]; 4558 4559 MUTEX_ENTER(&rcrp->lock); 4560 MUTEX_ENTER(&rbrp->lock); 4561 MUTEX_ENTER(&rbrp->post_lock); 4562 4563 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Disable RxDMA channel...")); 4564 4565 rs = npi_rxdma_cfg_rdc_disable(handle, channel); 4566 if (rs != NPI_SUCCESS) { 4567 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4568 "nxge_disable_rxdma_channel:failed")); 4569 goto fail; 4570 } 4571 4572 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Disable RxDMA interrupt...")); 4573 4574 /* Disable interrupt */ 4575 ent_mask.value = RX_DMA_ENT_MSK_ALL; 4576 rs = npi_rxdma_event_mask(handle, OP_SET, channel, &ent_mask); 4577 if (rs != NPI_SUCCESS) { 4578 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4579 "nxge_rxdma_stop_channel: " 4580 "set rxdma event masks failed (channel %d)", 4581 channel)); 4582 } 4583 4584 NXGE_DEBUG_MSG((nxgep, RX_CTL, "RxDMA channel reset...")); 4585 4586 /* Reset RXDMA channel */ 4587 rs = npi_rxdma_cfg_rdc_reset(handle, channel); 4588 if (rs != NPI_SUCCESS) { 4589 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4590 "nxge_rxdma_fatal_err_recover: " 4591 " reset rxdma failed (channel %d)", channel)); 4592 goto fail; 4593 } 4594 4595 nxge_port_rcr_size = nxgep->nxge_port_rcr_size; 4596 4597 mboxp = (p_rx_mbox_t)nxgep->rx_mbox_areas_p->rxmbox_areas[channel]; 4598 4599 rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 4600 rbrp->rbr_rd_index = 0; 4601 4602 rcrp->comp_rd_index = 0; 4603 rcrp->comp_wt_index = 0; 4604 rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p = 4605 (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc); 4606 #if defined(__i386) 4607 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 4608 (p_rcr_entry_t)(uint32_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 4609 #else 4610 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 4611 (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 4612 #endif 4613 4614 rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p + 4615 (nxge_port_rcr_size - 1); 4616 rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp + 4617 (nxge_port_rcr_size - 1); 4618 4619 dmap = (p_nxge_dma_common_t)&rcrp->rcr_desc; 4620 bzero((caddr_t)dmap->kaddrp, dmap->alength); 4621 4622 cmn_err(CE_NOTE, "!rbr entries = %d\n", rbrp->rbr_max_size); 4623 4624 for (i = 0; i < rbrp->rbr_max_size; i++) { 4625 rx_msg_p = rbrp->rx_msg_ring[i]; 4626 ref_cnt = rx_msg_p->ref_cnt; 4627 if (ref_cnt != 1) { 4628 if (rx_msg_p->cur_usage_cnt != 4629 rx_msg_p->max_usage_cnt) { 4630 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4631 "buf[%d]: cur_usage_cnt = %d " 4632 "max_usage_cnt = %d\n", i, 4633 rx_msg_p->cur_usage_cnt, 4634 rx_msg_p->max_usage_cnt)); 4635 } else { 4636 /* Buffer can be re-posted */ 4637 rx_msg_p->free = B_TRUE; 4638 rx_msg_p->cur_usage_cnt = 0; 4639 rx_msg_p->max_usage_cnt = 0xbaddcafe; 4640 rx_msg_p->pkt_buf_size = 0; 4641 } 4642 } 4643 } 4644 4645 NXGE_DEBUG_MSG((nxgep, RX_CTL, "RxDMA channel re-start...")); 4646 4647 status = nxge_rxdma_start_channel(nxgep, channel, rbrp, rcrp, mboxp); 4648 if (status != NXGE_OK) { 4649 goto fail; 4650 } 4651 4652 MUTEX_EXIT(&rbrp->post_lock); 4653 MUTEX_EXIT(&rbrp->lock); 4654 MUTEX_EXIT(&rcrp->lock); 4655 4656 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4657 "Recovery Successful, RxDMAChannel#%d Restored", 4658 channel)); 4659 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_fatal_err_recover")); 4660 4661 return (NXGE_OK); 4662 fail: 4663 MUTEX_EXIT(&rbrp->post_lock); 4664 MUTEX_EXIT(&rbrp->lock); 4665 MUTEX_EXIT(&rcrp->lock); 4666 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Recovery failed")); 4667 4668 return (NXGE_ERROR | rs); 4669 } 4670 4671 nxge_status_t 4672 nxge_rx_port_fatal_err_recover(p_nxge_t nxgep) 4673 { 4674 nxge_grp_set_t *set = &nxgep->rx_set; 4675 nxge_status_t status = NXGE_OK; 4676 int rdc; 4677 4678 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rx_port_fatal_err_recover")); 4679 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4680 "Recovering from RxPort error...")); 4681 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Disabling RxMAC...\n")); 4682 4683 if (nxge_rx_mac_disable(nxgep) != NXGE_OK) 4684 goto fail; 4685 4686 NXGE_DELAY(1000); 4687 4688 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Stopping all RxDMA channels...")); 4689 4690 for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 4691 if ((1 << rdc) & set->owned.map) { 4692 if (nxge_rxdma_fatal_err_recover(nxgep, rdc) 4693 != NXGE_OK) { 4694 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4695 "Could not recover channel %d", rdc)); 4696 } 4697 } 4698 } 4699 4700 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Resetting IPP...")); 4701 4702 /* Reset IPP */ 4703 if (nxge_ipp_reset(nxgep) != NXGE_OK) { 4704 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4705 "nxge_rx_port_fatal_err_recover: " 4706 "Failed to reset IPP")); 4707 goto fail; 4708 } 4709 4710 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Reset RxMAC...")); 4711 4712 /* Reset RxMAC */ 4713 if (nxge_rx_mac_reset(nxgep) != NXGE_OK) { 4714 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4715 "nxge_rx_port_fatal_err_recover: " 4716 "Failed to reset RxMAC")); 4717 goto fail; 4718 } 4719 4720 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Re-initialize IPP...")); 4721 4722 /* Re-Initialize IPP */ 4723 if (nxge_ipp_init(nxgep) != NXGE_OK) { 4724 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4725 "nxge_rx_port_fatal_err_recover: " 4726 "Failed to init IPP")); 4727 goto fail; 4728 } 4729 4730 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Re-initialize RxMAC...")); 4731 4732 /* Re-Initialize RxMAC */ 4733 if ((status = nxge_rx_mac_init(nxgep)) != NXGE_OK) { 4734 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4735 "nxge_rx_port_fatal_err_recover: " 4736 "Failed to reset RxMAC")); 4737 goto fail; 4738 } 4739 4740 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Re-enable RxMAC...")); 4741 4742 /* Re-enable RxMAC */ 4743 if ((status = nxge_rx_mac_enable(nxgep)) != NXGE_OK) { 4744 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4745 "nxge_rx_port_fatal_err_recover: " 4746 "Failed to enable RxMAC")); 4747 goto fail; 4748 } 4749 4750 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4751 "Recovery Successful, RxPort Restored")); 4752 4753 return (NXGE_OK); 4754 fail: 4755 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Recovery failed")); 4756 return (status); 4757 } 4758 4759 void 4760 nxge_rxdma_inject_err(p_nxge_t nxgep, uint32_t err_id, uint8_t chan) 4761 { 4762 rx_dma_ctl_stat_t cs; 4763 rx_ctl_dat_fifo_stat_t cdfs; 4764 4765 switch (err_id) { 4766 case NXGE_FM_EREPORT_RDMC_RCR_ACK_ERR: 4767 case NXGE_FM_EREPORT_RDMC_DC_FIFO_ERR: 4768 case NXGE_FM_EREPORT_RDMC_RCR_SHA_PAR: 4769 case NXGE_FM_EREPORT_RDMC_RBR_PRE_PAR: 4770 case NXGE_FM_EREPORT_RDMC_RBR_TMOUT: 4771 case NXGE_FM_EREPORT_RDMC_RSP_CNT_ERR: 4772 case NXGE_FM_EREPORT_RDMC_BYTE_EN_BUS: 4773 case NXGE_FM_EREPORT_RDMC_RSP_DAT_ERR: 4774 case NXGE_FM_EREPORT_RDMC_RCRINCON: 4775 case NXGE_FM_EREPORT_RDMC_RCRFULL: 4776 case NXGE_FM_EREPORT_RDMC_RBRFULL: 4777 case NXGE_FM_EREPORT_RDMC_RBRLOGPAGE: 4778 case NXGE_FM_EREPORT_RDMC_CFIGLOGPAGE: 4779 case NXGE_FM_EREPORT_RDMC_CONFIG_ERR: 4780 RXDMA_REG_READ64(nxgep->npi_handle, RX_DMA_CTL_STAT_DBG_REG, 4781 chan, &cs.value); 4782 if (err_id == NXGE_FM_EREPORT_RDMC_RCR_ACK_ERR) 4783 cs.bits.hdw.rcr_ack_err = 1; 4784 else if (err_id == NXGE_FM_EREPORT_RDMC_DC_FIFO_ERR) 4785 cs.bits.hdw.dc_fifo_err = 1; 4786 else if (err_id == NXGE_FM_EREPORT_RDMC_RCR_SHA_PAR) 4787 cs.bits.hdw.rcr_sha_par = 1; 4788 else if (err_id == NXGE_FM_EREPORT_RDMC_RBR_PRE_PAR) 4789 cs.bits.hdw.rbr_pre_par = 1; 4790 else if (err_id == NXGE_FM_EREPORT_RDMC_RBR_TMOUT) 4791 cs.bits.hdw.rbr_tmout = 1; 4792 else if (err_id == NXGE_FM_EREPORT_RDMC_RSP_CNT_ERR) 4793 cs.bits.hdw.rsp_cnt_err = 1; 4794 else if (err_id == NXGE_FM_EREPORT_RDMC_BYTE_EN_BUS) 4795 cs.bits.hdw.byte_en_bus = 1; 4796 else if (err_id == NXGE_FM_EREPORT_RDMC_RSP_DAT_ERR) 4797 cs.bits.hdw.rsp_dat_err = 1; 4798 else if (err_id == NXGE_FM_EREPORT_RDMC_CONFIG_ERR) 4799 cs.bits.hdw.config_err = 1; 4800 else if (err_id == NXGE_FM_EREPORT_RDMC_RCRINCON) 4801 cs.bits.hdw.rcrincon = 1; 4802 else if (err_id == NXGE_FM_EREPORT_RDMC_RCRFULL) 4803 cs.bits.hdw.rcrfull = 1; 4804 else if (err_id == NXGE_FM_EREPORT_RDMC_RBRFULL) 4805 cs.bits.hdw.rbrfull = 1; 4806 else if (err_id == NXGE_FM_EREPORT_RDMC_RBRLOGPAGE) 4807 cs.bits.hdw.rbrlogpage = 1; 4808 else if (err_id == NXGE_FM_EREPORT_RDMC_CFIGLOGPAGE) 4809 cs.bits.hdw.cfiglogpage = 1; 4810 #if defined(__i386) 4811 cmn_err(CE_NOTE, "!Write 0x%llx to RX_DMA_CTL_STAT_DBG_REG\n", 4812 cs.value); 4813 #else 4814 cmn_err(CE_NOTE, "!Write 0x%lx to RX_DMA_CTL_STAT_DBG_REG\n", 4815 cs.value); 4816 #endif 4817 RXDMA_REG_WRITE64(nxgep->npi_handle, RX_DMA_CTL_STAT_DBG_REG, 4818 chan, cs.value); 4819 break; 4820 case NXGE_FM_EREPORT_RDMC_ID_MISMATCH: 4821 case NXGE_FM_EREPORT_RDMC_ZCP_EOP_ERR: 4822 case NXGE_FM_EREPORT_RDMC_IPP_EOP_ERR: 4823 cdfs.value = 0; 4824 if (err_id == NXGE_FM_EREPORT_RDMC_ID_MISMATCH) 4825 cdfs.bits.ldw.id_mismatch = (1 << nxgep->mac.portnum); 4826 else if (err_id == NXGE_FM_EREPORT_RDMC_ZCP_EOP_ERR) 4827 cdfs.bits.ldw.zcp_eop_err = (1 << nxgep->mac.portnum); 4828 else if (err_id == NXGE_FM_EREPORT_RDMC_IPP_EOP_ERR) 4829 cdfs.bits.ldw.ipp_eop_err = (1 << nxgep->mac.portnum); 4830 #if defined(__i386) 4831 cmn_err(CE_NOTE, 4832 "!Write 0x%llx to RX_CTL_DAT_FIFO_STAT_DBG_REG\n", 4833 cdfs.value); 4834 #else 4835 cmn_err(CE_NOTE, 4836 "!Write 0x%lx to RX_CTL_DAT_FIFO_STAT_DBG_REG\n", 4837 cdfs.value); 4838 #endif 4839 NXGE_REG_WR64(nxgep->npi_handle, 4840 RX_CTL_DAT_FIFO_STAT_DBG_REG, cdfs.value); 4841 break; 4842 case NXGE_FM_EREPORT_RDMC_DCF_ERR: 4843 break; 4844 case NXGE_FM_EREPORT_RDMC_RCR_ERR: 4845 break; 4846 } 4847 } 4848 4849 static void 4850 nxge_rxdma_databuf_free(p_rx_rbr_ring_t rbr_p) 4851 { 4852 rxring_info_t *ring_info; 4853 int index; 4854 uint32_t chunk_size; 4855 uint64_t kaddr; 4856 uint_t num_blocks; 4857 4858 NXGE_DEBUG_MSG((NULL, DMA_CTL, "==> nxge_rxdma_databuf_free")); 4859 4860 if (rbr_p == NULL) { 4861 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 4862 "==> nxge_rxdma_databuf_free: NULL rbr pointer")); 4863 return; 4864 } 4865 4866 if (rbr_p->rbr_alloc_type == DDI_MEM_ALLOC) { 4867 NXGE_DEBUG_MSG((NULL, DMA_CTL, 4868 "<== nxge_rxdma_databuf_free: DDI")); 4869 return; 4870 } 4871 4872 ring_info = rbr_p->ring_info; 4873 if (ring_info == NULL) { 4874 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 4875 "==> nxge_rxdma_databuf_free: NULL ring info")); 4876 return; 4877 } 4878 num_blocks = rbr_p->num_blocks; 4879 for (index = 0; index < num_blocks; index++) { 4880 kaddr = ring_info->buffer[index].kaddr; 4881 chunk_size = ring_info->buffer[index].buf_size; 4882 NXGE_DEBUG_MSG((NULL, DMA_CTL, 4883 "==> nxge_rxdma_databuf_free: free chunk %d " 4884 "kaddrp $%p chunk size %d", 4885 index, kaddr, chunk_size)); 4886 if (kaddr == NULL) continue; 4887 nxge_free_buf(rbr_p->rbr_alloc_type, kaddr, chunk_size); 4888 ring_info->buffer[index].kaddr = NULL; 4889 } 4890 4891 NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_databuf_free")); 4892 } 4893 4894 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 4895 extern void contig_mem_free(void *, size_t); 4896 #endif 4897 4898 void 4899 nxge_free_buf(buf_alloc_type_t alloc_type, uint64_t kaddr, uint32_t buf_size) 4900 { 4901 NXGE_DEBUG_MSG((NULL, DMA_CTL, "==> nxge_free_buf")); 4902 4903 if (kaddr == NULL || !buf_size) { 4904 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 4905 "==> nxge_free_buf: invalid kaddr $%p size to free %d", 4906 kaddr, buf_size)); 4907 return; 4908 } 4909 4910 switch (alloc_type) { 4911 case KMEM_ALLOC: 4912 NXGE_DEBUG_MSG((NULL, DMA_CTL, 4913 "==> nxge_free_buf: freeing kmem $%p size %d", 4914 kaddr, buf_size)); 4915 #if defined(__i386) 4916 KMEM_FREE((void *)(uint32_t)kaddr, buf_size); 4917 #else 4918 KMEM_FREE((void *)kaddr, buf_size); 4919 #endif 4920 break; 4921 4922 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 4923 case CONTIG_MEM_ALLOC: 4924 NXGE_DEBUG_MSG((NULL, DMA_CTL, 4925 "==> nxge_free_buf: freeing contig_mem kaddr $%p size %d", 4926 kaddr, buf_size)); 4927 contig_mem_free((void *)kaddr, buf_size); 4928 break; 4929 #endif 4930 4931 default: 4932 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 4933 "<== nxge_free_buf: unsupported alloc type %d", 4934 alloc_type)); 4935 return; 4936 } 4937 4938 NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_free_buf")); 4939 } 4940