1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/nxge/nxge_impl.h> 29 #include <inet/common.h> 30 #include <inet/mi.h> 31 #include <inet/nd.h> 32 33 extern uint64_t npi_debug_level; 34 35 #define NXGE_PARAM_MAC_RW \ 36 NXGE_PARAM_RW | NXGE_PARAM_MAC | \ 37 NXGE_PARAM_NDD_WR_OK | NXGE_PARAM_READ_PROP 38 39 #define NXGE_PARAM_MAC_DONT_SHOW \ 40 NXGE_PARAM_RW | NXGE_PARAM_MAC | NXGE_PARAM_DONT_SHOW 41 42 #define NXGE_PARAM_RXDMA_RW \ 43 NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_NDD_WR_OK | \ 44 NXGE_PARAM_READ_PROP 45 46 #define NXGE_PARAM_RXDMA_RWC \ 47 NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_INIT_ONLY | \ 48 NXGE_PARAM_READ_PROP 49 50 #define NXGE_PARAM_L2CLASS_CFG \ 51 NXGE_PARAM_RW | NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_READ_PROP | \ 52 NXGE_PARAM_NDD_WR_OK 53 54 #define NXGE_PARAM_CLASS_RWS \ 55 NXGE_PARAM_RWS | NXGE_PARAM_READ_PROP 56 57 #define NXGE_PARAM_ARRAY_INIT_SIZE 0x20ULL 58 59 #define SET_RX_INTR_TIME_DISABLE 0 60 #define SET_RX_INTR_TIME_ENABLE 1 61 #define SET_RX_INTR_PKTS 2 62 63 #define BASE_ANY 0 64 #define BASE_BINARY 2 65 #define BASE_HEX 16 66 #define BASE_DECIMAL 10 67 #define ALL_FF_64 0xFFFFFFFFFFFFFFFFULL 68 #define ALL_FF_32 0xFFFFFFFFUL 69 70 #define NXGE_NDD_INFODUMP_BUFF_SIZE 2048 /* is 2k enough? */ 71 #define NXGE_NDD_INFODUMP_BUFF_8K 8192 72 #define NXGE_NDD_INFODUMP_BUFF_16K 0x2000 73 #define NXGE_NDD_INFODUMP_BUFF_64K 0x8000 74 75 #define PARAM_OUTOF_RANGE(vptr, eptr, rval, pa) \ 76 ((vptr == eptr) || (rval < pa->minimum) || (rval > pa->maximum)) 77 78 #define ADVANCE_PRINT_BUFFER(pmp, plen, rlen) { \ 79 ((mblk_t *)pmp)->b_wptr += plen; \ 80 rlen -= plen; \ 81 } 82 83 static int nxge_param_rx_intr_pkts(p_nxge_t, queue_t *, 84 mblk_t *, char *, caddr_t); 85 static int nxge_param_rx_intr_time(p_nxge_t, queue_t *, 86 mblk_t *, char *, caddr_t); 87 static int nxge_param_set_mac(p_nxge_t, queue_t *, 88 mblk_t *, char *, caddr_t); 89 static int nxge_param_set_port_rdc(p_nxge_t, queue_t *, 90 mblk_t *, char *, caddr_t); 91 static int nxge_param_set_grp_rdc(p_nxge_t, queue_t *, 92 mblk_t *, char *, caddr_t); 93 static int nxge_param_set_ether_usr(p_nxge_t, 94 queue_t *, mblk_t *, char *, caddr_t); 95 static int nxge_param_set_ip_usr(p_nxge_t, 96 queue_t *, mblk_t *, char *, caddr_t); 97 static int nxge_param_set_ip_opt(p_nxge_t, 98 queue_t *, mblk_t *, char *, caddr_t); 99 static int nxge_param_set_vlan_rdcgrp(p_nxge_t, 100 queue_t *, mblk_t *, char *, caddr_t); 101 static int nxge_param_set_mac_rdcgrp(p_nxge_t, 102 queue_t *, mblk_t *, char *, caddr_t); 103 static int nxge_param_fflp_hash_init(p_nxge_t, 104 queue_t *, mblk_t *, char *, caddr_t); 105 static int nxge_param_llc_snap_enable(p_nxge_t, queue_t *, 106 mblk_t *, char *, caddr_t); 107 static int nxge_param_hash_lookup_enable(p_nxge_t, queue_t *, 108 mblk_t *, char *, caddr_t); 109 static int nxge_param_tcam_enable(p_nxge_t, queue_t *, 110 mblk_t *, char *, caddr_t); 111 static int nxge_param_get_fw_ver(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 112 static int nxge_param_get_rxdma_info(p_nxge_t, queue_t *q, 113 p_mblk_t, caddr_t); 114 static int nxge_param_get_txdma_info(p_nxge_t, queue_t *q, 115 p_mblk_t, caddr_t); 116 static int nxge_param_get_vlan_rdcgrp(p_nxge_t, queue_t *, 117 p_mblk_t, caddr_t); 118 static int nxge_param_get_mac_rdcgrp(p_nxge_t, queue_t *, 119 p_mblk_t, caddr_t); 120 static int nxge_param_get_rxdma_rdcgrp_info(p_nxge_t, queue_t *, 121 p_mblk_t, caddr_t); 122 static int nxge_param_get_ip_opt(p_nxge_t, queue_t *, mblk_t *, caddr_t); 123 static int nxge_param_get_mac(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 124 static int nxge_param_get_debug_flag(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 125 static int nxge_param_set_nxge_debug_flag(p_nxge_t, queue_t *, mblk_t *, 126 char *, caddr_t); 127 static int nxge_param_set_npi_debug_flag(p_nxge_t, 128 queue_t *, mblk_t *, char *, caddr_t); 129 static int nxge_param_dump_rdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 130 static int nxge_param_dump_tdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 131 static int nxge_param_dump_mac_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 132 static int nxge_param_dump_ipp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 133 static int nxge_param_dump_fflp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 134 static int nxge_param_dump_vlan_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 135 static int nxge_param_dump_rdc_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 136 static int nxge_param_dump_ptrs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 137 static boolean_t nxge_param_link_update(p_nxge_t); 138 139 /* 140 * Global array of Neptune changable parameters. 141 * This array is initialized to correspond to the default 142 * Neptune 4 port configuration. This array would be copied 143 * into each port's parameter structure and modifed per 144 * fcode and nxge.conf configuration. Later, the parameters are 145 * exported to ndd to display and run-time configuration (at least 146 * some of them). 147 * 148 */ 149 150 static nxge_param_t nxge_param_arr[] = { 151 /* 152 * min max value old hw-name conf-name 153 */ 154 { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 155 0, 999, 1000, 0, "instance", "instance"}, 156 157 { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 158 0, 999, 1000, 0, "main-instance", "main_instance"}, 159 160 { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 161 0, 3, 0, 0, "function-number", "function_number"}, 162 163 /* Partition Id */ 164 { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 165 0, 8, 0, 0, "partition-id", "partition_id"}, 166 167 /* Read Write Permission Mode */ 168 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 169 0, 2, 0, 0, "read-write-mode", "read_write_mode"}, 170 171 { nxge_param_get_fw_ver, NULL, NXGE_PARAM_READ, 172 0, 32, 0, 0, "version", "fw_version"}, 173 174 /* hw cfg types */ 175 /* control the DMA config of Neptune/NIU */ 176 { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 177 CFG_DEFAULT, CFG_CUSTOM, CFG_DEFAULT, CFG_DEFAULT, 178 "niu-cfg-type", "niu_cfg_type"}, 179 180 /* control the TXDMA config of the Port controlled by tx-quick-cfg */ 181 { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 182 CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 183 "tx-qcfg-type", "tx_qcfg_type"}, 184 185 /* control the RXDMA config of the Port controlled by rx-quick-cfg */ 186 { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 187 CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 188 "rx-qcfg-type", "rx_qcfg_type"}, 189 190 { nxge_param_get_mac, nxge_param_set_mac, 191 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 192 0, 1, 0, 0, "master-cfg-enable", "master_cfg_enable"}, 193 194 { nxge_param_get_mac, nxge_param_set_mac, 195 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 196 0, 1, 0, 0, "master-cfg-value", "master_cfg_value"}, 197 198 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 199 0, 1, 1, 1, "adv-autoneg-cap", "adv_autoneg_cap"}, 200 201 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 202 0, 1, 1, 1, "adv-10gfdx-cap", "adv_10gfdx_cap"}, 203 204 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 205 0, 1, 0, 0, "adv-10ghdx-cap", "adv_10ghdx_cap"}, 206 207 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 208 0, 1, 1, 1, "adv-1000fdx-cap", "adv_1000fdx_cap"}, 209 210 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 211 0, 1, 0, 0, "adv-1000hdx-cap", "adv_1000hdx_cap"}, 212 213 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 214 0, 1, 0, 0, "adv-100T4-cap", "adv_100T4_cap"}, 215 216 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 217 0, 1, 1, 1, "adv-100fdx-cap", "adv_100fdx_cap"}, 218 219 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 220 0, 1, 0, 0, "adv-100hdx-cap", "adv_100hdx_cap"}, 221 222 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 223 0, 1, 1, 1, "adv-10fdx-cap", "adv_10fdx_cap"}, 224 225 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 226 0, 1, 0, 0, "adv-10hdx-cap", "adv_10hdx_cap"}, 227 228 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 229 0, 1, 0, 0, "adv-asmpause-cap", "adv_asmpause_cap"}, 230 231 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 232 0, 1, 0, 0, "adv-pause-cap", "adv_pause_cap"}, 233 234 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 235 0, 1, 0, 0, "use-int-xcvr", "use_int_xcvr"}, 236 237 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 238 0, 1, 1, 1, "enable-ipg0", "enable_ipg0"}, 239 240 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 241 0, 255, 8, 8, "ipg0", "ipg0"}, 242 243 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 244 0, 255, 8, 8, "ipg1", "ipg1"}, 245 246 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 247 0, 255, 4, 4, "ipg2", "ipg2"}, 248 249 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 250 0, 1, 0, 0, "accept-jumbo", "accept_jumbo"}, 251 252 /* Transmit DMA channels */ 253 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_READ_PROP, 254 0, 3, 0, 0, "tx-dma-weight", "tx_dma_weight"}, 255 256 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_READ_PROP, 257 0, 31, 0, 0, "tx-dma-channels-begin", "tx_dma_channels_begin"}, 258 259 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_READ_PROP, 260 0, 32, 0, 0, "tx-dma-channels", "tx_dma_channels"}, 261 { nxge_param_get_txdma_info, NULL, 262 NXGE_PARAM_READ | NXGE_PARAM_READ_PROP, 263 0, 32, 0, 0, "tx-dma-info", "tx_dma_info"}, 264 265 /* Receive DMA channels */ 266 { nxge_param_get_generic, NULL, 267 NXGE_PARAM_READ | NXGE_PARAM_READ_PROP, 268 0, 31, 0, 0, "rx-dma-channels-begin", "rx_dma_channels_begin"}, 269 270 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_READ_PROP, 271 0, 32, 0, 0, "rx-dma-channels", "rx_dma_channels"}, 272 273 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_READ_PROP, 274 0, 65535, PT_DRR_WT_DEFAULT_10G, 0, 275 "rx-drr-weight", "rx_drr_weight"}, 276 277 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_READ_PROP, 278 0, 1, 1, 0, "rx-full-header", "rx_full_header"}, 279 280 { nxge_param_get_rxdma_info, NULL, NXGE_PARAM_READ, 281 0, 32, 0, 0, "rx-dma-info", "rx_dma_info"}, 282 283 { nxge_param_get_rxdma_info, NULL, 284 NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 285 NXGE_RBR_RBB_MIN, NXGE_RBR_RBB_MAX, NXGE_RBR_RBB_DEFAULT, 0, 286 "rx-rbr-size", "rx_rbr_size"}, 287 288 { nxge_param_get_rxdma_info, NULL, 289 NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 290 NXGE_RCR_MIN, NXGE_RCR_MAX, NXGE_RCR_DEFAULT, 0, 291 "rx-rcr-size", "rx_rcr_size"}, 292 293 { nxge_param_get_generic, nxge_param_set_port_rdc, NXGE_PARAM_RXDMA_RW, 294 0, 15, 0, 0, "default-port-rdc", "default_port_rdc"}, 295 296 { nxge_param_get_generic, nxge_param_rx_intr_time, NXGE_PARAM_RXDMA_RW, 297 NXGE_RDC_RCR_TIMEOUT_MIN, NXGE_RDC_RCR_TIMEOUT_MAX, 298 RXDMA_RCR_TO_DEFAULT, 0, "rxdma-intr-time", "rxdma_intr_time"}, 299 300 { nxge_param_get_generic, nxge_param_rx_intr_pkts, NXGE_PARAM_RXDMA_RW, 301 NXGE_RDC_RCR_THRESHOLD_MIN, NXGE_RDC_RCR_THRESHOLD_MAX, 302 RXDMA_RCR_PTHRES_DEFAULT, 0, 303 "rxdma-intr-pkts", "rxdma_intr_pkts"}, 304 305 { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP, 306 0, 8, 0, 0, "rx-rdc-grps-begin", "rx_rdc_grps_begin"}, 307 308 { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP, 309 0, 8, 0, 0, "rx-rdc-grps", "rx_rdc_grps"}, 310 311 { nxge_param_get_generic, nxge_param_set_grp_rdc, NXGE_PARAM_RXDMA_RW, 312 0, 15, 0, 0, "default-grp0-rdc", "default_grp0_rdc"}, 313 314 { nxge_param_get_generic, nxge_param_set_grp_rdc, NXGE_PARAM_RXDMA_RW, 315 0, 15, 2, 0, "default-grp1-rdc", "default_grp1_rdc"}, 316 317 { nxge_param_get_generic, nxge_param_set_grp_rdc, NXGE_PARAM_RXDMA_RW, 318 0, 15, 4, 0, "default-grp2-rdc", "default_grp2_rdc"}, 319 320 { nxge_param_get_generic, nxge_param_set_grp_rdc, NXGE_PARAM_RXDMA_RW, 321 0, 15, 6, 0, "default-grp3-rdc", "default_grp3_rdc"}, 322 323 { nxge_param_get_generic, nxge_param_set_grp_rdc, NXGE_PARAM_RXDMA_RW, 324 0, 15, 8, 0, "default-grp4-rdc", "default_grp4_rdc"}, 325 326 { nxge_param_get_generic, nxge_param_set_grp_rdc, NXGE_PARAM_RXDMA_RW, 327 0, 15, 10, 0, "default-grp5-rdc", "default_grp5_rdc"}, 328 329 { nxge_param_get_generic, nxge_param_set_grp_rdc, NXGE_PARAM_RXDMA_RW, 330 0, 15, 12, 0, "default-grp6-rdc", "default_grp6_rdc"}, 331 332 { nxge_param_get_generic, nxge_param_set_grp_rdc, NXGE_PARAM_RXDMA_RW, 333 0, 15, 14, 0, "default-grp7-rdc", "default_grp7_rdc"}, 334 335 { nxge_param_get_rxdma_rdcgrp_info, NULL, 336 NXGE_PARAM_READ | NXGE_PARAM_CMPLX, 337 0, 8, 0, 0, "rdc-groups-info", "rdc_groups_info"}, 338 339 /* Logical device groups */ 340 { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 341 0, 63, 0, 0, "start-ldg", "start_ldg"}, 342 343 { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 344 0, 64, 0, 0, "max-ldg", "max_ldg" }, 345 346 /* MAC table information */ 347 { nxge_param_get_mac_rdcgrp, nxge_param_set_mac_rdcgrp, 348 NXGE_PARAM_L2CLASS_CFG, 349 0, 31, 0, 0, "mac-2rdc-grp", "mac_2rdc_grp"}, 350 351 /* VLAN table information */ 352 { nxge_param_get_vlan_rdcgrp, nxge_param_set_vlan_rdcgrp, 353 NXGE_PARAM_L2CLASS_CFG, 354 0, 31, 0, 0, "vlan-2rdc-grp", "vlan_2rdc_grp"}, 355 356 { nxge_param_get_generic, NULL, 357 NXGE_PARAM_READ_PROP | NXGE_PARAM_READ | NXGE_PARAM_PROP_ARR32, 358 0, 0x0ffff, 0x0ffff, 0, "fcram-part-cfg", "fcram_part_cfg"}, 359 360 { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS, 361 0, 0x10, 0xa, 0, "fcram-access-ratio", "fcram_access_ratio"}, 362 363 { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS, 364 0, 0x10, 0xa, 0, "tcam-access-ratio", "tcam_access_ratio"}, 365 366 { nxge_param_get_generic, nxge_param_tcam_enable, 367 NXGE_PARAM_CLASS_RWS, 368 0, 0x1, 0x0, 0, "tcam-enable", "tcam_enable"}, 369 370 { nxge_param_get_generic, nxge_param_hash_lookup_enable, 371 NXGE_PARAM_CLASS_RWS, 372 0, 0x01, 0x0, 0, "hash-lookup-enable", "hash_lookup_enable"}, 373 374 { nxge_param_get_generic, nxge_param_llc_snap_enable, 375 NXGE_PARAM_CLASS_RWS, 376 0, 0x01, 0x01, 0, "llc-snap-enable", "llc_snap_enable"}, 377 378 { nxge_param_get_generic, nxge_param_fflp_hash_init, 379 NXGE_PARAM_CLASS_RWS, 380 0, ALL_FF_32, ALL_FF_32, 0, "h1-init-value", "h1_init_value"}, 381 382 { nxge_param_get_generic, nxge_param_fflp_hash_init, 383 NXGE_PARAM_CLASS_RWS, 384 0, 0x0ffff, 0x0ffff, 0, "h2-init-value", "h2_init_value"}, 385 386 { nxge_param_get_generic, nxge_param_set_ether_usr, 387 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 388 0, ALL_FF_32, 0x0, 0, 389 "class-cfg-ether-usr1", "class_cfg_ether_usr1"}, 390 391 { nxge_param_get_generic, nxge_param_set_ether_usr, 392 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 393 0, ALL_FF_32, 0x0, 0, 394 "class-cfg-ether-usr2", "class_cfg_ether_usr2"}, 395 396 { nxge_param_get_generic, nxge_param_set_ip_usr, 397 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 398 0, ALL_FF_32, 0x0, 0, 399 "class-cfg-ip-usr4", "class_cfg_ip_usr4"}, 400 401 { nxge_param_get_generic, nxge_param_set_ip_usr, 402 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 403 0, ALL_FF_32, 0x0, 0, 404 "class-cfg-ip-usr5", "class_cfg_ip_usr5"}, 405 406 { nxge_param_get_generic, nxge_param_set_ip_usr, 407 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 408 0, ALL_FF_32, 0x0, 0, 409 "class-cfg-ip-usr6", "class_cfg_ip_usr6"}, 410 411 { nxge_param_get_generic, nxge_param_set_ip_usr, 412 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 413 0, ALL_FF_32, 0x0, 0, 414 "class-cfg-ip-usr7", "class_cfg_ip_usr7"}, 415 416 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 417 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 418 0, ALL_FF_32, 0x0, 0, 419 "class-opt-ip-usr4", "class_opt_ip_usr4"}, 420 421 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 422 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 423 0, ALL_FF_32, 0x0, 0, 424 "class-opt-ip-usr5", "class_opt_ip_usr5"}, 425 426 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 427 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 428 0, ALL_FF_32, 0x0, 0, 429 "class-opt-ip-usr6", "class_opt_ip_usr6"}, 430 431 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 432 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 433 0, ALL_FF_32, 0x0, 0, 434 "class-opt-ip-usr7", "class_opt_ip_usr7"}, 435 436 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 437 NXGE_PARAM_CLASS_RWS, 438 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 439 "class-opt-ipv4-tcp", "class_opt_ipv4_tcp"}, 440 441 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 442 NXGE_PARAM_CLASS_RWS, 443 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 444 "class-opt-ipv4-udp", "class_opt_ipv4_udp"}, 445 446 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 447 NXGE_PARAM_CLASS_RWS, 448 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 449 "class-opt-ipv4-ah", "class_opt_ipv4_ah"}, 450 451 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 452 NXGE_PARAM_CLASS_RWS, 453 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 454 "class-opt-ipv4-sctp", "class_opt_ipv4_sctp"}, 455 456 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 457 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 458 "class-opt-ipv6-tcp", "class_opt_ipv6_tcp"}, 459 460 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 461 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 462 "class-opt-ipv6-udp", "class_opt_ipv6_udp"}, 463 464 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 465 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 466 "class-opt-ipv6-ah", "class_opt_ipv6_ah"}, 467 468 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 469 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 470 "class-opt-ipv6-sctp", "class_opt_ipv6_sctp"}, 471 472 { nxge_param_get_debug_flag, nxge_param_set_nxge_debug_flag, 473 NXGE_PARAM_RW, 474 0ULL, ALL_FF_64, 0ULL, 0ULL, 475 "nxge-debug-flag", "nxge_debug_flag"}, 476 477 { nxge_param_get_debug_flag, nxge_param_set_npi_debug_flag, 478 NXGE_PARAM_RW, 479 0ULL, ALL_FF_64, 0ULL, 0ULL, 480 "npi-debug-flag", "npi_debug_flag"}, 481 482 { nxge_param_dump_tdc, NULL, NXGE_PARAM_READ, 483 0, 0x0fffffff, 0x0fffffff, 0, "dump-tdc", "dump_tdc"}, 484 485 { nxge_param_dump_rdc, NULL, NXGE_PARAM_READ, 486 0, 0x0fffffff, 0x0fffffff, 0, "dump-rdc", "dump_rdc"}, 487 488 { nxge_param_dump_mac_regs, NULL, NXGE_PARAM_READ, 489 0, 0x0fffffff, 0x0fffffff, 0, "dump-mac-regs", "dump_mac_regs"}, 490 491 { nxge_param_dump_ipp_regs, NULL, NXGE_PARAM_READ, 492 0, 0x0fffffff, 0x0fffffff, 0, "dump-ipp-regs", "dump_ipp_regs"}, 493 494 { nxge_param_dump_fflp_regs, NULL, NXGE_PARAM_READ, 495 0, 0x0fffffff, 0x0fffffff, 0, 496 "dump-fflp-regs", "dump_fflp_regs"}, 497 498 { nxge_param_dump_vlan_table, NULL, NXGE_PARAM_READ, 499 0, 0x0fffffff, 0x0fffffff, 0, 500 "dump-vlan-table", "dump_vlan_table"}, 501 502 { nxge_param_dump_rdc_table, NULL, NXGE_PARAM_READ, 503 0, 0x0fffffff, 0x0fffffff, 0, 504 "dump-rdc-table", "dump_rdc_table"}, 505 506 { nxge_param_dump_ptrs, NULL, NXGE_PARAM_READ, 507 0, 0x0fffffff, 0x0fffffff, 0, "dump-ptrs", "dump_ptrs"}, 508 509 { NULL, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 510 0, 0x0fffffff, 0x0fffffff, 0, "end", "end"}, 511 }; 512 513 extern void *nxge_list; 514 515 void 516 nxge_get_param_soft_properties(p_nxge_t nxgep) 517 { 518 519 p_nxge_param_t param_arr; 520 uint_t prop_len; 521 int i, j; 522 uint32_t param_count; 523 uint32_t *int_prop_val; 524 525 NXGE_DEBUG_MSG((nxgep, DDI_CTL, " ==> nxge_get_param_soft_properties")); 526 527 param_arr = nxgep->param_arr; 528 param_count = nxgep->param_count; 529 for (i = 0; i < param_count; i++) { 530 if ((param_arr[i].type & NXGE_PARAM_READ_PROP) == 0) 531 continue; 532 if ((param_arr[i].type & NXGE_PARAM_PROP_STR)) 533 continue; 534 if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 535 (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 536 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 537 nxgep->dip, 0, param_arr[i].fcode_name, 538 (int **)&int_prop_val, 539 (uint_t *)&prop_len) 540 == DDI_PROP_SUCCESS) { 541 uint32_t *cfg_value; 542 uint64_t prop_count; 543 544 if (prop_len > NXGE_PARAM_ARRAY_INIT_SIZE) 545 prop_len = NXGE_PARAM_ARRAY_INIT_SIZE; 546 cfg_value = (uint32_t *)param_arr[i].value; 547 for (j = 0; j < prop_len; j++) { 548 cfg_value[j] = int_prop_val[j]; 549 } 550 prop_count = prop_len; 551 param_arr[i].type |= 552 (prop_count << NXGE_PARAM_ARRAY_CNT_SHIFT); 553 ddi_prop_free(int_prop_val); 554 } 555 continue; 556 } 557 558 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 559 param_arr[i].fcode_name, 560 (int **)&int_prop_val, 561 &prop_len) == DDI_PROP_SUCCESS) { 562 if ((*int_prop_val >= param_arr[i].minimum) && 563 (*int_prop_val <= param_arr[i].maximum)) 564 param_arr[i].value = *int_prop_val; 565 #ifdef NXGE_DEBUG_ERROR 566 else { 567 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 568 "nxge%d: 'prom' file parameter error\n", 569 nxgep->instance)); 570 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 571 "Parameter keyword '%s'" 572 " is outside valid range\n", 573 param_arr[i].name)); 574 } 575 #endif 576 ddi_prop_free(int_prop_val); 577 } 578 579 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 580 param_arr[i].name, 581 (int **)&int_prop_val, 582 &prop_len) == DDI_PROP_SUCCESS) { 583 if ((*int_prop_val >= param_arr[i].minimum) && 584 (*int_prop_val <= param_arr[i].maximum)) 585 param_arr[i].value = *int_prop_val; 586 #ifdef NXGE_DEBUG_ERROR 587 else { 588 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 589 "nxge%d: 'conf' file parameter error\n", 590 nxgep->instance)); 591 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 592 "Parameter keyword '%s'" 593 "is outside valid range\n", 594 param_arr[i].name)); 595 } 596 #endif 597 ddi_prop_free(int_prop_val); 598 } 599 } 600 } 601 602 static int 603 nxge_private_param_register(p_nxge_t nxgep, p_nxge_param_t param_arr) 604 { 605 int status = B_TRUE; 606 int channel; 607 uint8_t grp; 608 char *prop_name; 609 char *end; 610 uint32_t name_chars; 611 612 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 613 "nxge_private_param_register %s", param_arr->name)); 614 615 if ((param_arr->type & NXGE_PARAM_PRIV) != NXGE_PARAM_PRIV) 616 return (B_TRUE); 617 618 prop_name = param_arr->name; 619 if (param_arr->type & NXGE_PARAM_RXDMA) { 620 if (strncmp("rxdma_intr", prop_name, 10) == 0) 621 return (B_TRUE); 622 name_chars = strlen("default_grp"); 623 if (strncmp("default_grp", prop_name, name_chars) == 0) { 624 prop_name += name_chars; 625 grp = mi_strtol(prop_name, &end, 10); 626 /* now check if this rdcgrp is in config */ 627 return (nxge_check_rdcgrp_port_member(nxgep, grp)); 628 } 629 name_chars = strlen(prop_name); 630 if (strncmp("default_port_rdc", prop_name, name_chars) == 0) { 631 return (B_TRUE); 632 } 633 return (B_FALSE); 634 } 635 636 if (param_arr->type & NXGE_PARAM_TXDMA) { 637 name_chars = strlen("txdma"); 638 if (strncmp("txdma", prop_name, name_chars) == 0) { 639 prop_name += name_chars; 640 channel = mi_strtol(prop_name, &end, 10); 641 /* now check if this rdc is in config */ 642 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 643 " nxge_private_param_register: %d", 644 channel)); 645 return (nxge_check_txdma_port_member(nxgep, channel)); 646 } 647 return (B_FALSE); 648 } 649 650 status = B_FALSE; 651 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, "<== nxge_private_param_register")); 652 653 return (status); 654 } 655 656 void 657 nxge_setup_param(p_nxge_t nxgep) 658 { 659 p_nxge_param_t param_arr; 660 int i; 661 pfi_t set_pfi; 662 663 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_setup_param")); 664 665 /* 666 * Make sure the param_instance is set to a valid device instance. 667 */ 668 if (nxge_param_arr[param_instance].value == 1000) 669 nxge_param_arr[param_instance].value = nxgep->instance; 670 671 param_arr = nxgep->param_arr; 672 param_arr[param_instance].value = nxgep->instance; 673 param_arr[param_function_number].value = nxgep->function_num; 674 675 for (i = 0; i < nxgep->param_count; i++) { 676 if ((param_arr[i].type & NXGE_PARAM_PRIV) && 677 (nxge_private_param_register(nxgep, 678 ¶m_arr[i]) == B_FALSE)) { 679 param_arr[i].setf = NULL; 680 param_arr[i].getf = NULL; 681 } 682 683 if (param_arr[i].type & NXGE_PARAM_CMPLX) 684 param_arr[i].setf = NULL; 685 686 if (param_arr[i].type & NXGE_PARAM_DONT_SHOW) { 687 param_arr[i].setf = NULL; 688 param_arr[i].getf = NULL; 689 } 690 691 set_pfi = (pfi_t)param_arr[i].setf; 692 693 if ((set_pfi) && (param_arr[i].type & NXGE_PARAM_INIT_ONLY)) { 694 set_pfi = NULL; 695 } 696 697 if (!nxge_nd_load(&nxgep->param_list, param_arr[i].name, 698 (pfi_t)param_arr[i].getf, set_pfi, 699 (caddr_t)¶m_arr[i])) { 700 (void) nxge_nd_free(&nxgep->param_list); 701 break; 702 } 703 } 704 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_setup_param")); 705 } 706 707 void 708 nxge_init_param(p_nxge_t nxgep) 709 { 710 p_nxge_param_t param_arr; 711 int i, alloc_size; 712 uint64_t alloc_count; 713 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_init_param")); 714 /* 715 * Make sure the param_instance is set to a valid device instance. 716 */ 717 if (nxge_param_arr[param_instance].value == 1000) 718 nxge_param_arr[param_instance].value = nxgep->instance; 719 720 param_arr = nxgep->param_arr; 721 if (param_arr == NULL) { 722 param_arr = (p_nxge_param_t) 723 KMEM_ZALLOC(sizeof (nxge_param_arr), KM_SLEEP); 724 } 725 726 for (i = 0; i < sizeof (nxge_param_arr)/sizeof (nxge_param_t); i++) { 727 param_arr[i] = nxge_param_arr[i]; 728 if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 729 (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 730 alloc_count = NXGE_PARAM_ARRAY_INIT_SIZE; 731 alloc_size = alloc_count * sizeof (uint64_t); 732 param_arr[i].value = 733 (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 734 param_arr[i].old_value = 735 (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 736 param_arr[i].type |= 737 (alloc_count << NXGE_PARAM_ARRAY_ALLOC_SHIFT); 738 } 739 } 740 741 nxgep->param_arr = param_arr; 742 nxgep->param_count = sizeof (nxge_param_arr)/sizeof (nxge_param_t); 743 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init_param: count %d", 744 nxgep->param_count)); 745 } 746 747 void 748 nxge_destroy_param(p_nxge_t nxgep) 749 { 750 int i; 751 uint64_t free_size, free_count; 752 753 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_param")); 754 755 /* 756 * Make sure the param_instance is set to a valid device instance. 757 */ 758 if (nxge_param_arr[param_instance].value == nxgep->instance) { 759 for (i = 0; i <= nxge_param_arr[param_instance].maximum; i++) { 760 if ((ddi_get_soft_state(nxge_list, i) != NULL) && 761 (i != nxgep->instance)) 762 break; 763 } 764 nxge_param_arr[param_instance].value = i; 765 } 766 767 if (nxgep->param_list) 768 nxge_nd_free(&nxgep->param_list); 769 for (i = 0; i < nxgep->param_count; i++) 770 if ((nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 771 (nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 772 free_count = ((nxgep->param_arr[i].type & 773 NXGE_PARAM_ARRAY_ALLOC_MASK) >> 774 NXGE_PARAM_ARRAY_ALLOC_SHIFT); 775 free_count = NXGE_PARAM_ARRAY_INIT_SIZE; 776 free_size = sizeof (uint64_t) * free_count; 777 KMEM_FREE((void *)nxgep->param_arr[i].value, free_size); 778 KMEM_FREE((void *)nxgep->param_arr[i].old_value, 779 free_size); 780 } 781 782 KMEM_FREE(nxgep->param_arr, sizeof (nxge_param_arr)); 783 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_param")); 784 } 785 786 /* 787 * Extracts the value from the 'nxge' parameter array and prints the 788 * parameter value. cp points to the required parameter. 789 */ 790 791 /* ARGSUSED */ 792 int 793 nxge_param_get_generic(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 794 { 795 p_nxge_param_t pa = (p_nxge_param_t)cp; 796 797 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 798 "==> nxge_param_get_generic name %s ", pa->name)); 799 800 if (pa->value > 0xffffffff) 801 (void) mi_mpprintf(mp, "%x%x", 802 (int)(pa->value >> 32), (int)(pa->value & 0xffffffff)); 803 else 804 (void) mi_mpprintf(mp, "%x", (int)pa->value); 805 806 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_generic")); 807 return (0); 808 } 809 810 /* ARGSUSED */ 811 static int 812 nxge_param_get_mac(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 813 { 814 p_nxge_param_t pa = (p_nxge_param_t)cp; 815 816 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac")); 817 818 (void) mi_mpprintf(mp, "%d", (uint32_t)pa->value); 819 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_mac")); 820 return (0); 821 } 822 823 /* ARGSUSED */ 824 static int 825 nxge_param_get_fw_ver(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 826 { 827 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_fw_ver")); 828 829 (void) mi_mpprintf(mp, "Firmware version for nxge%d: %s\n", 830 nxgep->instance, nxgep->vpd_info.ver); 831 832 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_fw_ver")); 833 return (0); 834 } 835 836 /* ARGSUSED */ 837 int 838 nxge_param_get_txdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 839 { 840 841 uint_t print_len, buf_len; 842 p_mblk_t np; 843 int tdc; 844 845 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 846 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_txdma_info")); 847 848 (void) mi_mpprintf(mp, "TXDMA Information for Port\t %d \n", 849 nxgep->function_num); 850 851 852 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 853 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 854 return (0); 855 } 856 857 buf_len = buff_alloc_size; 858 mp->b_cont = np; 859 860 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 861 "Total TDCs\t %d\n", nxgep->ntdc); 862 863 ((mblk_t *)np)->b_wptr += print_len; 864 buf_len -= print_len; 865 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 866 "TDC\t HW TDC\t\n"); 867 ((mblk_t *)np)->b_wptr += print_len; 868 869 buf_len -= print_len; 870 for (tdc = 0; tdc < nxgep->ntdc; tdc++) { 871 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 872 buf_len, "%d\t %d\n", 873 tdc, nxgep->tdc[tdc]); 874 ((mblk_t *)np)->b_wptr += print_len; 875 buf_len -= print_len; 876 } 877 878 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_txdma_info")); 879 return (0); 880 } 881 882 /* ARGSUSED */ 883 int 884 nxge_param_get_rxdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 885 { 886 uint_t print_len, buf_len; 887 p_mblk_t np; 888 int rdc; 889 p_nxge_dma_pt_cfg_t p_dma_cfgp; 890 p_nxge_hw_pt_cfg_t p_cfgp; 891 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 892 p_rx_rcr_rings_t rx_rcr_rings; 893 p_rx_rcr_ring_t *rcr_rings; 894 p_rx_rbr_rings_t rx_rbr_rings; 895 p_rx_rbr_ring_t *rbr_rings; 896 897 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rxdma_info")); 898 899 (void) mi_mpprintf(mp, "RXDMA Information for Port\t %d \n", 900 nxgep->function_num); 901 902 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 903 /* The following may work even if we cannot get a large buf. */ 904 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 905 return (0); 906 } 907 908 buf_len = buff_alloc_size; 909 mp->b_cont = np; 910 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 911 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 912 913 rx_rcr_rings = nxgep->rx_rcr_rings; 914 rcr_rings = rx_rcr_rings->rcr_rings; 915 rx_rbr_rings = nxgep->rx_rbr_rings; 916 rbr_rings = rx_rbr_rings->rbr_rings; 917 918 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 919 "Total RDCs\t %d\n", p_cfgp->max_rdcs); 920 921 ((mblk_t *)np)->b_wptr += print_len; 922 buf_len -= print_len; 923 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 924 "RDC\t HW RDC\t Timeout\t Packets RBR ptr \t" 925 "chunks\t RCR ptr\n"); 926 927 ((mblk_t *)np)->b_wptr += print_len; 928 buf_len -= print_len; 929 for (rdc = 0; rdc < p_cfgp->max_rdcs; rdc++) { 930 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 931 " %d\t %d\t %x\t\t %x\t $%p\t 0x%x\t $%p\n", 932 rdc, nxgep->rdc[rdc], 933 p_dma_cfgp->rcr_timeout[rdc], 934 p_dma_cfgp->rcr_threshold[rdc], 935 rbr_rings[rdc], 936 rbr_rings[rdc]->num_blocks, rcr_rings[rdc]); 937 ((mblk_t *)np)->b_wptr += print_len; 938 buf_len -= print_len; 939 } 940 941 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rxdma_info")); 942 return (0); 943 } 944 945 /* ARGSUSED */ 946 int 947 nxge_param_get_rxdma_rdcgrp_info(p_nxge_t nxgep, queue_t *q, 948 p_mblk_t mp, caddr_t cp) 949 { 950 uint_t print_len, buf_len; 951 p_mblk_t np; 952 int offset, rdc, i, rdc_grp; 953 p_nxge_rdc_grp_t rdc_grp_p; 954 p_nxge_dma_pt_cfg_t p_dma_cfgp; 955 p_nxge_hw_pt_cfg_t p_cfgp; 956 957 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 958 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 959 "==> nxge_param_get_rxdma_rdcgrp_info")); 960 961 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 962 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 963 964 (void) mi_mpprintf(mp, "RXDMA RDC Group Information for Port\t %d \n", 965 nxgep->function_num); 966 967 rdc_grp = p_cfgp->start_rdc_grpid; 968 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 969 /* The following may work even if we cannot get a large buf. */ 970 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 971 return (0); 972 } 973 974 buf_len = buff_alloc_size; 975 mp->b_cont = np; 976 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 977 "Total RDC Groups\t %d \n" 978 "start RDC group\t %d\n", 979 p_cfgp->max_rdc_grpids, 980 p_cfgp->start_rdc_grpid); 981 982 ((mblk_t *)np)->b_wptr += print_len; 983 buf_len -= print_len; 984 985 for (i = 0, rdc_grp = p_cfgp->start_rdc_grpid; 986 rdc_grp < (p_cfgp->max_rdc_grpids + p_cfgp->start_rdc_grpid); 987 rdc_grp++, i++) { 988 rdc_grp_p = &p_dma_cfgp->rdc_grps[i]; 989 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 990 "\nRDC Group Info for Group [%d] %d\n" 991 "RDC Count %d\tstart RDC %d\n" 992 "RDC Group Population Information" 993 " (offsets 0 - 15)\n", 994 i, rdc_grp, rdc_grp_p->max_rdcs, 995 rdc_grp_p->start_rdc); 996 997 ((mblk_t *)np)->b_wptr += print_len; 998 buf_len -= print_len; 999 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1000 buf_len, "\n"); 1001 ((mblk_t *)np)->b_wptr += print_len; 1002 buf_len -= print_len; 1003 1004 for (rdc = 0; rdc < rdc_grp_p->max_rdcs; rdc++) { 1005 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1006 buf_len, "[%d]=%d ", rdc, 1007 rdc_grp_p->start_rdc + rdc); 1008 ((mblk_t *)np)->b_wptr += print_len; 1009 buf_len -= print_len; 1010 } 1011 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1012 buf_len, "\n"); 1013 ((mblk_t *)np)->b_wptr += print_len; 1014 buf_len -= print_len; 1015 1016 for (offset = 0; offset < 16; offset++) { 1017 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1018 buf_len, " %2d ", 1019 rdc_grp_p->rdc[offset]); 1020 ((mblk_t *)np)->b_wptr += print_len; 1021 buf_len -= print_len; 1022 } 1023 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1024 buf_len, "\n"); 1025 ((mblk_t *)np)->b_wptr += print_len; 1026 buf_len -= print_len; 1027 } 1028 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1029 "<== nxge_param_get_rxdma_rdcgrp_info")); 1030 return (0); 1031 } 1032 1033 int 1034 nxge_mk_mblk_tail_space(p_mblk_t mp, p_mblk_t *nmp, size_t size) 1035 { 1036 p_mblk_t tmp; 1037 1038 tmp = mp; 1039 while (tmp->b_cont) 1040 tmp = tmp->b_cont; 1041 if ((tmp->b_wptr + size) >= tmp->b_datap->db_lim) { 1042 tmp->b_cont = allocb(1024, BPRI_HI); 1043 tmp = tmp->b_cont; 1044 if (!tmp) 1045 return (ENOMEM); 1046 } 1047 1048 *nmp = tmp; 1049 return (0); 1050 } 1051 1052 /* 1053 * Sets the ge parameter to the value in the nxge_param_register using 1054 * nxge_nd_load(). 1055 */ 1056 1057 /* ARGSUSED */ 1058 int 1059 nxge_param_set_generic(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1060 char *value, caddr_t cp) 1061 { 1062 char *end; 1063 uint32_t new_value; 1064 p_nxge_param_t pa = (p_nxge_param_t)cp; 1065 1066 NXGE_DEBUG_MSG((nxgep, IOC_CTL, " ==> nxge_param_set_generic")); 1067 new_value = (uint32_t)mi_strtol(value, &end, 10); 1068 if (end == value || new_value < pa->minimum || 1069 new_value > pa->maximum) { 1070 return (EINVAL); 1071 } 1072 pa->value = new_value; 1073 NXGE_DEBUG_MSG((nxgep, IOC_CTL, " <== nxge_param_set_generic")); 1074 return (0); 1075 } 1076 1077 /* 1078 * Sets the ge parameter to the value in the nxge_param_register using 1079 * nxge_nd_load(). 1080 */ 1081 1082 /* ARGSUSED */ 1083 int 1084 nxge_param_set_instance(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1085 char *value, caddr_t cp) 1086 { 1087 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " ==> nxge_param_set_instance")); 1088 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_set_instance")); 1089 return (0); 1090 } 1091 1092 /* 1093 * Sets the ge parameter to the value in the nxge_param_register using 1094 * nxge_nd_load(). 1095 */ 1096 1097 /* ARGSUSED */ 1098 int 1099 nxge_param_set_mac(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1100 char *value, caddr_t cp) 1101 { 1102 char *end; 1103 uint32_t new_value; 1104 int status = 0; 1105 p_nxge_param_t pa = (p_nxge_param_t)cp; 1106 1107 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac")); 1108 new_value = (uint32_t)mi_strtol(value, &end, BASE_DECIMAL); 1109 if (PARAM_OUTOF_RANGE(value, end, new_value, pa)) { 1110 return (EINVAL); 1111 } 1112 1113 if (pa->value != new_value) { 1114 pa->old_value = pa->value; 1115 pa->value = new_value; 1116 } 1117 1118 if (!nxge_param_link_update(nxgep)) { 1119 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1120 " false ret from nxge_param_link_update")); 1121 status = EINVAL; 1122 } 1123 1124 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac")); 1125 return (status); 1126 } 1127 1128 /* ARGSUSED */ 1129 static int 1130 nxge_param_rx_intr_pkts(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1131 char *value, caddr_t cp) 1132 { 1133 char *end; 1134 uint32_t cfg_value; 1135 p_nxge_param_t pa = (p_nxge_param_t)cp; 1136 1137 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_pkts")); 1138 1139 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1140 1141 if ((cfg_value > NXGE_RDC_RCR_THRESHOLD_MAX) || 1142 (cfg_value < NXGE_RDC_RCR_THRESHOLD_MIN)) { 1143 return (EINVAL); 1144 } 1145 1146 if ((pa->value != cfg_value)) { 1147 pa->old_value = pa->value; 1148 pa->value = cfg_value; 1149 nxgep->intr_threshold = pa->value; 1150 } 1151 1152 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_pkts")); 1153 return (0); 1154 } 1155 1156 /* ARGSUSED */ 1157 static int 1158 nxge_param_rx_intr_time(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1159 char *value, caddr_t cp) 1160 { 1161 char *end; 1162 uint32_t cfg_value; 1163 p_nxge_param_t pa = (p_nxge_param_t)cp; 1164 1165 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_time")); 1166 1167 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1168 1169 if ((cfg_value > NXGE_RDC_RCR_TIMEOUT_MAX) || 1170 (cfg_value < NXGE_RDC_RCR_TIMEOUT_MIN)) { 1171 return (EINVAL); 1172 } 1173 1174 if ((pa->value != cfg_value)) { 1175 pa->old_value = pa->value; 1176 pa->value = cfg_value; 1177 nxgep->intr_timeout = pa->value; 1178 } 1179 1180 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_time")); 1181 return (0); 1182 } 1183 1184 /* ARGSUSED */ 1185 static int 1186 nxge_param_set_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1187 mblk_t *mp, char *value, caddr_t cp) 1188 { 1189 char *end; 1190 uint32_t status = 0, cfg_value; 1191 p_nxge_param_t pa = (p_nxge_param_t)cp; 1192 uint32_t cfg_it = B_FALSE; 1193 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1194 p_nxge_hw_pt_cfg_t p_cfgp; 1195 uint32_t *val_ptr, *old_val_ptr; 1196 nxge_param_map_t *mac_map; 1197 p_nxge_class_pt_cfg_t p_class_cfgp; 1198 nxge_mv_cfg_t *mac_host_info; 1199 1200 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac_rdcgrp ")); 1201 1202 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1203 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1204 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1205 mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 1206 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1207 1208 /* 1209 * now do decoding 1210 */ 1211 mac_map = (nxge_param_map_t *)&cfg_value; 1212 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " cfg_value %x id %x map_to %x", 1213 cfg_value, mac_map->param_id, mac_map->map_to)); 1214 1215 if ((mac_map->param_id < p_cfgp->max_macs) && 1216 (mac_map->map_to < (p_cfgp->max_rdc_grpids + 1217 p_cfgp->start_rdc_grpid)) && (mac_map->map_to >= 1218 p_cfgp->start_rdc_grpid)) { 1219 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1220 " nxge_param_set_mac_rdcgrp mapping" 1221 " id %d grp %d", mac_map->param_id, mac_map->map_to)); 1222 val_ptr = (uint32_t *)pa->value; 1223 old_val_ptr = (uint32_t *)pa->old_value; 1224 if (val_ptr[mac_map->param_id] != cfg_value) { 1225 old_val_ptr[mac_map->param_id] = 1226 val_ptr[mac_map->param_id]; 1227 val_ptr[mac_map->param_id] = cfg_value; 1228 mac_host_info[mac_map->param_id].mpr_npr = 1229 mac_map->pref; 1230 mac_host_info[mac_map->param_id].flag = 1; 1231 mac_host_info[mac_map->param_id].rdctbl = 1232 mac_map->map_to; 1233 cfg_it = B_TRUE; 1234 } 1235 } else { 1236 return (EINVAL); 1237 } 1238 1239 if (cfg_it == B_TRUE) { 1240 status = nxge_logical_mac_assign_rdc_table(nxgep, 1241 (uint8_t)mac_map->param_id); 1242 if (status != NXGE_OK) 1243 return (EINVAL); 1244 } 1245 1246 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac_rdcgrp")); 1247 return (0); 1248 } 1249 1250 /* ARGSUSED */ 1251 static int 1252 nxge_param_set_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1253 mblk_t *mp, char *value, caddr_t cp) 1254 { 1255 char *end; 1256 uint32_t status = 0, cfg_value; 1257 p_nxge_param_t pa = (p_nxge_param_t)cp; 1258 uint32_t cfg_it = B_FALSE; 1259 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1260 p_nxge_hw_pt_cfg_t p_cfgp; 1261 uint32_t *val_ptr, *old_val_ptr; 1262 nxge_param_map_t *vmap, *old_map; 1263 p_nxge_class_pt_cfg_t p_class_cfgp; 1264 uint64_t cfgd_vlans; 1265 int i, inc = 0, cfg_position; 1266 nxge_mv_cfg_t *vlan_tbl; 1267 1268 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 1269 1270 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1271 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1272 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1273 vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 1274 1275 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1276 1277 /* now do decoding */ 1278 cfgd_vlans = ((pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 1279 NXGE_PARAM_ARRAY_CNT_SHIFT); 1280 1281 if (cfgd_vlans == NXGE_PARAM_ARRAY_INIT_SIZE) { 1282 /* 1283 * for now, we process only upto max 1284 * NXGE_PARAM_ARRAY_INIT_SIZE parameters 1285 * In the future, we may want to expand 1286 * the storage array and continue 1287 */ 1288 return (EINVAL); 1289 } 1290 1291 vmap = (nxge_param_map_t *)&cfg_value; 1292 if ((vmap->param_id) && 1293 (vmap->param_id < NXGE_MAX_VLANS) && 1294 (vmap->map_to < p_cfgp->max_rdc_grpids)) { 1295 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1296 "nxge_param_set_vlan_rdcgrp mapping" 1297 " id %d grp %d", 1298 vmap->param_id, vmap->map_to)); 1299 val_ptr = (uint32_t *)pa->value; 1300 old_val_ptr = (uint32_t *)pa->old_value; 1301 1302 /* search to see if this vlan id is already configured */ 1303 for (i = 0; i < cfgd_vlans; i++) { 1304 old_map = (nxge_param_map_t *)&val_ptr[i]; 1305 if ((old_map->param_id == 0) || 1306 (vmap->param_id == old_map->param_id) || 1307 (vlan_tbl[vmap->param_id].flag)) { 1308 cfg_position = i; 1309 break; 1310 } 1311 } 1312 1313 if (cfgd_vlans == 0) { 1314 cfg_position = 0; 1315 inc++; 1316 } 1317 1318 if (i == cfgd_vlans) { 1319 cfg_position = i; 1320 inc++; 1321 } 1322 1323 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 1324 "set_vlan_rdcgrp mapping" 1325 " i %d cfgd_vlans %llx position %d ", 1326 i, cfgd_vlans, cfg_position)); 1327 if (val_ptr[cfg_position] != cfg_value) { 1328 old_val_ptr[cfg_position] = val_ptr[cfg_position]; 1329 val_ptr[cfg_position] = cfg_value; 1330 vlan_tbl[vmap->param_id].mpr_npr = vmap->pref; 1331 vlan_tbl[vmap->param_id].flag = 1; 1332 vlan_tbl[vmap->param_id].rdctbl = 1333 vmap->map_to + p_cfgp->start_rdc_grpid; 1334 cfg_it = B_TRUE; 1335 if (inc) { 1336 cfgd_vlans++; 1337 pa->type &= ~NXGE_PARAM_ARRAY_CNT_MASK; 1338 pa->type |= (cfgd_vlans << 1339 NXGE_PARAM_ARRAY_CNT_SHIFT); 1340 1341 } 1342 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 1343 "after: param_set_vlan_rdcgrp " 1344 " cfg_vlans %llx position %d \n", 1345 cfgd_vlans, cfg_position)); 1346 } 1347 } else { 1348 return (EINVAL); 1349 } 1350 1351 if (cfg_it == B_TRUE) { 1352 status = nxge_fflp_config_vlan_table(nxgep, 1353 (uint16_t)vmap->param_id); 1354 if (status != NXGE_OK) 1355 return (EINVAL); 1356 } 1357 1358 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_vlan_rdcgrp")); 1359 return (0); 1360 } 1361 1362 /* ARGSUSED */ 1363 static int 1364 nxge_param_get_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1365 mblk_t *mp, caddr_t cp) 1366 { 1367 1368 uint_t print_len, buf_len; 1369 p_mblk_t np; 1370 int i; 1371 uint32_t *val_ptr; 1372 nxge_param_map_t *vmap; 1373 p_nxge_param_t pa = (p_nxge_param_t)cp; 1374 p_nxge_class_pt_cfg_t p_class_cfgp; 1375 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1376 p_nxge_hw_pt_cfg_t p_cfgp; 1377 uint64_t cfgd_vlans = 0; 1378 nxge_mv_cfg_t *vlan_tbl; 1379 int buff_alloc_size = 1380 NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 1381 1382 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 1383 (void) mi_mpprintf(mp, "VLAN RDC Mapping Information for Port\t %d \n", 1384 nxgep->function_num); 1385 1386 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1387 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1388 return (0); 1389 } 1390 1391 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1392 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1393 1394 buf_len = buff_alloc_size; 1395 mp->b_cont = np; 1396 cfgd_vlans = (pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 1397 NXGE_PARAM_ARRAY_CNT_SHIFT; 1398 1399 i = (int)cfgd_vlans; 1400 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1401 vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 1402 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1403 "Configured VLANs %d\n" 1404 "VLAN ID\t RDC GRP (Actual/Port)\t" 1405 " Prefernce\n", i); 1406 ((mblk_t *)np)->b_wptr += print_len; 1407 buf_len -= print_len; 1408 1409 val_ptr = (uint32_t *)pa->value; 1410 1411 for (i = 0; i < cfgd_vlans; i++) { 1412 vmap = (nxge_param_map_t *)&val_ptr[i]; 1413 if (p_class_cfgp->vlan_tbl[vmap->param_id].flag) { 1414 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1415 buf_len, 1416 " %d\t\t %d/%d\t\t %d\n", 1417 vmap->param_id, 1418 vlan_tbl[vmap->param_id].rdctbl, 1419 vlan_tbl[vmap->param_id].rdctbl - 1420 p_cfgp->start_rdc_grpid, 1421 vlan_tbl[vmap->param_id].mpr_npr); 1422 ((mblk_t *)np)->b_wptr += print_len; 1423 buf_len -= print_len; 1424 } 1425 } 1426 1427 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_vlan_rdcgrp")); 1428 return (0); 1429 } 1430 1431 /* ARGSUSED */ 1432 static int 1433 nxge_param_get_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1434 mblk_t *mp, caddr_t cp) 1435 { 1436 uint_t print_len, buf_len; 1437 p_mblk_t np; 1438 int i; 1439 p_nxge_class_pt_cfg_t p_class_cfgp; 1440 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1441 p_nxge_hw_pt_cfg_t p_cfgp; 1442 nxge_mv_cfg_t *mac_host_info; 1443 1444 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 1445 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac_rdcgrp ")); 1446 (void) mi_mpprintf(mp, 1447 "MAC ADDR RDC Mapping Information for Port\t %d\n", 1448 nxgep->function_num); 1449 1450 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1451 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1452 return (0); 1453 } 1454 1455 buf_len = buff_alloc_size; 1456 mp->b_cont = np; 1457 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1458 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1459 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1460 mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 1461 print_len = snprintf((char *)np->b_wptr, buf_len, 1462 "MAC ID\t RDC GRP (Actual/Port)\t" 1463 " Prefernce\n"); 1464 ((mblk_t *)np)->b_wptr += print_len; 1465 buf_len -= print_len; 1466 for (i = 0; i < p_cfgp->max_macs; i++) { 1467 if (mac_host_info[i].flag) { 1468 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1469 buf_len, 1470 " %d\t %d/%d\t\t %d\n", 1471 i, mac_host_info[i].rdctbl, 1472 mac_host_info[i].rdctbl - 1473 p_cfgp->start_rdc_grpid, 1474 mac_host_info[i].mpr_npr); 1475 ((mblk_t *)np)->b_wptr += print_len; 1476 buf_len -= print_len; 1477 } 1478 } 1479 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1480 "Done Info Dumping \n"); 1481 ((mblk_t *)np)->b_wptr += print_len; 1482 buf_len -= print_len; 1483 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_macrdcgrp")); 1484 return (0); 1485 } 1486 1487 /* ARGSUSED */ 1488 static int 1489 nxge_param_tcam_enable(p_nxge_t nxgep, queue_t *q, 1490 mblk_t *mp, char *value, caddr_t cp) 1491 { 1492 uint32_t status = 0, cfg_value; 1493 p_nxge_param_t pa = (p_nxge_param_t)cp; 1494 uint32_t cfg_it = B_FALSE; 1495 char *end; 1496 1497 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_tcam_enable")); 1498 1499 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1500 if (pa->value != cfg_value) { 1501 pa->old_value = pa->value; 1502 pa->value = cfg_value; 1503 cfg_it = B_TRUE; 1504 } 1505 1506 if (cfg_it == B_TRUE) { 1507 if (pa->value) 1508 status = nxge_fflp_config_tcam_enable(nxgep); 1509 else 1510 status = nxge_fflp_config_tcam_disable(nxgep); 1511 if (status != NXGE_OK) 1512 return (EINVAL); 1513 } 1514 1515 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_tcam_enable")); 1516 return (0); 1517 } 1518 1519 /* ARGSUSED */ 1520 static int 1521 nxge_param_hash_lookup_enable(p_nxge_t nxgep, queue_t *q, 1522 mblk_t *mp, char *value, caddr_t cp) 1523 { 1524 uint32_t status = 0, cfg_value; 1525 p_nxge_param_t pa = (p_nxge_param_t)cp; 1526 uint32_t cfg_it = B_FALSE; 1527 char *end; 1528 1529 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_hash_lookup_enable")); 1530 1531 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1532 if (pa->value != cfg_value) { 1533 pa->old_value = pa->value; 1534 pa->value = cfg_value; 1535 cfg_it = B_TRUE; 1536 } 1537 1538 if (cfg_it == B_TRUE) { 1539 if (pa->value) 1540 status = nxge_fflp_config_hash_lookup_enable(nxgep); 1541 else 1542 status = nxge_fflp_config_hash_lookup_disable(nxgep); 1543 if (status != NXGE_OK) 1544 return (EINVAL); 1545 } 1546 1547 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_hash_lookup_enable")); 1548 return (0); 1549 } 1550 1551 /* ARGSUSED */ 1552 static int 1553 nxge_param_llc_snap_enable(p_nxge_t nxgep, queue_t *q, 1554 mblk_t *mp, char *value, caddr_t cp) 1555 { 1556 char *end; 1557 uint32_t status = 0, cfg_value; 1558 p_nxge_param_t pa = (p_nxge_param_t)cp; 1559 uint32_t cfg_it = B_FALSE; 1560 1561 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_llc_snap_enable")); 1562 1563 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1564 if (pa->value != cfg_value) { 1565 pa->old_value = pa->value; 1566 pa->value = cfg_value; 1567 cfg_it = B_TRUE; 1568 } 1569 1570 if (cfg_it == B_TRUE) { 1571 if (pa->value) 1572 status = nxge_fflp_config_tcam_enable(nxgep); 1573 else 1574 status = nxge_fflp_config_tcam_disable(nxgep); 1575 if (status != NXGE_OK) 1576 return (EINVAL); 1577 } 1578 1579 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_llc_snap_enable")); 1580 return (0); 1581 } 1582 1583 /* ARGSUSED */ 1584 static int 1585 nxge_param_set_ether_usr(p_nxge_t nxgep, queue_t *q, 1586 mblk_t *mp, char *value, caddr_t cp) 1587 { 1588 char *end; 1589 uint8_t ether_class; 1590 uint32_t status = 0, cfg_value; 1591 p_nxge_param_t pa = (p_nxge_param_t)cp; 1592 uint8_t cfg_it = B_FALSE; 1593 1594 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ether_usr")); 1595 1596 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1597 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1598 return (EINVAL); 1599 } 1600 1601 if (pa->value != cfg_value) { 1602 pa->old_value = pa->value; 1603 pa->value = cfg_value; 1604 cfg_it = B_TRUE; 1605 } 1606 1607 /* do the actual hw setup */ 1608 if (cfg_it == B_TRUE) { 1609 ether_class = mi_strtol(pa->name, &end, 10); 1610 #ifdef lint 1611 ether_class = ether_class; 1612 #endif 1613 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_ether_usr")); 1614 } 1615 1616 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ether_usr")); 1617 return (status); 1618 } 1619 1620 /* ARGSUSED */ 1621 static int 1622 nxge_param_set_ip_usr(p_nxge_t nxgep, queue_t *q, 1623 mblk_t *mp, char *value, caddr_t cp) 1624 { 1625 char *end; 1626 tcam_class_t class; 1627 uint32_t status, cfg_value; 1628 p_nxge_param_t pa = (p_nxge_param_t)cp; 1629 uint32_t cfg_it = B_FALSE; 1630 1631 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_usr")); 1632 1633 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1634 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1635 return (EINVAL); 1636 } 1637 1638 if (pa->value != cfg_value) { 1639 pa->old_value = pa->value; 1640 pa->value = cfg_value; 1641 cfg_it = B_TRUE; 1642 } 1643 1644 /* do the actual hw setup with cfg_value. */ 1645 if (cfg_it == B_TRUE) { 1646 class = mi_strtol(pa->name, &end, 10); 1647 status = nxge_fflp_ip_usr_class_config(nxgep, class, pa->value); 1648 } 1649 1650 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_usr")); 1651 return (status); 1652 } 1653 1654 /* ARGSUSED */ 1655 static int 1656 nxge_class_name_2value(p_nxge_t nxgep, char *name) 1657 { 1658 int i; 1659 int class_instance = param_class_opt_ip_usr4; 1660 p_nxge_param_t param_arr; 1661 1662 param_arr = nxgep->param_arr; 1663 for (i = TCAM_CLASS_IP_USER_4; i <= TCAM_CLASS_SCTP_IPV6; i++) { 1664 if (strcmp(param_arr[class_instance].name, name) == 0) 1665 return (i); 1666 class_instance++; 1667 } 1668 return (-1); 1669 } 1670 1671 /* ARGSUSED */ 1672 static int 1673 nxge_param_set_ip_opt(p_nxge_t nxgep, queue_t *q, 1674 mblk_t *mp, char *value, caddr_t cp) 1675 { 1676 char *end; 1677 uint32_t status, cfg_value; 1678 p_nxge_param_t pa = (p_nxge_param_t)cp; 1679 tcam_class_t class; 1680 uint32_t cfg_it = B_FALSE; 1681 1682 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_opt")); 1683 1684 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1685 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1686 return (EINVAL); 1687 } 1688 1689 if (pa->value != cfg_value) { 1690 pa->old_value = pa->value; 1691 pa->value = cfg_value; 1692 cfg_it = B_TRUE; 1693 } 1694 1695 if (cfg_it == B_TRUE) { 1696 /* do the actual hw setup */ 1697 class = nxge_class_name_2value(nxgep, pa->name); 1698 if (class == -1) 1699 return (EINVAL); 1700 1701 status = nxge_fflp_ip_class_config(nxgep, class, pa->value); 1702 if (status != NXGE_OK) 1703 return (EINVAL); 1704 } 1705 1706 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_opt")); 1707 return (0); 1708 } 1709 1710 /* ARGSUSED */ 1711 static int 1712 nxge_param_get_ip_opt(p_nxge_t nxgep, queue_t *q, 1713 mblk_t *mp, caddr_t cp) 1714 { 1715 uint32_t status, cfg_value; 1716 p_nxge_param_t pa = (p_nxge_param_t)cp; 1717 tcam_class_t class; 1718 1719 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_ip_opt")); 1720 1721 /* do the actual hw setup */ 1722 class = nxge_class_name_2value(nxgep, pa->name); 1723 if (class == -1) 1724 return (EINVAL); 1725 1726 cfg_value = 0; 1727 status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value); 1728 if (status != NXGE_OK) 1729 return (EINVAL); 1730 1731 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1732 "nxge_param_get_ip_opt_get %x ", cfg_value)); 1733 1734 pa->value = cfg_value; 1735 (void) mi_mpprintf(mp, "%x", cfg_value); 1736 1737 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status ")); 1738 return (0); 1739 } 1740 1741 /* ARGSUSED */ 1742 static int 1743 nxge_param_fflp_hash_init(p_nxge_t nxgep, queue_t *q, 1744 mblk_t *mp, char *value, caddr_t cp) 1745 { 1746 char *end; 1747 uint32_t status, cfg_value; 1748 p_nxge_param_t pa = (p_nxge_param_t)cp; 1749 tcam_class_t class; 1750 uint32_t cfg_it = B_FALSE; 1751 1752 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_fflp_hash_init")); 1753 1754 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1755 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1756 return (EINVAL); 1757 } 1758 1759 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1760 "nxge_param_fflp_hash_init value %x", cfg_value)); 1761 1762 if (pa->value != cfg_value) { 1763 pa->old_value = pa->value; 1764 pa->value = cfg_value; 1765 cfg_it = B_TRUE; 1766 } 1767 1768 if (cfg_it == B_TRUE) { 1769 char *h_name; 1770 1771 /* do the actual hw setup */ 1772 h_name = pa->name; 1773 h_name++; 1774 class = mi_strtol(h_name, &end, 10); 1775 switch (class) { 1776 case 1: 1777 status = nxge_fflp_set_hash1(nxgep, 1778 (uint32_t)pa->value); 1779 break; 1780 case 2: 1781 status = nxge_fflp_set_hash2(nxgep, 1782 (uint16_t)pa->value); 1783 break; 1784 1785 default: 1786 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1787 " nxge_param_fflp_hash_init" 1788 " %s Wrong hash var %d", 1789 pa->name, class)); 1790 return (EINVAL); 1791 } 1792 if (status != NXGE_OK) 1793 return (EINVAL); 1794 } 1795 1796 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_fflp_hash_init")); 1797 return (0); 1798 } 1799 1800 /* ARGSUSED */ 1801 static int 1802 nxge_param_set_grp_rdc(p_nxge_t nxgep, queue_t *q, 1803 mblk_t *mp, char *value, caddr_t cp) 1804 { 1805 char *end; 1806 uint32_t status = 0, cfg_value; 1807 p_nxge_param_t pa = (p_nxge_param_t)cp; 1808 uint32_t cfg_it = B_FALSE; 1809 int rdc_grp; 1810 uint8_t real_rdc; 1811 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1812 p_nxge_hw_pt_cfg_t p_cfgp; 1813 p_nxge_rdc_grp_t rdc_grp_p; 1814 1815 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1816 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1817 1818 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_grp_rdc")); 1819 1820 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1821 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1822 return (EINVAL); 1823 } 1824 1825 if (cfg_value >= p_cfgp->max_rdcs) { 1826 return (EINVAL); 1827 } 1828 1829 if (pa->value != cfg_value) { 1830 pa->old_value = pa->value; 1831 pa->value = cfg_value; 1832 cfg_it = B_TRUE; 1833 } 1834 1835 if (cfg_it == B_TRUE) { 1836 char *grp_name; 1837 grp_name = pa->name; 1838 grp_name += strlen("default-grp"); 1839 rdc_grp = mi_strtol(grp_name, &end, 10); 1840 rdc_grp_p = &p_dma_cfgp->rdc_grps[rdc_grp]; 1841 real_rdc = rdc_grp_p->start_rdc + cfg_value; 1842 if (nxge_check_rxdma_rdcgrp_member(nxgep, rdc_grp, 1843 cfg_value) == B_FALSE) { 1844 pa->value = pa->old_value; 1845 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1846 " nxge_param_set_grp_rdc" 1847 " %d read %d actual %d outof range", 1848 rdc_grp, cfg_value, real_rdc)); 1849 return (EINVAL); 1850 } 1851 status = nxge_rxdma_cfg_rdcgrp_default_rdc(nxgep, rdc_grp, 1852 real_rdc); 1853 if (status != NXGE_OK) 1854 return (EINVAL); 1855 } 1856 1857 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_grp_rdc")); 1858 return (0); 1859 } 1860 1861 /* ARGSUSED */ 1862 static int 1863 nxge_param_set_port_rdc(p_nxge_t nxgep, queue_t *q, 1864 mblk_t *mp, char *value, caddr_t cp) 1865 { 1866 char *end; 1867 uint32_t status = B_TRUE, cfg_value; 1868 p_nxge_param_t pa = (p_nxge_param_t)cp; 1869 uint32_t cfg_it = B_FALSE; 1870 1871 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1872 p_nxge_hw_pt_cfg_t p_cfgp; 1873 1874 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_port_rdc")); 1875 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1876 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1877 1878 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1879 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1880 return (EINVAL); 1881 } 1882 1883 if (pa->value != cfg_value) { 1884 if (cfg_value >= p_cfgp->max_rdcs) 1885 return (EINVAL); 1886 pa->old_value = pa->value; 1887 pa->value = cfg_value; 1888 cfg_it = B_TRUE; 1889 } 1890 1891 if (cfg_it == B_TRUE) { 1892 status = nxge_rxdma_cfg_port_default_rdc(nxgep, 1893 nxgep->function_num, 1894 nxgep->rdc[cfg_value]); 1895 if (status != NXGE_OK) 1896 return (EINVAL); 1897 } 1898 1899 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_port_rdc")); 1900 return (0); 1901 } 1902 1903 /* ARGSUSED */ 1904 static int 1905 nxge_param_set_nxge_debug_flag(p_nxge_t nxgep, queue_t *q, 1906 mblk_t *mp, char *value, caddr_t cp) 1907 { 1908 char *end; 1909 uint32_t status = 0; 1910 uint64_t cfg_value = 0; 1911 p_nxge_param_t pa = (p_nxge_param_t)cp; 1912 uint32_t cfg_it = B_FALSE; 1913 1914 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_nxge_debug_flag")); 1915 cfg_value = mi_strtol(value, &end, BASE_HEX); 1916 1917 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1918 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1919 " nxge_param_set_nxge_debug_flag" 1920 " outof range %llx", cfg_value)); 1921 return (EINVAL); 1922 } 1923 if (pa->value != cfg_value) { 1924 pa->old_value = pa->value; 1925 pa->value = cfg_value; 1926 cfg_it = B_TRUE; 1927 } 1928 1929 if (cfg_it == B_TRUE) { 1930 nxgep->nxge_debug_level = pa->value; 1931 } 1932 1933 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_nxge_debug_flag")); 1934 return (status); 1935 } 1936 1937 /* ARGSUSED */ 1938 static int 1939 nxge_param_get_debug_flag(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 1940 { 1941 int status = 0; 1942 p_nxge_param_t pa = (p_nxge_param_t)cp; 1943 1944 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_debug_flag")); 1945 1946 if (pa->value > 0xffffffff) 1947 (void) mi_mpprintf(mp, "%x%x", (int)(pa->value >> 32), 1948 (int)(pa->value & 0xffffffff)); 1949 else 1950 (void) mi_mpprintf(mp, "%x", (int)pa->value); 1951 1952 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_debug_flag")); 1953 return (status); 1954 } 1955 1956 /* ARGSUSED */ 1957 static int 1958 nxge_param_set_npi_debug_flag(p_nxge_t nxgep, queue_t *q, 1959 mblk_t *mp, char *value, caddr_t cp) 1960 { 1961 char *end; 1962 uint32_t status = 0; 1963 uint64_t cfg_value = 0; 1964 p_nxge_param_t pa; 1965 uint32_t cfg_it = B_FALSE; 1966 1967 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_npi_debug_flag")); 1968 cfg_value = mi_strtol(value, &end, BASE_HEX); 1969 pa = (p_nxge_param_t)cp; 1970 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1971 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_npi_debug_flag" 1972 " outof range %llx", cfg_value)); 1973 return (EINVAL); 1974 } 1975 if (pa->value != cfg_value) { 1976 pa->old_value = pa->value; 1977 pa->value = cfg_value; 1978 cfg_it = B_TRUE; 1979 } 1980 1981 if (cfg_it == B_TRUE) { 1982 npi_debug_level = pa->value; 1983 } 1984 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_debug_flag")); 1985 return (status); 1986 } 1987 1988 /* ARGSUSED */ 1989 static int 1990 nxge_param_dump_rdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 1991 { 1992 uint_t rdc; 1993 1994 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_rdc")); 1995 1996 (void) npi_rxdma_dump_fzc_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 1997 for (rdc = 0; rdc < nxgep->nrdc; rdc++) 1998 (void) nxge_dump_rxdma_channel(nxgep, nxgep->rdc[rdc]); 1999 2000 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_rdc")); 2001 return (0); 2002 } 2003 2004 /* ARGSUSED */ 2005 static int 2006 nxge_param_dump_tdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2007 { 2008 uint_t tdc; 2009 2010 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_tdc")); 2011 2012 for (tdc = 0; tdc < nxgep->ntdc; tdc++) 2013 (void) nxge_txdma_regs_dump(nxgep, nxgep->tdc[tdc]); 2014 2015 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_tdc")); 2016 return (0); 2017 } 2018 2019 /* ARGSUSED */ 2020 static int 2021 nxge_param_dump_fflp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2022 { 2023 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_fflp_regs")); 2024 2025 (void) npi_fflp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 2026 2027 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_fflp_regs")); 2028 return (0); 2029 } 2030 2031 /* ARGSUSED */ 2032 static int 2033 nxge_param_dump_mac_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2034 { 2035 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_mac_regs")); 2036 2037 (void) npi_mac_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 2038 nxgep->function_num); 2039 2040 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_mac_regs")); 2041 return (0); 2042 } 2043 2044 /* ARGSUSED */ 2045 static int 2046 nxge_param_dump_ipp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2047 { 2048 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_ipp_regs")); 2049 2050 (void) npi_ipp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 2051 nxgep->function_num); 2052 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ipp_regs")); 2053 return (0); 2054 } 2055 2056 /* ARGSUSED */ 2057 static int 2058 nxge_param_dump_vlan_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2059 { 2060 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_vlan_table")); 2061 2062 (void) npi_fflp_vlan_tbl_dump(NXGE_DEV_NPI_HANDLE(nxgep)); 2063 2064 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_vlan_table")); 2065 return (0); 2066 } 2067 2068 /* ARGSUSED */ 2069 static int 2070 nxge_param_dump_rdc_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2071 { 2072 uint8_t table; 2073 2074 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_rdc_table")); 2075 for (table = 0; table < NXGE_MAX_RDC_GROUPS; table++) { 2076 (void) npi_rxdma_dump_rdc_table(NXGE_DEV_NPI_HANDLE(nxgep), 2077 table); 2078 } 2079 2080 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_rdc_table")); 2081 return (0); 2082 } 2083 2084 typedef struct block_info { 2085 char *name; 2086 uint32_t offset; 2087 } block_info_t; 2088 2089 block_info_t reg_block[] = { 2090 {"PIO", PIO}, 2091 {"FZC_PIO", FZC_PIO}, 2092 {"FZC_XMAC", FZC_MAC}, 2093 {"FZC_IPP", FZC_IPP}, 2094 {"FFLP", FFLP}, 2095 {"FZC_FFLP", FZC_FFLP}, 2096 {"PIO_VADDR", PIO_VADDR}, 2097 {"ZCP", ZCP}, 2098 {"FZC_ZCP", FZC_ZCP}, 2099 {"DMC", DMC}, 2100 {"FZC_DMC", FZC_DMC}, 2101 {"TXC", TXC}, 2102 {"FZC_TXC", FZC_TXC}, 2103 {"PIO_LDSV", PIO_LDSV}, 2104 {"PIO_LDGIM", PIO_LDGIM}, 2105 {"PIO_IMASK0", PIO_IMASK0}, 2106 {"PIO_IMASK1", PIO_IMASK1}, 2107 {"FZC_PROM", FZC_PROM}, 2108 {"END", ALL_FF_32}, 2109 }; 2110 2111 /* ARGSUSED */ 2112 static int 2113 nxge_param_dump_ptrs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2114 { 2115 uint_t print_len, buf_len; 2116 p_mblk_t np; 2117 int rdc, tdc, block; 2118 uint64_t base; 2119 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2120 p_nxge_hw_pt_cfg_t p_cfgp; 2121 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_8K; 2122 p_tx_ring_t *tx_rings; 2123 p_rx_rcr_rings_t rx_rcr_rings; 2124 p_rx_rcr_ring_t *rcr_rings; 2125 p_rx_rbr_rings_t rx_rbr_rings; 2126 p_rx_rbr_ring_t *rbr_rings; 2127 2128 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2129 "==> nxge_param_dump_ptrs")); 2130 2131 (void) mi_mpprintf(mp, "ptr information for Port\t %d \n", 2132 nxgep->function_num); 2133 2134 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 2135 /* The following may work even if we cannot get a large buf. */ 2136 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 2137 return (0); 2138 } 2139 2140 buf_len = buff_alloc_size; 2141 mp->b_cont = np; 2142 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2143 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2144 2145 rx_rcr_rings = nxgep->rx_rcr_rings; 2146 rcr_rings = rx_rcr_rings->rcr_rings; 2147 rx_rbr_rings = nxgep->rx_rbr_rings; 2148 rbr_rings = rx_rbr_rings->rbr_rings; 2149 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2150 "nxgep (nxge_t) $%p\n" 2151 "dev_regs (dev_regs_t) $%p\n", 2152 nxgep, nxgep->dev_regs); 2153 2154 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2155 2156 /* do register pointers */ 2157 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2158 "reg base (npi_reg_ptr_t) $%p\t " 2159 "pci reg (npi_reg_ptr_t) $%p\n", 2160 nxgep->dev_regs->nxge_regp, 2161 nxgep->dev_regs->nxge_pciregp); 2162 2163 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2164 2165 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2166 "\nBlock \t Offset \n"); 2167 2168 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2169 block = 0; 2170 base = (uint64_t)nxgep->dev_regs->nxge_regp; 2171 while (reg_block[block].offset != ALL_FF_32) { 2172 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2173 "%9s\t 0x%llx\n", 2174 reg_block[block].name, 2175 (unsigned long long)(reg_block[block].offset + base)); 2176 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2177 block++; 2178 } 2179 2180 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2181 "\nRDC\t rcrp (rx_rcr_ring_t)\t " 2182 "rbrp (rx_rbr_ring_t)\n"); 2183 2184 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2185 2186 for (rdc = 0; rdc < p_cfgp->max_rdcs; rdc++) { 2187 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2188 " %d\t $%p\t\t $%p\n", 2189 rdc, rcr_rings[rdc], 2190 rbr_rings[rdc]); 2191 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2192 } 2193 2194 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2195 "\nTDC\t tdcp (tx_ring_t)\n"); 2196 2197 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2198 tx_rings = nxgep->tx_rings->rings; 2199 for (tdc = 0; tdc < p_cfgp->max_tdcs; tdc++) { 2200 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2201 " %d\t $%p\n", tdc, tx_rings[tdc]); 2202 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2203 } 2204 2205 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, "\n\n"); 2206 2207 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2208 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ptrs")); 2209 return (0); 2210 } 2211 2212 /* 2213 * Load 'name' into the named dispatch table pointed to by 'ndp'. 2214 * 'ndp' should be the address of a char pointer cell. If the table 2215 * does not exist (*ndp == 0), a new table is allocated and 'ndp' 2216 * is stuffed. If there is not enough space in the table for a new 2217 * entry, more space is allocated. 2218 */ 2219 /* ARGSUSED */ 2220 boolean_t 2221 nxge_nd_load(caddr_t *pparam, char *name, 2222 pfi_t get_pfi, pfi_t set_pfi, caddr_t data) 2223 { 2224 ND *nd; 2225 NDE *nde; 2226 2227 NXGE_DEBUG_MSG((NULL, NDD2_CTL, " ==> nxge_nd_load")); 2228 if (!pparam) 2229 return (B_FALSE); 2230 2231 if ((nd = (ND *)*pparam) == NULL) { 2232 if ((nd = (ND *)KMEM_ZALLOC(sizeof (ND), KM_NOSLEEP)) == NULL) 2233 return (B_FALSE); 2234 *pparam = (caddr_t)nd; 2235 } 2236 2237 if (nd->nd_tbl) { 2238 for (nde = nd->nd_tbl; nde->nde_name; nde++) { 2239 if (strcmp(name, nde->nde_name) == 0) 2240 goto fill_it; 2241 } 2242 } 2243 2244 if (nd->nd_free_count <= 1) { 2245 if ((nde = (NDE *)KMEM_ZALLOC(nd->nd_size + 2246 NDE_ALLOC_SIZE, KM_NOSLEEP)) == NULL) 2247 return (B_FALSE); 2248 nd->nd_free_count += NDE_ALLOC_COUNT; 2249 if (nd->nd_tbl) { 2250 bcopy((char *)nd->nd_tbl, (char *)nde, nd->nd_size); 2251 KMEM_FREE((char *)nd->nd_tbl, nd->nd_size); 2252 } else { 2253 nd->nd_free_count--; 2254 nde->nde_name = "?"; 2255 nde->nde_get_pfi = nxge_nd_get_names; 2256 nde->nde_set_pfi = nxge_set_default; 2257 } 2258 nde->nde_data = (caddr_t)nd; 2259 nd->nd_tbl = nde; 2260 nd->nd_size += NDE_ALLOC_SIZE; 2261 } 2262 for (nde = nd->nd_tbl; nde->nde_name; nde++) 2263 noop; 2264 nd->nd_free_count--; 2265 fill_it: 2266 nde->nde_name = name; 2267 nde->nde_get_pfi = get_pfi; 2268 nde->nde_set_pfi = set_pfi; 2269 nde->nde_data = data; 2270 NXGE_DEBUG_MSG((NULL, NDD2_CTL, " <== nxge_nd_load")); 2271 2272 return (B_TRUE); 2273 } 2274 2275 /* 2276 * Free the table pointed to by 'pparam' 2277 */ 2278 void 2279 nxge_nd_free(caddr_t *pparam) 2280 { 2281 ND *nd; 2282 2283 if ((nd = (ND *)*pparam) != NULL) { 2284 if (nd->nd_tbl) 2285 KMEM_FREE((char *)nd->nd_tbl, nd->nd_size); 2286 KMEM_FREE((char *)nd, sizeof (ND)); 2287 *pparam = nil(caddr_t); 2288 } 2289 } 2290 2291 int 2292 nxge_nd_getset(p_nxge_t nxgep, queue_t *q, caddr_t param, p_mblk_t mp) 2293 { 2294 int err; 2295 IOCP iocp; 2296 p_mblk_t mp1, mp2; 2297 ND *nd; 2298 NDE *nde; 2299 char *valp; 2300 size_t avail; 2301 2302 if (!param) { 2303 return (B_FALSE); 2304 } 2305 2306 nd = (ND *)param; 2307 iocp = (IOCP)mp->b_rptr; 2308 if ((iocp->ioc_count == 0) || !(mp1 = mp->b_cont)) { 2309 mp->b_datap->db_type = M_IOCACK; 2310 iocp->ioc_count = 0; 2311 iocp->ioc_error = EINVAL; 2312 return (B_FALSE); 2313 } 2314 2315 /* 2316 * NOTE - logic throughout nd_xxx assumes single data block for ioctl. 2317 * However, existing code sends in some big buffers. 2318 */ 2319 avail = iocp->ioc_count; 2320 if (mp1->b_cont) { 2321 freemsg(mp1->b_cont); 2322 mp1->b_cont = NULL; 2323 } 2324 2325 mp1->b_datap->db_lim[-1] = '\0'; /* Force null termination */ 2326 for (valp = (char *)mp1->b_rptr; *valp != '\0'; valp++) { 2327 if (*valp == '-') 2328 *valp = '_'; 2329 } 2330 2331 valp = (char *)mp1->b_rptr; 2332 2333 for (nde = nd->nd_tbl; /* */; nde++) { 2334 if (!nde->nde_name) 2335 return (B_FALSE); 2336 if (strcmp(nde->nde_name, valp) == 0) 2337 break; 2338 } 2339 err = EINVAL; 2340 while (*valp++) 2341 noop; 2342 if (!*valp || valp >= (char *)mp1->b_wptr) 2343 valp = nilp(char); 2344 switch (iocp->ioc_cmd) { 2345 case ND_GET: 2346 /* 2347 * (temporary) hack: "*valp" is size of user buffer for 2348 * copyout. If result of action routine is too big, free 2349 * excess and return ioc_rval as buffer size needed. 2350 * Return as many mblocks as will fit, free the rest. For 2351 * backward compatibility, assume size of original ioctl 2352 * buffer if "*valp" bad or not given. 2353 */ 2354 if (valp) 2355 avail = mi_strtol(valp, (char **)0, 10); 2356 /* 2357 * We overwrite the name/value with the reply data 2358 */ 2359 mp2 = mp1; 2360 while (mp2) { 2361 mp2->b_wptr = mp2->b_rptr; 2362 mp2 = mp2->b_cont; 2363 } 2364 2365 err = (*nde->nde_get_pfi)(nxgep, q, mp1, nde->nde_data); 2366 2367 if (!err) { 2368 size_t size_out = 0; 2369 size_t excess; 2370 2371 iocp->ioc_rval = 0; 2372 2373 /* Tack on the null */ 2374 err = nxge_mk_mblk_tail_space(mp1, &mp2, 1); 2375 if (!err) { 2376 *mp2->b_wptr++ = '\0'; 2377 size_out = msgdsize(mp1); 2378 excess = size_out - avail; 2379 if (excess > 0) { 2380 iocp->ioc_rval = (int)size_out; 2381 size_out -= excess; 2382 (void) adjmsg(mp1, -(excess + 1)); 2383 err = nxge_mk_mblk_tail_space( 2384 mp1, &mp2, 1); 2385 if (!err) 2386 *mp2->b_wptr++ = '\0'; 2387 else 2388 size_out = 0; 2389 } 2390 } else 2391 size_out = 0; 2392 iocp->ioc_count = size_out; 2393 } 2394 break; 2395 2396 case ND_SET: 2397 if (valp) { 2398 if (nde->nde_set_pfi) { 2399 err = (*nde->nde_set_pfi)(nxgep, q, mp1, valp, 2400 nde->nde_data); 2401 iocp->ioc_count = 0; 2402 freemsg(mp1); 2403 mp->b_cont = NULL; 2404 } 2405 } 2406 break; 2407 2408 default: 2409 break; 2410 } 2411 iocp->ioc_error = err; 2412 mp->b_datap->db_type = M_IOCACK; 2413 return (B_TRUE); 2414 } 2415 2416 /* ARGSUSED */ 2417 int 2418 nxge_nd_get_names(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t param) 2419 { 2420 ND *nd; 2421 NDE *nde; 2422 char *rwtag; 2423 boolean_t get_ok, set_ok; 2424 size_t param_len; 2425 int status = 0; 2426 2427 nd = (ND *)param; 2428 if (!nd) 2429 return (ENOENT); 2430 2431 for (nde = nd->nd_tbl; nde->nde_name; nde++) { 2432 get_ok = (nde->nde_get_pfi != nxge_get_default) && 2433 (nde->nde_get_pfi != NULL); 2434 set_ok = (nde->nde_set_pfi != nxge_set_default) && 2435 (nde->nde_set_pfi != NULL); 2436 if (get_ok) { 2437 if (set_ok) 2438 rwtag = "read and write"; 2439 else 2440 rwtag = "read only"; 2441 } else if (set_ok) 2442 rwtag = "write only"; 2443 else { 2444 continue; 2445 } 2446 param_len = strlen(rwtag); 2447 param_len += strlen(nde->nde_name); 2448 param_len += 4; 2449 2450 (void) mi_mpprintf(mp, "%s (%s)", nde->nde_name, rwtag); 2451 } 2452 return (status); 2453 } 2454 2455 /* ARGSUSED */ 2456 int 2457 nxge_get_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t data) 2458 { 2459 return (EACCES); 2460 } 2461 2462 /* ARGSUSED */ 2463 int 2464 nxge_set_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, char *value, 2465 caddr_t data) 2466 { 2467 return (EACCES); 2468 } 2469 2470 void 2471 nxge_param_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 2472 { 2473 int cmd; 2474 int status = B_FALSE; 2475 2476 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_ioctl")); 2477 cmd = iocp->ioc_cmd; 2478 2479 switch (cmd) { 2480 default: 2481 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2482 "nxge_param_ioctl: bad cmd 0x%0x", cmd)); 2483 break; 2484 2485 case ND_GET: 2486 case ND_SET: 2487 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2488 "nxge_param_ioctl: cmd 0x%0x", cmd)); 2489 if (!nxge_nd_getset(nxgep, wq, nxgep->param_list, mp)) { 2490 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2491 "false ret from nxge_nd_getset")); 2492 break; 2493 } 2494 status = B_TRUE; 2495 break; 2496 } 2497 2498 if (status) { 2499 qreply(wq, mp); 2500 } else { 2501 miocnak(wq, mp, 0, EINVAL); 2502 } 2503 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_ioctl")); 2504 } 2505 2506 /* ARGSUSED */ 2507 static boolean_t 2508 nxge_param_link_update(p_nxge_t nxgep) 2509 { 2510 p_nxge_param_t param_arr; 2511 nxge_param_index_t i; 2512 boolean_t update_xcvr; 2513 boolean_t update_dev; 2514 int instance; 2515 boolean_t status = B_TRUE; 2516 2517 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_link_update")); 2518 2519 param_arr = nxgep->param_arr; 2520 instance = nxgep->instance; 2521 update_xcvr = B_FALSE; 2522 for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) { 2523 update_xcvr |= param_arr[i].value; 2524 } 2525 2526 if (update_xcvr) { 2527 update_xcvr = B_FALSE; 2528 for (i = param_autoneg; i < param_enable_ipg0; i++) { 2529 update_xcvr |= 2530 (param_arr[i].value != param_arr[i].old_value); 2531 param_arr[i].old_value = param_arr[i].value; 2532 } 2533 if (update_xcvr) { 2534 RW_ENTER_WRITER(&nxgep->filter_lock); 2535 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 2536 (void) nxge_link_init(nxgep); 2537 (void) nxge_mac_init(nxgep); 2538 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 2539 RW_EXIT(&nxgep->filter_lock); 2540 } 2541 } else { 2542 cmn_err(CE_WARN, " Last setting will leave nxge%d with " 2543 " no link capabilities.", instance); 2544 cmn_err(CE_WARN, " Restoring previous setting."); 2545 for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) 2546 param_arr[i].value = param_arr[i].old_value; 2547 } 2548 2549 update_dev = B_FALSE; 2550 2551 if (update_dev) { 2552 RW_ENTER_WRITER(&nxgep->filter_lock); 2553 (void) nxge_rx_mac_disable(nxgep); 2554 (void) nxge_tx_mac_disable(nxgep); 2555 (void) nxge_tx_mac_enable(nxgep); 2556 (void) nxge_rx_mac_enable(nxgep); 2557 RW_EXIT(&nxgep->filter_lock); 2558 } 2559 2560 nxge_param_hw_update_exit: 2561 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 2562 "<== nxge_param_link_update status = 0x%08x", status)); 2563 return (status); 2564 } 2565