1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * SunOs MT STREAMS NIU/Neptune 10Gb Ethernet Device Driver. 29 */ 30 #include <sys/nxge/nxge_impl.h> 31 #include <sys/nxge/nxge_hio.h> 32 #include <sys/nxge/nxge_rxdma.h> 33 #include <sys/pcie.h> 34 35 uint32_t nxge_use_partition = 0; /* debug partition flag */ 36 uint32_t nxge_dma_obp_props_only = 1; /* use obp published props */ 37 uint32_t nxge_use_rdc_intr = 1; /* debug to assign rdc intr */ 38 /* 39 * PSARC/2007/453 MSI-X interrupt limit override 40 */ 41 uint32_t nxge_msi_enable = 2; 42 43 /* 44 * Software workaround for a Neptune (PCI-E) 45 * hardware interrupt bug which the hardware 46 * may generate spurious interrupts after the 47 * device interrupt handler was removed. If this flag 48 * is enabled, the driver will reset the 49 * hardware when devices are being detached. 50 */ 51 uint32_t nxge_peu_reset_enable = 0; 52 53 /* 54 * Software workaround for the hardware 55 * checksum bugs that affect packet transmission 56 * and receive: 57 * 58 * Usage of nxge_cksum_offload: 59 * 60 * (1) nxge_cksum_offload = 0 (default): 61 * - transmits packets: 62 * TCP: uses the hardware checksum feature. 63 * UDP: driver will compute the software checksum 64 * based on the partial checksum computed 65 * by the IP layer. 66 * - receives packets 67 * TCP: marks packets checksum flags based on hardware result. 68 * UDP: will not mark checksum flags. 69 * 70 * (2) nxge_cksum_offload = 1: 71 * - transmit packets: 72 * TCP/UDP: uses the hardware checksum feature. 73 * - receives packets 74 * TCP/UDP: marks packet checksum flags based on hardware result. 75 * 76 * (3) nxge_cksum_offload = 2: 77 * - The driver will not register its checksum capability. 78 * Checksum for both TCP and UDP will be computed 79 * by the stack. 80 * - The software LSO is not allowed in this case. 81 * 82 * (4) nxge_cksum_offload > 2: 83 * - Will be treated as it is set to 2 84 * (stack will compute the checksum). 85 * 86 * (5) If the hardware bug is fixed, this workaround 87 * needs to be updated accordingly to reflect 88 * the new hardware revision. 89 */ 90 uint32_t nxge_cksum_offload = 0; 91 92 /* 93 * Globals: tunable parameters (/etc/system or adb) 94 * 95 */ 96 uint32_t nxge_rbr_size = NXGE_RBR_RBB_DEFAULT; 97 uint32_t nxge_rbr_spare_size = 0; 98 uint32_t nxge_rcr_size = NXGE_RCR_DEFAULT; 99 uint32_t nxge_tx_ring_size = NXGE_TX_RING_DEFAULT; 100 boolean_t nxge_no_msg = B_TRUE; /* control message display */ 101 uint32_t nxge_no_link_notify = 0; /* control DL_NOTIFY */ 102 uint32_t nxge_bcopy_thresh = TX_BCOPY_MAX; 103 uint32_t nxge_dvma_thresh = TX_FASTDVMA_MIN; 104 uint32_t nxge_dma_stream_thresh = TX_STREAM_MIN; 105 uint32_t nxge_jumbo_mtu = TX_JUMBO_MTU; 106 nxge_tx_mode_t nxge_tx_scheme = NXGE_USE_SERIAL; 107 108 /* MAX LSO size */ 109 #define NXGE_LSO_MAXLEN 65535 110 uint32_t nxge_lso_max = NXGE_LSO_MAXLEN; 111 112 113 /* 114 * Add tunable to reduce the amount of time spent in the 115 * ISR doing Rx Processing. 116 */ 117 uint32_t nxge_max_rx_pkts = 1024; 118 119 /* 120 * Tunables to manage the receive buffer blocks. 121 * 122 * nxge_rx_threshold_hi: copy all buffers. 123 * nxge_rx_bcopy_size_type: receive buffer block size type. 124 * nxge_rx_threshold_lo: copy only up to tunable block size type. 125 */ 126 nxge_rxbuf_threshold_t nxge_rx_threshold_hi = NXGE_RX_COPY_6; 127 nxge_rxbuf_type_t nxge_rx_buf_size_type = RCR_PKTBUFSZ_0; 128 nxge_rxbuf_threshold_t nxge_rx_threshold_lo = NXGE_RX_COPY_3; 129 130 /* Use kmem_alloc() to allocate data buffers. */ 131 #if defined(_BIG_ENDIAN) 132 uint32_t nxge_use_kmem_alloc = 1; 133 #else 134 uint32_t nxge_use_kmem_alloc = 0; 135 #endif 136 137 rtrace_t npi_rtracebuf; 138 139 /* 140 * The hardware sometimes fails to allow enough time for the link partner 141 * to send an acknowledgement for packets that the hardware sent to it. The 142 * hardware resends the packets earlier than it should be in those instances. 143 * This behavior caused some switches to acknowledge the wrong packets 144 * and it triggered the fatal error. 145 * This software workaround is to set the replay timer to a value 146 * suggested by the hardware team. 147 * 148 * PCI config space replay timer register: 149 * The following replay timeout value is 0xc 150 * for bit 14:18. 151 */ 152 #define PCI_REPLAY_TIMEOUT_CFG_OFFSET 0xb8 153 #define PCI_REPLAY_TIMEOUT_SHIFT 14 154 155 uint32_t nxge_set_replay_timer = 1; 156 uint32_t nxge_replay_timeout = 0xc; 157 158 /* 159 * The transmit serialization sometimes causes 160 * longer sleep before calling the driver transmit 161 * function as it sleeps longer than it should. 162 * The performace group suggests that a time wait tunable 163 * can be used to set the maximum wait time when needed 164 * and the default is set to 1 tick. 165 */ 166 uint32_t nxge_tx_serial_maxsleep = 1; 167 168 #if defined(sun4v) 169 /* 170 * Hypervisor N2/NIU services information. 171 */ 172 static hsvc_info_t niu_hsvc = { 173 HSVC_REV_1, NULL, HSVC_GROUP_NIU, NIU_MAJOR_VER, 174 NIU_MINOR_VER, "nxge" 175 }; 176 177 static int nxge_hsvc_register(p_nxge_t); 178 #endif 179 180 /* 181 * Function Prototypes 182 */ 183 static int nxge_attach(dev_info_t *, ddi_attach_cmd_t); 184 static int nxge_detach(dev_info_t *, ddi_detach_cmd_t); 185 static void nxge_unattach(p_nxge_t); 186 static int nxge_quiesce(dev_info_t *); 187 188 #if NXGE_PROPERTY 189 static void nxge_remove_hard_properties(p_nxge_t); 190 #endif 191 192 /* 193 * These two functions are required by nxge_hio.c 194 */ 195 extern int nxge_m_mmac_remove(void *arg, int slot); 196 extern void nxge_grp_cleanup(p_nxge_t nxge); 197 198 static nxge_status_t nxge_setup_system_dma_pages(p_nxge_t); 199 200 static nxge_status_t nxge_setup_mutexes(p_nxge_t); 201 static void nxge_destroy_mutexes(p_nxge_t); 202 203 static nxge_status_t nxge_map_regs(p_nxge_t nxgep); 204 static void nxge_unmap_regs(p_nxge_t nxgep); 205 #ifdef NXGE_DEBUG 206 static void nxge_test_map_regs(p_nxge_t nxgep); 207 #endif 208 209 static nxge_status_t nxge_add_intrs(p_nxge_t nxgep); 210 static void nxge_remove_intrs(p_nxge_t nxgep); 211 212 static nxge_status_t nxge_add_intrs_adv(p_nxge_t nxgep); 213 static nxge_status_t nxge_add_intrs_adv_type(p_nxge_t, uint32_t); 214 static nxge_status_t nxge_add_intrs_adv_type_fix(p_nxge_t, uint32_t); 215 static void nxge_intrs_enable(p_nxge_t nxgep); 216 static void nxge_intrs_disable(p_nxge_t nxgep); 217 218 static void nxge_suspend(p_nxge_t); 219 static nxge_status_t nxge_resume(p_nxge_t); 220 221 static nxge_status_t nxge_setup_dev(p_nxge_t); 222 static void nxge_destroy_dev(p_nxge_t); 223 224 static nxge_status_t nxge_alloc_mem_pool(p_nxge_t); 225 static void nxge_free_mem_pool(p_nxge_t); 226 227 nxge_status_t nxge_alloc_rx_mem_pool(p_nxge_t); 228 static void nxge_free_rx_mem_pool(p_nxge_t); 229 230 nxge_status_t nxge_alloc_tx_mem_pool(p_nxge_t); 231 static void nxge_free_tx_mem_pool(p_nxge_t); 232 233 static nxge_status_t nxge_dma_mem_alloc(p_nxge_t, dma_method_t, 234 struct ddi_dma_attr *, 235 size_t, ddi_device_acc_attr_t *, uint_t, 236 p_nxge_dma_common_t); 237 238 static void nxge_dma_mem_free(p_nxge_dma_common_t); 239 static void nxge_dma_free_rx_data_buf(p_nxge_dma_common_t); 240 241 static nxge_status_t nxge_alloc_rx_buf_dma(p_nxge_t, uint16_t, 242 p_nxge_dma_common_t *, size_t, size_t, uint32_t *); 243 static void nxge_free_rx_buf_dma(p_nxge_t, p_nxge_dma_common_t, uint32_t); 244 245 static nxge_status_t nxge_alloc_rx_cntl_dma(p_nxge_t, uint16_t, 246 p_nxge_dma_common_t *, size_t); 247 static void nxge_free_rx_cntl_dma(p_nxge_t, p_nxge_dma_common_t); 248 249 extern nxge_status_t nxge_alloc_tx_buf_dma(p_nxge_t, uint16_t, 250 p_nxge_dma_common_t *, size_t, size_t, uint32_t *); 251 static void nxge_free_tx_buf_dma(p_nxge_t, p_nxge_dma_common_t, uint32_t); 252 253 extern nxge_status_t nxge_alloc_tx_cntl_dma(p_nxge_t, uint16_t, 254 p_nxge_dma_common_t *, 255 size_t); 256 static void nxge_free_tx_cntl_dma(p_nxge_t, p_nxge_dma_common_t); 257 258 static int nxge_init_common_dev(p_nxge_t); 259 static void nxge_uninit_common_dev(p_nxge_t); 260 extern int nxge_param_set_mac(p_nxge_t, queue_t *, mblk_t *, 261 char *, caddr_t); 262 #if defined(sun4v) 263 extern nxge_status_t nxge_hio_rdc_enable(p_nxge_t nxgep); 264 extern nxge_status_t nxge_hio_rdc_intr_arm(p_nxge_t nxge, boolean_t arm); 265 #endif 266 267 /* 268 * The next declarations are for the GLDv3 interface. 269 */ 270 static int nxge_m_start(void *); 271 static void nxge_m_stop(void *); 272 static int nxge_m_multicst(void *, boolean_t, const uint8_t *); 273 static int nxge_m_promisc(void *, boolean_t); 274 static void nxge_m_ioctl(void *, queue_t *, mblk_t *); 275 static nxge_status_t nxge_mac_register(p_nxge_t); 276 static int nxge_altmac_set(p_nxge_t nxgep, uint8_t *mac_addr, 277 int slot, int rdctbl, boolean_t usetbl); 278 void nxge_mmac_kstat_update(p_nxge_t nxgep, int slot, 279 boolean_t factory); 280 #if defined(sun4v) 281 extern mblk_t *nxge_m_tx(void *arg, mblk_t *mp); 282 #endif 283 284 static void nxge_m_getfactaddr(void *, uint_t, uint8_t *); 285 static boolean_t nxge_m_getcapab(void *, mac_capab_t, void *); 286 static int nxge_m_setprop(void *, const char *, mac_prop_id_t, 287 uint_t, const void *); 288 static int nxge_m_getprop(void *, const char *, mac_prop_id_t, 289 uint_t, uint_t, void *, uint_t *); 290 static int nxge_set_priv_prop(nxge_t *, const char *, uint_t, 291 const void *); 292 static int nxge_get_priv_prop(nxge_t *, const char *, uint_t, uint_t, 293 void *, uint_t *); 294 static int nxge_get_def_val(nxge_t *, mac_prop_id_t, uint_t, void *); 295 static void nxge_fill_ring(void *, mac_ring_type_t, const int, const int, 296 mac_ring_info_t *, mac_ring_handle_t); 297 static void nxge_group_add_ring(mac_group_driver_t, mac_ring_driver_t, 298 mac_ring_type_t); 299 static void nxge_group_rem_ring(mac_group_driver_t, mac_ring_driver_t, 300 mac_ring_type_t); 301 302 static void nxge_niu_peu_reset(p_nxge_t nxgep); 303 static void nxge_set_pci_replay_timeout(nxge_t *); 304 305 mac_priv_prop_t nxge_priv_props[] = { 306 {"_adv_10gfdx_cap", MAC_PROP_PERM_RW}, 307 {"_adv_pause_cap", MAC_PROP_PERM_RW}, 308 {"_function_number", MAC_PROP_PERM_READ}, 309 {"_fw_version", MAC_PROP_PERM_READ}, 310 {"_port_mode", MAC_PROP_PERM_READ}, 311 {"_hot_swap_phy", MAC_PROP_PERM_READ}, 312 {"_rxdma_intr_time", MAC_PROP_PERM_RW}, 313 {"_rxdma_intr_pkts", MAC_PROP_PERM_RW}, 314 {"_class_opt_ipv4_tcp", MAC_PROP_PERM_RW}, 315 {"_class_opt_ipv4_udp", MAC_PROP_PERM_RW}, 316 {"_class_opt_ipv4_ah", MAC_PROP_PERM_RW}, 317 {"_class_opt_ipv4_sctp", MAC_PROP_PERM_RW}, 318 {"_class_opt_ipv6_tcp", MAC_PROP_PERM_RW}, 319 {"_class_opt_ipv6_udp", MAC_PROP_PERM_RW}, 320 {"_class_opt_ipv6_ah", MAC_PROP_PERM_RW}, 321 {"_class_opt_ipv6_sctp", MAC_PROP_PERM_RW}, 322 {"_soft_lso_enable", MAC_PROP_PERM_RW} 323 }; 324 325 #define NXGE_MAX_PRIV_PROPS \ 326 (sizeof (nxge_priv_props)/sizeof (mac_priv_prop_t)) 327 328 #define NXGE_NEPTUNE_MAGIC 0x4E584745UL 329 #define MAX_DUMP_SZ 256 330 331 #define NXGE_M_CALLBACK_FLAGS \ 332 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 333 334 mac_callbacks_t nxge_m_callbacks = { 335 NXGE_M_CALLBACK_FLAGS, 336 nxge_m_stat, 337 nxge_m_start, 338 nxge_m_stop, 339 nxge_m_promisc, 340 nxge_m_multicst, 341 NULL, 342 NULL, 343 nxge_m_ioctl, 344 nxge_m_getcapab, 345 NULL, 346 NULL, 347 nxge_m_setprop, 348 nxge_m_getprop 349 }; 350 351 void 352 nxge_err_inject(p_nxge_t, queue_t *, mblk_t *); 353 354 /* PSARC/2007/453 MSI-X interrupt limit override. */ 355 #define NXGE_MSIX_REQUEST_10G 8 356 #define NXGE_MSIX_REQUEST_1G 2 357 static int nxge_create_msi_property(p_nxge_t); 358 /* 359 * For applications that care about the 360 * latency, it was requested by PAE and the 361 * customers that the driver has tunables that 362 * allow the user to tune it to a higher number 363 * interrupts to spread the interrupts among 364 * multiple channels. The DDI framework limits 365 * the maximum number of MSI-X resources to allocate 366 * to 8 (ddi_msix_alloc_limit). If more than 8 367 * is set, ddi_msix_alloc_limit must be set accordingly. 368 * The default number of MSI interrupts are set to 369 * 8 for 10G and 2 for 1G link. 370 */ 371 #define NXGE_MSIX_MAX_ALLOWED 32 372 uint32_t nxge_msix_10g_intrs = NXGE_MSIX_REQUEST_10G; 373 uint32_t nxge_msix_1g_intrs = NXGE_MSIX_REQUEST_1G; 374 375 /* 376 * These global variables control the message 377 * output. 378 */ 379 out_dbgmsg_t nxge_dbgmsg_out = DBG_CONSOLE | STR_LOG; 380 uint64_t nxge_debug_level; 381 382 /* 383 * This list contains the instance structures for the Neptune 384 * devices present in the system. The lock exists to guarantee 385 * mutually exclusive access to the list. 386 */ 387 void *nxge_list = NULL; 388 389 void *nxge_hw_list = NULL; 390 nxge_os_mutex_t nxge_common_lock; 391 392 extern uint64_t npi_debug_level; 393 394 extern nxge_status_t nxge_ldgv_init(p_nxge_t, int *, int *); 395 extern nxge_status_t nxge_ldgv_init_n2(p_nxge_t, int *, int *); 396 extern nxge_status_t nxge_ldgv_uninit(p_nxge_t); 397 extern nxge_status_t nxge_intr_ldgv_init(p_nxge_t); 398 extern void nxge_fm_init(p_nxge_t, 399 ddi_device_acc_attr_t *, 400 ddi_device_acc_attr_t *, 401 ddi_dma_attr_t *); 402 extern void nxge_fm_fini(p_nxge_t); 403 extern npi_status_t npi_mac_altaddr_disable(npi_handle_t, uint8_t, uint8_t); 404 405 /* 406 * Count used to maintain the number of buffers being used 407 * by Neptune instances and loaned up to the upper layers. 408 */ 409 uint32_t nxge_mblks_pending = 0; 410 411 /* 412 * Device register access attributes for PIO. 413 */ 414 static ddi_device_acc_attr_t nxge_dev_reg_acc_attr = { 415 DDI_DEVICE_ATTR_V0, 416 DDI_STRUCTURE_LE_ACC, 417 DDI_STRICTORDER_ACC, 418 }; 419 420 /* 421 * Device descriptor access attributes for DMA. 422 */ 423 static ddi_device_acc_attr_t nxge_dev_desc_dma_acc_attr = { 424 DDI_DEVICE_ATTR_V0, 425 DDI_STRUCTURE_LE_ACC, 426 DDI_STRICTORDER_ACC 427 }; 428 429 /* 430 * Device buffer access attributes for DMA. 431 */ 432 static ddi_device_acc_attr_t nxge_dev_buf_dma_acc_attr = { 433 DDI_DEVICE_ATTR_V0, 434 DDI_STRUCTURE_BE_ACC, 435 DDI_STRICTORDER_ACC 436 }; 437 438 ddi_dma_attr_t nxge_desc_dma_attr = { 439 DMA_ATTR_V0, /* version number. */ 440 0, /* low address */ 441 0xffffffffffffffff, /* high address */ 442 0xffffffffffffffff, /* address counter max */ 443 #ifndef NIU_PA_WORKAROUND 444 0x100000, /* alignment */ 445 #else 446 0x2000, 447 #endif 448 0xfc00fc, /* dlim_burstsizes */ 449 0x1, /* minimum transfer size */ 450 0xffffffffffffffff, /* maximum transfer size */ 451 0xffffffffffffffff, /* maximum segment size */ 452 1, /* scatter/gather list length */ 453 (unsigned int) 1, /* granularity */ 454 0 /* attribute flags */ 455 }; 456 457 ddi_dma_attr_t nxge_tx_dma_attr = { 458 DMA_ATTR_V0, /* version number. */ 459 0, /* low address */ 460 0xffffffffffffffff, /* high address */ 461 0xffffffffffffffff, /* address counter max */ 462 #if defined(_BIG_ENDIAN) 463 0x2000, /* alignment */ 464 #else 465 0x1000, /* alignment */ 466 #endif 467 0xfc00fc, /* dlim_burstsizes */ 468 0x1, /* minimum transfer size */ 469 0xffffffffffffffff, /* maximum transfer size */ 470 0xffffffffffffffff, /* maximum segment size */ 471 5, /* scatter/gather list length */ 472 (unsigned int) 1, /* granularity */ 473 0 /* attribute flags */ 474 }; 475 476 ddi_dma_attr_t nxge_rx_dma_attr = { 477 DMA_ATTR_V0, /* version number. */ 478 0, /* low address */ 479 0xffffffffffffffff, /* high address */ 480 0xffffffffffffffff, /* address counter max */ 481 0x2000, /* alignment */ 482 0xfc00fc, /* dlim_burstsizes */ 483 0x1, /* minimum transfer size */ 484 0xffffffffffffffff, /* maximum transfer size */ 485 0xffffffffffffffff, /* maximum segment size */ 486 1, /* scatter/gather list length */ 487 (unsigned int) 1, /* granularity */ 488 DDI_DMA_RELAXED_ORDERING /* attribute flags */ 489 }; 490 491 ddi_dma_lim_t nxge_dma_limits = { 492 (uint_t)0, /* dlim_addr_lo */ 493 (uint_t)0xffffffff, /* dlim_addr_hi */ 494 (uint_t)0xffffffff, /* dlim_cntr_max */ 495 (uint_t)0xfc00fc, /* dlim_burstsizes for 32 and 64 bit xfers */ 496 0x1, /* dlim_minxfer */ 497 1024 /* dlim_speed */ 498 }; 499 500 dma_method_t nxge_force_dma = DVMA; 501 502 /* 503 * dma chunk sizes. 504 * 505 * Try to allocate the largest possible size 506 * so that fewer number of dma chunks would be managed 507 */ 508 #ifdef NIU_PA_WORKAROUND 509 size_t alloc_sizes [] = {0x2000}; 510 #else 511 size_t alloc_sizes [] = {0x1000, 0x2000, 0x4000, 0x8000, 512 0x10000, 0x20000, 0x40000, 0x80000, 513 0x100000, 0x200000, 0x400000, 0x800000, 514 0x1000000, 0x2000000, 0x4000000}; 515 #endif 516 517 /* 518 * Translate "dev_t" to a pointer to the associated "dev_info_t". 519 */ 520 521 extern void nxge_get_environs(nxge_t *); 522 523 static int 524 nxge_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 525 { 526 p_nxge_t nxgep = NULL; 527 int instance; 528 int status = DDI_SUCCESS; 529 uint8_t portn; 530 nxge_mmac_t *mmac_info; 531 532 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_attach")); 533 534 /* 535 * Get the device instance since we'll need to setup 536 * or retrieve a soft state for this instance. 537 */ 538 instance = ddi_get_instance(dip); 539 540 switch (cmd) { 541 case DDI_ATTACH: 542 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_ATTACH")); 543 break; 544 545 case DDI_RESUME: 546 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_RESUME")); 547 nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance); 548 if (nxgep == NULL) { 549 status = DDI_FAILURE; 550 break; 551 } 552 if (nxgep->dip != dip) { 553 status = DDI_FAILURE; 554 break; 555 } 556 if (nxgep->suspended == DDI_PM_SUSPEND) { 557 status = ddi_dev_is_needed(nxgep->dip, 0, 1); 558 } else { 559 status = nxge_resume(nxgep); 560 } 561 goto nxge_attach_exit; 562 563 case DDI_PM_RESUME: 564 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_PM_RESUME")); 565 nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance); 566 if (nxgep == NULL) { 567 status = DDI_FAILURE; 568 break; 569 } 570 if (nxgep->dip != dip) { 571 status = DDI_FAILURE; 572 break; 573 } 574 status = nxge_resume(nxgep); 575 goto nxge_attach_exit; 576 577 default: 578 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing unknown")); 579 status = DDI_FAILURE; 580 goto nxge_attach_exit; 581 } 582 583 584 if (ddi_soft_state_zalloc(nxge_list, instance) == DDI_FAILURE) { 585 status = DDI_FAILURE; 586 goto nxge_attach_exit; 587 } 588 589 nxgep = ddi_get_soft_state(nxge_list, instance); 590 if (nxgep == NULL) { 591 status = NXGE_ERROR; 592 goto nxge_attach_fail2; 593 } 594 595 nxgep->nxge_magic = NXGE_MAGIC; 596 597 nxgep->drv_state = 0; 598 nxgep->dip = dip; 599 nxgep->instance = instance; 600 nxgep->p_dip = ddi_get_parent(dip); 601 nxgep->nxge_debug_level = nxge_debug_level; 602 npi_debug_level = nxge_debug_level; 603 604 /* Are we a guest running in a Hybrid I/O environment? */ 605 nxge_get_environs(nxgep); 606 607 status = nxge_map_regs(nxgep); 608 609 if (status != NXGE_OK) { 610 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_map_regs failed")); 611 goto nxge_attach_fail3; 612 } 613 614 nxge_fm_init(nxgep, &nxge_dev_reg_acc_attr, 615 &nxge_dev_desc_dma_acc_attr, 616 &nxge_rx_dma_attr); 617 618 /* Create & initialize the per-Neptune data structure */ 619 /* (even if we're a guest). */ 620 status = nxge_init_common_dev(nxgep); 621 if (status != NXGE_OK) { 622 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 623 "nxge_init_common_dev failed")); 624 goto nxge_attach_fail4; 625 } 626 627 /* 628 * Software workaround: set the replay timer. 629 */ 630 if (nxgep->niu_type != N2_NIU) { 631 nxge_set_pci_replay_timeout(nxgep); 632 } 633 #if defined(sun4v) 634 if (isLDOMguest(nxgep)) { 635 nxge_m_callbacks.mc_tx = nxge_m_tx; 636 } 637 #endif 638 639 #if defined(sun4v) 640 /* This is required by nxge_hio_init(), which follows. */ 641 if ((status = nxge_hsvc_register(nxgep)) != DDI_SUCCESS) 642 goto nxge_attach_fail4; 643 #endif 644 645 if ((status = nxge_hio_init(nxgep)) != NXGE_OK) { 646 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 647 "nxge_hio_init failed")); 648 goto nxge_attach_fail4; 649 } 650 651 if (nxgep->niu_type == NEPTUNE_2_10GF) { 652 if (nxgep->function_num > 1) { 653 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "Unsupported" 654 " function %d. Only functions 0 and 1 are " 655 "supported for this card.", nxgep->function_num)); 656 status = NXGE_ERROR; 657 goto nxge_attach_fail4; 658 } 659 } 660 661 if (isLDOMguest(nxgep)) { 662 /* 663 * Use the function number here. 664 */ 665 nxgep->mac.portnum = nxgep->function_num; 666 nxgep->mac.porttype = PORT_TYPE_LOGICAL; 667 668 /* XXX We'll set the MAC address counts to 1 for now. */ 669 mmac_info = &nxgep->nxge_mmac_info; 670 mmac_info->num_mmac = 1; 671 mmac_info->naddrfree = 1; 672 } else { 673 portn = NXGE_GET_PORT_NUM(nxgep->function_num); 674 nxgep->mac.portnum = portn; 675 if ((portn == 0) || (portn == 1)) 676 nxgep->mac.porttype = PORT_TYPE_XMAC; 677 else 678 nxgep->mac.porttype = PORT_TYPE_BMAC; 679 /* 680 * Neptune has 4 ports, the first 2 ports use XMAC (10G MAC) 681 * internally, the rest 2 ports use BMAC (1G "Big" MAC). 682 * The two types of MACs have different characterizations. 683 */ 684 mmac_info = &nxgep->nxge_mmac_info; 685 if (nxgep->function_num < 2) { 686 mmac_info->num_mmac = XMAC_MAX_ALT_ADDR_ENTRY; 687 mmac_info->naddrfree = XMAC_MAX_ALT_ADDR_ENTRY; 688 } else { 689 mmac_info->num_mmac = BMAC_MAX_ALT_ADDR_ENTRY; 690 mmac_info->naddrfree = BMAC_MAX_ALT_ADDR_ENTRY; 691 } 692 } 693 /* 694 * Setup the Ndd parameters for the this instance. 695 */ 696 nxge_init_param(nxgep); 697 698 /* 699 * Setup Register Tracing Buffer. 700 */ 701 npi_rtrace_buf_init((rtrace_t *)&npi_rtracebuf); 702 703 /* init stats ptr */ 704 nxge_init_statsp(nxgep); 705 706 /* 707 * Copy the vpd info from eeprom to a local data 708 * structure, and then check its validity. 709 */ 710 if (!isLDOMguest(nxgep)) { 711 int *regp; 712 uint_t reglen; 713 int rv; 714 715 nxge_vpd_info_get(nxgep); 716 717 /* Find the NIU config handle. */ 718 rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 719 ddi_get_parent(nxgep->dip), DDI_PROP_DONTPASS, 720 "reg", ®p, ®len); 721 722 if (rv != DDI_PROP_SUCCESS) { 723 goto nxge_attach_fail5; 724 } 725 /* 726 * The address_hi, that is the first int, in the reg 727 * property consists of config handle, but need to remove 728 * the bits 28-31 which are OBP specific info. 729 */ 730 nxgep->niu_cfg_hdl = (*regp) & 0xFFFFFFF; 731 ddi_prop_free(regp); 732 } 733 734 /* 735 * Set the defaults for the MTU size. 736 */ 737 nxge_hw_id_init(nxgep); 738 739 if (isLDOMguest(nxgep)) { 740 uchar_t *prop_val; 741 uint_t prop_len; 742 uint32_t max_frame_size; 743 744 extern void nxge_get_logical_props(p_nxge_t); 745 746 nxgep->statsp->mac_stats.xcvr_inuse = LOGICAL_XCVR; 747 nxgep->mac.portmode = PORT_LOGICAL; 748 (void) ddi_prop_update_string(DDI_DEV_T_NONE, nxgep->dip, 749 "phy-type", "virtual transceiver"); 750 751 nxgep->nports = 1; 752 nxgep->board_ver = 0; /* XXX What? */ 753 754 /* 755 * local-mac-address property gives us info on which 756 * specific MAC address the Hybrid resource is associated 757 * with. 758 */ 759 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0, 760 "local-mac-address", &prop_val, 761 &prop_len) != DDI_PROP_SUCCESS) { 762 goto nxge_attach_fail5; 763 } 764 if (prop_len != ETHERADDRL) { 765 ddi_prop_free(prop_val); 766 goto nxge_attach_fail5; 767 } 768 ether_copy(prop_val, nxgep->hio_mac_addr); 769 ddi_prop_free(prop_val); 770 nxge_get_logical_props(nxgep); 771 772 /* 773 * Enable Jumbo property based on the "max-frame-size" 774 * property value. 775 */ 776 max_frame_size = ddi_prop_get_int(DDI_DEV_T_ANY, 777 nxgep->dip, DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, 778 "max-frame-size", NXGE_MTU_DEFAULT_MAX); 779 if ((max_frame_size > NXGE_MTU_DEFAULT_MAX) && 780 (max_frame_size <= TX_JUMBO_MTU)) { 781 nxgep->mac.is_jumbo = B_TRUE; 782 nxgep->mac.maxframesize = (uint16_t)max_frame_size; 783 nxgep->mac.default_mtu = nxgep->mac.maxframesize - 784 NXGE_EHEADER_VLAN_CRC; 785 } 786 } else { 787 status = nxge_xcvr_find(nxgep); 788 789 if (status != NXGE_OK) { 790 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_attach: " 791 " Couldn't determine card type" 792 " .... exit ")); 793 goto nxge_attach_fail5; 794 } 795 796 status = nxge_get_config_properties(nxgep); 797 798 if (status != NXGE_OK) { 799 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 800 "get_hw create failed")); 801 goto nxge_attach_fail; 802 } 803 } 804 805 /* 806 * Setup the Kstats for the driver. 807 */ 808 nxge_setup_kstats(nxgep); 809 810 if (!isLDOMguest(nxgep)) 811 nxge_setup_param(nxgep); 812 813 status = nxge_setup_system_dma_pages(nxgep); 814 if (status != NXGE_OK) { 815 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "set dma page failed")); 816 goto nxge_attach_fail; 817 } 818 819 820 if (!isLDOMguest(nxgep)) 821 nxge_hw_init_niu_common(nxgep); 822 823 status = nxge_setup_mutexes(nxgep); 824 if (status != NXGE_OK) { 825 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "set mutex failed")); 826 goto nxge_attach_fail; 827 } 828 829 #if defined(sun4v) 830 if (isLDOMguest(nxgep)) { 831 /* Find our VR & channel sets. */ 832 status = nxge_hio_vr_add(nxgep); 833 if (status != NXGE_OK) { 834 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 835 "nxge_hio_vr_add failed")); 836 (void) hsvc_unregister(&nxgep->niu_hsvc); 837 nxgep->niu_hsvc_available = B_FALSE; 838 } 839 goto nxge_attach_exit; 840 } 841 #endif 842 843 status = nxge_setup_dev(nxgep); 844 if (status != DDI_SUCCESS) { 845 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "set dev failed")); 846 goto nxge_attach_fail; 847 } 848 849 status = nxge_add_intrs(nxgep); 850 if (status != DDI_SUCCESS) { 851 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "add_intr failed")); 852 goto nxge_attach_fail; 853 } 854 855 /* If a guest, register with vio_net instead. */ 856 if ((status = nxge_mac_register(nxgep)) != NXGE_OK) { 857 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 858 "unable to register to mac layer (%d)", status)); 859 goto nxge_attach_fail; 860 } 861 862 mac_link_update(nxgep->mach, LINK_STATE_UNKNOWN); 863 864 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 865 "registered to mac (instance %d)", instance)); 866 867 /* nxge_link_monitor calls xcvr.check_link recursively */ 868 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 869 870 goto nxge_attach_exit; 871 872 nxge_attach_fail: 873 nxge_unattach(nxgep); 874 goto nxge_attach_fail1; 875 876 nxge_attach_fail5: 877 /* 878 * Tear down the ndd parameters setup. 879 */ 880 nxge_destroy_param(nxgep); 881 882 /* 883 * Tear down the kstat setup. 884 */ 885 nxge_destroy_kstats(nxgep); 886 887 nxge_attach_fail4: 888 if (nxgep->nxge_hw_p) { 889 nxge_uninit_common_dev(nxgep); 890 nxgep->nxge_hw_p = NULL; 891 } 892 893 nxge_attach_fail3: 894 /* 895 * Unmap the register setup. 896 */ 897 nxge_unmap_regs(nxgep); 898 899 nxge_fm_fini(nxgep); 900 901 nxge_attach_fail2: 902 ddi_soft_state_free(nxge_list, nxgep->instance); 903 904 nxge_attach_fail1: 905 if (status != NXGE_OK) 906 status = (NXGE_ERROR | NXGE_DDI_FAILED); 907 nxgep = NULL; 908 909 nxge_attach_exit: 910 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_attach status = 0x%08x", 911 status)); 912 913 return (status); 914 } 915 916 static int 917 nxge_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 918 { 919 int status = DDI_SUCCESS; 920 int instance; 921 p_nxge_t nxgep = NULL; 922 923 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_detach")); 924 instance = ddi_get_instance(dip); 925 nxgep = ddi_get_soft_state(nxge_list, instance); 926 if (nxgep == NULL) { 927 status = DDI_FAILURE; 928 goto nxge_detach_exit; 929 } 930 931 switch (cmd) { 932 case DDI_DETACH: 933 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_DETACH")); 934 break; 935 936 case DDI_PM_SUSPEND: 937 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_PM_SUSPEND")); 938 nxgep->suspended = DDI_PM_SUSPEND; 939 nxge_suspend(nxgep); 940 break; 941 942 case DDI_SUSPEND: 943 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_SUSPEND")); 944 if (nxgep->suspended != DDI_PM_SUSPEND) { 945 nxgep->suspended = DDI_SUSPEND; 946 nxge_suspend(nxgep); 947 } 948 break; 949 950 default: 951 status = DDI_FAILURE; 952 } 953 954 if (cmd != DDI_DETACH) 955 goto nxge_detach_exit; 956 957 /* 958 * Stop the xcvr polling. 959 */ 960 nxgep->suspended = cmd; 961 962 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 963 964 if (isLDOMguest(nxgep)) { 965 if (nxgep->nxge_mac_state == NXGE_MAC_STARTED) 966 nxge_m_stop((void *)nxgep); 967 nxge_hio_unregister(nxgep); 968 } else if (nxgep->mach && (status = mac_unregister(nxgep->mach)) != 0) { 969 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 970 "<== nxge_detach status = 0x%08X", status)); 971 return (DDI_FAILURE); 972 } 973 974 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 975 "<== nxge_detach (mac_unregister) status = 0x%08X", status)); 976 977 nxge_unattach(nxgep); 978 nxgep = NULL; 979 980 nxge_detach_exit: 981 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_detach status = 0x%08X", 982 status)); 983 984 return (status); 985 } 986 987 static void 988 nxge_unattach(p_nxge_t nxgep) 989 { 990 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_unattach")); 991 992 if (nxgep == NULL || nxgep->dev_regs == NULL) { 993 return; 994 } 995 996 nxgep->nxge_magic = 0; 997 998 if (nxgep->nxge_timerid) { 999 nxge_stop_timer(nxgep, nxgep->nxge_timerid); 1000 nxgep->nxge_timerid = 0; 1001 } 1002 1003 /* 1004 * If this flag is set, it will affect the Neptune 1005 * only. 1006 */ 1007 if ((nxgep->niu_type != N2_NIU) && nxge_peu_reset_enable) { 1008 nxge_niu_peu_reset(nxgep); 1009 } 1010 1011 #if defined(sun4v) 1012 if (isLDOMguest(nxgep)) { 1013 (void) nxge_hio_vr_release(nxgep); 1014 } 1015 #endif 1016 1017 if (nxgep->nxge_hw_p) { 1018 nxge_uninit_common_dev(nxgep); 1019 nxgep->nxge_hw_p = NULL; 1020 } 1021 1022 #if defined(sun4v) 1023 if (nxgep->niu_type == N2_NIU && nxgep->niu_hsvc_available == B_TRUE) { 1024 (void) hsvc_unregister(&nxgep->niu_hsvc); 1025 nxgep->niu_hsvc_available = B_FALSE; 1026 } 1027 #endif 1028 /* 1029 * Stop any further interrupts. 1030 */ 1031 nxge_remove_intrs(nxgep); 1032 1033 /* 1034 * Stop the device and free resources. 1035 */ 1036 if (!isLDOMguest(nxgep)) { 1037 nxge_destroy_dev(nxgep); 1038 } 1039 1040 /* 1041 * Tear down the ndd parameters setup. 1042 */ 1043 nxge_destroy_param(nxgep); 1044 1045 /* 1046 * Tear down the kstat setup. 1047 */ 1048 nxge_destroy_kstats(nxgep); 1049 1050 /* 1051 * Destroy all mutexes. 1052 */ 1053 nxge_destroy_mutexes(nxgep); 1054 1055 /* 1056 * Remove the list of ndd parameters which 1057 * were setup during attach. 1058 */ 1059 if (nxgep->dip) { 1060 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1061 " nxge_unattach: remove all properties")); 1062 1063 (void) ddi_prop_remove_all(nxgep->dip); 1064 } 1065 1066 #if NXGE_PROPERTY 1067 nxge_remove_hard_properties(nxgep); 1068 #endif 1069 1070 /* 1071 * Unmap the register setup. 1072 */ 1073 nxge_unmap_regs(nxgep); 1074 1075 nxge_fm_fini(nxgep); 1076 1077 ddi_soft_state_free(nxge_list, nxgep->instance); 1078 1079 NXGE_DEBUG_MSG((NULL, DDI_CTL, "<== nxge_unattach")); 1080 } 1081 1082 #if defined(sun4v) 1083 int 1084 nxge_hsvc_register(nxge_t *nxgep) 1085 { 1086 nxge_status_t status; 1087 1088 if (nxgep->niu_type == N2_NIU) { 1089 nxgep->niu_hsvc_available = B_FALSE; 1090 bcopy(&niu_hsvc, &nxgep->niu_hsvc, sizeof (hsvc_info_t)); 1091 if ((status = hsvc_register(&nxgep->niu_hsvc, 1092 &nxgep->niu_min_ver)) != 0) { 1093 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1094 "nxge_attach: %s: cannot negotiate " 1095 "hypervisor services revision %d group: 0x%lx " 1096 "major: 0x%lx minor: 0x%lx errno: %d", 1097 niu_hsvc.hsvc_modname, niu_hsvc.hsvc_rev, 1098 niu_hsvc.hsvc_group, niu_hsvc.hsvc_major, 1099 niu_hsvc.hsvc_minor, status)); 1100 return (DDI_FAILURE); 1101 } 1102 nxgep->niu_hsvc_available = B_TRUE; 1103 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1104 "NIU Hypervisor service enabled")); 1105 } 1106 1107 return (DDI_SUCCESS); 1108 } 1109 #endif 1110 1111 static char n2_siu_name[] = "niu"; 1112 1113 static nxge_status_t 1114 nxge_map_regs(p_nxge_t nxgep) 1115 { 1116 int ddi_status = DDI_SUCCESS; 1117 p_dev_regs_t dev_regs; 1118 char buf[MAXPATHLEN + 1]; 1119 char *devname; 1120 #ifdef NXGE_DEBUG 1121 char *sysname; 1122 #endif 1123 off_t regsize; 1124 nxge_status_t status = NXGE_OK; 1125 #if !defined(_BIG_ENDIAN) 1126 off_t pci_offset; 1127 uint16_t pcie_devctl; 1128 #endif 1129 1130 if (isLDOMguest(nxgep)) { 1131 return (nxge_guest_regs_map(nxgep)); 1132 } 1133 1134 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_map_regs")); 1135 nxgep->dev_regs = NULL; 1136 dev_regs = KMEM_ZALLOC(sizeof (dev_regs_t), KM_SLEEP); 1137 dev_regs->nxge_regh = NULL; 1138 dev_regs->nxge_pciregh = NULL; 1139 dev_regs->nxge_msix_regh = NULL; 1140 dev_regs->nxge_vir_regh = NULL; 1141 dev_regs->nxge_vir2_regh = NULL; 1142 nxgep->niu_type = NIU_TYPE_NONE; 1143 1144 devname = ddi_pathname(nxgep->dip, buf); 1145 ASSERT(strlen(devname) > 0); 1146 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1147 "nxge_map_regs: pathname devname %s", devname)); 1148 1149 /* 1150 * The driver is running on a N2-NIU system if devname is something 1151 * like "/niu@80/network@0" 1152 */ 1153 if (strstr(devname, n2_siu_name)) { 1154 /* N2/NIU */ 1155 nxgep->niu_type = N2_NIU; 1156 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1157 "nxge_map_regs: N2/NIU devname %s", devname)); 1158 /* get function number */ 1159 nxgep->function_num = 1160 (devname[strlen(devname) -1] == '1' ? 1 : 0); 1161 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1162 "nxge_map_regs: N2/NIU function number %d", 1163 nxgep->function_num)); 1164 } else { 1165 int *prop_val; 1166 uint_t prop_len; 1167 uint8_t func_num; 1168 1169 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 1170 0, "reg", 1171 &prop_val, &prop_len) != DDI_PROP_SUCCESS) { 1172 NXGE_DEBUG_MSG((nxgep, VPD_CTL, 1173 "Reg property not found")); 1174 ddi_status = DDI_FAILURE; 1175 goto nxge_map_regs_fail0; 1176 1177 } else { 1178 func_num = (prop_val[0] >> 8) & 0x7; 1179 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1180 "Reg property found: fun # %d", 1181 func_num)); 1182 nxgep->function_num = func_num; 1183 if (isLDOMguest(nxgep)) { 1184 nxgep->function_num /= 2; 1185 return (NXGE_OK); 1186 } 1187 ddi_prop_free(prop_val); 1188 } 1189 } 1190 1191 switch (nxgep->niu_type) { 1192 default: 1193 (void) ddi_dev_regsize(nxgep->dip, 0, ®size); 1194 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1195 "nxge_map_regs: pci config size 0x%x", regsize)); 1196 1197 ddi_status = ddi_regs_map_setup(nxgep->dip, 0, 1198 (caddr_t *)&(dev_regs->nxge_pciregp), 0, 0, 1199 &nxge_dev_reg_acc_attr, &dev_regs->nxge_pciregh); 1200 if (ddi_status != DDI_SUCCESS) { 1201 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1202 "ddi_map_regs, nxge bus config regs failed")); 1203 goto nxge_map_regs_fail0; 1204 } 1205 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1206 "nxge_map_reg: PCI config addr 0x%0llx " 1207 " handle 0x%0llx", dev_regs->nxge_pciregp, 1208 dev_regs->nxge_pciregh)); 1209 /* 1210 * IMP IMP 1211 * workaround for bit swapping bug in HW 1212 * which ends up in no-snoop = yes 1213 * resulting, in DMA not synched properly 1214 */ 1215 #if !defined(_BIG_ENDIAN) 1216 /* workarounds for x86 systems */ 1217 pci_offset = 0x80 + PCIE_DEVCTL; 1218 pcie_devctl = pci_config_get16(dev_regs->nxge_pciregh, 1219 pci_offset); 1220 pcie_devctl &= ~PCIE_DEVCTL_ENABLE_NO_SNOOP; 1221 pcie_devctl |= PCIE_DEVCTL_RO_EN; 1222 pci_config_put16(dev_regs->nxge_pciregh, pci_offset, 1223 pcie_devctl); 1224 #endif 1225 1226 (void) ddi_dev_regsize(nxgep->dip, 1, ®size); 1227 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1228 "nxge_map_regs: pio size 0x%x", regsize)); 1229 /* set up the device mapped register */ 1230 ddi_status = ddi_regs_map_setup(nxgep->dip, 1, 1231 (caddr_t *)&(dev_regs->nxge_regp), 0, 0, 1232 &nxge_dev_reg_acc_attr, &dev_regs->nxge_regh); 1233 if (ddi_status != DDI_SUCCESS) { 1234 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1235 "ddi_map_regs for Neptune global reg failed")); 1236 goto nxge_map_regs_fail1; 1237 } 1238 1239 /* set up the msi/msi-x mapped register */ 1240 (void) ddi_dev_regsize(nxgep->dip, 2, ®size); 1241 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1242 "nxge_map_regs: msix size 0x%x", regsize)); 1243 ddi_status = ddi_regs_map_setup(nxgep->dip, 2, 1244 (caddr_t *)&(dev_regs->nxge_msix_regp), 0, 0, 1245 &nxge_dev_reg_acc_attr, &dev_regs->nxge_msix_regh); 1246 if (ddi_status != DDI_SUCCESS) { 1247 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1248 "ddi_map_regs for msi reg failed")); 1249 goto nxge_map_regs_fail2; 1250 } 1251 1252 /* set up the vio region mapped register */ 1253 (void) ddi_dev_regsize(nxgep->dip, 3, ®size); 1254 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1255 "nxge_map_regs: vio size 0x%x", regsize)); 1256 ddi_status = ddi_regs_map_setup(nxgep->dip, 3, 1257 (caddr_t *)&(dev_regs->nxge_vir_regp), 0, 0, 1258 &nxge_dev_reg_acc_attr, &dev_regs->nxge_vir_regh); 1259 1260 if (ddi_status != DDI_SUCCESS) { 1261 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1262 "ddi_map_regs for nxge vio reg failed")); 1263 goto nxge_map_regs_fail3; 1264 } 1265 nxgep->dev_regs = dev_regs; 1266 1267 NPI_PCI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_pciregh); 1268 NPI_PCI_ADD_HANDLE_SET(nxgep, 1269 (npi_reg_ptr_t)dev_regs->nxge_pciregp); 1270 NPI_MSI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_msix_regh); 1271 NPI_MSI_ADD_HANDLE_SET(nxgep, 1272 (npi_reg_ptr_t)dev_regs->nxge_msix_regp); 1273 1274 NPI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 1275 NPI_ADD_HANDLE_SET(nxgep, (npi_reg_ptr_t)dev_regs->nxge_regp); 1276 1277 NPI_REG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 1278 NPI_REG_ADD_HANDLE_SET(nxgep, 1279 (npi_reg_ptr_t)dev_regs->nxge_regp); 1280 1281 NPI_VREG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir_regh); 1282 NPI_VREG_ADD_HANDLE_SET(nxgep, 1283 (npi_reg_ptr_t)dev_regs->nxge_vir_regp); 1284 1285 break; 1286 1287 case N2_NIU: 1288 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "ddi_map_regs, NIU")); 1289 /* 1290 * Set up the device mapped register (FWARC 2006/556) 1291 * (changed back to 1: reg starts at 1!) 1292 */ 1293 (void) ddi_dev_regsize(nxgep->dip, 1, ®size); 1294 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1295 "nxge_map_regs: dev size 0x%x", regsize)); 1296 ddi_status = ddi_regs_map_setup(nxgep->dip, 1, 1297 (caddr_t *)&(dev_regs->nxge_regp), 0, 0, 1298 &nxge_dev_reg_acc_attr, &dev_regs->nxge_regh); 1299 1300 if (ddi_status != DDI_SUCCESS) { 1301 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1302 "ddi_map_regs for N2/NIU, global reg failed ")); 1303 goto nxge_map_regs_fail1; 1304 } 1305 1306 /* set up the first vio region mapped register */ 1307 (void) ddi_dev_regsize(nxgep->dip, 2, ®size); 1308 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1309 "nxge_map_regs: vio (1) size 0x%x", regsize)); 1310 ddi_status = ddi_regs_map_setup(nxgep->dip, 2, 1311 (caddr_t *)&(dev_regs->nxge_vir_regp), 0, 0, 1312 &nxge_dev_reg_acc_attr, &dev_regs->nxge_vir_regh); 1313 1314 if (ddi_status != DDI_SUCCESS) { 1315 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1316 "ddi_map_regs for nxge vio reg failed")); 1317 goto nxge_map_regs_fail2; 1318 } 1319 /* set up the second vio region mapped register */ 1320 (void) ddi_dev_regsize(nxgep->dip, 3, ®size); 1321 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1322 "nxge_map_regs: vio (3) size 0x%x", regsize)); 1323 ddi_status = ddi_regs_map_setup(nxgep->dip, 3, 1324 (caddr_t *)&(dev_regs->nxge_vir2_regp), 0, 0, 1325 &nxge_dev_reg_acc_attr, &dev_regs->nxge_vir2_regh); 1326 1327 if (ddi_status != DDI_SUCCESS) { 1328 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1329 "ddi_map_regs for nxge vio2 reg failed")); 1330 goto nxge_map_regs_fail3; 1331 } 1332 nxgep->dev_regs = dev_regs; 1333 1334 NPI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 1335 NPI_ADD_HANDLE_SET(nxgep, (npi_reg_ptr_t)dev_regs->nxge_regp); 1336 1337 NPI_REG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 1338 NPI_REG_ADD_HANDLE_SET(nxgep, 1339 (npi_reg_ptr_t)dev_regs->nxge_regp); 1340 1341 NPI_VREG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir_regh); 1342 NPI_VREG_ADD_HANDLE_SET(nxgep, 1343 (npi_reg_ptr_t)dev_regs->nxge_vir_regp); 1344 1345 NPI_V2REG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir2_regh); 1346 NPI_V2REG_ADD_HANDLE_SET(nxgep, 1347 (npi_reg_ptr_t)dev_regs->nxge_vir2_regp); 1348 1349 break; 1350 } 1351 1352 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "nxge_map_reg: hardware addr 0x%0llx " 1353 " handle 0x%0llx", dev_regs->nxge_regp, dev_regs->nxge_regh)); 1354 1355 goto nxge_map_regs_exit; 1356 nxge_map_regs_fail3: 1357 if (dev_regs->nxge_msix_regh) { 1358 ddi_regs_map_free(&dev_regs->nxge_msix_regh); 1359 } 1360 if (dev_regs->nxge_vir_regh) { 1361 ddi_regs_map_free(&dev_regs->nxge_regh); 1362 } 1363 nxge_map_regs_fail2: 1364 if (dev_regs->nxge_regh) { 1365 ddi_regs_map_free(&dev_regs->nxge_regh); 1366 } 1367 nxge_map_regs_fail1: 1368 if (dev_regs->nxge_pciregh) { 1369 ddi_regs_map_free(&dev_regs->nxge_pciregh); 1370 } 1371 nxge_map_regs_fail0: 1372 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "Freeing register set memory")); 1373 kmem_free(dev_regs, sizeof (dev_regs_t)); 1374 1375 nxge_map_regs_exit: 1376 if (ddi_status != DDI_SUCCESS) 1377 status |= (NXGE_ERROR | NXGE_DDI_FAILED); 1378 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_map_regs")); 1379 return (status); 1380 } 1381 1382 static void 1383 nxge_unmap_regs(p_nxge_t nxgep) 1384 { 1385 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_unmap_regs")); 1386 1387 if (isLDOMguest(nxgep)) { 1388 nxge_guest_regs_map_free(nxgep); 1389 return; 1390 } 1391 1392 if (nxgep->dev_regs) { 1393 if (nxgep->dev_regs->nxge_pciregh) { 1394 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1395 "==> nxge_unmap_regs: bus")); 1396 ddi_regs_map_free(&nxgep->dev_regs->nxge_pciregh); 1397 nxgep->dev_regs->nxge_pciregh = NULL; 1398 } 1399 if (nxgep->dev_regs->nxge_regh) { 1400 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1401 "==> nxge_unmap_regs: device registers")); 1402 ddi_regs_map_free(&nxgep->dev_regs->nxge_regh); 1403 nxgep->dev_regs->nxge_regh = NULL; 1404 } 1405 if (nxgep->dev_regs->nxge_msix_regh) { 1406 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1407 "==> nxge_unmap_regs: device interrupts")); 1408 ddi_regs_map_free(&nxgep->dev_regs->nxge_msix_regh); 1409 nxgep->dev_regs->nxge_msix_regh = NULL; 1410 } 1411 if (nxgep->dev_regs->nxge_vir_regh) { 1412 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1413 "==> nxge_unmap_regs: vio region")); 1414 ddi_regs_map_free(&nxgep->dev_regs->nxge_vir_regh); 1415 nxgep->dev_regs->nxge_vir_regh = NULL; 1416 } 1417 if (nxgep->dev_regs->nxge_vir2_regh) { 1418 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1419 "==> nxge_unmap_regs: vio2 region")); 1420 ddi_regs_map_free(&nxgep->dev_regs->nxge_vir2_regh); 1421 nxgep->dev_regs->nxge_vir2_regh = NULL; 1422 } 1423 1424 kmem_free(nxgep->dev_regs, sizeof (dev_regs_t)); 1425 nxgep->dev_regs = NULL; 1426 } 1427 1428 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_unmap_regs")); 1429 } 1430 1431 static nxge_status_t 1432 nxge_setup_mutexes(p_nxge_t nxgep) 1433 { 1434 int ddi_status = DDI_SUCCESS; 1435 nxge_status_t status = NXGE_OK; 1436 nxge_classify_t *classify_ptr; 1437 int partition; 1438 1439 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_setup_mutexes")); 1440 1441 /* 1442 * Get the interrupt cookie so the mutexes can be 1443 * Initialized. 1444 */ 1445 if (isLDOMguest(nxgep)) { 1446 nxgep->interrupt_cookie = 0; 1447 } else { 1448 ddi_status = ddi_get_iblock_cookie(nxgep->dip, 0, 1449 &nxgep->interrupt_cookie); 1450 1451 if (ddi_status != DDI_SUCCESS) { 1452 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1453 "<== nxge_setup_mutexes: failed 0x%x", 1454 ddi_status)); 1455 goto nxge_setup_mutexes_exit; 1456 } 1457 } 1458 1459 cv_init(&nxgep->poll_cv, NULL, CV_DRIVER, NULL); 1460 MUTEX_INIT(&nxgep->poll_lock, NULL, 1461 MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1462 1463 /* 1464 * Initialize mutexes for this device. 1465 */ 1466 MUTEX_INIT(nxgep->genlock, NULL, 1467 MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1468 MUTEX_INIT(&nxgep->ouraddr_lock, NULL, 1469 MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1470 MUTEX_INIT(&nxgep->mif_lock, NULL, 1471 MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1472 MUTEX_INIT(&nxgep->group_lock, NULL, 1473 MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1474 RW_INIT(&nxgep->filter_lock, NULL, 1475 RW_DRIVER, (void *)nxgep->interrupt_cookie); 1476 1477 classify_ptr = &nxgep->classifier; 1478 /* 1479 * FFLP Mutexes are never used in interrupt context 1480 * as fflp operation can take very long time to 1481 * complete and hence not suitable to invoke from interrupt 1482 * handlers. 1483 */ 1484 MUTEX_INIT(&classify_ptr->tcam_lock, NULL, 1485 NXGE_MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1486 if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 1487 MUTEX_INIT(&classify_ptr->fcram_lock, NULL, 1488 NXGE_MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1489 for (partition = 0; partition < MAX_PARTITION; partition++) { 1490 MUTEX_INIT(&classify_ptr->hash_lock[partition], NULL, 1491 NXGE_MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1492 } 1493 } 1494 1495 nxge_setup_mutexes_exit: 1496 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1497 "<== nxge_setup_mutexes status = %x", status)); 1498 1499 if (ddi_status != DDI_SUCCESS) 1500 status |= (NXGE_ERROR | NXGE_DDI_FAILED); 1501 1502 return (status); 1503 } 1504 1505 static void 1506 nxge_destroy_mutexes(p_nxge_t nxgep) 1507 { 1508 int partition; 1509 nxge_classify_t *classify_ptr; 1510 1511 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_mutexes")); 1512 RW_DESTROY(&nxgep->filter_lock); 1513 MUTEX_DESTROY(&nxgep->group_lock); 1514 MUTEX_DESTROY(&nxgep->mif_lock); 1515 MUTEX_DESTROY(&nxgep->ouraddr_lock); 1516 MUTEX_DESTROY(nxgep->genlock); 1517 1518 classify_ptr = &nxgep->classifier; 1519 MUTEX_DESTROY(&classify_ptr->tcam_lock); 1520 1521 /* Destroy all polling resources. */ 1522 MUTEX_DESTROY(&nxgep->poll_lock); 1523 cv_destroy(&nxgep->poll_cv); 1524 1525 /* free data structures, based on HW type */ 1526 if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 1527 MUTEX_DESTROY(&classify_ptr->fcram_lock); 1528 for (partition = 0; partition < MAX_PARTITION; partition++) { 1529 MUTEX_DESTROY(&classify_ptr->hash_lock[partition]); 1530 } 1531 } 1532 1533 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_mutexes")); 1534 } 1535 1536 nxge_status_t 1537 nxge_init(p_nxge_t nxgep) 1538 { 1539 nxge_status_t status = NXGE_OK; 1540 1541 NXGE_DEBUG_MSG((nxgep, STR_CTL, "==> nxge_init")); 1542 1543 if (nxgep->drv_state & STATE_HW_INITIALIZED) { 1544 return (status); 1545 } 1546 1547 /* 1548 * Allocate system memory for the receive/transmit buffer blocks 1549 * and receive/transmit descriptor rings. 1550 */ 1551 status = nxge_alloc_mem_pool(nxgep); 1552 if (status != NXGE_OK) { 1553 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "alloc mem failed\n")); 1554 goto nxge_init_fail1; 1555 } 1556 1557 if (!isLDOMguest(nxgep)) { 1558 /* 1559 * Initialize and enable the TXC registers. 1560 * (Globally enable the Tx controller, 1561 * enable the port, configure the dma channel bitmap, 1562 * configure the max burst size). 1563 */ 1564 status = nxge_txc_init(nxgep); 1565 if (status != NXGE_OK) { 1566 NXGE_ERROR_MSG((nxgep, 1567 NXGE_ERR_CTL, "init txc failed\n")); 1568 goto nxge_init_fail2; 1569 } 1570 } 1571 1572 /* 1573 * Initialize and enable TXDMA channels. 1574 */ 1575 status = nxge_init_txdma_channels(nxgep); 1576 if (status != NXGE_OK) { 1577 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init txdma failed\n")); 1578 goto nxge_init_fail3; 1579 } 1580 1581 /* 1582 * Initialize and enable RXDMA channels. 1583 */ 1584 status = nxge_init_rxdma_channels(nxgep); 1585 if (status != NXGE_OK) { 1586 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init rxdma failed\n")); 1587 goto nxge_init_fail4; 1588 } 1589 1590 /* 1591 * The guest domain is now done. 1592 */ 1593 if (isLDOMguest(nxgep)) { 1594 nxgep->drv_state |= STATE_HW_INITIALIZED; 1595 goto nxge_init_exit; 1596 } 1597 1598 /* 1599 * Initialize TCAM and FCRAM (Neptune). 1600 */ 1601 status = nxge_classify_init(nxgep); 1602 if (status != NXGE_OK) { 1603 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init classify failed\n")); 1604 goto nxge_init_fail5; 1605 } 1606 1607 /* 1608 * Initialize ZCP 1609 */ 1610 status = nxge_zcp_init(nxgep); 1611 if (status != NXGE_OK) { 1612 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init ZCP failed\n")); 1613 goto nxge_init_fail5; 1614 } 1615 1616 /* 1617 * Initialize IPP. 1618 */ 1619 status = nxge_ipp_init(nxgep); 1620 if (status != NXGE_OK) { 1621 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init IPP failed\n")); 1622 goto nxge_init_fail5; 1623 } 1624 1625 /* 1626 * Initialize the MAC block. 1627 */ 1628 status = nxge_mac_init(nxgep); 1629 if (status != NXGE_OK) { 1630 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init MAC failed\n")); 1631 goto nxge_init_fail5; 1632 } 1633 1634 /* 1635 * Enable the interrrupts for DDI. 1636 */ 1637 nxge_intrs_enable(nxgep); 1638 1639 nxgep->drv_state |= STATE_HW_INITIALIZED; 1640 1641 goto nxge_init_exit; 1642 1643 nxge_init_fail5: 1644 nxge_uninit_rxdma_channels(nxgep); 1645 nxge_init_fail4: 1646 nxge_uninit_txdma_channels(nxgep); 1647 nxge_init_fail3: 1648 if (!isLDOMguest(nxgep)) { 1649 (void) nxge_txc_uninit(nxgep); 1650 } 1651 nxge_init_fail2: 1652 nxge_free_mem_pool(nxgep); 1653 nxge_init_fail1: 1654 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1655 "<== nxge_init status (failed) = 0x%08x", status)); 1656 return (status); 1657 1658 nxge_init_exit: 1659 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init status = 0x%08x", 1660 status)); 1661 return (status); 1662 } 1663 1664 1665 timeout_id_t 1666 nxge_start_timer(p_nxge_t nxgep, fptrv_t func, int msec) 1667 { 1668 if ((nxgep->suspended == 0) || (nxgep->suspended == DDI_RESUME)) { 1669 return (timeout(func, (caddr_t)nxgep, 1670 drv_usectohz(1000 * msec))); 1671 } 1672 return (NULL); 1673 } 1674 1675 /*ARGSUSED*/ 1676 void 1677 nxge_stop_timer(p_nxge_t nxgep, timeout_id_t timerid) 1678 { 1679 if (timerid) { 1680 (void) untimeout(timerid); 1681 } 1682 } 1683 1684 void 1685 nxge_uninit(p_nxge_t nxgep) 1686 { 1687 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_uninit")); 1688 1689 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 1690 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1691 "==> nxge_uninit: not initialized")); 1692 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1693 "<== nxge_uninit")); 1694 return; 1695 } 1696 1697 if (!isLDOMguest(nxgep)) { 1698 /* 1699 * Reset the receive MAC side. 1700 */ 1701 (void) nxge_rx_mac_disable(nxgep); 1702 1703 /* 1704 * Drain the IPP. 1705 */ 1706 (void) nxge_ipp_drain(nxgep); 1707 } 1708 1709 /* stop timer */ 1710 if (nxgep->nxge_timerid) { 1711 nxge_stop_timer(nxgep, nxgep->nxge_timerid); 1712 nxgep->nxge_timerid = 0; 1713 } 1714 1715 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 1716 (void) nxge_intr_hw_disable(nxgep); 1717 1718 1719 /* Disable and soft reset the IPP */ 1720 if (!isLDOMguest(nxgep)) 1721 (void) nxge_ipp_disable(nxgep); 1722 1723 /* Free classification resources */ 1724 (void) nxge_classify_uninit(nxgep); 1725 1726 /* 1727 * Reset the transmit/receive DMA side. 1728 */ 1729 (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_STOP); 1730 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP); 1731 1732 nxge_uninit_txdma_channels(nxgep); 1733 nxge_uninit_rxdma_channels(nxgep); 1734 1735 /* 1736 * Reset the transmit MAC side. 1737 */ 1738 (void) nxge_tx_mac_disable(nxgep); 1739 1740 nxge_free_mem_pool(nxgep); 1741 1742 /* 1743 * Start the timer if the reset flag is not set. 1744 * If this reset flag is set, the link monitor 1745 * will not be started in order to stop furthur bus 1746 * activities coming from this interface. 1747 * The driver will start the monitor function 1748 * if the interface was initialized again later. 1749 */ 1750 if (!nxge_peu_reset_enable) { 1751 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 1752 } 1753 1754 nxgep->drv_state &= ~STATE_HW_INITIALIZED; 1755 1756 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_uninit: " 1757 "nxge_mblks_pending %d", nxge_mblks_pending)); 1758 } 1759 1760 void 1761 nxge_get64(p_nxge_t nxgep, p_mblk_t mp) 1762 { 1763 uint64_t reg; 1764 uint64_t regdata; 1765 int i, retry; 1766 1767 bcopy((char *)mp->b_rptr, (char *)®, sizeof (uint64_t)); 1768 regdata = 0; 1769 retry = 1; 1770 1771 for (i = 0; i < retry; i++) { 1772 NXGE_REG_RD64(nxgep->npi_handle, reg, ®data); 1773 } 1774 bcopy((char *)®data, (char *)mp->b_rptr, sizeof (uint64_t)); 1775 } 1776 1777 void 1778 nxge_put64(p_nxge_t nxgep, p_mblk_t mp) 1779 { 1780 uint64_t reg; 1781 uint64_t buf[2]; 1782 1783 bcopy((char *)mp->b_rptr, (char *)&buf[0], 2 * sizeof (uint64_t)); 1784 reg = buf[0]; 1785 1786 NXGE_NPI_PIO_WRITE64(nxgep->npi_handle, reg, buf[1]); 1787 } 1788 1789 1790 nxge_os_mutex_t nxgedebuglock; 1791 int nxge_debug_init = 0; 1792 1793 /*ARGSUSED*/ 1794 /*VARARGS*/ 1795 void 1796 nxge_debug_msg(p_nxge_t nxgep, uint64_t level, char *fmt, ...) 1797 { 1798 char msg_buffer[1048]; 1799 char prefix_buffer[32]; 1800 int instance; 1801 uint64_t debug_level; 1802 int cmn_level = CE_CONT; 1803 va_list ap; 1804 1805 if (nxgep && nxgep->nxge_debug_level != nxge_debug_level) { 1806 /* In case a developer has changed nxge_debug_level. */ 1807 if (nxgep->nxge_debug_level != nxge_debug_level) 1808 nxgep->nxge_debug_level = nxge_debug_level; 1809 } 1810 1811 debug_level = (nxgep == NULL) ? nxge_debug_level : 1812 nxgep->nxge_debug_level; 1813 1814 if ((level & debug_level) || 1815 (level == NXGE_NOTE) || 1816 (level == NXGE_ERR_CTL)) { 1817 /* do the msg processing */ 1818 if (nxge_debug_init == 0) { 1819 MUTEX_INIT(&nxgedebuglock, NULL, MUTEX_DRIVER, NULL); 1820 nxge_debug_init = 1; 1821 } 1822 1823 MUTEX_ENTER(&nxgedebuglock); 1824 1825 if ((level & NXGE_NOTE)) { 1826 cmn_level = CE_NOTE; 1827 } 1828 1829 if (level & NXGE_ERR_CTL) { 1830 cmn_level = CE_WARN; 1831 } 1832 1833 va_start(ap, fmt); 1834 (void) vsprintf(msg_buffer, fmt, ap); 1835 va_end(ap); 1836 if (nxgep == NULL) { 1837 instance = -1; 1838 (void) sprintf(prefix_buffer, "%s :", "nxge"); 1839 } else { 1840 instance = nxgep->instance; 1841 (void) sprintf(prefix_buffer, 1842 "%s%d :", "nxge", instance); 1843 } 1844 1845 MUTEX_EXIT(&nxgedebuglock); 1846 cmn_err(cmn_level, "!%s %s\n", 1847 prefix_buffer, msg_buffer); 1848 1849 } 1850 } 1851 1852 char * 1853 nxge_dump_packet(char *addr, int size) 1854 { 1855 uchar_t *ap = (uchar_t *)addr; 1856 int i; 1857 static char etherbuf[1024]; 1858 char *cp = etherbuf; 1859 char digits[] = "0123456789abcdef"; 1860 1861 if (!size) 1862 size = 60; 1863 1864 if (size > MAX_DUMP_SZ) { 1865 /* Dump the leading bytes */ 1866 for (i = 0; i < MAX_DUMP_SZ/2; i++) { 1867 if (*ap > 0x0f) 1868 *cp++ = digits[*ap >> 4]; 1869 *cp++ = digits[*ap++ & 0xf]; 1870 *cp++ = ':'; 1871 } 1872 for (i = 0; i < 20; i++) 1873 *cp++ = '.'; 1874 /* Dump the last MAX_DUMP_SZ/2 bytes */ 1875 ap = (uchar_t *)(addr + (size - MAX_DUMP_SZ/2)); 1876 for (i = 0; i < MAX_DUMP_SZ/2; i++) { 1877 if (*ap > 0x0f) 1878 *cp++ = digits[*ap >> 4]; 1879 *cp++ = digits[*ap++ & 0xf]; 1880 *cp++ = ':'; 1881 } 1882 } else { 1883 for (i = 0; i < size; i++) { 1884 if (*ap > 0x0f) 1885 *cp++ = digits[*ap >> 4]; 1886 *cp++ = digits[*ap++ & 0xf]; 1887 *cp++ = ':'; 1888 } 1889 } 1890 *--cp = 0; 1891 return (etherbuf); 1892 } 1893 1894 #ifdef NXGE_DEBUG 1895 static void 1896 nxge_test_map_regs(p_nxge_t nxgep) 1897 { 1898 ddi_acc_handle_t cfg_handle; 1899 p_pci_cfg_t cfg_ptr; 1900 ddi_acc_handle_t dev_handle; 1901 char *dev_ptr; 1902 ddi_acc_handle_t pci_config_handle; 1903 uint32_t regval; 1904 int i; 1905 1906 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_test_map_regs")); 1907 1908 dev_handle = nxgep->dev_regs->nxge_regh; 1909 dev_ptr = (char *)nxgep->dev_regs->nxge_regp; 1910 1911 if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 1912 cfg_handle = nxgep->dev_regs->nxge_pciregh; 1913 cfg_ptr = (void *)nxgep->dev_regs->nxge_pciregp; 1914 1915 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1916 "Neptune PCI regp cfg_ptr 0x%llx", (char *)cfg_ptr)); 1917 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1918 "Neptune PCI cfg_ptr vendor id ptr 0x%llx", 1919 &cfg_ptr->vendorid)); 1920 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1921 "\tvendorid 0x%x devid 0x%x", 1922 NXGE_PIO_READ16(cfg_handle, &cfg_ptr->vendorid, 0), 1923 NXGE_PIO_READ16(cfg_handle, &cfg_ptr->devid, 0))); 1924 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1925 "PCI BAR: base 0x%x base14 0x%x base 18 0x%x " 1926 "bar1c 0x%x", 1927 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base, 0), 1928 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base14, 0), 1929 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base18, 0), 1930 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base1c, 0))); 1931 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1932 "\nNeptune PCI BAR: base20 0x%x base24 0x%x " 1933 "base 28 0x%x bar2c 0x%x\n", 1934 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base20, 0), 1935 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base24, 0), 1936 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base28, 0), 1937 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base2c, 0))); 1938 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1939 "\nNeptune PCI BAR: base30 0x%x\n", 1940 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base30, 0))); 1941 1942 cfg_handle = nxgep->dev_regs->nxge_pciregh; 1943 cfg_ptr = (void *)nxgep->dev_regs->nxge_pciregp; 1944 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1945 "first 0x%llx second 0x%llx third 0x%llx " 1946 "last 0x%llx ", 1947 NXGE_PIO_READ64(dev_handle, 1948 (uint64_t *)(dev_ptr + 0), 0), 1949 NXGE_PIO_READ64(dev_handle, 1950 (uint64_t *)(dev_ptr + 8), 0), 1951 NXGE_PIO_READ64(dev_handle, 1952 (uint64_t *)(dev_ptr + 16), 0), 1953 NXGE_PIO_READ64(cfg_handle, 1954 (uint64_t *)(dev_ptr + 24), 0))); 1955 } 1956 } 1957 1958 #endif 1959 1960 static void 1961 nxge_suspend(p_nxge_t nxgep) 1962 { 1963 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_suspend")); 1964 1965 nxge_intrs_disable(nxgep); 1966 nxge_destroy_dev(nxgep); 1967 1968 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_suspend")); 1969 } 1970 1971 static nxge_status_t 1972 nxge_resume(p_nxge_t nxgep) 1973 { 1974 nxge_status_t status = NXGE_OK; 1975 1976 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_resume")); 1977 1978 nxgep->suspended = DDI_RESUME; 1979 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 1980 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_START); 1981 (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_START); 1982 (void) nxge_rx_mac_enable(nxgep); 1983 (void) nxge_tx_mac_enable(nxgep); 1984 nxge_intrs_enable(nxgep); 1985 nxgep->suspended = 0; 1986 1987 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1988 "<== nxge_resume status = 0x%x", status)); 1989 return (status); 1990 } 1991 1992 static nxge_status_t 1993 nxge_setup_dev(p_nxge_t nxgep) 1994 { 1995 nxge_status_t status = NXGE_OK; 1996 1997 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_setup_dev port %d", 1998 nxgep->mac.portnum)); 1999 2000 status = nxge_link_init(nxgep); 2001 2002 if (fm_check_acc_handle(nxgep->dev_regs->nxge_regh) != DDI_FM_OK) { 2003 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2004 "port%d Bad register acc handle", nxgep->mac.portnum)); 2005 status = NXGE_ERROR; 2006 } 2007 2008 if (status != NXGE_OK) { 2009 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2010 " nxge_setup_dev status " 2011 "(xcvr init 0x%08x)", status)); 2012 goto nxge_setup_dev_exit; 2013 } 2014 2015 nxge_setup_dev_exit: 2016 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 2017 "<== nxge_setup_dev port %d status = 0x%08x", 2018 nxgep->mac.portnum, status)); 2019 2020 return (status); 2021 } 2022 2023 static void 2024 nxge_destroy_dev(p_nxge_t nxgep) 2025 { 2026 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_dev")); 2027 2028 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 2029 2030 (void) nxge_hw_stop(nxgep); 2031 2032 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_dev")); 2033 } 2034 2035 static nxge_status_t 2036 nxge_setup_system_dma_pages(p_nxge_t nxgep) 2037 { 2038 int ddi_status = DDI_SUCCESS; 2039 uint_t count; 2040 ddi_dma_cookie_t cookie; 2041 uint_t iommu_pagesize; 2042 nxge_status_t status = NXGE_OK; 2043 2044 NXGE_ERROR_MSG((nxgep, DDI_CTL, "==> nxge_setup_system_dma_pages")); 2045 nxgep->sys_page_sz = ddi_ptob(nxgep->dip, (ulong_t)1); 2046 if (nxgep->niu_type != N2_NIU) { 2047 iommu_pagesize = dvma_pagesize(nxgep->dip); 2048 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 2049 " nxge_setup_system_dma_pages: page %d (ddi_ptob %d) " 2050 " default_block_size %d iommu_pagesize %d", 2051 nxgep->sys_page_sz, 2052 ddi_ptob(nxgep->dip, (ulong_t)1), 2053 nxgep->rx_default_block_size, 2054 iommu_pagesize)); 2055 2056 if (iommu_pagesize != 0) { 2057 if (nxgep->sys_page_sz == iommu_pagesize) { 2058 if (iommu_pagesize > 0x4000) 2059 nxgep->sys_page_sz = 0x4000; 2060 } else { 2061 if (nxgep->sys_page_sz > iommu_pagesize) 2062 nxgep->sys_page_sz = iommu_pagesize; 2063 } 2064 } 2065 } 2066 nxgep->sys_page_mask = ~(nxgep->sys_page_sz - 1); 2067 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 2068 "==> nxge_setup_system_dma_pages: page %d (ddi_ptob %d) " 2069 "default_block_size %d page mask %d", 2070 nxgep->sys_page_sz, 2071 ddi_ptob(nxgep->dip, (ulong_t)1), 2072 nxgep->rx_default_block_size, 2073 nxgep->sys_page_mask)); 2074 2075 2076 switch (nxgep->sys_page_sz) { 2077 default: 2078 nxgep->sys_page_sz = 0x1000; 2079 nxgep->sys_page_mask = ~(nxgep->sys_page_sz - 1); 2080 nxgep->rx_default_block_size = 0x1000; 2081 nxgep->rx_bksize_code = RBR_BKSIZE_4K; 2082 break; 2083 case 0x1000: 2084 nxgep->rx_default_block_size = 0x1000; 2085 nxgep->rx_bksize_code = RBR_BKSIZE_4K; 2086 break; 2087 case 0x2000: 2088 nxgep->rx_default_block_size = 0x2000; 2089 nxgep->rx_bksize_code = RBR_BKSIZE_8K; 2090 break; 2091 case 0x4000: 2092 nxgep->rx_default_block_size = 0x4000; 2093 nxgep->rx_bksize_code = RBR_BKSIZE_16K; 2094 break; 2095 case 0x8000: 2096 nxgep->rx_default_block_size = 0x8000; 2097 nxgep->rx_bksize_code = RBR_BKSIZE_32K; 2098 break; 2099 } 2100 2101 #ifndef USE_RX_BIG_BUF 2102 nxge_rx_dma_attr.dma_attr_align = nxgep->sys_page_sz; 2103 #else 2104 nxgep->rx_default_block_size = 0x2000; 2105 nxgep->rx_bksize_code = RBR_BKSIZE_8K; 2106 #endif 2107 /* 2108 * Get the system DMA burst size. 2109 */ 2110 ddi_status = ddi_dma_alloc_handle(nxgep->dip, &nxge_tx_dma_attr, 2111 DDI_DMA_DONTWAIT, 0, 2112 &nxgep->dmasparehandle); 2113 if (ddi_status != DDI_SUCCESS) { 2114 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2115 "ddi_dma_alloc_handle: failed " 2116 " status 0x%x", ddi_status)); 2117 goto nxge_get_soft_properties_exit; 2118 } 2119 2120 ddi_status = ddi_dma_addr_bind_handle(nxgep->dmasparehandle, NULL, 2121 (caddr_t)nxgep->dmasparehandle, 2122 sizeof (nxgep->dmasparehandle), 2123 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 2124 DDI_DMA_DONTWAIT, 0, 2125 &cookie, &count); 2126 if (ddi_status != DDI_DMA_MAPPED) { 2127 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2128 "Binding spare handle to find system" 2129 " burstsize failed.")); 2130 ddi_status = DDI_FAILURE; 2131 goto nxge_get_soft_properties_fail1; 2132 } 2133 2134 nxgep->sys_burst_sz = ddi_dma_burstsizes(nxgep->dmasparehandle); 2135 (void) ddi_dma_unbind_handle(nxgep->dmasparehandle); 2136 2137 nxge_get_soft_properties_fail1: 2138 ddi_dma_free_handle(&nxgep->dmasparehandle); 2139 2140 nxge_get_soft_properties_exit: 2141 2142 if (ddi_status != DDI_SUCCESS) 2143 status |= (NXGE_ERROR | NXGE_DDI_FAILED); 2144 2145 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 2146 "<== nxge_setup_system_dma_pages status = 0x%08x", status)); 2147 return (status); 2148 } 2149 2150 static nxge_status_t 2151 nxge_alloc_mem_pool(p_nxge_t nxgep) 2152 { 2153 nxge_status_t status = NXGE_OK; 2154 2155 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_alloc_mem_pool")); 2156 2157 status = nxge_alloc_rx_mem_pool(nxgep); 2158 if (status != NXGE_OK) { 2159 return (NXGE_ERROR); 2160 } 2161 2162 status = nxge_alloc_tx_mem_pool(nxgep); 2163 if (status != NXGE_OK) { 2164 nxge_free_rx_mem_pool(nxgep); 2165 return (NXGE_ERROR); 2166 } 2167 2168 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_alloc_mem_pool")); 2169 return (NXGE_OK); 2170 } 2171 2172 static void 2173 nxge_free_mem_pool(p_nxge_t nxgep) 2174 { 2175 NXGE_DEBUG_MSG((nxgep, MEM_CTL, "==> nxge_free_mem_pool")); 2176 2177 nxge_free_rx_mem_pool(nxgep); 2178 nxge_free_tx_mem_pool(nxgep); 2179 2180 NXGE_DEBUG_MSG((nxgep, MEM_CTL, "<== nxge_free_mem_pool")); 2181 } 2182 2183 nxge_status_t 2184 nxge_alloc_rx_mem_pool(p_nxge_t nxgep) 2185 { 2186 uint32_t rdc_max; 2187 p_nxge_dma_pt_cfg_t p_all_cfgp; 2188 p_nxge_hw_pt_cfg_t p_cfgp; 2189 p_nxge_dma_pool_t dma_poolp; 2190 p_nxge_dma_common_t *dma_buf_p; 2191 p_nxge_dma_pool_t dma_cntl_poolp; 2192 p_nxge_dma_common_t *dma_cntl_p; 2193 uint32_t *num_chunks; /* per dma */ 2194 nxge_status_t status = NXGE_OK; 2195 2196 uint32_t nxge_port_rbr_size; 2197 uint32_t nxge_port_rbr_spare_size; 2198 uint32_t nxge_port_rcr_size; 2199 uint32_t rx_cntl_alloc_size; 2200 2201 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rx_mem_pool")); 2202 2203 p_all_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2204 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_all_cfgp->hw_config; 2205 rdc_max = NXGE_MAX_RDCS; 2206 2207 /* 2208 * Allocate memory for the common DMA data structures. 2209 */ 2210 dma_poolp = (p_nxge_dma_pool_t)KMEM_ZALLOC(sizeof (nxge_dma_pool_t), 2211 KM_SLEEP); 2212 dma_buf_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 2213 sizeof (p_nxge_dma_common_t) * rdc_max, KM_SLEEP); 2214 2215 dma_cntl_poolp = (p_nxge_dma_pool_t) 2216 KMEM_ZALLOC(sizeof (nxge_dma_pool_t), KM_SLEEP); 2217 dma_cntl_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 2218 sizeof (p_nxge_dma_common_t) * rdc_max, KM_SLEEP); 2219 2220 num_chunks = (uint32_t *)KMEM_ZALLOC( 2221 sizeof (uint32_t) * rdc_max, KM_SLEEP); 2222 2223 /* 2224 * Assume that each DMA channel will be configured with 2225 * the default block size. 2226 * rbr block counts are modulo the batch count (16). 2227 */ 2228 nxge_port_rbr_size = p_all_cfgp->rbr_size; 2229 nxge_port_rcr_size = p_all_cfgp->rcr_size; 2230 2231 if (!nxge_port_rbr_size) { 2232 nxge_port_rbr_size = NXGE_RBR_RBB_DEFAULT; 2233 } 2234 if (nxge_port_rbr_size % NXGE_RXDMA_POST_BATCH) { 2235 nxge_port_rbr_size = (NXGE_RXDMA_POST_BATCH * 2236 (nxge_port_rbr_size / NXGE_RXDMA_POST_BATCH + 1)); 2237 } 2238 2239 p_all_cfgp->rbr_size = nxge_port_rbr_size; 2240 nxge_port_rbr_spare_size = nxge_rbr_spare_size; 2241 2242 if (nxge_port_rbr_spare_size % NXGE_RXDMA_POST_BATCH) { 2243 nxge_port_rbr_spare_size = (NXGE_RXDMA_POST_BATCH * 2244 (nxge_port_rbr_spare_size / NXGE_RXDMA_POST_BATCH + 1)); 2245 } 2246 if (nxge_port_rbr_size > RBR_DEFAULT_MAX_BLKS) { 2247 NXGE_DEBUG_MSG((nxgep, MEM_CTL, 2248 "nxge_alloc_rx_mem_pool: RBR size too high %d, " 2249 "set to default %d", 2250 nxge_port_rbr_size, RBR_DEFAULT_MAX_BLKS)); 2251 nxge_port_rbr_size = RBR_DEFAULT_MAX_BLKS; 2252 } 2253 if (nxge_port_rcr_size > RCR_DEFAULT_MAX) { 2254 NXGE_DEBUG_MSG((nxgep, MEM_CTL, 2255 "nxge_alloc_rx_mem_pool: RCR too high %d, " 2256 "set to default %d", 2257 nxge_port_rcr_size, RCR_DEFAULT_MAX)); 2258 nxge_port_rcr_size = RCR_DEFAULT_MAX; 2259 } 2260 2261 /* 2262 * N2/NIU has limitation on the descriptor sizes (contiguous 2263 * memory allocation on data buffers to 4M (contig_mem_alloc) 2264 * and little endian for control buffers (must use the ddi/dki mem alloc 2265 * function). 2266 */ 2267 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2268 if (nxgep->niu_type == N2_NIU) { 2269 nxge_port_rbr_spare_size = 0; 2270 if ((nxge_port_rbr_size > NXGE_NIU_CONTIG_RBR_MAX) || 2271 (!ISP2(nxge_port_rbr_size))) { 2272 nxge_port_rbr_size = NXGE_NIU_CONTIG_RBR_MAX; 2273 } 2274 if ((nxge_port_rcr_size > NXGE_NIU_CONTIG_RCR_MAX) || 2275 (!ISP2(nxge_port_rcr_size))) { 2276 nxge_port_rcr_size = NXGE_NIU_CONTIG_RCR_MAX; 2277 } 2278 } 2279 #endif 2280 2281 /* 2282 * Addresses of receive block ring, receive completion ring and the 2283 * mailbox must be all cache-aligned (64 bytes). 2284 */ 2285 rx_cntl_alloc_size = nxge_port_rbr_size + nxge_port_rbr_spare_size; 2286 rx_cntl_alloc_size *= (sizeof (rx_desc_t)); 2287 rx_cntl_alloc_size += (sizeof (rcr_entry_t) * nxge_port_rcr_size); 2288 rx_cntl_alloc_size += sizeof (rxdma_mailbox_t); 2289 2290 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_alloc_rx_mem_pool: " 2291 "nxge_port_rbr_size = %d nxge_port_rbr_spare_size = %d " 2292 "nxge_port_rcr_size = %d " 2293 "rx_cntl_alloc_size = %d", 2294 nxge_port_rbr_size, nxge_port_rbr_spare_size, 2295 nxge_port_rcr_size, 2296 rx_cntl_alloc_size)); 2297 2298 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2299 if (nxgep->niu_type == N2_NIU) { 2300 uint32_t rx_buf_alloc_size = (nxgep->rx_default_block_size * 2301 (nxge_port_rbr_size + nxge_port_rbr_spare_size)); 2302 2303 if (!ISP2(rx_buf_alloc_size)) { 2304 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2305 "==> nxge_alloc_rx_mem_pool: " 2306 " must be power of 2")); 2307 status |= (NXGE_ERROR | NXGE_DDI_FAILED); 2308 goto nxge_alloc_rx_mem_pool_exit; 2309 } 2310 2311 if (rx_buf_alloc_size > (1 << 22)) { 2312 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2313 "==> nxge_alloc_rx_mem_pool: " 2314 " limit size to 4M")); 2315 status |= (NXGE_ERROR | NXGE_DDI_FAILED); 2316 goto nxge_alloc_rx_mem_pool_exit; 2317 } 2318 2319 if (rx_cntl_alloc_size < 0x2000) { 2320 rx_cntl_alloc_size = 0x2000; 2321 } 2322 } 2323 #endif 2324 nxgep->nxge_port_rbr_size = nxge_port_rbr_size; 2325 nxgep->nxge_port_rcr_size = nxge_port_rcr_size; 2326 nxgep->nxge_port_rbr_spare_size = nxge_port_rbr_spare_size; 2327 nxgep->nxge_port_rx_cntl_alloc_size = rx_cntl_alloc_size; 2328 2329 dma_poolp->ndmas = p_cfgp->max_rdcs; 2330 dma_poolp->num_chunks = num_chunks; 2331 dma_poolp->buf_allocated = B_TRUE; 2332 nxgep->rx_buf_pool_p = dma_poolp; 2333 dma_poolp->dma_buf_pool_p = dma_buf_p; 2334 2335 dma_cntl_poolp->ndmas = p_cfgp->max_rdcs; 2336 dma_cntl_poolp->buf_allocated = B_TRUE; 2337 nxgep->rx_cntl_pool_p = dma_cntl_poolp; 2338 dma_cntl_poolp->dma_buf_pool_p = dma_cntl_p; 2339 2340 /* Allocate the receive rings, too. */ 2341 nxgep->rx_rbr_rings = 2342 KMEM_ZALLOC(sizeof (rx_rbr_rings_t), KM_SLEEP); 2343 nxgep->rx_rbr_rings->rbr_rings = 2344 KMEM_ZALLOC(sizeof (p_rx_rbr_ring_t) * rdc_max, KM_SLEEP); 2345 nxgep->rx_rcr_rings = 2346 KMEM_ZALLOC(sizeof (rx_rcr_rings_t), KM_SLEEP); 2347 nxgep->rx_rcr_rings->rcr_rings = 2348 KMEM_ZALLOC(sizeof (p_rx_rcr_ring_t) * rdc_max, KM_SLEEP); 2349 nxgep->rx_mbox_areas_p = 2350 KMEM_ZALLOC(sizeof (rx_mbox_areas_t), KM_SLEEP); 2351 nxgep->rx_mbox_areas_p->rxmbox_areas = 2352 KMEM_ZALLOC(sizeof (p_rx_mbox_t) * rdc_max, KM_SLEEP); 2353 2354 nxgep->rx_rbr_rings->ndmas = nxgep->rx_rcr_rings->ndmas = 2355 p_cfgp->max_rdcs; 2356 2357 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 2358 "<== nxge_alloc_rx_mem_pool:status 0x%08x", status)); 2359 2360 nxge_alloc_rx_mem_pool_exit: 2361 return (status); 2362 } 2363 2364 /* 2365 * nxge_alloc_rxb 2366 * 2367 * Allocate buffers for an RDC. 2368 * 2369 * Arguments: 2370 * nxgep 2371 * channel The channel to map into our kernel space. 2372 * 2373 * Notes: 2374 * 2375 * NPI function calls: 2376 * 2377 * NXGE function calls: 2378 * 2379 * Registers accessed: 2380 * 2381 * Context: 2382 * 2383 * Taking apart: 2384 * 2385 * Open questions: 2386 * 2387 */ 2388 nxge_status_t 2389 nxge_alloc_rxb( 2390 p_nxge_t nxgep, 2391 int channel) 2392 { 2393 size_t rx_buf_alloc_size; 2394 nxge_status_t status = NXGE_OK; 2395 2396 nxge_dma_common_t **data; 2397 nxge_dma_common_t **control; 2398 uint32_t *num_chunks; 2399 2400 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rbb")); 2401 2402 /* 2403 * Allocate memory for the receive buffers and descriptor rings. 2404 * Replace these allocation functions with the interface functions 2405 * provided by the partition manager if/when they are available. 2406 */ 2407 2408 /* 2409 * Allocate memory for the receive buffer blocks. 2410 */ 2411 rx_buf_alloc_size = (nxgep->rx_default_block_size * 2412 (nxgep->nxge_port_rbr_size + nxgep->nxge_port_rbr_spare_size)); 2413 2414 data = &nxgep->rx_buf_pool_p->dma_buf_pool_p[channel]; 2415 num_chunks = &nxgep->rx_buf_pool_p->num_chunks[channel]; 2416 2417 if ((status = nxge_alloc_rx_buf_dma( 2418 nxgep, channel, data, rx_buf_alloc_size, 2419 nxgep->rx_default_block_size, num_chunks)) != NXGE_OK) { 2420 return (status); 2421 } 2422 2423 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_alloc_rxb(): " 2424 "dma %d dma_buf_p %llx &dma_buf_p %llx", channel, *data, data)); 2425 2426 /* 2427 * Allocate memory for descriptor rings and mailbox. 2428 */ 2429 control = &nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel]; 2430 2431 if ((status = nxge_alloc_rx_cntl_dma( 2432 nxgep, channel, control, nxgep->nxge_port_rx_cntl_alloc_size)) 2433 != NXGE_OK) { 2434 nxge_free_rx_cntl_dma(nxgep, *control); 2435 (*data)->buf_alloc_state |= BUF_ALLOCATED_WAIT_FREE; 2436 nxge_free_rx_buf_dma(nxgep, *data, *num_chunks); 2437 return (status); 2438 } 2439 2440 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 2441 "<== nxge_alloc_rx_mem_pool:status 0x%08x", status)); 2442 2443 return (status); 2444 } 2445 2446 void 2447 nxge_free_rxb( 2448 p_nxge_t nxgep, 2449 int channel) 2450 { 2451 nxge_dma_common_t *data; 2452 nxge_dma_common_t *control; 2453 uint32_t num_chunks; 2454 2455 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rbb")); 2456 2457 data = nxgep->rx_buf_pool_p->dma_buf_pool_p[channel]; 2458 num_chunks = nxgep->rx_buf_pool_p->num_chunks[channel]; 2459 nxge_free_rx_buf_dma(nxgep, data, num_chunks); 2460 2461 nxgep->rx_buf_pool_p->dma_buf_pool_p[channel] = 0; 2462 nxgep->rx_buf_pool_p->num_chunks[channel] = 0; 2463 2464 control = nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel]; 2465 nxge_free_rx_cntl_dma(nxgep, control); 2466 2467 nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel] = 0; 2468 2469 KMEM_FREE(data, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 2470 KMEM_FREE(control, sizeof (nxge_dma_common_t)); 2471 2472 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_alloc_rbb")); 2473 } 2474 2475 static void 2476 nxge_free_rx_mem_pool(p_nxge_t nxgep) 2477 { 2478 int rdc_max = NXGE_MAX_RDCS; 2479 2480 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_free_rx_mem_pool")); 2481 2482 if (!nxgep->rx_buf_pool_p || !nxgep->rx_buf_pool_p->buf_allocated) { 2483 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2484 "<== nxge_free_rx_mem_pool " 2485 "(null rx buf pool or buf not allocated")); 2486 return; 2487 } 2488 if (!nxgep->rx_cntl_pool_p || !nxgep->rx_cntl_pool_p->buf_allocated) { 2489 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2490 "<== nxge_free_rx_mem_pool " 2491 "(null rx cntl buf pool or cntl buf not allocated")); 2492 return; 2493 } 2494 2495 KMEM_FREE(nxgep->rx_cntl_pool_p->dma_buf_pool_p, 2496 sizeof (p_nxge_dma_common_t) * rdc_max); 2497 KMEM_FREE(nxgep->rx_cntl_pool_p, sizeof (nxge_dma_pool_t)); 2498 2499 KMEM_FREE(nxgep->rx_buf_pool_p->num_chunks, 2500 sizeof (uint32_t) * rdc_max); 2501 KMEM_FREE(nxgep->rx_buf_pool_p->dma_buf_pool_p, 2502 sizeof (p_nxge_dma_common_t) * rdc_max); 2503 KMEM_FREE(nxgep->rx_buf_pool_p, sizeof (nxge_dma_pool_t)); 2504 2505 nxgep->rx_buf_pool_p = 0; 2506 nxgep->rx_cntl_pool_p = 0; 2507 2508 KMEM_FREE(nxgep->rx_rbr_rings->rbr_rings, 2509 sizeof (p_rx_rbr_ring_t) * rdc_max); 2510 KMEM_FREE(nxgep->rx_rbr_rings, sizeof (rx_rbr_rings_t)); 2511 KMEM_FREE(nxgep->rx_rcr_rings->rcr_rings, 2512 sizeof (p_rx_rcr_ring_t) * rdc_max); 2513 KMEM_FREE(nxgep->rx_rcr_rings, sizeof (rx_rcr_rings_t)); 2514 KMEM_FREE(nxgep->rx_mbox_areas_p->rxmbox_areas, 2515 sizeof (p_rx_mbox_t) * rdc_max); 2516 KMEM_FREE(nxgep->rx_mbox_areas_p, sizeof (rx_mbox_areas_t)); 2517 2518 nxgep->rx_rbr_rings = 0; 2519 nxgep->rx_rcr_rings = 0; 2520 nxgep->rx_mbox_areas_p = 0; 2521 2522 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_free_rx_mem_pool")); 2523 } 2524 2525 2526 static nxge_status_t 2527 nxge_alloc_rx_buf_dma(p_nxge_t nxgep, uint16_t dma_channel, 2528 p_nxge_dma_common_t *dmap, 2529 size_t alloc_size, size_t block_size, uint32_t *num_chunks) 2530 { 2531 p_nxge_dma_common_t rx_dmap; 2532 nxge_status_t status = NXGE_OK; 2533 size_t total_alloc_size; 2534 size_t allocated = 0; 2535 int i, size_index, array_size; 2536 boolean_t use_kmem_alloc = B_FALSE; 2537 2538 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rx_buf_dma")); 2539 2540 rx_dmap = (p_nxge_dma_common_t) 2541 KMEM_ZALLOC(sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK, 2542 KM_SLEEP); 2543 2544 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2545 " alloc_rx_buf_dma rdc %d asize %x bsize %x bbuf %llx ", 2546 dma_channel, alloc_size, block_size, dmap)); 2547 2548 total_alloc_size = alloc_size; 2549 2550 #if defined(RX_USE_RECLAIM_POST) 2551 total_alloc_size = alloc_size + alloc_size/4; 2552 #endif 2553 2554 i = 0; 2555 size_index = 0; 2556 array_size = sizeof (alloc_sizes)/sizeof (size_t); 2557 while ((size_index < array_size) && 2558 (alloc_sizes[size_index] < alloc_size)) 2559 size_index++; 2560 if (size_index >= array_size) { 2561 size_index = array_size - 1; 2562 } 2563 2564 /* For Neptune, use kmem_alloc if the kmem flag is set. */ 2565 if (nxgep->niu_type != N2_NIU && nxge_use_kmem_alloc) { 2566 use_kmem_alloc = B_TRUE; 2567 #if defined(__i386) || defined(__amd64) 2568 size_index = 0; 2569 #endif 2570 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2571 "==> nxge_alloc_rx_buf_dma: " 2572 "Neptune use kmem_alloc() - size_index %d", 2573 size_index)); 2574 } 2575 2576 while ((allocated < total_alloc_size) && 2577 (size_index >= 0) && (i < NXGE_DMA_BLOCK)) { 2578 rx_dmap[i].dma_chunk_index = i; 2579 rx_dmap[i].block_size = block_size; 2580 rx_dmap[i].alength = alloc_sizes[size_index]; 2581 rx_dmap[i].orig_alength = rx_dmap[i].alength; 2582 rx_dmap[i].nblocks = alloc_sizes[size_index] / block_size; 2583 rx_dmap[i].dma_channel = dma_channel; 2584 rx_dmap[i].contig_alloc_type = B_FALSE; 2585 rx_dmap[i].kmem_alloc_type = B_FALSE; 2586 rx_dmap[i].buf_alloc_type = DDI_MEM_ALLOC; 2587 2588 /* 2589 * N2/NIU: data buffers must be contiguous as the driver 2590 * needs to call Hypervisor api to set up 2591 * logical pages. 2592 */ 2593 if ((nxgep->niu_type == N2_NIU) && (NXGE_DMA_BLOCK == 1)) { 2594 rx_dmap[i].contig_alloc_type = B_TRUE; 2595 rx_dmap[i].buf_alloc_type = CONTIG_MEM_ALLOC; 2596 } else if (use_kmem_alloc) { 2597 /* For Neptune, use kmem_alloc */ 2598 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2599 "==> nxge_alloc_rx_buf_dma: " 2600 "Neptune use kmem_alloc()")); 2601 rx_dmap[i].kmem_alloc_type = B_TRUE; 2602 rx_dmap[i].buf_alloc_type = KMEM_ALLOC; 2603 } 2604 2605 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2606 "alloc_rx_buf_dma rdc %d chunk %d bufp %llx size %x " 2607 "i %d nblocks %d alength %d", 2608 dma_channel, i, &rx_dmap[i], block_size, 2609 i, rx_dmap[i].nblocks, 2610 rx_dmap[i].alength)); 2611 status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 2612 &nxge_rx_dma_attr, 2613 rx_dmap[i].alength, 2614 &nxge_dev_buf_dma_acc_attr, 2615 DDI_DMA_READ | DDI_DMA_STREAMING, 2616 (p_nxge_dma_common_t)(&rx_dmap[i])); 2617 if (status != NXGE_OK) { 2618 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2619 "nxge_alloc_rx_buf_dma: Alloc Failed: " 2620 "dma %d size_index %d size requested %d", 2621 dma_channel, 2622 size_index, 2623 rx_dmap[i].alength)); 2624 size_index--; 2625 } else { 2626 rx_dmap[i].buf_alloc_state = BUF_ALLOCATED; 2627 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2628 " nxge_alloc_rx_buf_dma DONE alloc mem: " 2629 "dma %d dma_buf_p $%p kaddrp $%p alength %d " 2630 "buf_alloc_state %d alloc_type %d", 2631 dma_channel, 2632 &rx_dmap[i], 2633 rx_dmap[i].kaddrp, 2634 rx_dmap[i].alength, 2635 rx_dmap[i].buf_alloc_state, 2636 rx_dmap[i].buf_alloc_type)); 2637 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2638 " alloc_rx_buf_dma allocated rdc %d " 2639 "chunk %d size %x dvma %x bufp %llx kaddrp $%p", 2640 dma_channel, i, rx_dmap[i].alength, 2641 rx_dmap[i].ioaddr_pp, &rx_dmap[i], 2642 rx_dmap[i].kaddrp)); 2643 i++; 2644 allocated += alloc_sizes[size_index]; 2645 } 2646 } 2647 2648 if (allocated < total_alloc_size) { 2649 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2650 "==> nxge_alloc_rx_buf_dma: not enough for channel %d " 2651 "allocated 0x%x requested 0x%x", 2652 dma_channel, 2653 allocated, total_alloc_size)); 2654 status = NXGE_ERROR; 2655 goto nxge_alloc_rx_mem_fail1; 2656 } 2657 2658 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2659 "==> nxge_alloc_rx_buf_dma: Allocated for channel %d " 2660 "allocated 0x%x requested 0x%x", 2661 dma_channel, 2662 allocated, total_alloc_size)); 2663 2664 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 2665 " alloc_rx_buf_dma rdc %d allocated %d chunks", 2666 dma_channel, i)); 2667 *num_chunks = i; 2668 *dmap = rx_dmap; 2669 2670 goto nxge_alloc_rx_mem_exit; 2671 2672 nxge_alloc_rx_mem_fail1: 2673 KMEM_FREE(rx_dmap, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 2674 2675 nxge_alloc_rx_mem_exit: 2676 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 2677 "<== nxge_alloc_rx_buf_dma status 0x%08x", status)); 2678 2679 return (status); 2680 } 2681 2682 /*ARGSUSED*/ 2683 static void 2684 nxge_free_rx_buf_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap, 2685 uint32_t num_chunks) 2686 { 2687 int i; 2688 2689 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2690 "==> nxge_free_rx_buf_dma: # of chunks %d", num_chunks)); 2691 2692 if (dmap == 0) 2693 return; 2694 2695 for (i = 0; i < num_chunks; i++) { 2696 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2697 "==> nxge_free_rx_buf_dma: chunk %d dmap 0x%llx", 2698 i, dmap)); 2699 nxge_dma_free_rx_data_buf(dmap++); 2700 } 2701 2702 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_free_rx_buf_dma")); 2703 } 2704 2705 /*ARGSUSED*/ 2706 static nxge_status_t 2707 nxge_alloc_rx_cntl_dma(p_nxge_t nxgep, uint16_t dma_channel, 2708 p_nxge_dma_common_t *dmap, size_t size) 2709 { 2710 p_nxge_dma_common_t rx_dmap; 2711 nxge_status_t status = NXGE_OK; 2712 2713 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rx_cntl_dma")); 2714 2715 rx_dmap = (p_nxge_dma_common_t) 2716 KMEM_ZALLOC(sizeof (nxge_dma_common_t), KM_SLEEP); 2717 2718 rx_dmap->contig_alloc_type = B_FALSE; 2719 rx_dmap->kmem_alloc_type = B_FALSE; 2720 2721 status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 2722 &nxge_desc_dma_attr, 2723 size, 2724 &nxge_dev_desc_dma_acc_attr, 2725 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 2726 rx_dmap); 2727 if (status != NXGE_OK) { 2728 goto nxge_alloc_rx_cntl_dma_fail1; 2729 } 2730 2731 *dmap = rx_dmap; 2732 goto nxge_alloc_rx_cntl_dma_exit; 2733 2734 nxge_alloc_rx_cntl_dma_fail1: 2735 KMEM_FREE(rx_dmap, sizeof (nxge_dma_common_t)); 2736 2737 nxge_alloc_rx_cntl_dma_exit: 2738 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 2739 "<== nxge_alloc_rx_cntl_dma status 0x%08x", status)); 2740 2741 return (status); 2742 } 2743 2744 /*ARGSUSED*/ 2745 static void 2746 nxge_free_rx_cntl_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap) 2747 { 2748 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_free_rx_cntl_dma")); 2749 2750 if (dmap == 0) 2751 return; 2752 2753 nxge_dma_mem_free(dmap); 2754 2755 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_free_rx_cntl_dma")); 2756 } 2757 2758 typedef struct { 2759 size_t tx_size; 2760 size_t cr_size; 2761 size_t threshhold; 2762 } nxge_tdc_sizes_t; 2763 2764 static 2765 nxge_status_t 2766 nxge_tdc_sizes( 2767 nxge_t *nxgep, 2768 nxge_tdc_sizes_t *sizes) 2769 { 2770 uint32_t threshhold; /* The bcopy() threshhold */ 2771 size_t tx_size; /* Transmit buffer size */ 2772 size_t cr_size; /* Completion ring size */ 2773 2774 /* 2775 * Assume that each DMA channel will be configured with the 2776 * default transmit buffer size for copying transmit data. 2777 * (If a packet is bigger than this, it will not be copied.) 2778 */ 2779 if (nxgep->niu_type == N2_NIU) { 2780 threshhold = TX_BCOPY_SIZE; 2781 } else { 2782 threshhold = nxge_bcopy_thresh; 2783 } 2784 tx_size = nxge_tx_ring_size * threshhold; 2785 2786 cr_size = nxge_tx_ring_size * sizeof (tx_desc_t); 2787 cr_size += sizeof (txdma_mailbox_t); 2788 2789 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2790 if (nxgep->niu_type == N2_NIU) { 2791 if (!ISP2(tx_size)) { 2792 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2793 "==> nxge_tdc_sizes: Tx size" 2794 " must be power of 2")); 2795 return (NXGE_ERROR); 2796 } 2797 2798 if (tx_size > (1 << 22)) { 2799 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2800 "==> nxge_tdc_sizes: Tx size" 2801 " limited to 4M")); 2802 return (NXGE_ERROR); 2803 } 2804 2805 if (cr_size < 0x2000) 2806 cr_size = 0x2000; 2807 } 2808 #endif 2809 2810 sizes->threshhold = threshhold; 2811 sizes->tx_size = tx_size; 2812 sizes->cr_size = cr_size; 2813 2814 return (NXGE_OK); 2815 } 2816 /* 2817 * nxge_alloc_txb 2818 * 2819 * Allocate buffers for an TDC. 2820 * 2821 * Arguments: 2822 * nxgep 2823 * channel The channel to map into our kernel space. 2824 * 2825 * Notes: 2826 * 2827 * NPI function calls: 2828 * 2829 * NXGE function calls: 2830 * 2831 * Registers accessed: 2832 * 2833 * Context: 2834 * 2835 * Taking apart: 2836 * 2837 * Open questions: 2838 * 2839 */ 2840 nxge_status_t 2841 nxge_alloc_txb( 2842 p_nxge_t nxgep, 2843 int channel) 2844 { 2845 nxge_dma_common_t **dma_buf_p; 2846 nxge_dma_common_t **dma_cntl_p; 2847 uint32_t *num_chunks; 2848 nxge_status_t status = NXGE_OK; 2849 2850 nxge_tdc_sizes_t sizes; 2851 2852 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_tbb")); 2853 2854 if (nxge_tdc_sizes(nxgep, &sizes) != NXGE_OK) 2855 return (NXGE_ERROR); 2856 2857 /* 2858 * Allocate memory for transmit buffers and descriptor rings. 2859 * Replace these allocation functions with the interface functions 2860 * provided by the partition manager Real Soon Now. 2861 */ 2862 dma_buf_p = &nxgep->tx_buf_pool_p->dma_buf_pool_p[channel]; 2863 num_chunks = &nxgep->tx_buf_pool_p->num_chunks[channel]; 2864 2865 dma_cntl_p = &nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel]; 2866 2867 /* 2868 * Allocate memory for transmit buffers and descriptor rings. 2869 * Replace allocation functions with interface functions provided 2870 * by the partition manager when it is available. 2871 * 2872 * Allocate memory for the transmit buffer pool. 2873 */ 2874 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 2875 "sizes: tx: %ld, cr:%ld, th:%ld", 2876 sizes.tx_size, sizes.cr_size, sizes.threshhold)); 2877 2878 *num_chunks = 0; 2879 status = nxge_alloc_tx_buf_dma(nxgep, channel, dma_buf_p, 2880 sizes.tx_size, sizes.threshhold, num_chunks); 2881 if (status != NXGE_OK) { 2882 cmn_err(CE_NOTE, "nxge_alloc_tx_buf_dma failed!"); 2883 return (status); 2884 } 2885 2886 /* 2887 * Allocate memory for descriptor rings and mailbox. 2888 */ 2889 status = nxge_alloc_tx_cntl_dma(nxgep, channel, dma_cntl_p, 2890 sizes.cr_size); 2891 if (status != NXGE_OK) { 2892 nxge_free_tx_buf_dma(nxgep, *dma_buf_p, *num_chunks); 2893 cmn_err(CE_NOTE, "nxge_alloc_tx_cntl_dma failed!"); 2894 return (status); 2895 } 2896 2897 return (NXGE_OK); 2898 } 2899 2900 void 2901 nxge_free_txb( 2902 p_nxge_t nxgep, 2903 int channel) 2904 { 2905 nxge_dma_common_t *data; 2906 nxge_dma_common_t *control; 2907 uint32_t num_chunks; 2908 2909 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_free_txb")); 2910 2911 data = nxgep->tx_buf_pool_p->dma_buf_pool_p[channel]; 2912 num_chunks = nxgep->tx_buf_pool_p->num_chunks[channel]; 2913 nxge_free_tx_buf_dma(nxgep, data, num_chunks); 2914 2915 nxgep->tx_buf_pool_p->dma_buf_pool_p[channel] = 0; 2916 nxgep->tx_buf_pool_p->num_chunks[channel] = 0; 2917 2918 control = nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel]; 2919 nxge_free_tx_cntl_dma(nxgep, control); 2920 2921 nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel] = 0; 2922 2923 KMEM_FREE(data, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 2924 KMEM_FREE(control, sizeof (nxge_dma_common_t)); 2925 2926 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_free_txb")); 2927 } 2928 2929 /* 2930 * nxge_alloc_tx_mem_pool 2931 * 2932 * This function allocates all of the per-port TDC control data structures. 2933 * The per-channel (TDC) data structures are allocated when needed. 2934 * 2935 * Arguments: 2936 * nxgep 2937 * 2938 * Notes: 2939 * 2940 * Context: 2941 * Any domain 2942 */ 2943 nxge_status_t 2944 nxge_alloc_tx_mem_pool(p_nxge_t nxgep) 2945 { 2946 nxge_hw_pt_cfg_t *p_cfgp; 2947 nxge_dma_pool_t *dma_poolp; 2948 nxge_dma_common_t **dma_buf_p; 2949 nxge_dma_pool_t *dma_cntl_poolp; 2950 nxge_dma_common_t **dma_cntl_p; 2951 uint32_t *num_chunks; /* per dma */ 2952 int tdc_max; 2953 2954 NXGE_DEBUG_MSG((nxgep, MEM_CTL, "==> nxge_alloc_tx_mem_pool")); 2955 2956 p_cfgp = &nxgep->pt_config.hw_config; 2957 tdc_max = NXGE_MAX_TDCS; 2958 2959 /* 2960 * Allocate memory for each transmit DMA channel. 2961 */ 2962 dma_poolp = (p_nxge_dma_pool_t)KMEM_ZALLOC(sizeof (nxge_dma_pool_t), 2963 KM_SLEEP); 2964 dma_buf_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 2965 sizeof (p_nxge_dma_common_t) * tdc_max, KM_SLEEP); 2966 2967 dma_cntl_poolp = (p_nxge_dma_pool_t) 2968 KMEM_ZALLOC(sizeof (nxge_dma_pool_t), KM_SLEEP); 2969 dma_cntl_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 2970 sizeof (p_nxge_dma_common_t) * tdc_max, KM_SLEEP); 2971 2972 if (nxge_tx_ring_size > TDC_DEFAULT_MAX) { 2973 NXGE_DEBUG_MSG((nxgep, MEM_CTL, 2974 "nxge_alloc_tx_mem_pool: TDC too high %d, " 2975 "set to default %d", 2976 nxge_tx_ring_size, TDC_DEFAULT_MAX)); 2977 nxge_tx_ring_size = TDC_DEFAULT_MAX; 2978 } 2979 2980 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2981 /* 2982 * N2/NIU has limitation on the descriptor sizes (contiguous 2983 * memory allocation on data buffers to 4M (contig_mem_alloc) 2984 * and little endian for control buffers (must use the ddi/dki mem alloc 2985 * function). The transmit ring is limited to 8K (includes the 2986 * mailbox). 2987 */ 2988 if (nxgep->niu_type == N2_NIU) { 2989 if ((nxge_tx_ring_size > NXGE_NIU_CONTIG_TX_MAX) || 2990 (!ISP2(nxge_tx_ring_size))) { 2991 nxge_tx_ring_size = NXGE_NIU_CONTIG_TX_MAX; 2992 } 2993 } 2994 #endif 2995 2996 nxgep->nxge_port_tx_ring_size = nxge_tx_ring_size; 2997 2998 num_chunks = (uint32_t *)KMEM_ZALLOC( 2999 sizeof (uint32_t) * tdc_max, KM_SLEEP); 3000 3001 dma_poolp->ndmas = p_cfgp->tdc.owned; 3002 dma_poolp->num_chunks = num_chunks; 3003 dma_poolp->dma_buf_pool_p = dma_buf_p; 3004 nxgep->tx_buf_pool_p = dma_poolp; 3005 3006 dma_poolp->buf_allocated = B_TRUE; 3007 3008 dma_cntl_poolp->ndmas = p_cfgp->tdc.owned; 3009 dma_cntl_poolp->dma_buf_pool_p = dma_cntl_p; 3010 nxgep->tx_cntl_pool_p = dma_cntl_poolp; 3011 3012 dma_cntl_poolp->buf_allocated = B_TRUE; 3013 3014 nxgep->tx_rings = 3015 KMEM_ZALLOC(sizeof (tx_rings_t), KM_SLEEP); 3016 nxgep->tx_rings->rings = 3017 KMEM_ZALLOC(sizeof (p_tx_ring_t) * tdc_max, KM_SLEEP); 3018 nxgep->tx_mbox_areas_p = 3019 KMEM_ZALLOC(sizeof (tx_mbox_areas_t), KM_SLEEP); 3020 nxgep->tx_mbox_areas_p->txmbox_areas_p = 3021 KMEM_ZALLOC(sizeof (p_tx_mbox_t) * tdc_max, KM_SLEEP); 3022 3023 nxgep->tx_rings->ndmas = p_cfgp->tdc.owned; 3024 3025 NXGE_DEBUG_MSG((nxgep, MEM_CTL, 3026 "==> nxge_alloc_tx_mem_pool: ndmas %d poolp->ndmas %d", 3027 tdc_max, dma_poolp->ndmas)); 3028 3029 return (NXGE_OK); 3030 } 3031 3032 nxge_status_t 3033 nxge_alloc_tx_buf_dma(p_nxge_t nxgep, uint16_t dma_channel, 3034 p_nxge_dma_common_t *dmap, size_t alloc_size, 3035 size_t block_size, uint32_t *num_chunks) 3036 { 3037 p_nxge_dma_common_t tx_dmap; 3038 nxge_status_t status = NXGE_OK; 3039 size_t total_alloc_size; 3040 size_t allocated = 0; 3041 int i, size_index, array_size; 3042 3043 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_tx_buf_dma")); 3044 3045 tx_dmap = (p_nxge_dma_common_t) 3046 KMEM_ZALLOC(sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK, 3047 KM_SLEEP); 3048 3049 total_alloc_size = alloc_size; 3050 i = 0; 3051 size_index = 0; 3052 array_size = sizeof (alloc_sizes) / sizeof (size_t); 3053 while ((size_index < array_size) && 3054 (alloc_sizes[size_index] < alloc_size)) 3055 size_index++; 3056 if (size_index >= array_size) { 3057 size_index = array_size - 1; 3058 } 3059 3060 while ((allocated < total_alloc_size) && 3061 (size_index >= 0) && (i < NXGE_DMA_BLOCK)) { 3062 3063 tx_dmap[i].dma_chunk_index = i; 3064 tx_dmap[i].block_size = block_size; 3065 tx_dmap[i].alength = alloc_sizes[size_index]; 3066 tx_dmap[i].orig_alength = tx_dmap[i].alength; 3067 tx_dmap[i].nblocks = alloc_sizes[size_index] / block_size; 3068 tx_dmap[i].dma_channel = dma_channel; 3069 tx_dmap[i].contig_alloc_type = B_FALSE; 3070 tx_dmap[i].kmem_alloc_type = B_FALSE; 3071 3072 /* 3073 * N2/NIU: data buffers must be contiguous as the driver 3074 * needs to call Hypervisor api to set up 3075 * logical pages. 3076 */ 3077 if ((nxgep->niu_type == N2_NIU) && (NXGE_DMA_BLOCK == 1)) { 3078 tx_dmap[i].contig_alloc_type = B_TRUE; 3079 } 3080 3081 status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 3082 &nxge_tx_dma_attr, 3083 tx_dmap[i].alength, 3084 &nxge_dev_buf_dma_acc_attr, 3085 DDI_DMA_WRITE | DDI_DMA_STREAMING, 3086 (p_nxge_dma_common_t)(&tx_dmap[i])); 3087 if (status != NXGE_OK) { 3088 size_index--; 3089 } else { 3090 i++; 3091 allocated += alloc_sizes[size_index]; 3092 } 3093 } 3094 3095 if (allocated < total_alloc_size) { 3096 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3097 "==> nxge_alloc_tx_buf_dma: not enough channel %d: " 3098 "allocated 0x%x requested 0x%x", 3099 dma_channel, 3100 allocated, total_alloc_size)); 3101 status = NXGE_ERROR; 3102 goto nxge_alloc_tx_mem_fail1; 3103 } 3104 3105 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3106 "==> nxge_alloc_tx_buf_dma: Allocated for channel %d: " 3107 "allocated 0x%x requested 0x%x", 3108 dma_channel, 3109 allocated, total_alloc_size)); 3110 3111 *num_chunks = i; 3112 *dmap = tx_dmap; 3113 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3114 "==> nxge_alloc_tx_buf_dma dmap 0x%016llx num chunks %d", 3115 *dmap, i)); 3116 goto nxge_alloc_tx_mem_exit; 3117 3118 nxge_alloc_tx_mem_fail1: 3119 KMEM_FREE(tx_dmap, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 3120 3121 nxge_alloc_tx_mem_exit: 3122 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3123 "<== nxge_alloc_tx_buf_dma status 0x%08x", status)); 3124 3125 return (status); 3126 } 3127 3128 /*ARGSUSED*/ 3129 static void 3130 nxge_free_tx_buf_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap, 3131 uint32_t num_chunks) 3132 { 3133 int i; 3134 3135 NXGE_DEBUG_MSG((nxgep, MEM_CTL, "==> nxge_free_tx_buf_dma")); 3136 3137 if (dmap == 0) 3138 return; 3139 3140 for (i = 0; i < num_chunks; i++) { 3141 nxge_dma_mem_free(dmap++); 3142 } 3143 3144 NXGE_DEBUG_MSG((nxgep, MEM_CTL, "<== nxge_free_tx_buf_dma")); 3145 } 3146 3147 /*ARGSUSED*/ 3148 nxge_status_t 3149 nxge_alloc_tx_cntl_dma(p_nxge_t nxgep, uint16_t dma_channel, 3150 p_nxge_dma_common_t *dmap, size_t size) 3151 { 3152 p_nxge_dma_common_t tx_dmap; 3153 nxge_status_t status = NXGE_OK; 3154 3155 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_tx_cntl_dma")); 3156 tx_dmap = (p_nxge_dma_common_t) 3157 KMEM_ZALLOC(sizeof (nxge_dma_common_t), KM_SLEEP); 3158 3159 tx_dmap->contig_alloc_type = B_FALSE; 3160 tx_dmap->kmem_alloc_type = B_FALSE; 3161 3162 status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 3163 &nxge_desc_dma_attr, 3164 size, 3165 &nxge_dev_desc_dma_acc_attr, 3166 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 3167 tx_dmap); 3168 if (status != NXGE_OK) { 3169 goto nxge_alloc_tx_cntl_dma_fail1; 3170 } 3171 3172 *dmap = tx_dmap; 3173 goto nxge_alloc_tx_cntl_dma_exit; 3174 3175 nxge_alloc_tx_cntl_dma_fail1: 3176 KMEM_FREE(tx_dmap, sizeof (nxge_dma_common_t)); 3177 3178 nxge_alloc_tx_cntl_dma_exit: 3179 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3180 "<== nxge_alloc_tx_cntl_dma status 0x%08x", status)); 3181 3182 return (status); 3183 } 3184 3185 /*ARGSUSED*/ 3186 static void 3187 nxge_free_tx_cntl_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap) 3188 { 3189 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_free_tx_cntl_dma")); 3190 3191 if (dmap == 0) 3192 return; 3193 3194 nxge_dma_mem_free(dmap); 3195 3196 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_free_tx_cntl_dma")); 3197 } 3198 3199 /* 3200 * nxge_free_tx_mem_pool 3201 * 3202 * This function frees all of the per-port TDC control data structures. 3203 * The per-channel (TDC) data structures are freed when the channel 3204 * is stopped. 3205 * 3206 * Arguments: 3207 * nxgep 3208 * 3209 * Notes: 3210 * 3211 * Context: 3212 * Any domain 3213 */ 3214 static void 3215 nxge_free_tx_mem_pool(p_nxge_t nxgep) 3216 { 3217 int tdc_max = NXGE_MAX_TDCS; 3218 3219 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_free_tx_mem_pool")); 3220 3221 if (!nxgep->tx_buf_pool_p || !nxgep->tx_buf_pool_p->buf_allocated) { 3222 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3223 "<== nxge_free_tx_mem_pool " 3224 "(null tx buf pool or buf not allocated")); 3225 return; 3226 } 3227 if (!nxgep->tx_cntl_pool_p || !nxgep->tx_cntl_pool_p->buf_allocated) { 3228 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3229 "<== nxge_free_tx_mem_pool " 3230 "(null tx cntl buf pool or cntl buf not allocated")); 3231 return; 3232 } 3233 3234 /* 1. Free the mailboxes. */ 3235 KMEM_FREE(nxgep->tx_mbox_areas_p->txmbox_areas_p, 3236 sizeof (p_tx_mbox_t) * tdc_max); 3237 KMEM_FREE(nxgep->tx_mbox_areas_p, sizeof (tx_mbox_areas_t)); 3238 3239 nxgep->tx_mbox_areas_p = 0; 3240 3241 /* 2. Free the transmit ring arrays. */ 3242 KMEM_FREE(nxgep->tx_rings->rings, 3243 sizeof (p_tx_ring_t) * tdc_max); 3244 KMEM_FREE(nxgep->tx_rings, sizeof (tx_rings_t)); 3245 3246 nxgep->tx_rings = 0; 3247 3248 /* 3. Free the completion ring data structures. */ 3249 KMEM_FREE(nxgep->tx_cntl_pool_p->dma_buf_pool_p, 3250 sizeof (p_nxge_dma_common_t) * tdc_max); 3251 KMEM_FREE(nxgep->tx_cntl_pool_p, sizeof (nxge_dma_pool_t)); 3252 3253 nxgep->tx_cntl_pool_p = 0; 3254 3255 /* 4. Free the data ring data structures. */ 3256 KMEM_FREE(nxgep->tx_buf_pool_p->num_chunks, 3257 sizeof (uint32_t) * tdc_max); 3258 KMEM_FREE(nxgep->tx_buf_pool_p->dma_buf_pool_p, 3259 sizeof (p_nxge_dma_common_t) * tdc_max); 3260 KMEM_FREE(nxgep->tx_buf_pool_p, sizeof (nxge_dma_pool_t)); 3261 3262 nxgep->tx_buf_pool_p = 0; 3263 3264 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_free_tx_mem_pool")); 3265 } 3266 3267 /*ARGSUSED*/ 3268 static nxge_status_t 3269 nxge_dma_mem_alloc(p_nxge_t nxgep, dma_method_t method, 3270 struct ddi_dma_attr *dma_attrp, 3271 size_t length, ddi_device_acc_attr_t *acc_attr_p, uint_t xfer_flags, 3272 p_nxge_dma_common_t dma_p) 3273 { 3274 caddr_t kaddrp; 3275 int ddi_status = DDI_SUCCESS; 3276 boolean_t contig_alloc_type; 3277 boolean_t kmem_alloc_type; 3278 3279 contig_alloc_type = dma_p->contig_alloc_type; 3280 3281 if (contig_alloc_type && (nxgep->niu_type != N2_NIU)) { 3282 /* 3283 * contig_alloc_type for contiguous memory only allowed 3284 * for N2/NIU. 3285 */ 3286 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3287 "nxge_dma_mem_alloc: alloc type not allowed (%d)", 3288 dma_p->contig_alloc_type)); 3289 return (NXGE_ERROR | NXGE_DDI_FAILED); 3290 } 3291 3292 dma_p->dma_handle = NULL; 3293 dma_p->acc_handle = NULL; 3294 dma_p->kaddrp = dma_p->last_kaddrp = NULL; 3295 dma_p->first_ioaddr_pp = dma_p->last_ioaddr_pp = NULL; 3296 ddi_status = ddi_dma_alloc_handle(nxgep->dip, dma_attrp, 3297 DDI_DMA_DONTWAIT, NULL, &dma_p->dma_handle); 3298 if (ddi_status != DDI_SUCCESS) { 3299 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3300 "nxge_dma_mem_alloc:ddi_dma_alloc_handle failed.")); 3301 return (NXGE_ERROR | NXGE_DDI_FAILED); 3302 } 3303 3304 kmem_alloc_type = dma_p->kmem_alloc_type; 3305 3306 switch (contig_alloc_type) { 3307 case B_FALSE: 3308 switch (kmem_alloc_type) { 3309 case B_FALSE: 3310 ddi_status = ddi_dma_mem_alloc(dma_p->dma_handle, 3311 length, 3312 acc_attr_p, 3313 xfer_flags, 3314 DDI_DMA_DONTWAIT, 0, &kaddrp, &dma_p->alength, 3315 &dma_p->acc_handle); 3316 if (ddi_status != DDI_SUCCESS) { 3317 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3318 "nxge_dma_mem_alloc: " 3319 "ddi_dma_mem_alloc failed")); 3320 ddi_dma_free_handle(&dma_p->dma_handle); 3321 dma_p->dma_handle = NULL; 3322 return (NXGE_ERROR | NXGE_DDI_FAILED); 3323 } 3324 if (dma_p->alength < length) { 3325 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3326 "nxge_dma_mem_alloc:di_dma_mem_alloc " 3327 "< length.")); 3328 ddi_dma_mem_free(&dma_p->acc_handle); 3329 ddi_dma_free_handle(&dma_p->dma_handle); 3330 dma_p->acc_handle = NULL; 3331 dma_p->dma_handle = NULL; 3332 return (NXGE_ERROR); 3333 } 3334 3335 ddi_status = ddi_dma_addr_bind_handle(dma_p->dma_handle, 3336 NULL, 3337 kaddrp, dma_p->alength, xfer_flags, 3338 DDI_DMA_DONTWAIT, 3339 0, &dma_p->dma_cookie, &dma_p->ncookies); 3340 if (ddi_status != DDI_DMA_MAPPED) { 3341 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3342 "nxge_dma_mem_alloc: ddi_dma_addr_bind " 3343 "failed " 3344 "(staus 0x%x ncookies %d.)", ddi_status, 3345 dma_p->ncookies)); 3346 if (dma_p->acc_handle) { 3347 ddi_dma_mem_free(&dma_p->acc_handle); 3348 dma_p->acc_handle = NULL; 3349 } 3350 ddi_dma_free_handle(&dma_p->dma_handle); 3351 dma_p->dma_handle = NULL; 3352 return (NXGE_ERROR | NXGE_DDI_FAILED); 3353 } 3354 3355 if (dma_p->ncookies != 1) { 3356 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3357 "nxge_dma_mem_alloc:ddi_dma_addr_bind " 3358 "> 1 cookie" 3359 "(staus 0x%x ncookies %d.)", ddi_status, 3360 dma_p->ncookies)); 3361 (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3362 if (dma_p->acc_handle) { 3363 ddi_dma_mem_free(&dma_p->acc_handle); 3364 dma_p->acc_handle = NULL; 3365 } 3366 ddi_dma_free_handle(&dma_p->dma_handle); 3367 dma_p->dma_handle = NULL; 3368 dma_p->acc_handle = NULL; 3369 return (NXGE_ERROR); 3370 } 3371 break; 3372 3373 case B_TRUE: 3374 kaddrp = KMEM_ALLOC(length, KM_NOSLEEP); 3375 if (kaddrp == NULL) { 3376 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3377 "nxge_dma_mem_alloc:ddi_dma_mem_alloc " 3378 "kmem alloc failed")); 3379 return (NXGE_ERROR); 3380 } 3381 3382 dma_p->alength = length; 3383 ddi_status = ddi_dma_addr_bind_handle(dma_p->dma_handle, 3384 NULL, kaddrp, dma_p->alength, xfer_flags, 3385 DDI_DMA_DONTWAIT, 0, 3386 &dma_p->dma_cookie, &dma_p->ncookies); 3387 if (ddi_status != DDI_DMA_MAPPED) { 3388 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3389 "nxge_dma_mem_alloc:ddi_dma_addr_bind: " 3390 "(kmem_alloc) failed kaddrp $%p length %d " 3391 "(staus 0x%x (%d) ncookies %d.)", 3392 kaddrp, length, 3393 ddi_status, ddi_status, dma_p->ncookies)); 3394 KMEM_FREE(kaddrp, length); 3395 dma_p->acc_handle = NULL; 3396 ddi_dma_free_handle(&dma_p->dma_handle); 3397 dma_p->dma_handle = NULL; 3398 dma_p->kaddrp = NULL; 3399 return (NXGE_ERROR | NXGE_DDI_FAILED); 3400 } 3401 3402 if (dma_p->ncookies != 1) { 3403 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3404 "nxge_dma_mem_alloc:ddi_dma_addr_bind " 3405 "(kmem_alloc) > 1 cookie" 3406 "(staus 0x%x ncookies %d.)", ddi_status, 3407 dma_p->ncookies)); 3408 (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3409 KMEM_FREE(kaddrp, length); 3410 ddi_dma_free_handle(&dma_p->dma_handle); 3411 dma_p->dma_handle = NULL; 3412 dma_p->acc_handle = NULL; 3413 dma_p->kaddrp = NULL; 3414 return (NXGE_ERROR); 3415 } 3416 3417 dma_p->kaddrp = kaddrp; 3418 3419 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 3420 "nxge_dma_mem_alloc: kmem_alloc dmap $%p " 3421 "kaddr $%p alength %d", 3422 dma_p, 3423 kaddrp, 3424 dma_p->alength)); 3425 break; 3426 } 3427 break; 3428 3429 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 3430 case B_TRUE: 3431 kaddrp = (caddr_t)contig_mem_alloc(length); 3432 if (kaddrp == NULL) { 3433 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3434 "nxge_dma_mem_alloc:contig_mem_alloc failed.")); 3435 ddi_dma_free_handle(&dma_p->dma_handle); 3436 return (NXGE_ERROR | NXGE_DDI_FAILED); 3437 } 3438 3439 dma_p->alength = length; 3440 ddi_status = ddi_dma_addr_bind_handle(dma_p->dma_handle, NULL, 3441 kaddrp, dma_p->alength, xfer_flags, DDI_DMA_DONTWAIT, 0, 3442 &dma_p->dma_cookie, &dma_p->ncookies); 3443 if (ddi_status != DDI_DMA_MAPPED) { 3444 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3445 "nxge_dma_mem_alloc:di_dma_addr_bind failed " 3446 "(status 0x%x ncookies %d.)", ddi_status, 3447 dma_p->ncookies)); 3448 3449 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3450 "==> nxge_dma_mem_alloc: (not mapped)" 3451 "length %lu (0x%x) " 3452 "free contig kaddrp $%p " 3453 "va_to_pa $%p", 3454 length, length, 3455 kaddrp, 3456 va_to_pa(kaddrp))); 3457 3458 3459 contig_mem_free((void *)kaddrp, length); 3460 ddi_dma_free_handle(&dma_p->dma_handle); 3461 3462 dma_p->dma_handle = NULL; 3463 dma_p->acc_handle = NULL; 3464 dma_p->alength = NULL; 3465 dma_p->kaddrp = NULL; 3466 3467 return (NXGE_ERROR | NXGE_DDI_FAILED); 3468 } 3469 3470 if (dma_p->ncookies != 1 || 3471 (dma_p->dma_cookie.dmac_laddress == NULL)) { 3472 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3473 "nxge_dma_mem_alloc:di_dma_addr_bind > 1 " 3474 "cookie or " 3475 "dmac_laddress is NULL $%p size %d " 3476 " (status 0x%x ncookies %d.)", 3477 ddi_status, 3478 dma_p->dma_cookie.dmac_laddress, 3479 dma_p->dma_cookie.dmac_size, 3480 dma_p->ncookies)); 3481 3482 contig_mem_free((void *)kaddrp, length); 3483 (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3484 ddi_dma_free_handle(&dma_p->dma_handle); 3485 3486 dma_p->alength = 0; 3487 dma_p->dma_handle = NULL; 3488 dma_p->acc_handle = NULL; 3489 dma_p->kaddrp = NULL; 3490 3491 return (NXGE_ERROR | NXGE_DDI_FAILED); 3492 } 3493 break; 3494 3495 #else 3496 case B_TRUE: 3497 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3498 "nxge_dma_mem_alloc: invalid alloc type for !sun4v")); 3499 return (NXGE_ERROR | NXGE_DDI_FAILED); 3500 #endif 3501 } 3502 3503 dma_p->kaddrp = kaddrp; 3504 dma_p->last_kaddrp = (unsigned char *)kaddrp + 3505 dma_p->alength - RXBUF_64B_ALIGNED; 3506 #if defined(__i386) 3507 dma_p->ioaddr_pp = 3508 (unsigned char *)(uint32_t)dma_p->dma_cookie.dmac_laddress; 3509 #else 3510 dma_p->ioaddr_pp = (unsigned char *)dma_p->dma_cookie.dmac_laddress; 3511 #endif 3512 dma_p->last_ioaddr_pp = 3513 #if defined(__i386) 3514 (unsigned char *)(uint32_t)dma_p->dma_cookie.dmac_laddress + 3515 #else 3516 (unsigned char *)dma_p->dma_cookie.dmac_laddress + 3517 #endif 3518 dma_p->alength - RXBUF_64B_ALIGNED; 3519 3520 NPI_DMA_ACC_HANDLE_SET(dma_p, dma_p->acc_handle); 3521 3522 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 3523 dma_p->orig_ioaddr_pp = 3524 (unsigned char *)dma_p->dma_cookie.dmac_laddress; 3525 dma_p->orig_alength = length; 3526 dma_p->orig_kaddrp = kaddrp; 3527 dma_p->orig_vatopa = (uint64_t)va_to_pa(kaddrp); 3528 #endif 3529 3530 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_dma_mem_alloc: " 3531 "dma buffer allocated: dma_p $%p " 3532 "return dmac_ladress from cookie $%p cookie dmac_size %d " 3533 "dma_p->ioaddr_p $%p " 3534 "dma_p->orig_ioaddr_p $%p " 3535 "orig_vatopa $%p " 3536 "alength %d (0x%x) " 3537 "kaddrp $%p " 3538 "length %d (0x%x)", 3539 dma_p, 3540 dma_p->dma_cookie.dmac_laddress, dma_p->dma_cookie.dmac_size, 3541 dma_p->ioaddr_pp, 3542 dma_p->orig_ioaddr_pp, 3543 dma_p->orig_vatopa, 3544 dma_p->alength, dma_p->alength, 3545 kaddrp, 3546 length, length)); 3547 3548 return (NXGE_OK); 3549 } 3550 3551 static void 3552 nxge_dma_mem_free(p_nxge_dma_common_t dma_p) 3553 { 3554 if (dma_p->dma_handle != NULL) { 3555 if (dma_p->ncookies) { 3556 (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3557 dma_p->ncookies = 0; 3558 } 3559 ddi_dma_free_handle(&dma_p->dma_handle); 3560 dma_p->dma_handle = NULL; 3561 } 3562 3563 if (dma_p->acc_handle != NULL) { 3564 ddi_dma_mem_free(&dma_p->acc_handle); 3565 dma_p->acc_handle = NULL; 3566 NPI_DMA_ACC_HANDLE_SET(dma_p, NULL); 3567 } 3568 3569 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 3570 if (dma_p->contig_alloc_type && 3571 dma_p->orig_kaddrp && dma_p->orig_alength) { 3572 NXGE_DEBUG_MSG((NULL, DMA_CTL, "nxge_dma_mem_free: " 3573 "kaddrp $%p (orig_kaddrp $%p)" 3574 "mem type %d ", 3575 "orig_alength %d " 3576 "alength 0x%x (%d)", 3577 dma_p->kaddrp, 3578 dma_p->orig_kaddrp, 3579 dma_p->contig_alloc_type, 3580 dma_p->orig_alength, 3581 dma_p->alength, dma_p->alength)); 3582 3583 contig_mem_free(dma_p->orig_kaddrp, dma_p->orig_alength); 3584 dma_p->orig_alength = NULL; 3585 dma_p->orig_kaddrp = NULL; 3586 dma_p->contig_alloc_type = B_FALSE; 3587 } 3588 #endif 3589 dma_p->kaddrp = NULL; 3590 dma_p->alength = NULL; 3591 } 3592 3593 static void 3594 nxge_dma_free_rx_data_buf(p_nxge_dma_common_t dma_p) 3595 { 3596 uint64_t kaddr; 3597 uint32_t buf_size; 3598 3599 NXGE_DEBUG_MSG((NULL, DMA_CTL, "==> nxge_dma_free_rx_data_buf")); 3600 3601 if (dma_p->dma_handle != NULL) { 3602 if (dma_p->ncookies) { 3603 (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3604 dma_p->ncookies = 0; 3605 } 3606 ddi_dma_free_handle(&dma_p->dma_handle); 3607 dma_p->dma_handle = NULL; 3608 } 3609 3610 if (dma_p->acc_handle != NULL) { 3611 ddi_dma_mem_free(&dma_p->acc_handle); 3612 dma_p->acc_handle = NULL; 3613 NPI_DMA_ACC_HANDLE_SET(dma_p, NULL); 3614 } 3615 3616 NXGE_DEBUG_MSG((NULL, DMA_CTL, 3617 "==> nxge_dma_free_rx_data_buf: dmap $%p buf_alloc_state %d", 3618 dma_p, 3619 dma_p->buf_alloc_state)); 3620 3621 if (!(dma_p->buf_alloc_state & BUF_ALLOCATED_WAIT_FREE)) { 3622 NXGE_DEBUG_MSG((NULL, DMA_CTL, 3623 "<== nxge_dma_free_rx_data_buf: " 3624 "outstanding data buffers")); 3625 return; 3626 } 3627 3628 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 3629 if (dma_p->contig_alloc_type && 3630 dma_p->orig_kaddrp && dma_p->orig_alength) { 3631 NXGE_DEBUG_MSG((NULL, DMA_CTL, "nxge_dma_free_rx_data_buf: " 3632 "kaddrp $%p (orig_kaddrp $%p)" 3633 "mem type %d ", 3634 "orig_alength %d " 3635 "alength 0x%x (%d)", 3636 dma_p->kaddrp, 3637 dma_p->orig_kaddrp, 3638 dma_p->contig_alloc_type, 3639 dma_p->orig_alength, 3640 dma_p->alength, dma_p->alength)); 3641 3642 kaddr = (uint64_t)dma_p->orig_kaddrp; 3643 buf_size = dma_p->orig_alength; 3644 nxge_free_buf(CONTIG_MEM_ALLOC, kaddr, buf_size); 3645 dma_p->orig_alength = NULL; 3646 dma_p->orig_kaddrp = NULL; 3647 dma_p->contig_alloc_type = B_FALSE; 3648 dma_p->kaddrp = NULL; 3649 dma_p->alength = NULL; 3650 return; 3651 } 3652 #endif 3653 3654 if (dma_p->kmem_alloc_type) { 3655 NXGE_DEBUG_MSG((NULL, DMA_CTL, 3656 "nxge_dma_free_rx_data_buf: free kmem " 3657 "kaddrp $%p (orig_kaddrp $%p)" 3658 "alloc type %d " 3659 "orig_alength %d " 3660 "alength 0x%x (%d)", 3661 dma_p->kaddrp, 3662 dma_p->orig_kaddrp, 3663 dma_p->kmem_alloc_type, 3664 dma_p->orig_alength, 3665 dma_p->alength, dma_p->alength)); 3666 #if defined(__i386) 3667 kaddr = (uint64_t)(uint32_t)dma_p->kaddrp; 3668 #else 3669 kaddr = (uint64_t)dma_p->kaddrp; 3670 #endif 3671 buf_size = dma_p->orig_alength; 3672 NXGE_DEBUG_MSG((NULL, DMA_CTL, 3673 "nxge_dma_free_rx_data_buf: free dmap $%p " 3674 "kaddr $%p buf_size %d", 3675 dma_p, 3676 kaddr, buf_size)); 3677 nxge_free_buf(KMEM_ALLOC, kaddr, buf_size); 3678 dma_p->alength = 0; 3679 dma_p->orig_alength = 0; 3680 dma_p->kaddrp = NULL; 3681 dma_p->kmem_alloc_type = B_FALSE; 3682 } 3683 3684 NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_dma_free_rx_data_buf")); 3685 } 3686 3687 /* 3688 * nxge_m_start() -- start transmitting and receiving. 3689 * 3690 * This function is called by the MAC layer when the first 3691 * stream is open to prepare the hardware ready for sending 3692 * and transmitting packets. 3693 */ 3694 static int 3695 nxge_m_start(void *arg) 3696 { 3697 p_nxge_t nxgep = (p_nxge_t)arg; 3698 3699 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_start")); 3700 3701 /* 3702 * Are we already started? 3703 */ 3704 if (nxgep->nxge_mac_state == NXGE_MAC_STARTED) { 3705 return (0); 3706 } 3707 3708 if (nxge_peu_reset_enable && !nxgep->nxge_link_poll_timerid) { 3709 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 3710 } 3711 3712 /* 3713 * Make sure RX MAC is disabled while we initialize. 3714 */ 3715 if (!isLDOMguest(nxgep)) { 3716 (void) nxge_rx_mac_disable(nxgep); 3717 } 3718 3719 /* 3720 * Grab the global lock. 3721 */ 3722 MUTEX_ENTER(nxgep->genlock); 3723 3724 /* 3725 * Initialize the driver and hardware. 3726 */ 3727 if (nxge_init(nxgep) != NXGE_OK) { 3728 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3729 "<== nxge_m_start: initialization failed")); 3730 MUTEX_EXIT(nxgep->genlock); 3731 return (EIO); 3732 } 3733 3734 /* 3735 * Start timer to check the system error and tx hangs 3736 */ 3737 if (!isLDOMguest(nxgep)) 3738 nxgep->nxge_timerid = nxge_start_timer(nxgep, 3739 nxge_check_hw_state, NXGE_CHECK_TIMER); 3740 #if defined(sun4v) 3741 else 3742 nxge_hio_start_timer(nxgep); 3743 #endif 3744 3745 nxgep->link_notify = B_TRUE; 3746 nxgep->nxge_mac_state = NXGE_MAC_STARTED; 3747 3748 /* 3749 * Let the global lock go, since we are intialized. 3750 */ 3751 MUTEX_EXIT(nxgep->genlock); 3752 3753 /* 3754 * Let the MAC start receiving packets, now that 3755 * we are initialized. 3756 */ 3757 if (!isLDOMguest(nxgep)) { 3758 if (nxge_rx_mac_enable(nxgep) != NXGE_OK) { 3759 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3760 "<== nxge_m_start: enable of RX mac failed")); 3761 return (EIO); 3762 } 3763 3764 /* 3765 * Enable hardware interrupts. 3766 */ 3767 nxge_intr_hw_enable(nxgep); 3768 } 3769 #if defined(sun4v) 3770 else { 3771 /* 3772 * In guest domain we enable RDCs and their interrupts as 3773 * the last step. 3774 */ 3775 if (nxge_hio_rdc_enable(nxgep) != NXGE_OK) { 3776 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3777 "<== nxge_m_start: enable of RDCs failed")); 3778 return (EIO); 3779 } 3780 3781 if (nxge_hio_rdc_intr_arm(nxgep, B_TRUE) != NXGE_OK) { 3782 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3783 "<== nxge_m_start: intrs enable for RDCs failed")); 3784 return (EIO); 3785 } 3786 } 3787 #endif 3788 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_start")); 3789 return (0); 3790 } 3791 3792 static boolean_t 3793 nxge_check_groups_stopped(p_nxge_t nxgep) 3794 { 3795 int i; 3796 3797 for (i = 0; i < NXGE_MAX_RDC_GROUPS; i++) { 3798 if (nxgep->rx_hio_groups[i].started) 3799 return (B_FALSE); 3800 } 3801 3802 return (B_TRUE); 3803 } 3804 3805 /* 3806 * nxge_m_stop(): stop transmitting and receiving. 3807 */ 3808 static void 3809 nxge_m_stop(void *arg) 3810 { 3811 p_nxge_t nxgep = (p_nxge_t)arg; 3812 boolean_t groups_stopped; 3813 3814 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_stop")); 3815 3816 /* 3817 * Are the groups stopped? 3818 */ 3819 groups_stopped = nxge_check_groups_stopped(nxgep); 3820 ASSERT(groups_stopped == B_TRUE); 3821 if (!groups_stopped) { 3822 cmn_err(CE_WARN, "nxge(%d): groups are not stopped!\n", 3823 nxgep->instance); 3824 return; 3825 } 3826 3827 if (!isLDOMguest(nxgep)) { 3828 /* 3829 * Disable the RX mac. 3830 */ 3831 (void) nxge_rx_mac_disable(nxgep); 3832 3833 /* 3834 * Wait for the IPP to drain. 3835 */ 3836 (void) nxge_ipp_drain(nxgep); 3837 3838 /* 3839 * Disable hardware interrupts. 3840 */ 3841 nxge_intr_hw_disable(nxgep); 3842 } 3843 #if defined(sun4v) 3844 else { 3845 (void) nxge_hio_rdc_intr_arm(nxgep, B_FALSE); 3846 } 3847 #endif 3848 3849 /* 3850 * Grab the global lock. 3851 */ 3852 MUTEX_ENTER(nxgep->genlock); 3853 3854 nxgep->nxge_mac_state = NXGE_MAC_STOPPING; 3855 if (nxgep->nxge_timerid) { 3856 nxge_stop_timer(nxgep, nxgep->nxge_timerid); 3857 nxgep->nxge_timerid = 0; 3858 } 3859 3860 /* 3861 * Clean up. 3862 */ 3863 nxge_uninit(nxgep); 3864 3865 nxgep->nxge_mac_state = NXGE_MAC_STOPPED; 3866 3867 /* 3868 * Let go of the global lock. 3869 */ 3870 MUTEX_EXIT(nxgep->genlock); 3871 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_stop")); 3872 } 3873 3874 static int 3875 nxge_m_multicst(void *arg, boolean_t add, const uint8_t *mca) 3876 { 3877 p_nxge_t nxgep = (p_nxge_t)arg; 3878 struct ether_addr addrp; 3879 3880 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 3881 "==> nxge_m_multicst: add %d", add)); 3882 3883 bcopy(mca, (uint8_t *)&addrp, ETHERADDRL); 3884 if (add) { 3885 if (nxge_add_mcast_addr(nxgep, &addrp)) { 3886 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3887 "<== nxge_m_multicst: add multicast failed")); 3888 return (EINVAL); 3889 } 3890 } else { 3891 if (nxge_del_mcast_addr(nxgep, &addrp)) { 3892 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3893 "<== nxge_m_multicst: del multicast failed")); 3894 return (EINVAL); 3895 } 3896 } 3897 3898 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_m_multicst")); 3899 3900 return (0); 3901 } 3902 3903 static int 3904 nxge_m_promisc(void *arg, boolean_t on) 3905 { 3906 p_nxge_t nxgep = (p_nxge_t)arg; 3907 3908 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 3909 "==> nxge_m_promisc: on %d", on)); 3910 3911 if (nxge_set_promisc(nxgep, on)) { 3912 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3913 "<== nxge_m_promisc: set promisc failed")); 3914 return (EINVAL); 3915 } 3916 3917 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 3918 "<== nxge_m_promisc: on %d", on)); 3919 3920 return (0); 3921 } 3922 3923 static void 3924 nxge_m_ioctl(void *arg, queue_t *wq, mblk_t *mp) 3925 { 3926 p_nxge_t nxgep = (p_nxge_t)arg; 3927 struct iocblk *iocp; 3928 boolean_t need_privilege; 3929 int err; 3930 int cmd; 3931 3932 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_ioctl")); 3933 3934 iocp = (struct iocblk *)mp->b_rptr; 3935 iocp->ioc_error = 0; 3936 need_privilege = B_TRUE; 3937 cmd = iocp->ioc_cmd; 3938 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_ioctl: cmd 0x%08x", cmd)); 3939 switch (cmd) { 3940 default: 3941 miocnak(wq, mp, 0, EINVAL); 3942 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_ioctl: invalid")); 3943 return; 3944 3945 case LB_GET_INFO_SIZE: 3946 case LB_GET_INFO: 3947 case LB_GET_MODE: 3948 need_privilege = B_FALSE; 3949 break; 3950 case LB_SET_MODE: 3951 break; 3952 3953 3954 case NXGE_GET_MII: 3955 case NXGE_PUT_MII: 3956 case NXGE_GET64: 3957 case NXGE_PUT64: 3958 case NXGE_GET_TX_RING_SZ: 3959 case NXGE_GET_TX_DESC: 3960 case NXGE_TX_SIDE_RESET: 3961 case NXGE_RX_SIDE_RESET: 3962 case NXGE_GLOBAL_RESET: 3963 case NXGE_RESET_MAC: 3964 case NXGE_TX_REGS_DUMP: 3965 case NXGE_RX_REGS_DUMP: 3966 case NXGE_INT_REGS_DUMP: 3967 case NXGE_VIR_INT_REGS_DUMP: 3968 case NXGE_PUT_TCAM: 3969 case NXGE_GET_TCAM: 3970 case NXGE_RTRACE: 3971 case NXGE_RDUMP: 3972 3973 need_privilege = B_FALSE; 3974 break; 3975 case NXGE_INJECT_ERR: 3976 cmn_err(CE_NOTE, "!nxge_m_ioctl: Inject error\n"); 3977 nxge_err_inject(nxgep, wq, mp); 3978 break; 3979 } 3980 3981 if (need_privilege) { 3982 err = secpolicy_net_config(iocp->ioc_cr, B_FALSE); 3983 if (err != 0) { 3984 miocnak(wq, mp, 0, err); 3985 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3986 "<== nxge_m_ioctl: no priv")); 3987 return; 3988 } 3989 } 3990 3991 switch (cmd) { 3992 3993 case LB_GET_MODE: 3994 case LB_SET_MODE: 3995 case LB_GET_INFO_SIZE: 3996 case LB_GET_INFO: 3997 nxge_loopback_ioctl(nxgep, wq, mp, iocp); 3998 break; 3999 4000 case NXGE_GET_MII: 4001 case NXGE_PUT_MII: 4002 case NXGE_PUT_TCAM: 4003 case NXGE_GET_TCAM: 4004 case NXGE_GET64: 4005 case NXGE_PUT64: 4006 case NXGE_GET_TX_RING_SZ: 4007 case NXGE_GET_TX_DESC: 4008 case NXGE_TX_SIDE_RESET: 4009 case NXGE_RX_SIDE_RESET: 4010 case NXGE_GLOBAL_RESET: 4011 case NXGE_RESET_MAC: 4012 case NXGE_TX_REGS_DUMP: 4013 case NXGE_RX_REGS_DUMP: 4014 case NXGE_INT_REGS_DUMP: 4015 case NXGE_VIR_INT_REGS_DUMP: 4016 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4017 "==> nxge_m_ioctl: cmd 0x%x", cmd)); 4018 nxge_hw_ioctl(nxgep, wq, mp, iocp); 4019 break; 4020 } 4021 4022 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_ioctl")); 4023 } 4024 4025 extern void nxge_rx_hw_blank(void *arg, time_t ticks, uint_t count); 4026 4027 void 4028 nxge_mmac_kstat_update(p_nxge_t nxgep, int slot, boolean_t factory) 4029 { 4030 p_nxge_mmac_stats_t mmac_stats; 4031 int i; 4032 nxge_mmac_t *mmac_info; 4033 4034 mmac_info = &nxgep->nxge_mmac_info; 4035 4036 mmac_stats = &nxgep->statsp->mmac_stats; 4037 mmac_stats->mmac_max_cnt = mmac_info->num_mmac; 4038 mmac_stats->mmac_avail_cnt = mmac_info->naddrfree; 4039 4040 for (i = 0; i < ETHERADDRL; i++) { 4041 if (factory) { 4042 mmac_stats->mmac_avail_pool[slot-1].ether_addr_octet[i] 4043 = mmac_info->factory_mac_pool[slot][ 4044 (ETHERADDRL-1) - i]; 4045 } else { 4046 mmac_stats->mmac_avail_pool[slot-1].ether_addr_octet[i] 4047 = mmac_info->mac_pool[slot].addr[ 4048 (ETHERADDRL - 1) - i]; 4049 } 4050 } 4051 } 4052 4053 /* 4054 * nxge_altmac_set() -- Set an alternate MAC address 4055 */ 4056 static int 4057 nxge_altmac_set(p_nxge_t nxgep, uint8_t *maddr, int slot, 4058 int rdctbl, boolean_t usetbl) 4059 { 4060 uint8_t addrn; 4061 uint8_t portn; 4062 npi_mac_addr_t altmac; 4063 hostinfo_t mac_rdc; 4064 p_nxge_class_pt_cfg_t clscfgp; 4065 4066 4067 altmac.w2 = ((uint16_t)maddr[0] << 8) | ((uint16_t)maddr[1] & 0x0ff); 4068 altmac.w1 = ((uint16_t)maddr[2] << 8) | ((uint16_t)maddr[3] & 0x0ff); 4069 altmac.w0 = ((uint16_t)maddr[4] << 8) | ((uint16_t)maddr[5] & 0x0ff); 4070 4071 portn = nxgep->mac.portnum; 4072 addrn = (uint8_t)slot - 1; 4073 4074 if (npi_mac_altaddr_entry(nxgep->npi_handle, OP_SET, 4075 nxgep->function_num, addrn, &altmac) != NPI_SUCCESS) 4076 return (EIO); 4077 4078 /* 4079 * Set the rdc table number for the host info entry 4080 * for this mac address slot. 4081 */ 4082 clscfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 4083 mac_rdc.value = 0; 4084 if (usetbl) 4085 mac_rdc.bits.w0.rdc_tbl_num = rdctbl; 4086 else 4087 mac_rdc.bits.w0.rdc_tbl_num = 4088 clscfgp->mac_host_info[addrn].rdctbl; 4089 mac_rdc.bits.w0.mac_pref = clscfgp->mac_host_info[addrn].mpr_npr; 4090 4091 if (npi_mac_hostinfo_entry(nxgep->npi_handle, OP_SET, 4092 nxgep->function_num, addrn, &mac_rdc) != NPI_SUCCESS) { 4093 return (EIO); 4094 } 4095 4096 /* 4097 * Enable comparison with the alternate MAC address. 4098 * While the first alternate addr is enabled by bit 1 of register 4099 * BMAC_ALTAD_CMPEN, it is enabled by bit 0 of register 4100 * XMAC_ADDR_CMPEN, so slot needs to be converted to addrn 4101 * accordingly before calling npi_mac_altaddr_entry. 4102 */ 4103 if (portn == XMAC_PORT_0 || portn == XMAC_PORT_1) 4104 addrn = (uint8_t)slot - 1; 4105 else 4106 addrn = (uint8_t)slot; 4107 4108 if (npi_mac_altaddr_enable(nxgep->npi_handle, 4109 nxgep->function_num, addrn) != NPI_SUCCESS) { 4110 return (EIO); 4111 } 4112 4113 return (0); 4114 } 4115 4116 /* 4117 * nxeg_m_mmac_add_g() - find an unused address slot, set the address 4118 * value to the one specified, enable the port to start filtering on 4119 * the new MAC address. Returns 0 on success. 4120 */ 4121 int 4122 nxge_m_mmac_add_g(void *arg, const uint8_t *maddr, int rdctbl, 4123 boolean_t usetbl) 4124 { 4125 p_nxge_t nxgep = arg; 4126 int slot; 4127 nxge_mmac_t *mmac_info; 4128 int err; 4129 nxge_status_t status; 4130 4131 mutex_enter(nxgep->genlock); 4132 4133 /* 4134 * Make sure that nxge is initialized, if _start() has 4135 * not been called. 4136 */ 4137 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 4138 status = nxge_init(nxgep); 4139 if (status != NXGE_OK) { 4140 mutex_exit(nxgep->genlock); 4141 return (ENXIO); 4142 } 4143 } 4144 4145 mmac_info = &nxgep->nxge_mmac_info; 4146 if (mmac_info->naddrfree == 0) { 4147 mutex_exit(nxgep->genlock); 4148 return (ENOSPC); 4149 } 4150 4151 /* 4152 * Search for the first available slot. Because naddrfree 4153 * is not zero, we are guaranteed to find one. 4154 * Each of the first two ports of Neptune has 16 alternate 4155 * MAC slots but only the first 7 (of 15) slots have assigned factory 4156 * MAC addresses. We first search among the slots without bundled 4157 * factory MACs. If we fail to find one in that range, then we 4158 * search the slots with bundled factory MACs. A factory MAC 4159 * will be wasted while the slot is used with a user MAC address. 4160 * But the slot could be used by factory MAC again after calling 4161 * nxge_m_mmac_remove and nxge_m_mmac_reserve. 4162 */ 4163 for (slot = 0; slot <= mmac_info->num_mmac; slot++) { 4164 if (!(mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED)) 4165 break; 4166 } 4167 4168 ASSERT(slot <= mmac_info->num_mmac); 4169 4170 if ((err = nxge_altmac_set(nxgep, (uint8_t *)maddr, slot, rdctbl, 4171 usetbl)) != 0) { 4172 mutex_exit(nxgep->genlock); 4173 return (err); 4174 } 4175 4176 bcopy(maddr, mmac_info->mac_pool[slot].addr, ETHERADDRL); 4177 mmac_info->mac_pool[slot].flags |= MMAC_SLOT_USED; 4178 mmac_info->mac_pool[slot].flags &= ~MMAC_VENDOR_ADDR; 4179 mmac_info->naddrfree--; 4180 nxge_mmac_kstat_update(nxgep, slot, B_FALSE); 4181 4182 mutex_exit(nxgep->genlock); 4183 return (0); 4184 } 4185 4186 /* 4187 * Remove the specified mac address and update the HW not to filter 4188 * the mac address anymore. 4189 */ 4190 int 4191 nxge_m_mmac_remove(void *arg, int slot) 4192 { 4193 p_nxge_t nxgep = arg; 4194 nxge_mmac_t *mmac_info; 4195 uint8_t addrn; 4196 uint8_t portn; 4197 int err = 0; 4198 nxge_status_t status; 4199 4200 mutex_enter(nxgep->genlock); 4201 4202 /* 4203 * Make sure that nxge is initialized, if _start() has 4204 * not been called. 4205 */ 4206 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 4207 status = nxge_init(nxgep); 4208 if (status != NXGE_OK) { 4209 mutex_exit(nxgep->genlock); 4210 return (ENXIO); 4211 } 4212 } 4213 4214 mmac_info = &nxgep->nxge_mmac_info; 4215 if (slot < 1 || slot > mmac_info->num_mmac) { 4216 mutex_exit(nxgep->genlock); 4217 return (EINVAL); 4218 } 4219 4220 portn = nxgep->mac.portnum; 4221 if (portn == XMAC_PORT_0 || portn == XMAC_PORT_1) 4222 addrn = (uint8_t)slot - 1; 4223 else 4224 addrn = (uint8_t)slot; 4225 4226 if (mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED) { 4227 if (npi_mac_altaddr_disable(nxgep->npi_handle, portn, addrn) 4228 == NPI_SUCCESS) { 4229 mmac_info->naddrfree++; 4230 mmac_info->mac_pool[slot].flags &= ~MMAC_SLOT_USED; 4231 /* 4232 * Regardless if the MAC we just stopped filtering 4233 * is a user addr or a facory addr, we must set 4234 * the MMAC_VENDOR_ADDR flag if this slot has an 4235 * associated factory MAC to indicate that a factory 4236 * MAC is available. 4237 */ 4238 if (slot <= mmac_info->num_factory_mmac) { 4239 mmac_info->mac_pool[slot].flags 4240 |= MMAC_VENDOR_ADDR; 4241 } 4242 /* 4243 * Clear mac_pool[slot].addr so that kstat shows 0 4244 * alternate MAC address if the slot is not used. 4245 * (But nxge_m_mmac_get returns the factory MAC even 4246 * when the slot is not used!) 4247 */ 4248 bzero(mmac_info->mac_pool[slot].addr, ETHERADDRL); 4249 nxge_mmac_kstat_update(nxgep, slot, B_FALSE); 4250 } else { 4251 err = EIO; 4252 } 4253 } else { 4254 err = EINVAL; 4255 } 4256 4257 mutex_exit(nxgep->genlock); 4258 return (err); 4259 } 4260 4261 /* 4262 * The callback to query all the factory addresses. naddr must be the same as 4263 * the number of factory addresses (returned by MAC_CAPAB_MULTIFACTADDR), and 4264 * mcm_addr is the space allocated for keep all the addresses, whose size is 4265 * naddr * MAXMACADDRLEN. 4266 */ 4267 static void 4268 nxge_m_getfactaddr(void *arg, uint_t naddr, uint8_t *addr) 4269 { 4270 nxge_t *nxgep = arg; 4271 nxge_mmac_t *mmac_info; 4272 int i; 4273 4274 mutex_enter(nxgep->genlock); 4275 4276 mmac_info = &nxgep->nxge_mmac_info; 4277 ASSERT(naddr == mmac_info->num_factory_mmac); 4278 4279 for (i = 0; i < naddr; i++) { 4280 bcopy(mmac_info->factory_mac_pool[i + 1], 4281 addr + i * MAXMACADDRLEN, ETHERADDRL); 4282 } 4283 4284 mutex_exit(nxgep->genlock); 4285 } 4286 4287 4288 static boolean_t 4289 nxge_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 4290 { 4291 nxge_t *nxgep = arg; 4292 uint32_t *txflags = cap_data; 4293 4294 switch (cap) { 4295 case MAC_CAPAB_HCKSUM: 4296 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4297 "==> nxge_m_getcapab: checksum %d", nxge_cksum_offload)); 4298 if (nxge_cksum_offload <= 1) { 4299 *txflags = HCKSUM_INET_PARTIAL; 4300 } 4301 break; 4302 4303 case MAC_CAPAB_MULTIFACTADDR: { 4304 mac_capab_multifactaddr_t *mfacp = cap_data; 4305 4306 mutex_enter(nxgep->genlock); 4307 mfacp->mcm_naddr = nxgep->nxge_mmac_info.num_factory_mmac; 4308 mfacp->mcm_getaddr = nxge_m_getfactaddr; 4309 mutex_exit(nxgep->genlock); 4310 break; 4311 } 4312 4313 case MAC_CAPAB_LSO: { 4314 mac_capab_lso_t *cap_lso = cap_data; 4315 4316 if (nxgep->soft_lso_enable) { 4317 if (nxge_cksum_offload <= 1) { 4318 cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4; 4319 if (nxge_lso_max > NXGE_LSO_MAXLEN) { 4320 nxge_lso_max = NXGE_LSO_MAXLEN; 4321 } 4322 cap_lso->lso_basic_tcp_ipv4.lso_max = 4323 nxge_lso_max; 4324 } 4325 break; 4326 } else { 4327 return (B_FALSE); 4328 } 4329 } 4330 4331 case MAC_CAPAB_RINGS: { 4332 mac_capab_rings_t *cap_rings = cap_data; 4333 p_nxge_hw_pt_cfg_t p_cfgp = &nxgep->pt_config.hw_config; 4334 4335 mutex_enter(nxgep->genlock); 4336 if (cap_rings->mr_type == MAC_RING_TYPE_RX) { 4337 cap_rings->mr_group_type = MAC_GROUP_TYPE_DYNAMIC; 4338 cap_rings->mr_rnum = p_cfgp->max_rdcs; 4339 cap_rings->mr_rget = nxge_fill_ring; 4340 cap_rings->mr_gnum = p_cfgp->max_rdc_grpids; 4341 cap_rings->mr_gget = nxge_hio_group_get; 4342 cap_rings->mr_gaddring = nxge_group_add_ring; 4343 cap_rings->mr_gremring = nxge_group_rem_ring; 4344 4345 NXGE_DEBUG_MSG((nxgep, RX_CTL, 4346 "==> nxge_m_getcapab: rx nrings[%d] ngroups[%d]", 4347 p_cfgp->max_rdcs, p_cfgp->max_rdc_grpids)); 4348 } else { 4349 cap_rings->mr_group_type = MAC_GROUP_TYPE_DYNAMIC; 4350 cap_rings->mr_rnum = p_cfgp->tdc.count; 4351 cap_rings->mr_rget = nxge_fill_ring; 4352 if (isLDOMservice(nxgep)) { 4353 /* share capable */ 4354 /* Do not report the default ring: hence -1 */ 4355 cap_rings->mr_gnum = 4356 NXGE_MAX_TDC_GROUPS / nxgep->nports - 1; 4357 } else { 4358 cap_rings->mr_gnum = 0; 4359 } 4360 4361 cap_rings->mr_gget = nxge_hio_group_get; 4362 cap_rings->mr_gaddring = nxge_group_add_ring; 4363 cap_rings->mr_gremring = nxge_group_rem_ring; 4364 4365 NXGE_DEBUG_MSG((nxgep, TX_CTL, 4366 "==> nxge_m_getcapab: tx rings # of rings %d", 4367 p_cfgp->tdc.count)); 4368 } 4369 mutex_exit(nxgep->genlock); 4370 break; 4371 } 4372 4373 #if defined(sun4v) 4374 case MAC_CAPAB_SHARES: { 4375 mac_capab_share_t *mshares = (mac_capab_share_t *)cap_data; 4376 4377 /* 4378 * Only the service domain driver responds to 4379 * this capability request. 4380 */ 4381 mutex_enter(nxgep->genlock); 4382 if (isLDOMservice(nxgep)) { 4383 mshares->ms_snum = 3; 4384 mshares->ms_handle = (void *)nxgep; 4385 mshares->ms_salloc = nxge_hio_share_alloc; 4386 mshares->ms_sfree = nxge_hio_share_free; 4387 mshares->ms_sadd = nxge_hio_share_add_group; 4388 mshares->ms_sremove = nxge_hio_share_rem_group; 4389 mshares->ms_squery = nxge_hio_share_query; 4390 mshares->ms_sbind = nxge_hio_share_bind; 4391 mshares->ms_sunbind = nxge_hio_share_unbind; 4392 mutex_exit(nxgep->genlock); 4393 } else { 4394 mutex_exit(nxgep->genlock); 4395 return (B_FALSE); 4396 } 4397 break; 4398 } 4399 #endif 4400 default: 4401 return (B_FALSE); 4402 } 4403 return (B_TRUE); 4404 } 4405 4406 static boolean_t 4407 nxge_param_locked(mac_prop_id_t pr_num) 4408 { 4409 /* 4410 * All adv_* parameters are locked (read-only) while 4411 * the device is in any sort of loopback mode ... 4412 */ 4413 switch (pr_num) { 4414 case MAC_PROP_ADV_1000FDX_CAP: 4415 case MAC_PROP_EN_1000FDX_CAP: 4416 case MAC_PROP_ADV_1000HDX_CAP: 4417 case MAC_PROP_EN_1000HDX_CAP: 4418 case MAC_PROP_ADV_100FDX_CAP: 4419 case MAC_PROP_EN_100FDX_CAP: 4420 case MAC_PROP_ADV_100HDX_CAP: 4421 case MAC_PROP_EN_100HDX_CAP: 4422 case MAC_PROP_ADV_10FDX_CAP: 4423 case MAC_PROP_EN_10FDX_CAP: 4424 case MAC_PROP_ADV_10HDX_CAP: 4425 case MAC_PROP_EN_10HDX_CAP: 4426 case MAC_PROP_AUTONEG: 4427 case MAC_PROP_FLOWCTRL: 4428 return (B_TRUE); 4429 } 4430 return (B_FALSE); 4431 } 4432 4433 /* 4434 * callback functions for set/get of properties 4435 */ 4436 static int 4437 nxge_m_setprop(void *barg, const char *pr_name, mac_prop_id_t pr_num, 4438 uint_t pr_valsize, const void *pr_val) 4439 { 4440 nxge_t *nxgep = barg; 4441 p_nxge_param_t param_arr; 4442 p_nxge_stats_t statsp; 4443 int err = 0; 4444 uint8_t val; 4445 uint32_t cur_mtu, new_mtu, old_framesize; 4446 link_flowctrl_t fl; 4447 4448 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_setprop")); 4449 param_arr = nxgep->param_arr; 4450 statsp = nxgep->statsp; 4451 mutex_enter(nxgep->genlock); 4452 if (statsp->port_stats.lb_mode != nxge_lb_normal && 4453 nxge_param_locked(pr_num)) { 4454 /* 4455 * All adv_* parameters are locked (read-only) 4456 * while the device is in any sort of loopback mode. 4457 */ 4458 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4459 "==> nxge_m_setprop: loopback mode: read only")); 4460 mutex_exit(nxgep->genlock); 4461 return (EBUSY); 4462 } 4463 4464 val = *(uint8_t *)pr_val; 4465 switch (pr_num) { 4466 case MAC_PROP_EN_1000FDX_CAP: 4467 nxgep->param_en_1000fdx = val; 4468 param_arr[param_anar_1000fdx].value = val; 4469 4470 goto reprogram; 4471 4472 case MAC_PROP_EN_100FDX_CAP: 4473 nxgep->param_en_100fdx = val; 4474 param_arr[param_anar_100fdx].value = val; 4475 4476 goto reprogram; 4477 4478 case MAC_PROP_EN_10FDX_CAP: 4479 nxgep->param_en_10fdx = val; 4480 param_arr[param_anar_10fdx].value = val; 4481 4482 goto reprogram; 4483 4484 case MAC_PROP_EN_1000HDX_CAP: 4485 case MAC_PROP_EN_100HDX_CAP: 4486 case MAC_PROP_EN_10HDX_CAP: 4487 case MAC_PROP_ADV_1000FDX_CAP: 4488 case MAC_PROP_ADV_1000HDX_CAP: 4489 case MAC_PROP_ADV_100FDX_CAP: 4490 case MAC_PROP_ADV_100HDX_CAP: 4491 case MAC_PROP_ADV_10FDX_CAP: 4492 case MAC_PROP_ADV_10HDX_CAP: 4493 case MAC_PROP_STATUS: 4494 case MAC_PROP_SPEED: 4495 case MAC_PROP_DUPLEX: 4496 err = EINVAL; /* cannot set read-only properties */ 4497 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4498 "==> nxge_m_setprop: read only property %d", 4499 pr_num)); 4500 break; 4501 4502 case MAC_PROP_AUTONEG: 4503 param_arr[param_autoneg].value = val; 4504 4505 goto reprogram; 4506 4507 case MAC_PROP_MTU: 4508 cur_mtu = nxgep->mac.default_mtu; 4509 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 4510 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4511 "==> nxge_m_setprop: set MTU: %d is_jumbo %d", 4512 new_mtu, nxgep->mac.is_jumbo)); 4513 4514 if (new_mtu == cur_mtu) { 4515 err = 0; 4516 break; 4517 } 4518 4519 if (nxgep->nxge_mac_state == NXGE_MAC_STARTED) { 4520 err = EBUSY; 4521 break; 4522 } 4523 4524 if ((new_mtu < NXGE_DEFAULT_MTU) || 4525 (new_mtu > NXGE_MAXIMUM_MTU)) { 4526 err = EINVAL; 4527 break; 4528 } 4529 4530 old_framesize = (uint32_t)nxgep->mac.maxframesize; 4531 nxgep->mac.maxframesize = (uint16_t) 4532 (new_mtu + NXGE_EHEADER_VLAN_CRC); 4533 if (nxge_mac_set_framesize(nxgep)) { 4534 nxgep->mac.maxframesize = 4535 (uint16_t)old_framesize; 4536 err = EINVAL; 4537 break; 4538 } 4539 4540 err = mac_maxsdu_update(nxgep->mach, new_mtu); 4541 if (err) { 4542 nxgep->mac.maxframesize = 4543 (uint16_t)old_framesize; 4544 err = EINVAL; 4545 break; 4546 } 4547 4548 nxgep->mac.default_mtu = new_mtu; 4549 if (new_mtu > NXGE_DEFAULT_MTU) 4550 nxgep->mac.is_jumbo = B_TRUE; 4551 else 4552 nxgep->mac.is_jumbo = B_FALSE; 4553 4554 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4555 "==> nxge_m_setprop: set MTU: %d maxframe %d", 4556 new_mtu, nxgep->mac.maxframesize)); 4557 break; 4558 4559 case MAC_PROP_FLOWCTRL: 4560 bcopy(pr_val, &fl, sizeof (fl)); 4561 switch (fl) { 4562 default: 4563 err = EINVAL; 4564 break; 4565 4566 case LINK_FLOWCTRL_NONE: 4567 param_arr[param_anar_pause].value = 0; 4568 break; 4569 4570 case LINK_FLOWCTRL_RX: 4571 param_arr[param_anar_pause].value = 1; 4572 break; 4573 4574 case LINK_FLOWCTRL_TX: 4575 case LINK_FLOWCTRL_BI: 4576 err = EINVAL; 4577 break; 4578 } 4579 4580 reprogram: 4581 if (err == 0) { 4582 if (!nxge_param_link_update(nxgep)) { 4583 err = EINVAL; 4584 } 4585 } 4586 break; 4587 case MAC_PROP_PRIVATE: 4588 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4589 "==> nxge_m_setprop: private property")); 4590 err = nxge_set_priv_prop(nxgep, pr_name, pr_valsize, 4591 pr_val); 4592 break; 4593 4594 default: 4595 err = ENOTSUP; 4596 break; 4597 } 4598 4599 mutex_exit(nxgep->genlock); 4600 4601 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4602 "<== nxge_m_setprop (return %d)", err)); 4603 return (err); 4604 } 4605 4606 static int 4607 nxge_m_getprop(void *barg, const char *pr_name, mac_prop_id_t pr_num, 4608 uint_t pr_flags, uint_t pr_valsize, void *pr_val, uint_t *perm) 4609 { 4610 nxge_t *nxgep = barg; 4611 p_nxge_param_t param_arr = nxgep->param_arr; 4612 p_nxge_stats_t statsp = nxgep->statsp; 4613 int err = 0; 4614 link_flowctrl_t fl; 4615 uint64_t tmp = 0; 4616 link_state_t ls; 4617 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 4618 4619 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4620 "==> nxge_m_getprop: pr_num %d", pr_num)); 4621 4622 if (pr_valsize == 0) 4623 return (EINVAL); 4624 4625 *perm = MAC_PROP_PERM_RW; 4626 4627 if ((is_default) && (pr_num != MAC_PROP_PRIVATE)) { 4628 err = nxge_get_def_val(nxgep, pr_num, pr_valsize, pr_val); 4629 return (err); 4630 } 4631 4632 bzero(pr_val, pr_valsize); 4633 switch (pr_num) { 4634 case MAC_PROP_DUPLEX: 4635 *perm = MAC_PROP_PERM_READ; 4636 *(uint8_t *)pr_val = statsp->mac_stats.link_duplex; 4637 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4638 "==> nxge_m_getprop: duplex mode %d", 4639 *(uint8_t *)pr_val)); 4640 break; 4641 4642 case MAC_PROP_SPEED: 4643 if (pr_valsize < sizeof (uint64_t)) 4644 return (EINVAL); 4645 *perm = MAC_PROP_PERM_READ; 4646 tmp = statsp->mac_stats.link_speed * 1000000ull; 4647 bcopy(&tmp, pr_val, sizeof (tmp)); 4648 break; 4649 4650 case MAC_PROP_STATUS: 4651 if (pr_valsize < sizeof (link_state_t)) 4652 return (EINVAL); 4653 *perm = MAC_PROP_PERM_READ; 4654 if (!statsp->mac_stats.link_up) 4655 ls = LINK_STATE_DOWN; 4656 else 4657 ls = LINK_STATE_UP; 4658 bcopy(&ls, pr_val, sizeof (ls)); 4659 break; 4660 4661 case MAC_PROP_AUTONEG: 4662 *(uint8_t *)pr_val = 4663 param_arr[param_autoneg].value; 4664 break; 4665 4666 case MAC_PROP_FLOWCTRL: 4667 if (pr_valsize < sizeof (link_flowctrl_t)) 4668 return (EINVAL); 4669 4670 fl = LINK_FLOWCTRL_NONE; 4671 if (param_arr[param_anar_pause].value) { 4672 fl = LINK_FLOWCTRL_RX; 4673 } 4674 bcopy(&fl, pr_val, sizeof (fl)); 4675 break; 4676 4677 case MAC_PROP_ADV_1000FDX_CAP: 4678 *perm = MAC_PROP_PERM_READ; 4679 *(uint8_t *)pr_val = 4680 param_arr[param_anar_1000fdx].value; 4681 break; 4682 4683 case MAC_PROP_EN_1000FDX_CAP: 4684 *(uint8_t *)pr_val = nxgep->param_en_1000fdx; 4685 break; 4686 4687 case MAC_PROP_ADV_100FDX_CAP: 4688 *perm = MAC_PROP_PERM_READ; 4689 *(uint8_t *)pr_val = 4690 param_arr[param_anar_100fdx].value; 4691 break; 4692 4693 case MAC_PROP_EN_100FDX_CAP: 4694 *(uint8_t *)pr_val = nxgep->param_en_100fdx; 4695 break; 4696 4697 case MAC_PROP_ADV_10FDX_CAP: 4698 *perm = MAC_PROP_PERM_READ; 4699 *(uint8_t *)pr_val = 4700 param_arr[param_anar_10fdx].value; 4701 break; 4702 4703 case MAC_PROP_EN_10FDX_CAP: 4704 *(uint8_t *)pr_val = nxgep->param_en_10fdx; 4705 break; 4706 4707 case MAC_PROP_EN_1000HDX_CAP: 4708 case MAC_PROP_EN_100HDX_CAP: 4709 case MAC_PROP_EN_10HDX_CAP: 4710 case MAC_PROP_ADV_1000HDX_CAP: 4711 case MAC_PROP_ADV_100HDX_CAP: 4712 case MAC_PROP_ADV_10HDX_CAP: 4713 err = ENOTSUP; 4714 break; 4715 4716 case MAC_PROP_PRIVATE: 4717 err = nxge_get_priv_prop(nxgep, pr_name, pr_flags, 4718 pr_valsize, pr_val, perm); 4719 break; 4720 4721 case MAC_PROP_MTU: { 4722 mac_propval_range_t range; 4723 4724 if (!(pr_flags & MAC_PROP_POSSIBLE)) 4725 return (ENOTSUP); 4726 if (pr_valsize < sizeof (mac_propval_range_t)) 4727 return (EINVAL); 4728 range.mpr_count = 1; 4729 range.mpr_type = MAC_PROPVAL_UINT32; 4730 range.range_uint32[0].mpur_min = 4731 range.range_uint32[0].mpur_max = NXGE_DEFAULT_MTU; 4732 if (nxgep->mac.is_jumbo) 4733 range.range_uint32[0].mpur_max = 4734 NXGE_MAXIMUM_MTU; 4735 bcopy(&range, pr_val, sizeof (range)); 4736 break; 4737 } 4738 default: 4739 err = EINVAL; 4740 break; 4741 } 4742 4743 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_getprop")); 4744 4745 return (err); 4746 } 4747 4748 /* ARGSUSED */ 4749 static int 4750 nxge_set_priv_prop(p_nxge_t nxgep, const char *pr_name, uint_t pr_valsize, 4751 const void *pr_val) 4752 { 4753 p_nxge_param_t param_arr = nxgep->param_arr; 4754 int err = 0; 4755 long result; 4756 4757 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4758 "==> nxge_set_priv_prop: name %s", pr_name)); 4759 4760 /* Blanking */ 4761 if (strcmp(pr_name, "_rxdma_intr_time") == 0) { 4762 err = nxge_param_rx_intr_time(nxgep, NULL, NULL, 4763 (char *)pr_val, 4764 (caddr_t)¶m_arr[param_rxdma_intr_time]); 4765 if (err) { 4766 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4767 "<== nxge_set_priv_prop: " 4768 "unable to set (%s)", pr_name)); 4769 err = EINVAL; 4770 } else { 4771 err = 0; 4772 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4773 "<== nxge_set_priv_prop: " 4774 "set (%s)", pr_name)); 4775 } 4776 4777 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4778 "<== nxge_set_priv_prop: name %s (value %d)", 4779 pr_name, result)); 4780 4781 return (err); 4782 } 4783 4784 if (strcmp(pr_name, "_rxdma_intr_pkts") == 0) { 4785 err = nxge_param_rx_intr_pkts(nxgep, NULL, NULL, 4786 (char *)pr_val, 4787 (caddr_t)¶m_arr[param_rxdma_intr_pkts]); 4788 if (err) { 4789 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4790 "<== nxge_set_priv_prop: " 4791 "unable to set (%s)", pr_name)); 4792 err = EINVAL; 4793 } else { 4794 err = 0; 4795 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4796 "<== nxge_set_priv_prop: " 4797 "set (%s)", pr_name)); 4798 } 4799 4800 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4801 "<== nxge_set_priv_prop: name %s (value %d)", 4802 pr_name, result)); 4803 4804 return (err); 4805 } 4806 4807 /* Classification */ 4808 if (strcmp(pr_name, "_class_opt_ipv4_tcp") == 0) { 4809 if (pr_val == NULL) { 4810 err = EINVAL; 4811 return (err); 4812 } 4813 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 4814 4815 err = nxge_param_set_ip_opt(nxgep, NULL, 4816 NULL, (char *)pr_val, 4817 (caddr_t)¶m_arr[param_class_opt_ipv4_tcp]); 4818 4819 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4820 "<== nxge_set_priv_prop: name %s (value 0x%x)", 4821 pr_name, result)); 4822 4823 return (err); 4824 } 4825 4826 if (strcmp(pr_name, "_class_opt_ipv4_udp") == 0) { 4827 if (pr_val == NULL) { 4828 err = EINVAL; 4829 return (err); 4830 } 4831 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 4832 4833 err = nxge_param_set_ip_opt(nxgep, NULL, 4834 NULL, (char *)pr_val, 4835 (caddr_t)¶m_arr[param_class_opt_ipv4_udp]); 4836 4837 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4838 "<== nxge_set_priv_prop: name %s (value 0x%x)", 4839 pr_name, result)); 4840 4841 return (err); 4842 } 4843 if (strcmp(pr_name, "_class_opt_ipv4_ah") == 0) { 4844 if (pr_val == NULL) { 4845 err = EINVAL; 4846 return (err); 4847 } 4848 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 4849 4850 err = nxge_param_set_ip_opt(nxgep, NULL, 4851 NULL, (char *)pr_val, 4852 (caddr_t)¶m_arr[param_class_opt_ipv4_ah]); 4853 4854 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4855 "<== nxge_set_priv_prop: name %s (value 0x%x)", 4856 pr_name, result)); 4857 4858 return (err); 4859 } 4860 if (strcmp(pr_name, "_class_opt_ipv4_sctp") == 0) { 4861 if (pr_val == NULL) { 4862 err = EINVAL; 4863 return (err); 4864 } 4865 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 4866 4867 err = nxge_param_set_ip_opt(nxgep, NULL, 4868 NULL, (char *)pr_val, 4869 (caddr_t)¶m_arr[param_class_opt_ipv4_sctp]); 4870 4871 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4872 "<== nxge_set_priv_prop: name %s (value 0x%x)", 4873 pr_name, result)); 4874 4875 return (err); 4876 } 4877 4878 if (strcmp(pr_name, "_class_opt_ipv6_tcp") == 0) { 4879 if (pr_val == NULL) { 4880 err = EINVAL; 4881 return (err); 4882 } 4883 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 4884 4885 err = nxge_param_set_ip_opt(nxgep, NULL, 4886 NULL, (char *)pr_val, 4887 (caddr_t)¶m_arr[param_class_opt_ipv6_tcp]); 4888 4889 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4890 "<== nxge_set_priv_prop: name %s (value 0x%x)", 4891 pr_name, result)); 4892 4893 return (err); 4894 } 4895 4896 if (strcmp(pr_name, "_class_opt_ipv6_udp") == 0) { 4897 if (pr_val == NULL) { 4898 err = EINVAL; 4899 return (err); 4900 } 4901 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 4902 4903 err = nxge_param_set_ip_opt(nxgep, NULL, 4904 NULL, (char *)pr_val, 4905 (caddr_t)¶m_arr[param_class_opt_ipv6_udp]); 4906 4907 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4908 "<== nxge_set_priv_prop: name %s (value 0x%x)", 4909 pr_name, result)); 4910 4911 return (err); 4912 } 4913 if (strcmp(pr_name, "_class_opt_ipv6_ah") == 0) { 4914 if (pr_val == NULL) { 4915 err = EINVAL; 4916 return (err); 4917 } 4918 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 4919 4920 err = nxge_param_set_ip_opt(nxgep, NULL, 4921 NULL, (char *)pr_val, 4922 (caddr_t)¶m_arr[param_class_opt_ipv6_ah]); 4923 4924 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4925 "<== nxge_set_priv_prop: name %s (value 0x%x)", 4926 pr_name, result)); 4927 4928 return (err); 4929 } 4930 if (strcmp(pr_name, "_class_opt_ipv6_sctp") == 0) { 4931 if (pr_val == NULL) { 4932 err = EINVAL; 4933 return (err); 4934 } 4935 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 4936 4937 err = nxge_param_set_ip_opt(nxgep, NULL, 4938 NULL, (char *)pr_val, 4939 (caddr_t)¶m_arr[param_class_opt_ipv6_sctp]); 4940 4941 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4942 "<== nxge_set_priv_prop: name %s (value 0x%x)", 4943 pr_name, result)); 4944 4945 return (err); 4946 } 4947 4948 if (strcmp(pr_name, "_soft_lso_enable") == 0) { 4949 if (pr_val == NULL) { 4950 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4951 "==> nxge_set_priv_prop: name %s (null)", pr_name)); 4952 err = EINVAL; 4953 return (err); 4954 } 4955 4956 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 4957 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4958 "<== nxge_set_priv_prop: name %s " 4959 "(lso %d pr_val %s value %d)", 4960 pr_name, nxgep->soft_lso_enable, pr_val, result)); 4961 4962 if (result > 1 || result < 0) { 4963 err = EINVAL; 4964 } else { 4965 if (nxgep->soft_lso_enable == (uint32_t)result) { 4966 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4967 "no change (%d %d)", 4968 nxgep->soft_lso_enable, result)); 4969 return (0); 4970 } 4971 } 4972 4973 nxgep->soft_lso_enable = (int)result; 4974 4975 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4976 "<== nxge_set_priv_prop: name %s (value %d)", 4977 pr_name, result)); 4978 4979 return (err); 4980 } 4981 /* 4982 * Commands like "ndd -set /dev/nxge0 adv_10gfdx_cap 1" cause the 4983 * following code to be executed. 4984 */ 4985 if (strcmp(pr_name, "_adv_10gfdx_cap") == 0) { 4986 err = nxge_param_set_mac(nxgep, NULL, NULL, (char *)pr_val, 4987 (caddr_t)¶m_arr[param_anar_10gfdx]); 4988 return (err); 4989 } 4990 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 4991 err = nxge_param_set_mac(nxgep, NULL, NULL, (char *)pr_val, 4992 (caddr_t)¶m_arr[param_anar_pause]); 4993 return (err); 4994 } 4995 4996 return (EINVAL); 4997 } 4998 4999 static int 5000 nxge_get_priv_prop(p_nxge_t nxgep, const char *pr_name, uint_t pr_flags, 5001 uint_t pr_valsize, void *pr_val, uint_t *perm) 5002 { 5003 p_nxge_param_t param_arr = nxgep->param_arr; 5004 char valstr[MAXNAMELEN]; 5005 int err = EINVAL; 5006 uint_t strsize; 5007 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 5008 5009 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5010 "==> nxge_get_priv_prop: property %s", pr_name)); 5011 5012 /* function number */ 5013 if (strcmp(pr_name, "_function_number") == 0) { 5014 if (is_default) 5015 return (ENOTSUP); 5016 *perm = MAC_PROP_PERM_READ; 5017 (void) snprintf(valstr, sizeof (valstr), "%d", 5018 nxgep->function_num); 5019 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5020 "==> nxge_get_priv_prop: name %s " 5021 "(value %d valstr %s)", 5022 pr_name, nxgep->function_num, valstr)); 5023 5024 err = 0; 5025 goto done; 5026 } 5027 5028 /* Neptune firmware version */ 5029 if (strcmp(pr_name, "_fw_version") == 0) { 5030 if (is_default) 5031 return (ENOTSUP); 5032 *perm = MAC_PROP_PERM_READ; 5033 (void) snprintf(valstr, sizeof (valstr), "%s", 5034 nxgep->vpd_info.ver); 5035 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5036 "==> nxge_get_priv_prop: name %s " 5037 "(value %d valstr %s)", 5038 pr_name, nxgep->vpd_info.ver, valstr)); 5039 5040 err = 0; 5041 goto done; 5042 } 5043 5044 /* port PHY mode */ 5045 if (strcmp(pr_name, "_port_mode") == 0) { 5046 if (is_default) 5047 return (ENOTSUP); 5048 *perm = MAC_PROP_PERM_READ; 5049 switch (nxgep->mac.portmode) { 5050 case PORT_1G_COPPER: 5051 (void) snprintf(valstr, sizeof (valstr), "1G copper %s", 5052 nxgep->hot_swappable_phy ? 5053 "[Hot Swappable]" : ""); 5054 break; 5055 case PORT_1G_FIBER: 5056 (void) snprintf(valstr, sizeof (valstr), "1G fiber %s", 5057 nxgep->hot_swappable_phy ? 5058 "[hot swappable]" : ""); 5059 break; 5060 case PORT_10G_COPPER: 5061 (void) snprintf(valstr, sizeof (valstr), 5062 "10G copper %s", 5063 nxgep->hot_swappable_phy ? 5064 "[hot swappable]" : ""); 5065 break; 5066 case PORT_10G_FIBER: 5067 (void) snprintf(valstr, sizeof (valstr), "10G fiber %s", 5068 nxgep->hot_swappable_phy ? 5069 "[hot swappable]" : ""); 5070 break; 5071 case PORT_10G_SERDES: 5072 (void) snprintf(valstr, sizeof (valstr), 5073 "10G serdes %s", nxgep->hot_swappable_phy ? 5074 "[hot swappable]" : ""); 5075 break; 5076 case PORT_1G_SERDES: 5077 (void) snprintf(valstr, sizeof (valstr), "1G serdes %s", 5078 nxgep->hot_swappable_phy ? 5079 "[hot swappable]" : ""); 5080 break; 5081 case PORT_1G_TN1010: 5082 (void) snprintf(valstr, sizeof (valstr), 5083 "1G TN1010 copper %s", nxgep->hot_swappable_phy ? 5084 "[hot swappable]" : ""); 5085 break; 5086 case PORT_10G_TN1010: 5087 (void) snprintf(valstr, sizeof (valstr), 5088 "10G TN1010 copper %s", nxgep->hot_swappable_phy ? 5089 "[hot swappable]" : ""); 5090 break; 5091 case PORT_1G_RGMII_FIBER: 5092 (void) snprintf(valstr, sizeof (valstr), 5093 "1G rgmii fiber %s", nxgep->hot_swappable_phy ? 5094 "[hot swappable]" : ""); 5095 break; 5096 case PORT_HSP_MODE: 5097 (void) snprintf(valstr, sizeof (valstr), 5098 "phy not present[hot swappable]"); 5099 break; 5100 default: 5101 (void) snprintf(valstr, sizeof (valstr), "unknown %s", 5102 nxgep->hot_swappable_phy ? 5103 "[hot swappable]" : ""); 5104 break; 5105 } 5106 5107 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5108 "==> nxge_get_priv_prop: name %s (value %s)", 5109 pr_name, valstr)); 5110 5111 err = 0; 5112 goto done; 5113 } 5114 5115 /* Hot swappable PHY */ 5116 if (strcmp(pr_name, "_hot_swap_phy") == 0) { 5117 if (is_default) 5118 return (ENOTSUP); 5119 *perm = MAC_PROP_PERM_READ; 5120 (void) snprintf(valstr, sizeof (valstr), "%s", 5121 nxgep->hot_swappable_phy ? 5122 "yes" : "no"); 5123 5124 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5125 "==> nxge_get_priv_prop: name %s " 5126 "(value %d valstr %s)", 5127 pr_name, nxgep->hot_swappable_phy, valstr)); 5128 5129 err = 0; 5130 goto done; 5131 } 5132 5133 5134 /* Receive Interrupt Blanking Parameters */ 5135 if (strcmp(pr_name, "_rxdma_intr_time") == 0) { 5136 err = 0; 5137 if (is_default) { 5138 (void) snprintf(valstr, sizeof (valstr), 5139 "%d", RXDMA_RCR_TO_DEFAULT); 5140 goto done; 5141 } 5142 5143 (void) snprintf(valstr, sizeof (valstr), "%d", 5144 nxgep->intr_timeout); 5145 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5146 "==> nxge_get_priv_prop: name %s (value %d)", 5147 pr_name, 5148 (uint32_t)nxgep->intr_timeout)); 5149 goto done; 5150 } 5151 5152 if (strcmp(pr_name, "_rxdma_intr_pkts") == 0) { 5153 err = 0; 5154 if (is_default) { 5155 (void) snprintf(valstr, sizeof (valstr), 5156 "%d", RXDMA_RCR_PTHRES_DEFAULT); 5157 goto done; 5158 } 5159 (void) snprintf(valstr, sizeof (valstr), "%d", 5160 nxgep->intr_threshold); 5161 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5162 "==> nxge_get_priv_prop: name %s (value %d)", 5163 pr_name, (uint32_t)nxgep->intr_threshold)); 5164 5165 goto done; 5166 } 5167 5168 /* Classification and Load Distribution Configuration */ 5169 if (strcmp(pr_name, "_class_opt_ipv4_tcp") == 0) { 5170 if (is_default) { 5171 (void) snprintf(valstr, sizeof (valstr), "%x", 5172 NXGE_CLASS_FLOW_GEN_SERVER); 5173 err = 0; 5174 goto done; 5175 } 5176 err = nxge_dld_get_ip_opt(nxgep, 5177 (caddr_t)¶m_arr[param_class_opt_ipv4_tcp]); 5178 5179 (void) snprintf(valstr, sizeof (valstr), "%x", 5180 (int)param_arr[param_class_opt_ipv4_tcp].value); 5181 5182 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5183 "==> nxge_get_priv_prop: %s", valstr)); 5184 goto done; 5185 } 5186 5187 if (strcmp(pr_name, "_class_opt_ipv4_udp") == 0) { 5188 if (is_default) { 5189 (void) snprintf(valstr, sizeof (valstr), "%x", 5190 NXGE_CLASS_FLOW_GEN_SERVER); 5191 err = 0; 5192 goto done; 5193 } 5194 err = nxge_dld_get_ip_opt(nxgep, 5195 (caddr_t)¶m_arr[param_class_opt_ipv4_udp]); 5196 5197 (void) snprintf(valstr, sizeof (valstr), "%x", 5198 (int)param_arr[param_class_opt_ipv4_udp].value); 5199 5200 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5201 "==> nxge_get_priv_prop: %s", valstr)); 5202 goto done; 5203 } 5204 if (strcmp(pr_name, "_class_opt_ipv4_ah") == 0) { 5205 if (is_default) { 5206 (void) snprintf(valstr, sizeof (valstr), "%x", 5207 NXGE_CLASS_FLOW_GEN_SERVER); 5208 err = 0; 5209 goto done; 5210 } 5211 err = nxge_dld_get_ip_opt(nxgep, 5212 (caddr_t)¶m_arr[param_class_opt_ipv4_ah]); 5213 5214 (void) snprintf(valstr, sizeof (valstr), "%x", 5215 (int)param_arr[param_class_opt_ipv4_ah].value); 5216 5217 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5218 "==> nxge_get_priv_prop: %s", valstr)); 5219 goto done; 5220 } 5221 5222 if (strcmp(pr_name, "_class_opt_ipv4_sctp") == 0) { 5223 if (is_default) { 5224 (void) snprintf(valstr, sizeof (valstr), "%x", 5225 NXGE_CLASS_FLOW_GEN_SERVER); 5226 err = 0; 5227 goto done; 5228 } 5229 err = nxge_dld_get_ip_opt(nxgep, 5230 (caddr_t)¶m_arr[param_class_opt_ipv4_sctp]); 5231 5232 (void) snprintf(valstr, sizeof (valstr), "%x", 5233 (int)param_arr[param_class_opt_ipv4_sctp].value); 5234 5235 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5236 "==> nxge_get_priv_prop: %s", valstr)); 5237 goto done; 5238 } 5239 5240 if (strcmp(pr_name, "_class_opt_ipv6_tcp") == 0) { 5241 if (is_default) { 5242 (void) snprintf(valstr, sizeof (valstr), "%x", 5243 NXGE_CLASS_FLOW_GEN_SERVER); 5244 err = 0; 5245 goto done; 5246 } 5247 err = nxge_dld_get_ip_opt(nxgep, 5248 (caddr_t)¶m_arr[param_class_opt_ipv6_tcp]); 5249 5250 (void) snprintf(valstr, sizeof (valstr), "%x", 5251 (int)param_arr[param_class_opt_ipv6_tcp].value); 5252 5253 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5254 "==> nxge_get_priv_prop: %s", valstr)); 5255 goto done; 5256 } 5257 5258 if (strcmp(pr_name, "_class_opt_ipv6_udp") == 0) { 5259 if (is_default) { 5260 (void) snprintf(valstr, sizeof (valstr), "%x", 5261 NXGE_CLASS_FLOW_GEN_SERVER); 5262 err = 0; 5263 goto done; 5264 } 5265 err = nxge_dld_get_ip_opt(nxgep, 5266 (caddr_t)¶m_arr[param_class_opt_ipv6_udp]); 5267 5268 (void) snprintf(valstr, sizeof (valstr), "%x", 5269 (int)param_arr[param_class_opt_ipv6_udp].value); 5270 5271 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5272 "==> nxge_get_priv_prop: %s", valstr)); 5273 goto done; 5274 } 5275 5276 if (strcmp(pr_name, "_class_opt_ipv6_ah") == 0) { 5277 if (is_default) { 5278 (void) snprintf(valstr, sizeof (valstr), "%x", 5279 NXGE_CLASS_FLOW_GEN_SERVER); 5280 err = 0; 5281 goto done; 5282 } 5283 err = nxge_dld_get_ip_opt(nxgep, 5284 (caddr_t)¶m_arr[param_class_opt_ipv6_ah]); 5285 5286 (void) snprintf(valstr, sizeof (valstr), "%x", 5287 (int)param_arr[param_class_opt_ipv6_ah].value); 5288 5289 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5290 "==> nxge_get_priv_prop: %s", valstr)); 5291 goto done; 5292 } 5293 5294 if (strcmp(pr_name, "_class_opt_ipv6_sctp") == 0) { 5295 if (is_default) { 5296 (void) snprintf(valstr, sizeof (valstr), "%x", 5297 NXGE_CLASS_FLOW_GEN_SERVER); 5298 err = 0; 5299 goto done; 5300 } 5301 err = nxge_dld_get_ip_opt(nxgep, 5302 (caddr_t)¶m_arr[param_class_opt_ipv6_sctp]); 5303 5304 (void) snprintf(valstr, sizeof (valstr), "%x", 5305 (int)param_arr[param_class_opt_ipv6_sctp].value); 5306 5307 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5308 "==> nxge_get_priv_prop: %s", valstr)); 5309 goto done; 5310 } 5311 5312 /* Software LSO */ 5313 if (strcmp(pr_name, "_soft_lso_enable") == 0) { 5314 if (is_default) { 5315 (void) snprintf(valstr, sizeof (valstr), "%d", 0); 5316 err = 0; 5317 goto done; 5318 } 5319 (void) snprintf(valstr, sizeof (valstr), 5320 "%d", nxgep->soft_lso_enable); 5321 err = 0; 5322 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5323 "==> nxge_get_priv_prop: name %s (value %d)", 5324 pr_name, nxgep->soft_lso_enable)); 5325 5326 goto done; 5327 } 5328 if (strcmp(pr_name, "_adv_10gfdx_cap") == 0) { 5329 err = 0; 5330 if (is_default || 5331 nxgep->param_arr[param_anar_10gfdx].value != 0) { 5332 (void) snprintf(valstr, sizeof (valstr), "%d", 1); 5333 goto done; 5334 } else { 5335 (void) snprintf(valstr, sizeof (valstr), "%d", 0); 5336 goto done; 5337 } 5338 } 5339 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 5340 err = 0; 5341 if (is_default || 5342 nxgep->param_arr[param_anar_pause].value != 0) { 5343 (void) snprintf(valstr, sizeof (valstr), "%d", 1); 5344 goto done; 5345 } else { 5346 (void) snprintf(valstr, sizeof (valstr), "%d", 0); 5347 goto done; 5348 } 5349 } 5350 5351 done: 5352 if (err == 0) { 5353 strsize = (uint_t)strlen(valstr); 5354 if (pr_valsize < strsize) { 5355 err = ENOBUFS; 5356 } else { 5357 (void) strlcpy(pr_val, valstr, pr_valsize); 5358 } 5359 } 5360 5361 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5362 "<== nxge_get_priv_prop: return %d", err)); 5363 return (err); 5364 } 5365 5366 /* 5367 * Module loading and removing entry points. 5368 */ 5369 5370 DDI_DEFINE_STREAM_OPS(nxge_dev_ops, nulldev, nulldev, nxge_attach, nxge_detach, 5371 nodev, NULL, D_MP, NULL, nxge_quiesce); 5372 5373 #define NXGE_DESC_VER "Sun NIU 10Gb Ethernet" 5374 5375 /* 5376 * Module linkage information for the kernel. 5377 */ 5378 static struct modldrv nxge_modldrv = { 5379 &mod_driverops, 5380 NXGE_DESC_VER, 5381 &nxge_dev_ops 5382 }; 5383 5384 static struct modlinkage modlinkage = { 5385 MODREV_1, (void *) &nxge_modldrv, NULL 5386 }; 5387 5388 int 5389 _init(void) 5390 { 5391 int status; 5392 5393 NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _init")); 5394 mac_init_ops(&nxge_dev_ops, "nxge"); 5395 status = ddi_soft_state_init(&nxge_list, sizeof (nxge_t), 0); 5396 if (status != 0) { 5397 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 5398 "failed to init device soft state")); 5399 goto _init_exit; 5400 } 5401 status = mod_install(&modlinkage); 5402 if (status != 0) { 5403 ddi_soft_state_fini(&nxge_list); 5404 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, "Mod install failed")); 5405 goto _init_exit; 5406 } 5407 5408 MUTEX_INIT(&nxge_common_lock, NULL, MUTEX_DRIVER, NULL); 5409 5410 _init_exit: 5411 NXGE_DEBUG_MSG((NULL, MOD_CTL, "_init status = 0x%X", status)); 5412 5413 return (status); 5414 } 5415 5416 int 5417 _fini(void) 5418 { 5419 int status; 5420 5421 NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _fini")); 5422 5423 NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _fini: mod_remove")); 5424 5425 if (nxge_mblks_pending) 5426 return (EBUSY); 5427 5428 status = mod_remove(&modlinkage); 5429 if (status != DDI_SUCCESS) { 5430 NXGE_DEBUG_MSG((NULL, MOD_CTL, 5431 "Module removal failed 0x%08x", 5432 status)); 5433 goto _fini_exit; 5434 } 5435 5436 mac_fini_ops(&nxge_dev_ops); 5437 5438 ddi_soft_state_fini(&nxge_list); 5439 5440 MUTEX_DESTROY(&nxge_common_lock); 5441 _fini_exit: 5442 NXGE_DEBUG_MSG((NULL, MOD_CTL, "_fini status = 0x%08x", status)); 5443 5444 return (status); 5445 } 5446 5447 int 5448 _info(struct modinfo *modinfop) 5449 { 5450 int status; 5451 5452 NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _info")); 5453 status = mod_info(&modlinkage, modinfop); 5454 NXGE_DEBUG_MSG((NULL, MOD_CTL, " _info status = 0x%X", status)); 5455 5456 return (status); 5457 } 5458 5459 /*ARGSUSED*/ 5460 static int 5461 nxge_tx_ring_start(mac_ring_driver_t rdriver, uint64_t mr_gen_num) 5462 { 5463 p_nxge_ring_handle_t rhp = (p_nxge_ring_handle_t)rdriver; 5464 p_nxge_t nxgep = rhp->nxgep; 5465 uint32_t channel; 5466 p_tx_ring_t ring; 5467 5468 channel = nxgep->pt_config.hw_config.tdc.start + rhp->index; 5469 ring = nxgep->tx_rings->rings[channel]; 5470 5471 MUTEX_ENTER(&ring->lock); 5472 ring->tx_ring_handle = rhp->ring_handle; 5473 MUTEX_EXIT(&ring->lock); 5474 5475 return (0); 5476 } 5477 5478 static void 5479 nxge_tx_ring_stop(mac_ring_driver_t rdriver) 5480 { 5481 p_nxge_ring_handle_t rhp = (p_nxge_ring_handle_t)rdriver; 5482 p_nxge_t nxgep = rhp->nxgep; 5483 uint32_t channel; 5484 p_tx_ring_t ring; 5485 5486 channel = nxgep->pt_config.hw_config.tdc.start + rhp->index; 5487 ring = nxgep->tx_rings->rings[channel]; 5488 5489 MUTEX_ENTER(&ring->lock); 5490 ring->tx_ring_handle = (mac_ring_handle_t)NULL; 5491 MUTEX_EXIT(&ring->lock); 5492 } 5493 5494 static int 5495 nxge_rx_ring_start(mac_ring_driver_t rdriver, uint64_t mr_gen_num) 5496 { 5497 p_nxge_ring_handle_t rhp = (p_nxge_ring_handle_t)rdriver; 5498 p_nxge_t nxgep = rhp->nxgep; 5499 uint32_t channel; 5500 p_rx_rcr_ring_t ring; 5501 int i; 5502 5503 channel = nxgep->pt_config.hw_config.start_rdc + rhp->index; 5504 ring = nxgep->rx_rcr_rings->rcr_rings[channel]; 5505 5506 MUTEX_ENTER(&ring->lock); 5507 5508 if (nxgep->rx_channel_started[channel] == B_TRUE) { 5509 MUTEX_EXIT(&ring->lock); 5510 return (0); 5511 } 5512 5513 /* set rcr_ring */ 5514 for (i = 0; i < nxgep->ldgvp->maxldvs; i++) { 5515 if ((nxgep->ldgvp->ldvp[i].is_rxdma == 1) && 5516 (nxgep->ldgvp->ldvp[i].channel == channel)) { 5517 ring->ldvp = &nxgep->ldgvp->ldvp[i]; 5518 ring->ldgp = nxgep->ldgvp->ldvp[i].ldgp; 5519 } 5520 } 5521 5522 nxgep->rx_channel_started[channel] = B_TRUE; 5523 ring->rcr_mac_handle = rhp->ring_handle; 5524 ring->rcr_gen_num = mr_gen_num; 5525 MUTEX_EXIT(&ring->lock); 5526 5527 return (0); 5528 } 5529 5530 static void 5531 nxge_rx_ring_stop(mac_ring_driver_t rdriver) 5532 { 5533 p_nxge_ring_handle_t rhp = (p_nxge_ring_handle_t)rdriver; 5534 p_nxge_t nxgep = rhp->nxgep; 5535 uint32_t channel; 5536 p_rx_rcr_ring_t ring; 5537 5538 channel = nxgep->pt_config.hw_config.start_rdc + rhp->index; 5539 ring = nxgep->rx_rcr_rings->rcr_rings[channel]; 5540 5541 MUTEX_ENTER(&ring->lock); 5542 nxgep->rx_channel_started[channel] = B_FALSE; 5543 ring->rcr_mac_handle = NULL; 5544 MUTEX_EXIT(&ring->lock); 5545 } 5546 5547 /* 5548 * Callback funtion for MAC layer to register all rings. 5549 */ 5550 static void 5551 nxge_fill_ring(void *arg, mac_ring_type_t rtype, const int rg_index, 5552 const int index, mac_ring_info_t *infop, mac_ring_handle_t rh) 5553 { 5554 p_nxge_t nxgep = (p_nxge_t)arg; 5555 p_nxge_hw_pt_cfg_t p_cfgp = &nxgep->pt_config.hw_config; 5556 5557 NXGE_DEBUG_MSG((nxgep, TX_CTL, 5558 "==> nxge_fill_ring 0x%x index %d", rtype, index)); 5559 5560 switch (rtype) { 5561 case MAC_RING_TYPE_TX: { 5562 p_nxge_ring_handle_t rhandlep; 5563 5564 NXGE_DEBUG_MSG((nxgep, TX_CTL, 5565 "==> nxge_fill_ring (TX) 0x%x index %d ntdcs %d", 5566 rtype, index, p_cfgp->tdc.count)); 5567 5568 ASSERT((index >= 0) && (index < p_cfgp->tdc.count)); 5569 rhandlep = &nxgep->tx_ring_handles[index]; 5570 rhandlep->nxgep = nxgep; 5571 rhandlep->index = index; 5572 rhandlep->ring_handle = rh; 5573 5574 infop->mri_driver = (mac_ring_driver_t)rhandlep; 5575 infop->mri_start = nxge_tx_ring_start; 5576 infop->mri_stop = nxge_tx_ring_stop; 5577 infop->mri_tx = nxge_tx_ring_send; 5578 5579 break; 5580 } 5581 case MAC_RING_TYPE_RX: { 5582 p_nxge_ring_handle_t rhandlep; 5583 int nxge_rindex; 5584 mac_intr_t nxge_mac_intr; 5585 5586 NXGE_DEBUG_MSG((nxgep, RX_CTL, 5587 "==> nxge_fill_ring (RX) 0x%x index %d nrdcs %d", 5588 rtype, index, p_cfgp->max_rdcs)); 5589 5590 /* 5591 * 'index' is the ring index within the group. 5592 * Find the ring index in the nxge instance. 5593 */ 5594 nxge_rindex = nxge_get_rxring_index(nxgep, rg_index, index); 5595 5596 ASSERT((nxge_rindex >= 0) && (nxge_rindex < p_cfgp->max_rdcs)); 5597 rhandlep = &nxgep->rx_ring_handles[nxge_rindex]; 5598 rhandlep->nxgep = nxgep; 5599 rhandlep->index = nxge_rindex; 5600 rhandlep->ring_handle = rh; 5601 5602 /* 5603 * Entrypoint to enable interrupt (disable poll) and 5604 * disable interrupt (enable poll). 5605 */ 5606 nxge_mac_intr.mi_handle = (mac_intr_handle_t)rhandlep; 5607 nxge_mac_intr.mi_enable = (mac_intr_enable_t)nxge_disable_poll; 5608 nxge_mac_intr.mi_disable = (mac_intr_disable_t)nxge_enable_poll; 5609 infop->mri_driver = (mac_ring_driver_t)rhandlep; 5610 infop->mri_start = nxge_rx_ring_start; 5611 infop->mri_stop = nxge_rx_ring_stop; 5612 infop->mri_intr = nxge_mac_intr; /* ??? */ 5613 infop->mri_poll = nxge_rx_poll; 5614 5615 break; 5616 } 5617 default: 5618 break; 5619 } 5620 5621 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_fill_ring 0x%x", 5622 rtype)); 5623 } 5624 5625 static void 5626 nxge_group_add_ring(mac_group_driver_t gh, mac_ring_driver_t rh, 5627 mac_ring_type_t type) 5628 { 5629 nxge_ring_group_t *rgroup = (nxge_ring_group_t *)gh; 5630 nxge_ring_handle_t *rhandle = (nxge_ring_handle_t *)rh; 5631 nxge_t *nxge; 5632 nxge_grp_t *grp; 5633 nxge_rdc_grp_t *rdc_grp; 5634 uint16_t channel; /* device-wise ring id */ 5635 int dev_gindex; 5636 int rv; 5637 5638 nxge = rgroup->nxgep; 5639 5640 switch (type) { 5641 case MAC_RING_TYPE_TX: 5642 /* 5643 * nxge_grp_dc_add takes a channel number which is a 5644 * "devise" ring ID. 5645 */ 5646 channel = nxge->pt_config.hw_config.tdc.start + rhandle->index; 5647 5648 /* 5649 * Remove the ring from the default group 5650 */ 5651 if (rgroup->gindex != 0) { 5652 (void) nxge_grp_dc_remove(nxge, VP_BOUND_TX, channel); 5653 } 5654 5655 /* 5656 * nxge->tx_set.group[] is an array of groups indexed by 5657 * a "port" group ID. 5658 */ 5659 grp = nxge->tx_set.group[rgroup->gindex]; 5660 rv = nxge_grp_dc_add(nxge, grp, VP_BOUND_TX, channel); 5661 if (rv != 0) { 5662 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, 5663 "nxge_group_add_ring: nxge_grp_dc_add failed")); 5664 } 5665 break; 5666 5667 case MAC_RING_TYPE_RX: 5668 /* 5669 * nxge->rx_set.group[] is an array of groups indexed by 5670 * a "port" group ID. 5671 */ 5672 grp = nxge->rx_set.group[rgroup->gindex]; 5673 5674 dev_gindex = nxge->pt_config.hw_config.def_mac_rxdma_grpid + 5675 rgroup->gindex; 5676 rdc_grp = &nxge->pt_config.rdc_grps[dev_gindex]; 5677 5678 /* 5679 * nxge_grp_dc_add takes a channel number which is a 5680 * "devise" ring ID. 5681 */ 5682 channel = nxge->pt_config.hw_config.start_rdc + rhandle->index; 5683 rv = nxge_grp_dc_add(nxge, grp, VP_BOUND_RX, channel); 5684 if (rv != 0) { 5685 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, 5686 "nxge_group_add_ring: nxge_grp_dc_add failed")); 5687 } 5688 5689 rdc_grp->map |= (1 << channel); 5690 rdc_grp->max_rdcs++; 5691 5692 (void) nxge_init_fzc_rdc_tbl(nxge, rdc_grp, rgroup->rdctbl); 5693 break; 5694 } 5695 } 5696 5697 static void 5698 nxge_group_rem_ring(mac_group_driver_t gh, mac_ring_driver_t rh, 5699 mac_ring_type_t type) 5700 { 5701 nxge_ring_group_t *rgroup = (nxge_ring_group_t *)gh; 5702 nxge_ring_handle_t *rhandle = (nxge_ring_handle_t *)rh; 5703 nxge_t *nxge; 5704 uint16_t channel; /* device-wise ring id */ 5705 nxge_rdc_grp_t *rdc_grp; 5706 int dev_gindex; 5707 5708 nxge = rgroup->nxgep; 5709 5710 switch (type) { 5711 case MAC_RING_TYPE_TX: 5712 dev_gindex = nxge->pt_config.hw_config.def_mac_txdma_grpid + 5713 rgroup->gindex; 5714 channel = nxge->pt_config.hw_config.tdc.start + rhandle->index; 5715 nxge_grp_dc_remove(nxge, VP_BOUND_TX, channel); 5716 5717 /* 5718 * Add the ring back to the default group 5719 */ 5720 if (rgroup->gindex != 0) { 5721 nxge_grp_t *grp; 5722 grp = nxge->tx_set.group[0]; 5723 (void) nxge_grp_dc_add(nxge, grp, VP_BOUND_TX, channel); 5724 } 5725 break; 5726 5727 case MAC_RING_TYPE_RX: 5728 dev_gindex = nxge->pt_config.hw_config.def_mac_rxdma_grpid + 5729 rgroup->gindex; 5730 rdc_grp = &nxge->pt_config.rdc_grps[dev_gindex]; 5731 channel = rdc_grp->start_rdc + rhandle->index; 5732 nxge_grp_dc_remove(nxge, VP_BOUND_RX, channel); 5733 5734 rdc_grp->map &= ~(1 << channel); 5735 rdc_grp->max_rdcs--; 5736 5737 (void) nxge_init_fzc_rdc_tbl(nxge, rdc_grp, rgroup->rdctbl); 5738 break; 5739 } 5740 } 5741 5742 5743 /*ARGSUSED*/ 5744 static nxge_status_t 5745 nxge_add_intrs(p_nxge_t nxgep) 5746 { 5747 5748 int intr_types; 5749 int type = 0; 5750 int ddi_status = DDI_SUCCESS; 5751 nxge_status_t status = NXGE_OK; 5752 5753 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs")); 5754 5755 nxgep->nxge_intr_type.intr_registered = B_FALSE; 5756 nxgep->nxge_intr_type.intr_enabled = B_FALSE; 5757 nxgep->nxge_intr_type.msi_intx_cnt = 0; 5758 nxgep->nxge_intr_type.intr_added = 0; 5759 nxgep->nxge_intr_type.niu_msi_enable = B_FALSE; 5760 nxgep->nxge_intr_type.intr_type = 0; 5761 5762 if (nxgep->niu_type == N2_NIU) { 5763 nxgep->nxge_intr_type.niu_msi_enable = B_TRUE; 5764 } else if (nxge_msi_enable) { 5765 nxgep->nxge_intr_type.niu_msi_enable = B_TRUE; 5766 } 5767 5768 /* Get the supported interrupt types */ 5769 if ((ddi_status = ddi_intr_get_supported_types(nxgep->dip, &intr_types)) 5770 != DDI_SUCCESS) { 5771 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_add_intrs: " 5772 "ddi_intr_get_supported_types failed: status 0x%08x", 5773 ddi_status)); 5774 return (NXGE_ERROR | NXGE_DDI_FAILED); 5775 } 5776 nxgep->nxge_intr_type.intr_types = intr_types; 5777 5778 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 5779 "ddi_intr_get_supported_types: 0x%08x", intr_types)); 5780 5781 /* 5782 * Solaris MSIX is not supported yet. use MSI for now. 5783 * nxge_msi_enable (1): 5784 * 1 - MSI 2 - MSI-X others - FIXED 5785 */ 5786 switch (nxge_msi_enable) { 5787 default: 5788 type = DDI_INTR_TYPE_FIXED; 5789 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 5790 "use fixed (intx emulation) type %08x", 5791 type)); 5792 break; 5793 5794 case 2: 5795 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 5796 "ddi_intr_get_supported_types: 0x%08x", intr_types)); 5797 if (intr_types & DDI_INTR_TYPE_MSIX) { 5798 type = DDI_INTR_TYPE_MSIX; 5799 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 5800 "ddi_intr_get_supported_types: MSIX 0x%08x", 5801 type)); 5802 } else if (intr_types & DDI_INTR_TYPE_MSI) { 5803 type = DDI_INTR_TYPE_MSI; 5804 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 5805 "ddi_intr_get_supported_types: MSI 0x%08x", 5806 type)); 5807 } else if (intr_types & DDI_INTR_TYPE_FIXED) { 5808 type = DDI_INTR_TYPE_FIXED; 5809 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 5810 "ddi_intr_get_supported_types: MSXED0x%08x", 5811 type)); 5812 } 5813 break; 5814 5815 case 1: 5816 if (intr_types & DDI_INTR_TYPE_MSI) { 5817 type = DDI_INTR_TYPE_MSI; 5818 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 5819 "ddi_intr_get_supported_types: MSI 0x%08x", 5820 type)); 5821 } else if (intr_types & DDI_INTR_TYPE_MSIX) { 5822 type = DDI_INTR_TYPE_MSIX; 5823 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 5824 "ddi_intr_get_supported_types: MSIX 0x%08x", 5825 type)); 5826 } else if (intr_types & DDI_INTR_TYPE_FIXED) { 5827 type = DDI_INTR_TYPE_FIXED; 5828 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 5829 "ddi_intr_get_supported_types: MSXED0x%08x", 5830 type)); 5831 } 5832 } 5833 5834 nxgep->nxge_intr_type.intr_type = type; 5835 if ((type == DDI_INTR_TYPE_MSIX || type == DDI_INTR_TYPE_MSI || 5836 type == DDI_INTR_TYPE_FIXED) && 5837 nxgep->nxge_intr_type.niu_msi_enable) { 5838 if ((status = nxge_add_intrs_adv(nxgep)) != DDI_SUCCESS) { 5839 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5840 " nxge_add_intrs: " 5841 " nxge_add_intrs_adv failed: status 0x%08x", 5842 status)); 5843 return (status); 5844 } else { 5845 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 5846 "interrupts registered : type %d", type)); 5847 nxgep->nxge_intr_type.intr_registered = B_TRUE; 5848 5849 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 5850 "\nAdded advanced nxge add_intr_adv " 5851 "intr type 0x%x\n", type)); 5852 5853 return (status); 5854 } 5855 } 5856 5857 if (!nxgep->nxge_intr_type.intr_registered) { 5858 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "==> nxge_add_intrs: " 5859 "failed to register interrupts")); 5860 return (NXGE_ERROR | NXGE_DDI_FAILED); 5861 } 5862 5863 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_add_intrs")); 5864 return (status); 5865 } 5866 5867 static nxge_status_t 5868 nxge_add_intrs_adv(p_nxge_t nxgep) 5869 { 5870 int intr_type; 5871 p_nxge_intr_t intrp; 5872 5873 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs_adv")); 5874 5875 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 5876 intr_type = intrp->intr_type; 5877 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs_adv: type 0x%x", 5878 intr_type)); 5879 5880 switch (intr_type) { 5881 case DDI_INTR_TYPE_MSI: /* 0x2 */ 5882 case DDI_INTR_TYPE_MSIX: /* 0x4 */ 5883 return (nxge_add_intrs_adv_type(nxgep, intr_type)); 5884 5885 case DDI_INTR_TYPE_FIXED: /* 0x1 */ 5886 return (nxge_add_intrs_adv_type_fix(nxgep, intr_type)); 5887 5888 default: 5889 return (NXGE_ERROR); 5890 } 5891 } 5892 5893 5894 /*ARGSUSED*/ 5895 static nxge_status_t 5896 nxge_add_intrs_adv_type(p_nxge_t nxgep, uint32_t int_type) 5897 { 5898 dev_info_t *dip = nxgep->dip; 5899 p_nxge_ldg_t ldgp; 5900 p_nxge_intr_t intrp; 5901 uint_t *inthandler; 5902 void *arg1, *arg2; 5903 int behavior; 5904 int nintrs, navail, nrequest; 5905 int nactual, nrequired; 5906 int inum = 0; 5907 int x, y; 5908 int ddi_status = DDI_SUCCESS; 5909 nxge_status_t status = NXGE_OK; 5910 5911 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs_adv_type")); 5912 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 5913 intrp->start_inum = 0; 5914 5915 ddi_status = ddi_intr_get_nintrs(dip, int_type, &nintrs); 5916 if ((ddi_status != DDI_SUCCESS) || (nintrs == 0)) { 5917 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5918 "ddi_intr_get_nintrs() failed, status: 0x%x%, " 5919 "nintrs: %d", ddi_status, nintrs)); 5920 return (NXGE_ERROR | NXGE_DDI_FAILED); 5921 } 5922 5923 ddi_status = ddi_intr_get_navail(dip, int_type, &navail); 5924 if ((ddi_status != DDI_SUCCESS) || (navail == 0)) { 5925 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5926 "ddi_intr_get_navail() failed, status: 0x%x%, " 5927 "nintrs: %d", ddi_status, navail)); 5928 return (NXGE_ERROR | NXGE_DDI_FAILED); 5929 } 5930 5931 NXGE_DEBUG_MSG((nxgep, INT_CTL, 5932 "ddi_intr_get_navail() returned: nintrs %d, navail %d", 5933 nintrs, navail)); 5934 5935 /* PSARC/2007/453 MSI-X interrupt limit override */ 5936 if (int_type == DDI_INTR_TYPE_MSIX) { 5937 nrequest = nxge_create_msi_property(nxgep); 5938 if (nrequest < navail) { 5939 navail = nrequest; 5940 NXGE_DEBUG_MSG((nxgep, INT_CTL, 5941 "nxge_add_intrs_adv_type: nintrs %d " 5942 "navail %d (nrequest %d)", 5943 nintrs, navail, nrequest)); 5944 } 5945 } 5946 5947 if (int_type == DDI_INTR_TYPE_MSI && !ISP2(navail)) { 5948 /* MSI must be power of 2 */ 5949 if ((navail & 16) == 16) { 5950 navail = 16; 5951 } else if ((navail & 8) == 8) { 5952 navail = 8; 5953 } else if ((navail & 4) == 4) { 5954 navail = 4; 5955 } else if ((navail & 2) == 2) { 5956 navail = 2; 5957 } else { 5958 navail = 1; 5959 } 5960 NXGE_DEBUG_MSG((nxgep, INT_CTL, 5961 "ddi_intr_get_navail(): (msi power of 2) nintrs %d, " 5962 "navail %d", nintrs, navail)); 5963 } 5964 5965 behavior = ((int_type == DDI_INTR_TYPE_FIXED) ? DDI_INTR_ALLOC_STRICT : 5966 DDI_INTR_ALLOC_NORMAL); 5967 intrp->intr_size = navail * sizeof (ddi_intr_handle_t); 5968 intrp->htable = kmem_alloc(intrp->intr_size, KM_SLEEP); 5969 ddi_status = ddi_intr_alloc(dip, intrp->htable, int_type, inum, 5970 navail, &nactual, behavior); 5971 if (ddi_status != DDI_SUCCESS || nactual == 0) { 5972 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5973 " ddi_intr_alloc() failed: %d", 5974 ddi_status)); 5975 kmem_free(intrp->htable, intrp->intr_size); 5976 return (NXGE_ERROR | NXGE_DDI_FAILED); 5977 } 5978 5979 if ((ddi_status = ddi_intr_get_pri(intrp->htable[0], 5980 (uint_t *)&intrp->pri)) != DDI_SUCCESS) { 5981 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5982 " ddi_intr_get_pri() failed: %d", 5983 ddi_status)); 5984 /* Free already allocated interrupts */ 5985 for (y = 0; y < nactual; y++) { 5986 (void) ddi_intr_free(intrp->htable[y]); 5987 } 5988 5989 kmem_free(intrp->htable, intrp->intr_size); 5990 return (NXGE_ERROR | NXGE_DDI_FAILED); 5991 } 5992 5993 nrequired = 0; 5994 switch (nxgep->niu_type) { 5995 default: 5996 status = nxge_ldgv_init(nxgep, &nactual, &nrequired); 5997 break; 5998 5999 case N2_NIU: 6000 status = nxge_ldgv_init_n2(nxgep, &nactual, &nrequired); 6001 break; 6002 } 6003 6004 if (status != NXGE_OK) { 6005 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6006 "nxge_add_intrs_adv_typ:nxge_ldgv_init " 6007 "failed: 0x%x", status)); 6008 /* Free already allocated interrupts */ 6009 for (y = 0; y < nactual; y++) { 6010 (void) ddi_intr_free(intrp->htable[y]); 6011 } 6012 6013 kmem_free(intrp->htable, intrp->intr_size); 6014 return (status); 6015 } 6016 6017 ldgp = nxgep->ldgvp->ldgp; 6018 for (x = 0; x < nrequired; x++, ldgp++) { 6019 ldgp->vector = (uint8_t)x; 6020 ldgp->intdata = SID_DATA(ldgp->func, x); 6021 arg1 = ldgp->ldvp; 6022 arg2 = nxgep; 6023 if (ldgp->nldvs == 1) { 6024 inthandler = (uint_t *)ldgp->ldvp->ldv_intr_handler; 6025 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6026 "nxge_add_intrs_adv_type: " 6027 "arg1 0x%x arg2 0x%x: " 6028 "1-1 int handler (entry %d intdata 0x%x)\n", 6029 arg1, arg2, 6030 x, ldgp->intdata)); 6031 } else if (ldgp->nldvs > 1) { 6032 inthandler = (uint_t *)ldgp->sys_intr_handler; 6033 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6034 "nxge_add_intrs_adv_type: " 6035 "arg1 0x%x arg2 0x%x: " 6036 "nldevs %d int handler " 6037 "(entry %d intdata 0x%x)\n", 6038 arg1, arg2, 6039 ldgp->nldvs, x, ldgp->intdata)); 6040 } 6041 6042 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6043 "==> nxge_add_intrs_adv_type: ddi_add_intr(inum) #%d " 6044 "htable 0x%llx", x, intrp->htable[x])); 6045 6046 if ((ddi_status = ddi_intr_add_handler(intrp->htable[x], 6047 (ddi_intr_handler_t *)inthandler, arg1, arg2)) 6048 != DDI_SUCCESS) { 6049 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6050 "==> nxge_add_intrs_adv_type: failed #%d " 6051 "status 0x%x", x, ddi_status)); 6052 for (y = 0; y < intrp->intr_added; y++) { 6053 (void) ddi_intr_remove_handler( 6054 intrp->htable[y]); 6055 } 6056 /* Free already allocated intr */ 6057 for (y = 0; y < nactual; y++) { 6058 (void) ddi_intr_free(intrp->htable[y]); 6059 } 6060 kmem_free(intrp->htable, intrp->intr_size); 6061 6062 (void) nxge_ldgv_uninit(nxgep); 6063 6064 return (NXGE_ERROR | NXGE_DDI_FAILED); 6065 } 6066 intrp->intr_added++; 6067 } 6068 6069 intrp->msi_intx_cnt = nactual; 6070 6071 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6072 "Requested: %d, Allowed: %d msi_intx_cnt %d intr_added %d", 6073 navail, nactual, 6074 intrp->msi_intx_cnt, 6075 intrp->intr_added)); 6076 6077 (void) ddi_intr_get_cap(intrp->htable[0], &intrp->intr_cap); 6078 6079 (void) nxge_intr_ldgv_init(nxgep); 6080 6081 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_add_intrs_adv_type")); 6082 6083 return (status); 6084 } 6085 6086 /*ARGSUSED*/ 6087 static nxge_status_t 6088 nxge_add_intrs_adv_type_fix(p_nxge_t nxgep, uint32_t int_type) 6089 { 6090 dev_info_t *dip = nxgep->dip; 6091 p_nxge_ldg_t ldgp; 6092 p_nxge_intr_t intrp; 6093 uint_t *inthandler; 6094 void *arg1, *arg2; 6095 int behavior; 6096 int nintrs, navail; 6097 int nactual, nrequired; 6098 int inum = 0; 6099 int x, y; 6100 int ddi_status = DDI_SUCCESS; 6101 nxge_status_t status = NXGE_OK; 6102 6103 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs_adv_type_fix")); 6104 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 6105 intrp->start_inum = 0; 6106 6107 ddi_status = ddi_intr_get_nintrs(dip, int_type, &nintrs); 6108 if ((ddi_status != DDI_SUCCESS) || (nintrs == 0)) { 6109 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6110 "ddi_intr_get_nintrs() failed, status: 0x%x%, " 6111 "nintrs: %d", status, nintrs)); 6112 return (NXGE_ERROR | NXGE_DDI_FAILED); 6113 } 6114 6115 ddi_status = ddi_intr_get_navail(dip, int_type, &navail); 6116 if ((ddi_status != DDI_SUCCESS) || (navail == 0)) { 6117 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6118 "ddi_intr_get_navail() failed, status: 0x%x%, " 6119 "nintrs: %d", ddi_status, navail)); 6120 return (NXGE_ERROR | NXGE_DDI_FAILED); 6121 } 6122 6123 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6124 "ddi_intr_get_navail() returned: nintrs %d, naavail %d", 6125 nintrs, navail)); 6126 6127 behavior = ((int_type == DDI_INTR_TYPE_FIXED) ? DDI_INTR_ALLOC_STRICT : 6128 DDI_INTR_ALLOC_NORMAL); 6129 intrp->intr_size = navail * sizeof (ddi_intr_handle_t); 6130 intrp->htable = kmem_alloc(intrp->intr_size, KM_SLEEP); 6131 ddi_status = ddi_intr_alloc(dip, intrp->htable, int_type, inum, 6132 navail, &nactual, behavior); 6133 if (ddi_status != DDI_SUCCESS || nactual == 0) { 6134 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6135 " ddi_intr_alloc() failed: %d", 6136 ddi_status)); 6137 kmem_free(intrp->htable, intrp->intr_size); 6138 return (NXGE_ERROR | NXGE_DDI_FAILED); 6139 } 6140 6141 if ((ddi_status = ddi_intr_get_pri(intrp->htable[0], 6142 (uint_t *)&intrp->pri)) != DDI_SUCCESS) { 6143 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6144 " ddi_intr_get_pri() failed: %d", 6145 ddi_status)); 6146 /* Free already allocated interrupts */ 6147 for (y = 0; y < nactual; y++) { 6148 (void) ddi_intr_free(intrp->htable[y]); 6149 } 6150 6151 kmem_free(intrp->htable, intrp->intr_size); 6152 return (NXGE_ERROR | NXGE_DDI_FAILED); 6153 } 6154 6155 nrequired = 0; 6156 switch (nxgep->niu_type) { 6157 default: 6158 status = nxge_ldgv_init(nxgep, &nactual, &nrequired); 6159 break; 6160 6161 case N2_NIU: 6162 status = nxge_ldgv_init_n2(nxgep, &nactual, &nrequired); 6163 break; 6164 } 6165 6166 if (status != NXGE_OK) { 6167 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6168 "nxge_add_intrs_adv_type_fix:nxge_ldgv_init " 6169 "failed: 0x%x", status)); 6170 /* Free already allocated interrupts */ 6171 for (y = 0; y < nactual; y++) { 6172 (void) ddi_intr_free(intrp->htable[y]); 6173 } 6174 6175 kmem_free(intrp->htable, intrp->intr_size); 6176 return (status); 6177 } 6178 6179 ldgp = nxgep->ldgvp->ldgp; 6180 for (x = 0; x < nrequired; x++, ldgp++) { 6181 ldgp->vector = (uint8_t)x; 6182 if (nxgep->niu_type != N2_NIU) { 6183 ldgp->intdata = SID_DATA(ldgp->func, x); 6184 } 6185 6186 arg1 = ldgp->ldvp; 6187 arg2 = nxgep; 6188 if (ldgp->nldvs == 1) { 6189 inthandler = (uint_t *)ldgp->ldvp->ldv_intr_handler; 6190 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6191 "nxge_add_intrs_adv_type_fix: " 6192 "1-1 int handler(%d) ldg %d ldv %d " 6193 "arg1 $%p arg2 $%p\n", 6194 x, ldgp->ldg, ldgp->ldvp->ldv, 6195 arg1, arg2)); 6196 } else if (ldgp->nldvs > 1) { 6197 inthandler = (uint_t *)ldgp->sys_intr_handler; 6198 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6199 "nxge_add_intrs_adv_type_fix: " 6200 "shared ldv %d int handler(%d) ldv %d ldg %d" 6201 "arg1 0x%016llx arg2 0x%016llx\n", 6202 x, ldgp->nldvs, ldgp->ldg, ldgp->ldvp->ldv, 6203 arg1, arg2)); 6204 } 6205 6206 if ((ddi_status = ddi_intr_add_handler(intrp->htable[x], 6207 (ddi_intr_handler_t *)inthandler, arg1, arg2)) 6208 != DDI_SUCCESS) { 6209 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6210 "==> nxge_add_intrs_adv_type_fix: failed #%d " 6211 "status 0x%x", x, ddi_status)); 6212 for (y = 0; y < intrp->intr_added; y++) { 6213 (void) ddi_intr_remove_handler( 6214 intrp->htable[y]); 6215 } 6216 for (y = 0; y < nactual; y++) { 6217 (void) ddi_intr_free(intrp->htable[y]); 6218 } 6219 /* Free already allocated intr */ 6220 kmem_free(intrp->htable, intrp->intr_size); 6221 6222 (void) nxge_ldgv_uninit(nxgep); 6223 6224 return (NXGE_ERROR | NXGE_DDI_FAILED); 6225 } 6226 intrp->intr_added++; 6227 } 6228 6229 intrp->msi_intx_cnt = nactual; 6230 6231 (void) ddi_intr_get_cap(intrp->htable[0], &intrp->intr_cap); 6232 6233 status = nxge_intr_ldgv_init(nxgep); 6234 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_add_intrs_adv_type_fix")); 6235 6236 return (status); 6237 } 6238 6239 static void 6240 nxge_remove_intrs(p_nxge_t nxgep) 6241 { 6242 int i, inum; 6243 p_nxge_intr_t intrp; 6244 6245 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_remove_intrs")); 6246 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 6247 if (!intrp->intr_registered) { 6248 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6249 "<== nxge_remove_intrs: interrupts not registered")); 6250 return; 6251 } 6252 6253 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_remove_intrs:advanced")); 6254 6255 if (intrp->intr_cap & DDI_INTR_FLAG_BLOCK) { 6256 (void) ddi_intr_block_disable(intrp->htable, 6257 intrp->intr_added); 6258 } else { 6259 for (i = 0; i < intrp->intr_added; i++) { 6260 (void) ddi_intr_disable(intrp->htable[i]); 6261 } 6262 } 6263 6264 for (inum = 0; inum < intrp->intr_added; inum++) { 6265 if (intrp->htable[inum]) { 6266 (void) ddi_intr_remove_handler(intrp->htable[inum]); 6267 } 6268 } 6269 6270 for (inum = 0; inum < intrp->msi_intx_cnt; inum++) { 6271 if (intrp->htable[inum]) { 6272 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6273 "nxge_remove_intrs: ddi_intr_free inum %d " 6274 "msi_intx_cnt %d intr_added %d", 6275 inum, 6276 intrp->msi_intx_cnt, 6277 intrp->intr_added)); 6278 6279 (void) ddi_intr_free(intrp->htable[inum]); 6280 } 6281 } 6282 6283 kmem_free(intrp->htable, intrp->intr_size); 6284 intrp->intr_registered = B_FALSE; 6285 intrp->intr_enabled = B_FALSE; 6286 intrp->msi_intx_cnt = 0; 6287 intrp->intr_added = 0; 6288 6289 (void) nxge_ldgv_uninit(nxgep); 6290 6291 (void) ddi_prop_remove(DDI_DEV_T_NONE, nxgep->dip, 6292 "#msix-request"); 6293 6294 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_remove_intrs")); 6295 } 6296 6297 /*ARGSUSED*/ 6298 static void 6299 nxge_intrs_enable(p_nxge_t nxgep) 6300 { 6301 p_nxge_intr_t intrp; 6302 int i; 6303 int status; 6304 6305 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_enable")); 6306 6307 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 6308 6309 if (!intrp->intr_registered) { 6310 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_intrs_enable: " 6311 "interrupts are not registered")); 6312 return; 6313 } 6314 6315 if (intrp->intr_enabled) { 6316 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6317 "<== nxge_intrs_enable: already enabled")); 6318 return; 6319 } 6320 6321 if (intrp->intr_cap & DDI_INTR_FLAG_BLOCK) { 6322 status = ddi_intr_block_enable(intrp->htable, 6323 intrp->intr_added); 6324 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_enable " 6325 "block enable - status 0x%x total inums #%d\n", 6326 status, intrp->intr_added)); 6327 } else { 6328 for (i = 0; i < intrp->intr_added; i++) { 6329 status = ddi_intr_enable(intrp->htable[i]); 6330 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_enable " 6331 "ddi_intr_enable:enable - status 0x%x " 6332 "total inums %d enable inum #%d\n", 6333 status, intrp->intr_added, i)); 6334 if (status == DDI_SUCCESS) { 6335 intrp->intr_enabled = B_TRUE; 6336 } 6337 } 6338 } 6339 6340 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intrs_enable")); 6341 } 6342 6343 /*ARGSUSED*/ 6344 static void 6345 nxge_intrs_disable(p_nxge_t nxgep) 6346 { 6347 p_nxge_intr_t intrp; 6348 int i; 6349 6350 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_disable")); 6351 6352 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 6353 6354 if (!intrp->intr_registered) { 6355 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intrs_disable: " 6356 "interrupts are not registered")); 6357 return; 6358 } 6359 6360 if (intrp->intr_cap & DDI_INTR_FLAG_BLOCK) { 6361 (void) ddi_intr_block_disable(intrp->htable, 6362 intrp->intr_added); 6363 } else { 6364 for (i = 0; i < intrp->intr_added; i++) { 6365 (void) ddi_intr_disable(intrp->htable[i]); 6366 } 6367 } 6368 6369 intrp->intr_enabled = B_FALSE; 6370 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intrs_disable")); 6371 } 6372 6373 static nxge_status_t 6374 nxge_mac_register(p_nxge_t nxgep) 6375 { 6376 mac_register_t *macp; 6377 int status; 6378 6379 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_mac_register")); 6380 6381 if ((macp = mac_alloc(MAC_VERSION)) == NULL) 6382 return (NXGE_ERROR); 6383 6384 macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 6385 macp->m_driver = nxgep; 6386 macp->m_dip = nxgep->dip; 6387 macp->m_src_addr = nxgep->ouraddr.ether_addr_octet; 6388 macp->m_callbacks = &nxge_m_callbacks; 6389 macp->m_min_sdu = 0; 6390 nxgep->mac.default_mtu = nxgep->mac.maxframesize - 6391 NXGE_EHEADER_VLAN_CRC; 6392 macp->m_max_sdu = nxgep->mac.default_mtu; 6393 macp->m_margin = VLAN_TAGSZ; 6394 macp->m_priv_props = nxge_priv_props; 6395 macp->m_priv_prop_count = NXGE_MAX_PRIV_PROPS; 6396 macp->m_v12n = MAC_VIRT_HIO | MAC_VIRT_LEVEL1 | MAC_VIRT_SERIALIZE; 6397 6398 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6399 "==> nxge_mac_register: instance %d " 6400 "max_sdu %d margin %d maxframe %d (header %d)", 6401 nxgep->instance, 6402 macp->m_max_sdu, macp->m_margin, 6403 nxgep->mac.maxframesize, 6404 NXGE_EHEADER_VLAN_CRC)); 6405 6406 status = mac_register(macp, &nxgep->mach); 6407 mac_free(macp); 6408 6409 if (status != 0) { 6410 cmn_err(CE_WARN, 6411 "!nxge_mac_register failed (status %d instance %d)", 6412 status, nxgep->instance); 6413 return (NXGE_ERROR); 6414 } 6415 6416 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_mac_register success " 6417 "(instance %d)", nxgep->instance)); 6418 6419 return (NXGE_OK); 6420 } 6421 6422 void 6423 nxge_err_inject(p_nxge_t nxgep, queue_t *wq, mblk_t *mp) 6424 { 6425 ssize_t size; 6426 mblk_t *nmp; 6427 uint8_t blk_id; 6428 uint8_t chan; 6429 uint32_t err_id; 6430 err_inject_t *eip; 6431 6432 NXGE_DEBUG_MSG((nxgep, STR_CTL, "==> nxge_err_inject")); 6433 6434 size = 1024; 6435 nmp = mp->b_cont; 6436 eip = (err_inject_t *)nmp->b_rptr; 6437 blk_id = eip->blk_id; 6438 err_id = eip->err_id; 6439 chan = eip->chan; 6440 cmn_err(CE_NOTE, "!blk_id = 0x%x\n", blk_id); 6441 cmn_err(CE_NOTE, "!err_id = 0x%x\n", err_id); 6442 cmn_err(CE_NOTE, "!chan = 0x%x\n", chan); 6443 switch (blk_id) { 6444 case MAC_BLK_ID: 6445 break; 6446 case TXMAC_BLK_ID: 6447 break; 6448 case RXMAC_BLK_ID: 6449 break; 6450 case MIF_BLK_ID: 6451 break; 6452 case IPP_BLK_ID: 6453 nxge_ipp_inject_err(nxgep, err_id); 6454 break; 6455 case TXC_BLK_ID: 6456 nxge_txc_inject_err(nxgep, err_id); 6457 break; 6458 case TXDMA_BLK_ID: 6459 nxge_txdma_inject_err(nxgep, err_id, chan); 6460 break; 6461 case RXDMA_BLK_ID: 6462 nxge_rxdma_inject_err(nxgep, err_id, chan); 6463 break; 6464 case ZCP_BLK_ID: 6465 nxge_zcp_inject_err(nxgep, err_id); 6466 break; 6467 case ESPC_BLK_ID: 6468 break; 6469 case FFLP_BLK_ID: 6470 break; 6471 case PHY_BLK_ID: 6472 break; 6473 case ETHER_SERDES_BLK_ID: 6474 break; 6475 case PCIE_SERDES_BLK_ID: 6476 break; 6477 case VIR_BLK_ID: 6478 break; 6479 } 6480 6481 nmp->b_wptr = nmp->b_rptr + size; 6482 NXGE_DEBUG_MSG((nxgep, STR_CTL, "<== nxge_err_inject")); 6483 6484 miocack(wq, mp, (int)size, 0); 6485 } 6486 6487 static int 6488 nxge_init_common_dev(p_nxge_t nxgep) 6489 { 6490 p_nxge_hw_list_t hw_p; 6491 dev_info_t *p_dip; 6492 6493 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "==> nxge_init_common_device")); 6494 6495 p_dip = nxgep->p_dip; 6496 MUTEX_ENTER(&nxge_common_lock); 6497 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6498 "==> nxge_init_common_dev:func # %d", 6499 nxgep->function_num)); 6500 /* 6501 * Loop through existing per neptune hardware list. 6502 */ 6503 for (hw_p = nxge_hw_list; hw_p; hw_p = hw_p->next) { 6504 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6505 "==> nxge_init_common_device:func # %d " 6506 "hw_p $%p parent dip $%p", 6507 nxgep->function_num, 6508 hw_p, 6509 p_dip)); 6510 if (hw_p->parent_devp == p_dip) { 6511 nxgep->nxge_hw_p = hw_p; 6512 hw_p->ndevs++; 6513 hw_p->nxge_p[nxgep->function_num] = nxgep; 6514 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6515 "==> nxge_init_common_device:func # %d " 6516 "hw_p $%p parent dip $%p " 6517 "ndevs %d (found)", 6518 nxgep->function_num, 6519 hw_p, 6520 p_dip, 6521 hw_p->ndevs)); 6522 break; 6523 } 6524 } 6525 6526 if (hw_p == NULL) { 6527 6528 char **prop_val; 6529 uint_t prop_len; 6530 int i; 6531 6532 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6533 "==> nxge_init_common_device:func # %d " 6534 "parent dip $%p (new)", 6535 nxgep->function_num, 6536 p_dip)); 6537 hw_p = kmem_zalloc(sizeof (nxge_hw_list_t), KM_SLEEP); 6538 hw_p->parent_devp = p_dip; 6539 hw_p->magic = NXGE_NEPTUNE_MAGIC; 6540 nxgep->nxge_hw_p = hw_p; 6541 hw_p->ndevs++; 6542 hw_p->nxge_p[nxgep->function_num] = nxgep; 6543 hw_p->next = nxge_hw_list; 6544 if (nxgep->niu_type == N2_NIU) { 6545 hw_p->niu_type = N2_NIU; 6546 hw_p->platform_type = P_NEPTUNE_NIU; 6547 } else { 6548 hw_p->niu_type = NIU_TYPE_NONE; 6549 hw_p->platform_type = P_NEPTUNE_NONE; 6550 } 6551 6552 MUTEX_INIT(&hw_p->nxge_cfg_lock, NULL, MUTEX_DRIVER, NULL); 6553 MUTEX_INIT(&hw_p->nxge_tcam_lock, NULL, MUTEX_DRIVER, NULL); 6554 MUTEX_INIT(&hw_p->nxge_vlan_lock, NULL, MUTEX_DRIVER, NULL); 6555 MUTEX_INIT(&hw_p->nxge_mdio_lock, NULL, MUTEX_DRIVER, NULL); 6556 6557 nxge_hw_list = hw_p; 6558 6559 if (ddi_prop_lookup_string_array(DDI_DEV_T_ANY, nxgep->dip, 0, 6560 "compatible", &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 6561 for (i = 0; i < prop_len; i++) { 6562 if ((strcmp((caddr_t)prop_val[i], 6563 NXGE_ROCK_COMPATIBLE) == 0)) { 6564 hw_p->platform_type = P_NEPTUNE_ROCK; 6565 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6566 "ROCK hw_p->platform_type %d", 6567 hw_p->platform_type)); 6568 break; 6569 } 6570 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6571 "nxge_init_common_dev: read compatible" 6572 " property[%d] val[%s]", 6573 i, (caddr_t)prop_val[i])); 6574 } 6575 } 6576 6577 ddi_prop_free(prop_val); 6578 6579 (void) nxge_scan_ports_phy(nxgep, nxge_hw_list); 6580 } 6581 6582 MUTEX_EXIT(&nxge_common_lock); 6583 6584 nxgep->platform_type = hw_p->platform_type; 6585 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "nxgep->platform_type %d", 6586 nxgep->platform_type)); 6587 if (nxgep->niu_type != N2_NIU) { 6588 nxgep->niu_type = hw_p->niu_type; 6589 } 6590 6591 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6592 "==> nxge_init_common_device (nxge_hw_list) $%p", 6593 nxge_hw_list)); 6594 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "<== nxge_init_common_device")); 6595 6596 return (NXGE_OK); 6597 } 6598 6599 static void 6600 nxge_uninit_common_dev(p_nxge_t nxgep) 6601 { 6602 p_nxge_hw_list_t hw_p, h_hw_p; 6603 p_nxge_dma_pt_cfg_t p_dma_cfgp; 6604 p_nxge_hw_pt_cfg_t p_cfgp; 6605 dev_info_t *p_dip; 6606 6607 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "==> nxge_uninit_common_device")); 6608 if (nxgep->nxge_hw_p == NULL) { 6609 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6610 "<== nxge_uninit_common_device (no common)")); 6611 return; 6612 } 6613 6614 MUTEX_ENTER(&nxge_common_lock); 6615 h_hw_p = nxge_hw_list; 6616 for (hw_p = nxge_hw_list; hw_p; hw_p = hw_p->next) { 6617 p_dip = hw_p->parent_devp; 6618 if (nxgep->nxge_hw_p == hw_p && 6619 p_dip == nxgep->p_dip && 6620 nxgep->nxge_hw_p->magic == NXGE_NEPTUNE_MAGIC && 6621 hw_p->magic == NXGE_NEPTUNE_MAGIC) { 6622 6623 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6624 "==> nxge_uninit_common_device:func # %d " 6625 "hw_p $%p parent dip $%p " 6626 "ndevs %d (found)", 6627 nxgep->function_num, 6628 hw_p, 6629 p_dip, 6630 hw_p->ndevs)); 6631 6632 /* 6633 * Release the RDC table, a shared resoruce 6634 * of the nxge hardware. The RDC table was 6635 * assigned to this instance of nxge in 6636 * nxge_use_cfg_dma_config(). 6637 */ 6638 if (!isLDOMguest(nxgep)) { 6639 p_dma_cfgp = 6640 (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 6641 p_cfgp = 6642 (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 6643 (void) nxge_fzc_rdc_tbl_unbind(nxgep, 6644 p_cfgp->def_mac_rxdma_grpid); 6645 6646 /* Cleanup any outstanding groups. */ 6647 nxge_grp_cleanup(nxgep); 6648 } 6649 6650 if (hw_p->ndevs) { 6651 hw_p->ndevs--; 6652 } 6653 hw_p->nxge_p[nxgep->function_num] = NULL; 6654 if (!hw_p->ndevs) { 6655 MUTEX_DESTROY(&hw_p->nxge_vlan_lock); 6656 MUTEX_DESTROY(&hw_p->nxge_tcam_lock); 6657 MUTEX_DESTROY(&hw_p->nxge_cfg_lock); 6658 MUTEX_DESTROY(&hw_p->nxge_mdio_lock); 6659 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6660 "==> nxge_uninit_common_device: " 6661 "func # %d " 6662 "hw_p $%p parent dip $%p " 6663 "ndevs %d (last)", 6664 nxgep->function_num, 6665 hw_p, 6666 p_dip, 6667 hw_p->ndevs)); 6668 6669 nxge_hio_uninit(nxgep); 6670 6671 if (hw_p == nxge_hw_list) { 6672 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6673 "==> nxge_uninit_common_device:" 6674 "remove head func # %d " 6675 "hw_p $%p parent dip $%p " 6676 "ndevs %d (head)", 6677 nxgep->function_num, 6678 hw_p, 6679 p_dip, 6680 hw_p->ndevs)); 6681 nxge_hw_list = hw_p->next; 6682 } else { 6683 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6684 "==> nxge_uninit_common_device:" 6685 "remove middle func # %d " 6686 "hw_p $%p parent dip $%p " 6687 "ndevs %d (middle)", 6688 nxgep->function_num, 6689 hw_p, 6690 p_dip, 6691 hw_p->ndevs)); 6692 h_hw_p->next = hw_p->next; 6693 } 6694 6695 nxgep->nxge_hw_p = NULL; 6696 KMEM_FREE(hw_p, sizeof (nxge_hw_list_t)); 6697 } 6698 break; 6699 } else { 6700 h_hw_p = hw_p; 6701 } 6702 } 6703 6704 MUTEX_EXIT(&nxge_common_lock); 6705 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6706 "==> nxge_uninit_common_device (nxge_hw_list) $%p", 6707 nxge_hw_list)); 6708 6709 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "<= nxge_uninit_common_device")); 6710 } 6711 6712 /* 6713 * Determines the number of ports from the niu_type or the platform type. 6714 * Returns the number of ports, or returns zero on failure. 6715 */ 6716 6717 int 6718 nxge_get_nports(p_nxge_t nxgep) 6719 { 6720 int nports = 0; 6721 6722 switch (nxgep->niu_type) { 6723 case N2_NIU: 6724 case NEPTUNE_2_10GF: 6725 nports = 2; 6726 break; 6727 case NEPTUNE_4_1GC: 6728 case NEPTUNE_2_10GF_2_1GC: 6729 case NEPTUNE_1_10GF_3_1GC: 6730 case NEPTUNE_1_1GC_1_10GF_2_1GC: 6731 case NEPTUNE_2_10GF_2_1GRF: 6732 nports = 4; 6733 break; 6734 default: 6735 switch (nxgep->platform_type) { 6736 case P_NEPTUNE_NIU: 6737 case P_NEPTUNE_ATLAS_2PORT: 6738 nports = 2; 6739 break; 6740 case P_NEPTUNE_ATLAS_4PORT: 6741 case P_NEPTUNE_MARAMBA_P0: 6742 case P_NEPTUNE_MARAMBA_P1: 6743 case P_NEPTUNE_ROCK: 6744 case P_NEPTUNE_ALONSO: 6745 nports = 4; 6746 break; 6747 default: 6748 break; 6749 } 6750 break; 6751 } 6752 6753 return (nports); 6754 } 6755 6756 /* 6757 * The following two functions are to support 6758 * PSARC/2007/453 MSI-X interrupt limit override. 6759 */ 6760 static int 6761 nxge_create_msi_property(p_nxge_t nxgep) 6762 { 6763 int nmsi; 6764 extern int ncpus; 6765 6766 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "==>nxge_create_msi_property")); 6767 6768 switch (nxgep->mac.portmode) { 6769 case PORT_10G_COPPER: 6770 case PORT_10G_FIBER: 6771 case PORT_10G_TN1010: 6772 (void) ddi_prop_create(DDI_DEV_T_NONE, nxgep->dip, 6773 DDI_PROP_CANSLEEP, "#msix-request", NULL, 0); 6774 /* 6775 * The maximum MSI-X requested will be 8. 6776 * If the # of CPUs is less than 8, we will request 6777 * # MSI-X based on the # of CPUs (default). 6778 */ 6779 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6780 "==>nxge_create_msi_property (10G): nxge_msix_10g_intrs %d", 6781 nxge_msix_10g_intrs)); 6782 if ((nxge_msix_10g_intrs == 0) || 6783 (nxge_msix_10g_intrs > NXGE_MSIX_MAX_ALLOWED)) { 6784 nmsi = NXGE_MSIX_REQUEST_10G; 6785 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6786 "==>nxge_create_msi_property (10G): reset to 8")); 6787 } else { 6788 nmsi = nxge_msix_10g_intrs; 6789 } 6790 6791 /* 6792 * If # of interrupts requested is 8 (default), 6793 * the checking of the number of cpus will be 6794 * be maintained. 6795 */ 6796 if ((nmsi == NXGE_MSIX_REQUEST_10G) && 6797 (ncpus < nmsi)) { 6798 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6799 "==>nxge_create_msi_property (10G): reset to 8")); 6800 nmsi = ncpus; 6801 } 6802 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6803 "==>nxge_create_msi_property(10G): exists 0x%x (nmsi %d)", 6804 ddi_prop_exists(DDI_DEV_T_NONE, nxgep->dip, 6805 DDI_PROP_CANSLEEP, "#msix-request"), nmsi)); 6806 break; 6807 6808 default: 6809 (void) ddi_prop_create(DDI_DEV_T_NONE, nxgep->dip, 6810 DDI_PROP_CANSLEEP, "#msix-request", NULL, 0); 6811 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6812 "==>nxge_create_msi_property (1G): nxge_msix_1g_intrs %d", 6813 nxge_msix_1g_intrs)); 6814 if ((nxge_msix_1g_intrs == 0) || 6815 (nxge_msix_1g_intrs > NXGE_MSIX_MAX_ALLOWED)) { 6816 nmsi = NXGE_MSIX_REQUEST_1G; 6817 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6818 "==>nxge_create_msi_property (1G): reset to 2")); 6819 } else { 6820 nmsi = nxge_msix_1g_intrs; 6821 } 6822 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6823 "==>nxge_create_msi_property(1G): exists 0x%x (nmsi %d)", 6824 ddi_prop_exists(DDI_DEV_T_NONE, nxgep->dip, 6825 DDI_PROP_CANSLEEP, "#msix-request"), nmsi)); 6826 break; 6827 } 6828 6829 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "<==nxge_create_msi_property")); 6830 return (nmsi); 6831 } 6832 6833 /* ARGSUSED */ 6834 static int 6835 nxge_get_def_val(nxge_t *nxgep, mac_prop_id_t pr_num, uint_t pr_valsize, 6836 void *pr_val) 6837 { 6838 int err = 0; 6839 link_flowctrl_t fl; 6840 6841 switch (pr_num) { 6842 case MAC_PROP_AUTONEG: 6843 *(uint8_t *)pr_val = 1; 6844 break; 6845 case MAC_PROP_FLOWCTRL: 6846 if (pr_valsize < sizeof (link_flowctrl_t)) 6847 return (EINVAL); 6848 fl = LINK_FLOWCTRL_RX; 6849 bcopy(&fl, pr_val, sizeof (fl)); 6850 break; 6851 case MAC_PROP_ADV_1000FDX_CAP: 6852 case MAC_PROP_EN_1000FDX_CAP: 6853 *(uint8_t *)pr_val = 1; 6854 break; 6855 case MAC_PROP_ADV_100FDX_CAP: 6856 case MAC_PROP_EN_100FDX_CAP: 6857 *(uint8_t *)pr_val = 1; 6858 break; 6859 default: 6860 err = ENOTSUP; 6861 break; 6862 } 6863 return (err); 6864 } 6865 6866 6867 /* 6868 * The following is a software around for the Neptune hardware's 6869 * interrupt bugs; The Neptune hardware may generate spurious interrupts when 6870 * an interrupr handler is removed. 6871 */ 6872 #define NXGE_PCI_PORT_LOGIC_OFFSET 0x98 6873 #define NXGE_PIM_RESET (1ULL << 29) 6874 #define NXGE_GLU_RESET (1ULL << 30) 6875 #define NXGE_NIU_RESET (1ULL << 31) 6876 #define NXGE_PCI_RESET_ALL (NXGE_PIM_RESET | \ 6877 NXGE_GLU_RESET | \ 6878 NXGE_NIU_RESET) 6879 6880 #define NXGE_WAIT_QUITE_TIME 200000 6881 #define NXGE_WAIT_QUITE_RETRY 40 6882 #define NXGE_PCI_RESET_WAIT 1000000 /* one second */ 6883 6884 static void 6885 nxge_niu_peu_reset(p_nxge_t nxgep) 6886 { 6887 uint32_t rvalue; 6888 p_nxge_hw_list_t hw_p; 6889 p_nxge_t fnxgep; 6890 int i, j; 6891 6892 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, "==> nxge_niu_peu_reset")); 6893 if ((hw_p = nxgep->nxge_hw_p) == NULL) { 6894 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6895 "==> nxge_niu_peu_reset: NULL hardware pointer")); 6896 return; 6897 } 6898 6899 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 6900 "==> nxge_niu_peu_reset: flags 0x%x link timer id %d timer id %d", 6901 hw_p->flags, nxgep->nxge_link_poll_timerid, 6902 nxgep->nxge_timerid)); 6903 6904 MUTEX_ENTER(&hw_p->nxge_cfg_lock); 6905 /* 6906 * Make sure other instances from the same hardware 6907 * stop sending PIO and in quiescent state. 6908 */ 6909 for (i = 0; i < NXGE_MAX_PORTS; i++) { 6910 fnxgep = hw_p->nxge_p[i]; 6911 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 6912 "==> nxge_niu_peu_reset: checking entry %d " 6913 "nxgep $%p", i, fnxgep)); 6914 #ifdef NXGE_DEBUG 6915 if (fnxgep) { 6916 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 6917 "==> nxge_niu_peu_reset: entry %d (function %d) " 6918 "link timer id %d hw timer id %d", 6919 i, fnxgep->function_num, 6920 fnxgep->nxge_link_poll_timerid, 6921 fnxgep->nxge_timerid)); 6922 } 6923 #endif 6924 if (fnxgep && fnxgep != nxgep && 6925 (fnxgep->nxge_timerid || fnxgep->nxge_link_poll_timerid)) { 6926 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 6927 "==> nxge_niu_peu_reset: checking $%p " 6928 "(function %d) timer ids", 6929 fnxgep, fnxgep->function_num)); 6930 for (j = 0; j < NXGE_WAIT_QUITE_RETRY; j++) { 6931 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 6932 "==> nxge_niu_peu_reset: waiting")); 6933 NXGE_DELAY(NXGE_WAIT_QUITE_TIME); 6934 if (!fnxgep->nxge_timerid && 6935 !fnxgep->nxge_link_poll_timerid) { 6936 break; 6937 } 6938 } 6939 NXGE_DELAY(NXGE_WAIT_QUITE_TIME); 6940 if (fnxgep->nxge_timerid || 6941 fnxgep->nxge_link_poll_timerid) { 6942 MUTEX_EXIT(&hw_p->nxge_cfg_lock); 6943 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6944 "<== nxge_niu_peu_reset: cannot reset " 6945 "hardware (devices are still in use)")); 6946 return; 6947 } 6948 } 6949 } 6950 6951 if ((hw_p->flags & COMMON_RESET_NIU_PCI) != COMMON_RESET_NIU_PCI) { 6952 hw_p->flags |= COMMON_RESET_NIU_PCI; 6953 rvalue = pci_config_get32(nxgep->dev_regs->nxge_pciregh, 6954 NXGE_PCI_PORT_LOGIC_OFFSET); 6955 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 6956 "nxge_niu_peu_reset: read offset 0x%x (%d) " 6957 "(data 0x%x)", 6958 NXGE_PCI_PORT_LOGIC_OFFSET, 6959 NXGE_PCI_PORT_LOGIC_OFFSET, 6960 rvalue)); 6961 6962 rvalue |= NXGE_PCI_RESET_ALL; 6963 pci_config_put32(nxgep->dev_regs->nxge_pciregh, 6964 NXGE_PCI_PORT_LOGIC_OFFSET, rvalue); 6965 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 6966 "nxge_niu_peu_reset: RESETTING NIU: write NIU reset 0x%x", 6967 rvalue)); 6968 6969 NXGE_DELAY(NXGE_PCI_RESET_WAIT); 6970 } 6971 6972 MUTEX_EXIT(&hw_p->nxge_cfg_lock); 6973 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_niu_peu_reset")); 6974 } 6975 6976 static void 6977 nxge_set_pci_replay_timeout(p_nxge_t nxgep) 6978 { 6979 p_dev_regs_t dev_regs; 6980 uint32_t value; 6981 6982 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_set_pci_replay_timeout")); 6983 6984 if (!nxge_set_replay_timer) { 6985 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6986 "==> nxge_set_pci_replay_timeout: will not change " 6987 "the timeout")); 6988 return; 6989 } 6990 6991 dev_regs = nxgep->dev_regs; 6992 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6993 "==> nxge_set_pci_replay_timeout: dev_regs 0x%p pcireg 0x%p", 6994 dev_regs, dev_regs->nxge_pciregh)); 6995 6996 if (dev_regs == NULL || (dev_regs->nxge_pciregh == NULL)) { 6997 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6998 "==> nxge_set_pci_replay_timeout: NULL dev_regs $%p or " 6999 "no PCI handle", 7000 dev_regs)); 7001 return; 7002 } 7003 value = (pci_config_get32(dev_regs->nxge_pciregh, 7004 PCI_REPLAY_TIMEOUT_CFG_OFFSET) | 7005 (nxge_replay_timeout << PCI_REPLAY_TIMEOUT_SHIFT)); 7006 7007 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 7008 "nxge_set_pci_replay_timeout: replay timeout value before set 0x%x " 7009 "(timeout value to set 0x%x at offset 0x%x) value 0x%x", 7010 pci_config_get32(dev_regs->nxge_pciregh, 7011 PCI_REPLAY_TIMEOUT_CFG_OFFSET), nxge_replay_timeout, 7012 PCI_REPLAY_TIMEOUT_CFG_OFFSET, value)); 7013 7014 pci_config_put32(dev_regs->nxge_pciregh, PCI_REPLAY_TIMEOUT_CFG_OFFSET, 7015 value); 7016 7017 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 7018 "nxge_set_pci_replay_timeout: replay timeout value after set 0x%x", 7019 pci_config_get32(dev_regs->nxge_pciregh, 7020 PCI_REPLAY_TIMEOUT_CFG_OFFSET))); 7021 7022 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_set_pci_replay_timeout")); 7023 } 7024 7025 /* 7026 * quiesce(9E) entry point. 7027 * 7028 * This function is called when the system is single-threaded at high 7029 * PIL with preemption disabled. Therefore, this function must not be 7030 * blocked. 7031 * 7032 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 7033 * DDI_FAILURE indicates an error condition and should almost never happen. 7034 */ 7035 static int 7036 nxge_quiesce(dev_info_t *dip) 7037 { 7038 int instance = ddi_get_instance(dip); 7039 p_nxge_t nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance); 7040 7041 if (nxgep == NULL) 7042 return (DDI_FAILURE); 7043 7044 /* Turn off debugging */ 7045 nxge_debug_level = NO_DEBUG; 7046 nxgep->nxge_debug_level = NO_DEBUG; 7047 npi_debug_level = NO_DEBUG; 7048 7049 /* 7050 * Stop link monitor only when linkchkmod is interrupt based 7051 */ 7052 if (nxgep->mac.linkchkmode == LINKCHK_INTR) { 7053 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 7054 } 7055 7056 (void) nxge_intr_hw_disable(nxgep); 7057 7058 /* 7059 * Reset the receive MAC side. 7060 */ 7061 (void) nxge_rx_mac_disable(nxgep); 7062 7063 /* Disable and soft reset the IPP */ 7064 if (!isLDOMguest(nxgep)) 7065 (void) nxge_ipp_disable(nxgep); 7066 7067 /* 7068 * Reset the transmit/receive DMA side. 7069 */ 7070 (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_STOP); 7071 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP); 7072 7073 /* 7074 * Reset the transmit MAC side. 7075 */ 7076 (void) nxge_tx_mac_disable(nxgep); 7077 7078 return (DDI_SUCCESS); 7079 } 7080