1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <sys/nxge/nxge_impl.h> 27 #include <sys/nxge/nxge_mac.h> 28 #include <sys/nxge/nxge_hio.h> 29 30 #define LINK_MONITOR_PERIOD (1000 * 1000) 31 #define LM_WAIT_MULTIPLIER 8 32 33 #define SERDES_RDY_WT_INTERVAL 50 34 #define MAX_SERDES_RDY_RETRIES 10 35 36 #define TN1010_SPEED_1G 1 37 #define TN1010_SPEED_10G 0 38 #define TN1010_AN_IN_PROG 0 /* Auto negotiation in progress */ 39 #define TN1010_AN_COMPLETE 1 40 #define TN1010_AN_RSVD 2 41 #define TN1010_AN_FAILED 3 42 43 extern uint32_t nxge_no_link_notify; 44 extern boolean_t nxge_no_msg; 45 extern uint32_t nxge_lb_dbg; 46 extern boolean_t nxge_jumbo_enable; 47 extern uint32_t nxge_jumbo_mtu; 48 49 /* The following functions may be found in nxge_main.c */ 50 extern void nxge_mmac_kstat_update(p_nxge_t nxgep, mac_addr_slot_t slot, 51 boolean_t factory); 52 extern int nxge_m_mmac_add(void *arg, mac_multi_addr_t *maddr); 53 extern int nxge_m_mmac_remove(void *arg, mac_addr_slot_t slot); 54 extern int nxge_altmac_set(p_nxge_t nxgep, uint8_t *mac_addr, 55 mac_addr_slot_t slot, uint8_t rdctbl); 56 57 typedef enum { 58 CHECK_LINK_RESCHEDULE, 59 CHECK_LINK_STOP 60 } check_link_state_t; 61 62 static check_link_state_t nxge_check_link_stop(nxge_t *); 63 64 /* 65 * Ethernet broadcast address definition. 66 */ 67 static ether_addr_st etherbroadcastaddr = 68 {{0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}; 69 /* 70 * Ethernet zero address definition. 71 */ 72 static ether_addr_st etherzeroaddr = 73 {{0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}; 74 /* 75 * Supported chip types 76 */ 77 static uint32_t nxge_supported_cl45_ids[] = { 78 BCM8704_DEV_ID, 79 MARVELL_88X_201X_DEV_ID, 80 BCM8706_DEV_ID, 81 TN1010_DEV_ID 82 }; 83 84 static uint32_t nxge_supported_cl22_ids[] = { 85 BCM5464R_PHY_ID, 86 BCM5482_PHY_ID 87 }; 88 89 #define NUM_CLAUSE_45_IDS (sizeof (nxge_supported_cl45_ids) / \ 90 sizeof (uint32_t)) 91 #define NUM_CLAUSE_22_IDS (sizeof (nxge_supported_cl22_ids) / \ 92 sizeof (uint32_t)) 93 /* 94 * static functions 95 */ 96 static uint32_t nxge_get_cl45_pma_pmd_id(p_nxge_t, int); 97 static uint32_t nxge_get_cl45_pcs_id(p_nxge_t, int); 98 static uint32_t nxge_get_cl22_phy_id(p_nxge_t, int); 99 static boolean_t nxge_is_supported_phy(uint32_t, uint8_t); 100 static boolean_t nxge_is_phy_present(p_nxge_t, int, uint32_t, uint32_t); 101 static nxge_status_t nxge_n2_serdes_init(p_nxge_t); 102 static nxge_status_t nxge_neptune_10G_serdes_init(p_nxge_t); 103 static nxge_status_t nxge_1G_serdes_init(p_nxge_t); 104 static nxge_status_t nxge_10G_link_intr_stop(p_nxge_t); 105 static nxge_status_t nxge_10G_link_intr_start(p_nxge_t); 106 static nxge_status_t nxge_1G_copper_link_intr_stop(p_nxge_t); 107 static nxge_status_t nxge_1G_copper_link_intr_start(p_nxge_t); 108 static nxge_status_t nxge_1G_fiber_link_intr_stop(p_nxge_t); 109 static nxge_status_t nxge_1G_fiber_link_intr_start(p_nxge_t); 110 static nxge_status_t nxge_check_mii_link(p_nxge_t); 111 static nxge_status_t nxge_check_10g_link(p_nxge_t); 112 static nxge_status_t nxge_10G_xcvr_init(p_nxge_t); 113 static nxge_status_t nxge_BCM8704_xcvr_init(p_nxge_t); 114 static nxge_status_t nxge_BCM8706_xcvr_init(p_nxge_t); 115 static nxge_status_t nxge_1G_xcvr_init(p_nxge_t); 116 static void nxge_bcm5464_link_led_off(p_nxge_t); 117 static nxge_status_t nxge_check_mrvl88x2011_link(p_nxge_t, boolean_t *); 118 static nxge_status_t nxge_mrvl88x2011_xcvr_init(p_nxge_t); 119 static nxge_status_t nxge_get_num_of_xaui(uint32_t *port_pma_pmd_dev_id, 120 uint32_t *port_pcs_dev_id, uint32_t *port_phy_id, uint8_t *num_xaui); 121 static nxge_status_t nxge_get_tn1010_speed(p_nxge_t nxgep, uint16_t *speed); 122 static nxge_status_t nxge_set_tn1010_param(p_nxge_t nxgep); 123 static nxge_status_t nxge_tn1010_check(p_nxge_t nxgep, 124 nxge_link_state_t *link_up); 125 static boolean_t nxge_is_tn1010_phy(p_nxge_t nxgep); 126 static nxge_status_t nxge_tn1010_xcvr_init(p_nxge_t nxgep); 127 128 nxge_status_t nxge_mac_init(p_nxge_t); 129 static nxge_status_t nxge_mii_get_link_mode(p_nxge_t); 130 131 #ifdef NXGE_DEBUG 132 static void nxge_mii_dump(p_nxge_t); 133 static nxge_status_t nxge_tn1010_reset(p_nxge_t nxgep); 134 static void nxge_dump_tn1010_status_regs(p_nxge_t nxgep); 135 #endif 136 137 /* 138 * xcvr tables for supported transceivers 139 */ 140 141 /* 142 * nxge_n2_10G_table is for 10G fiber or serdes on N2-NIU systems. 143 * The Teranetics TN1010 based copper XAUI card can also be used 144 * on N2-NIU systems in 10G mode, but it uses its own table 145 * nxge_n2_10G_tn1010_table below. 146 */ 147 static nxge_xcvr_table_t nxge_n2_10G_table = { 148 nxge_n2_serdes_init, 149 nxge_10G_xcvr_init, 150 nxge_10G_link_intr_stop, 151 nxge_10G_link_intr_start, 152 nxge_check_10g_link, 153 PCS_XCVR 154 }; 155 156 /* 157 * For the Teranetics TN1010 based copper XAUI card 158 */ 159 static nxge_xcvr_table_t nxge_n2_10G_tn1010_table = { 160 nxge_n2_serdes_init, /* Handle both 1G and 10G */ 161 nxge_tn1010_xcvr_init, /* Handle both 1G and 10G */ 162 nxge_10G_link_intr_stop, 163 nxge_10G_link_intr_start, 164 nxge_check_tn1010_link, /* Will figure out speed */ 165 XPCS_XCVR 166 }; 167 168 static nxge_xcvr_table_t nxge_n2_1G_table = { 169 nxge_n2_serdes_init, 170 nxge_1G_xcvr_init, 171 nxge_1G_fiber_link_intr_stop, 172 nxge_1G_fiber_link_intr_start, 173 nxge_check_mii_link, 174 PCS_XCVR 175 }; 176 177 static nxge_xcvr_table_t nxge_n2_1G_tn1010_table = { 178 nxge_n2_serdes_init, 179 nxge_tn1010_xcvr_init, 180 nxge_1G_fiber_link_intr_stop, /* TN1010 is a Cu PHY, but it uses */ 181 nxge_1G_fiber_link_intr_start, /* PCS for 1G, so call fiber func */ 182 nxge_check_tn1010_link, 183 PCS_XCVR 184 }; 185 186 static nxge_xcvr_table_t nxge_10G_tn1010_table = { 187 nxge_neptune_10G_serdes_init, 188 nxge_tn1010_xcvr_init, 189 nxge_10G_link_intr_stop, 190 nxge_10G_link_intr_start, 191 nxge_check_tn1010_link, 192 XPCS_XCVR 193 }; 194 195 static nxge_xcvr_table_t nxge_1G_tn1010_table = { 196 nxge_1G_serdes_init, 197 nxge_tn1010_xcvr_init, 198 nxge_1G_fiber_link_intr_stop, 199 nxge_1G_fiber_link_intr_start, 200 nxge_check_tn1010_link, 201 PCS_XCVR 202 }; 203 204 static nxge_xcvr_table_t nxge_10G_fiber_table = { 205 nxge_neptune_10G_serdes_init, 206 nxge_10G_xcvr_init, 207 nxge_10G_link_intr_stop, 208 nxge_10G_link_intr_start, 209 nxge_check_10g_link, 210 PCS_XCVR 211 }; 212 213 static nxge_xcvr_table_t nxge_1G_copper_table = { 214 NULL, 215 nxge_1G_xcvr_init, 216 nxge_1G_copper_link_intr_stop, 217 nxge_1G_copper_link_intr_start, 218 nxge_check_mii_link, 219 INT_MII_XCVR 220 }; 221 222 /* This table is for Neptune portmode == PORT_1G_SERDES cases */ 223 static nxge_xcvr_table_t nxge_1G_fiber_table = { 224 nxge_1G_serdes_init, 225 nxge_1G_xcvr_init, 226 nxge_1G_fiber_link_intr_stop, 227 nxge_1G_fiber_link_intr_start, 228 nxge_check_mii_link, 229 PCS_XCVR 230 }; 231 232 static nxge_xcvr_table_t nxge_10G_copper_table = { 233 nxge_neptune_10G_serdes_init, 234 NULL, 235 NULL, 236 NULL, 237 NULL, 238 PCS_XCVR 239 }; 240 241 /* 242 * NXGE_PORT_TN1010 is defined as, 243 * NXGE_PORT_SPD_NONE | (NXGE_PHY_TN1010 << NXGE_PHY_SHIFT) 244 * = 0 | 5 << 16 = 0x50000 245 * 246 * So NEPTUNE_2_TN1010 = 247 * (NXGE_PORT_TN1010 | 248 * (NXGE_PORT_TN1010 << 4) | 249 * (NXGE_PORT_NONE << 8) | 250 * (NXGE_PORT_NONE << 12)), 251 * = 0x50000 | (0x50000 << 4) 252 * = 0x550000 253 * 254 * This function partitions nxgep->nxge_hw_p->niu_type (which may have 255 * value NEPTUNE_2_TN1010) and checks if a port has type = NXGE_PORT_TN1010 256 * = 0x50000 257 */ 258 static boolean_t nxge_is_tn1010_phy(p_nxge_t nxgep) 259 { 260 uint8_t portn = NXGE_GET_PORT_NUM(nxgep->function_num); 261 262 if (((nxgep->nxge_hw_p->niu_type >> (NXGE_PORT_TYPE_SHIFT * portn)) 263 & NXGE_PHY_MASK) == NXGE_PORT_TN1010) { 264 return (B_TRUE); 265 } else { 266 return (B_FALSE); 267 } 268 } 269 270 271 /* 272 * Figure out nxgep->mac.portmode from nxge.conf, OBP's device properties, 273 * serial EEPROM or VPD if possible. Note that not all systems could get 274 * the portmode information by calling this function. For example, the 275 * Maramba system figures out the portmode information by calling function 276 * nxge_setup_xcvr_table. 277 */ 278 nxge_status_t 279 nxge_get_xcvr_type(p_nxge_t nxgep) 280 { 281 nxge_status_t status = NXGE_OK; 282 char *phy_type; 283 char *prop_val; 284 uint8_t portn = NXGE_GET_PORT_NUM(nxgep->function_num); 285 286 nxgep->mac.portmode = 0; 287 nxgep->xcvr_addr = 0; 288 289 /* 290 * First check for hot swappable phy property. 291 */ 292 if (nxgep->hot_swappable_phy == B_TRUE) { 293 nxgep->statsp->mac_stats.xcvr_inuse = HSP_XCVR; 294 nxgep->mac.portmode = PORT_HSP_MODE; 295 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "Other: Hot Swappable")); 296 } else if (ddi_prop_exists(DDI_DEV_T_ANY, nxgep->dip, 297 DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, 298 "hot-swappable-phy") == 1) { 299 nxgep->statsp->mac_stats.xcvr_inuse = HSP_XCVR; 300 nxgep->mac.portmode = PORT_HSP_MODE; 301 NXGE_DEBUG_MSG((nxgep, MAC_CTL, ".conf: Hot Swappable")); 302 } else if (nxgep->niu_type == N2_NIU && 303 ddi_prop_exists(DDI_DEV_T_ANY, nxgep->dip, 0, 304 "hot-swappable-phy") == 1) { 305 nxgep->statsp->mac_stats.xcvr_inuse = HSP_XCVR; 306 nxgep->mac.portmode = PORT_HSP_MODE; 307 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "OBP: Hot Swappable")); 308 } 309 310 /* 311 * MDIO polling support for Monza RTM card, Goa NEM card 312 */ 313 if (nxgep->mac.portmode == PORT_HSP_MODE) { 314 nxgep->hot_swappable_phy = B_TRUE; 315 /* 316 * If this is the 2nd NIU port, then check 2 addresses 317 * to take care of the Goa NEM card. Port 1 can have addr 17 318 * (in the eval board) or 20 (in the P0 board). 319 */ 320 if (portn == 1) { 321 if (nxge_is_phy_present(nxgep, 322 ALT_GOA_CLAUSE45_PORT1_ADDR, BCM8706_DEV_ID, 323 BCM_PHY_ID_MASK)) { 324 nxgep->xcvr_addr = 325 ALT_GOA_CLAUSE45_PORT1_ADDR; 326 goto found_phy; 327 } 328 } 329 if (nxge_is_phy_present(nxgep, 330 GOA_CLAUSE45_PORT_ADDR_BASE + portn, 331 BCM8706_DEV_ID, BCM_PHY_ID_MASK)) { 332 nxgep->xcvr_addr = GOA_CLAUSE45_PORT_ADDR_BASE + 333 portn; 334 goto found_phy; 335 } 336 337 nxgep->phy_absent = B_TRUE; 338 goto check_phy_done; 339 found_phy: 340 nxgep->statsp->mac_stats.xcvr_inuse = XPCS_XCVR; 341 nxgep->mac.portmode = PORT_10G_FIBER; 342 nxgep->phy_absent = B_FALSE; 343 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "10G Fiber Xcvr " 344 "found for hot swappable phy")); 345 check_phy_done: 346 return (status); 347 } 348 349 /* Get phy-type property (May have been set by nxge.conf) */ 350 if ((ddi_prop_lookup_string(DDI_DEV_T_ANY, nxgep->dip, 351 DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, 352 "phy-type", &prop_val)) == DDI_PROP_SUCCESS) { 353 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 354 "found conf file: phy-type %s", prop_val)); 355 if (strcmp("xgsd", prop_val) == 0) { 356 nxgep->statsp->mac_stats.xcvr_inuse = XPCS_XCVR; 357 nxgep->mac.portmode = PORT_10G_SERDES; 358 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 359 "found: 10G Serdes")); 360 } else if (strcmp("gsd", prop_val) == 0) { 361 nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR; 362 nxgep->mac.portmode = PORT_1G_SERDES; 363 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "1G Serdes")); 364 } else if (strcmp("mif", prop_val) == 0) { 365 nxgep->statsp->mac_stats.xcvr_inuse = INT_MII_XCVR; 366 nxgep->mac.portmode = PORT_1G_COPPER; 367 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "1G Copper Xcvr")); 368 } else if (strcmp("pcs", prop_val) == 0) { 369 nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR; 370 nxgep->mac.portmode = PORT_1G_FIBER; 371 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "1G FIBER Xcvr")); 372 } else if (strcmp("xgf", prop_val) == 0) { 373 /* 374 * Before OBP supports new phy-type property 375 * value "xgc", the 10G copper XAUI may carry 376 * "xgf" instead of "xgc". If the OBP is 377 * upgraded to a newer version which supports 378 * "xgc", then the TN1010 related code in this 379 * "xgf" case will not be used anymore. 380 */ 381 if (nxge_is_tn1010_phy(nxgep)) { 382 if ((status = nxge_set_tn1010_param(nxgep)) 383 != NXGE_OK) { 384 return (status); 385 } 386 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "TN1010 Xcvr")); 387 } else { /* For Fiber XAUI */ 388 nxgep->statsp->mac_stats.xcvr_inuse = XPCS_XCVR; 389 nxgep->mac.portmode = PORT_10G_FIBER; 390 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 391 "10G Fiber Xcvr")); 392 } 393 } else if (strcmp("xgc", prop_val) == 0) { 394 if ((status = nxge_set_tn1010_param(nxgep)) != NXGE_OK) 395 return (status); 396 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "TN1010 Xcvr")); 397 } 398 399 (void) ddi_prop_update_string(DDI_DEV_T_NONE, nxgep->dip, 400 "phy-type", prop_val); 401 ddi_prop_free(prop_val); 402 403 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "nxge_get_xcvr_type: " 404 "Got phy type [0x%x] from conf file", 405 nxgep->mac.portmode)); 406 407 return (NXGE_OK); 408 } 409 410 /* Get phy-type property from OBP */ 411 if (nxgep->niu_type == N2_NIU) { 412 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, nxgep->dip, 0, 413 "phy-type", &prop_val) == DDI_PROP_SUCCESS) { 414 if (strcmp("xgf", prop_val) == 0) { 415 /* 416 * Before OBP supports new phy-type property 417 * value "xgc", the 10G copper XAUI may carry 418 * "xgf" instead of "xgc". If the OBP is 419 * upgraded to a newer version which supports 420 * "xgc", then the TN1010 related code in this 421 * "xgf" case will not be used anymore. 422 */ 423 if (nxge_is_tn1010_phy(nxgep)) { 424 if ((status = 425 nxge_set_tn1010_param(nxgep)) 426 != NXGE_OK) { 427 return (status); 428 } 429 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 430 "TN1010 Xcvr")); 431 } else { /* For Fiber XAUI */ 432 nxgep->statsp->mac_stats.xcvr_inuse 433 = XPCS_XCVR; 434 nxgep->mac.portmode = PORT_10G_FIBER; 435 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 436 "10G Fiber Xcvr")); 437 } 438 } else if (strcmp("mif", prop_val) == 0) { 439 nxgep->statsp->mac_stats.xcvr_inuse = 440 INT_MII_XCVR; 441 nxgep->mac.portmode = PORT_1G_COPPER; 442 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 443 "1G Copper Xcvr")); 444 } else if (strcmp("pcs", prop_val) == 0) { 445 nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR; 446 nxgep->mac.portmode = PORT_1G_FIBER; 447 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 448 "1G Fiber Xcvr")); 449 } else if (strcmp("xgc", prop_val) == 0) { 450 status = nxge_set_tn1010_param(nxgep); 451 if (status != NXGE_OK) 452 return (status); 453 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "TN1010 Xcvr")); 454 } else if (strcmp("xgsd", prop_val) == 0) { 455 nxgep->statsp->mac_stats.xcvr_inuse = XPCS_XCVR; 456 nxgep->mac.portmode = PORT_10G_SERDES; 457 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 458 "OBP: 10G Serdes")); 459 } else if (strcmp("gsd", prop_val) == 0) { 460 nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR; 461 nxgep->mac.portmode = PORT_1G_SERDES; 462 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 463 "OBP: 1G Serdes")); 464 } else { 465 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 466 "Unknown phy-type: %s", prop_val)); 467 ddi_prop_free(prop_val); 468 return (NXGE_ERROR); 469 } 470 status = NXGE_OK; 471 (void) ddi_prop_update_string(DDI_DEV_T_NONE, 472 nxgep->dip, "phy-type", prop_val); 473 ddi_prop_free(prop_val); 474 475 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "nxge_get_xcvr_type: " 476 "Got phy type [0x%x] from OBP", 477 nxgep->mac.portmode)); 478 479 return (status); 480 } else { 481 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 482 "Exiting...phy-type property not found")); 483 return (NXGE_ERROR); 484 } 485 } 486 487 488 if (!nxgep->vpd_info.present) { 489 return (NXGE_OK); 490 } 491 492 if (!nxgep->vpd_info.ver_valid) { 493 goto read_seeprom; 494 } 495 496 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 497 "Reading phy type from expansion ROM")); 498 /* 499 * Try to read the phy type from the vpd data read off the 500 * expansion ROM. 501 */ 502 phy_type = nxgep->vpd_info.phy_type; 503 504 if (strncmp(phy_type, "mif", 3) == 0) { 505 nxgep->mac.portmode = PORT_1G_COPPER; 506 nxgep->statsp->mac_stats.xcvr_inuse = INT_MII_XCVR; 507 } else if (strncmp(phy_type, "xgf", 3) == 0) { 508 nxgep->mac.portmode = PORT_10G_FIBER; 509 nxgep->statsp->mac_stats.xcvr_inuse = XPCS_XCVR; 510 } else if (strncmp(phy_type, "pcs", 3) == 0) { 511 nxgep->mac.portmode = PORT_1G_FIBER; 512 nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR; 513 } else if (strncmp(phy_type, "xgc", 3) == 0) { 514 status = nxge_set_tn1010_param(nxgep); 515 if (status != NXGE_OK) { 516 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 517 "nxge_get_xcvr_type: Failed to set TN1010 param")); 518 goto read_seeprom; 519 } 520 } else if (strncmp(phy_type, "xgsd", 4) == 0) { 521 nxgep->mac.portmode = PORT_10G_SERDES; 522 nxgep->statsp->mac_stats.xcvr_inuse = XPCS_XCVR; 523 } else if (strncmp(phy_type, "gsd", 3) == 0) { 524 nxgep->mac.portmode = PORT_1G_SERDES; 525 nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR; 526 } else { 527 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 528 "nxge_get_xcvr_type: Unknown phy type [%c%c%c] in EEPROM", 529 phy_type[0], phy_type[1], phy_type[2])); 530 goto read_seeprom; 531 } 532 533 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "nxge_get_xcvr_type: " 534 "Got phy type [0x%x] from VPD", nxgep->mac.portmode)); 535 536 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_get_xcvr_type")); 537 return (status); 538 539 read_seeprom: 540 /* 541 * read the phy type from the SEEPROM - NCR registers 542 */ 543 status = nxge_espc_phy_type_get(nxgep); 544 if (status != NXGE_OK) { 545 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 546 "Failed to get phy type")); 547 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "EEPROM version " 548 "[%s] invalid...please update", nxgep->vpd_info.ver)); 549 } 550 551 return (status); 552 553 } 554 555 /* Set up the PHY specific values. */ 556 557 nxge_status_t 558 nxge_setup_xcvr_table(p_nxge_t nxgep) 559 { 560 nxge_status_t status = NXGE_OK; 561 uint32_t port_type; 562 uint8_t portn = NXGE_GET_PORT_NUM(nxgep->function_num); 563 uint32_t pcs_id = 0; 564 uint32_t pma_pmd_id = 0; 565 uint32_t phy_id = 0; 566 uint16_t chip_id = 0; 567 568 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_setup_xcvr_table: port<%d>", 569 portn)); 570 571 switch (nxgep->niu_type) { 572 case N2_NIU: 573 switch (nxgep->mac.portmode) { 574 case PORT_1G_FIBER: 575 case PORT_1G_SERDES: 576 nxgep->xcvr = nxge_n2_1G_table; 577 nxgep->xcvr_addr = portn; 578 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "NIU 1G %s Xcvr", 579 (nxgep->mac.portmode == PORT_1G_FIBER) ? "Fiber" : 580 "Serdes")); 581 break; 582 case PORT_10G_FIBER: 583 case PORT_10G_SERDES: 584 nxgep->xcvr = nxge_n2_10G_table; 585 if (nxgep->nxge_hw_p->xcvr_addr[portn]) { 586 nxgep->xcvr_addr = 587 nxgep->nxge_hw_p->xcvr_addr[portn]; 588 } 589 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "NIU 10G %s Xcvr", 590 (nxgep->mac.portmode == PORT_10G_FIBER) ? "Fiber" : 591 "Serdes")); 592 break; 593 case PORT_1G_TN1010: 594 nxgep->xcvr = nxge_n2_1G_tn1010_table; 595 nxgep->xcvr_addr = nxgep->nxge_hw_p->xcvr_addr[portn]; 596 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 597 "TN1010 Copper Xcvr in 1G")); 598 break; 599 case PORT_10G_TN1010: 600 nxgep->xcvr = nxge_n2_10G_tn1010_table; 601 nxgep->xcvr_addr = nxgep->nxge_hw_p->xcvr_addr[portn]; 602 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 603 "TN1010 Copper Xcvr in 10G")); 604 break; 605 case PORT_HSP_MODE: 606 nxgep->xcvr = nxge_n2_10G_table; 607 nxgep->xcvr.xcvr_inuse = HSP_XCVR; 608 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "NIU 10G Hot " 609 "Swappable Xcvr (not present)")); 610 break; 611 default: 612 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 613 "<== nxge_setup_xcvr_table: " 614 "Unable to determine NIU portmode")); 615 return (NXGE_ERROR); 616 } 617 break; 618 default: 619 if (nxgep->mac.portmode == 0) { 620 /* 621 * Would be the case for platforms like Maramba 622 * in which the phy type could not be got from conf 623 * file, OBP, VPD or Serial PROM. 624 */ 625 if (!NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 626 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 627 "<== nxge_setup_xcvr_table:" 628 " Invalid Neptune type [0x%x]", 629 nxgep->niu_type)); 630 return (NXGE_ERROR); 631 } 632 633 port_type = nxgep->niu_type >> 634 (NXGE_PORT_TYPE_SHIFT * portn); 635 port_type = port_type & (NXGE_PORT_TYPE_MASK); 636 637 switch (port_type) { 638 639 case NXGE_PORT_1G_COPPER: 640 nxgep->mac.portmode = PORT_1G_COPPER; 641 break; 642 case NXGE_PORT_10G_COPPER: 643 nxgep->mac.portmode = PORT_10G_COPPER; 644 break; 645 case NXGE_PORT_1G_FIBRE: 646 nxgep->mac.portmode = PORT_1G_FIBER; 647 break; 648 case NXGE_PORT_10G_FIBRE: 649 nxgep->mac.portmode = PORT_10G_FIBER; 650 break; 651 case NXGE_PORT_1G_SERDES: 652 nxgep->mac.portmode = PORT_1G_SERDES; 653 break; 654 case NXGE_PORT_10G_SERDES: 655 nxgep->mac.portmode = PORT_10G_SERDES; 656 break; 657 /* Ports 2 and 3 of Alonso or ARTM */ 658 case NXGE_PORT_1G_RGMII_FIBER: 659 nxgep->mac.portmode = PORT_1G_RGMII_FIBER; 660 break; 661 case NXGE_PORT_TN1010: 662 /* 663 * If this port uses the TN1010 copper 664 * PHY, then its speed is not known yet 665 * because nxge_scan_ports_phy could only 666 * figure out the vendor of the PHY but 667 * not its speed. nxge_set_tn1010_param 668 * will read the PHY speed and set 669 * portmode accordingly. 670 */ 671 if ((status = nxge_set_tn1010_param(nxgep)) 672 != NXGE_OK) { 673 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 674 "nxge_set_tn1010_param failed")); 675 return (status); 676 } 677 break; 678 default: 679 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 680 "<== nxge_setup_xcvr_table: " 681 "Unknown port-type: 0x%x", port_type)); 682 return (NXGE_ERROR); 683 } 684 } 685 686 /* 687 * Above switch has figured out nxge->mac.portmode, now set 688 * nxgep->xcvr (the table) and nxgep->xcvr_addr according 689 * to portmode. 690 */ 691 switch (nxgep->mac.portmode) { 692 case PORT_1G_COPPER: 693 case PORT_1G_RGMII_FIBER: 694 nxgep->xcvr = nxge_1G_copper_table; 695 nxgep->xcvr_addr = nxgep->nxge_hw_p->xcvr_addr[portn]; 696 /* 697 * For Altas 4-1G copper, Xcvr port numbers are 698 * swapped with ethernet port number. This is 699 * designed for better signal integrity in 700 * routing. This is also the case for the 701 * on-board Neptune copper ports on the Maramba 702 * platform. 703 */ 704 switch (nxgep->platform_type) { 705 case P_NEPTUNE_ATLAS_4PORT: 706 case P_NEPTUNE_MARAMBA_P0: 707 case P_NEPTUNE_MARAMBA_P1: 708 switch (portn) { 709 case 0: 710 nxgep->xcvr_addr += 3; 711 break; 712 case 1: 713 nxgep->xcvr_addr += 1; 714 break; 715 case 2: 716 nxgep->xcvr_addr -= 1; 717 break; 718 case 3: 719 nxgep->xcvr_addr -= 3; 720 break; 721 default: 722 return (NXGE_ERROR); 723 } 724 break; 725 default: 726 break; 727 } 728 729 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "1G %s Xcvr", 730 (nxgep->mac.portmode == PORT_1G_COPPER) ? 731 "Copper" : "RGMII Fiber")); 732 break; 733 734 case PORT_10G_COPPER: 735 nxgep->xcvr = nxge_10G_copper_table; 736 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "10G Copper Xcvr")); 737 break; 738 739 case PORT_1G_TN1010: 740 nxgep->xcvr = nxge_1G_tn1010_table; 741 nxgep->xcvr_addr = nxgep->nxge_hw_p->xcvr_addr[portn]; 742 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 743 "1G TN1010 copper Xcvr")); 744 break; 745 746 case PORT_10G_TN1010: 747 nxgep->xcvr = nxge_10G_tn1010_table; 748 nxgep->xcvr_addr = nxgep->nxge_hw_p->xcvr_addr[portn]; 749 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 750 "10G TN1010 copper Xcvr")); 751 break; 752 753 case PORT_1G_FIBER: 754 case PORT_1G_SERDES: 755 nxgep->xcvr = nxge_1G_fiber_table; 756 nxgep->xcvr_addr = portn; 757 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "1G %s Xcvr", 758 (nxgep->mac.portmode == PORT_1G_FIBER) ? 759 "Fiber" : "Serdes")); 760 break; 761 case PORT_10G_FIBER: 762 case PORT_10G_SERDES: 763 nxgep->xcvr = nxge_10G_fiber_table; 764 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "10G xcvr " 765 "nxgep->nxge_hw_p->xcvr_addr[portn] = [%d] " 766 "nxgep->xcvr_addr = [%d]", 767 nxgep->nxge_hw_p->xcvr_addr[portn], 768 nxgep->xcvr_addr)); 769 if (nxgep->nxge_hw_p->xcvr_addr[portn]) { 770 nxgep->xcvr_addr = 771 nxgep->nxge_hw_p->xcvr_addr[portn]; 772 } 773 switch (nxgep->platform_type) { 774 case P_NEPTUNE_MARAMBA_P0: 775 case P_NEPTUNE_MARAMBA_P1: 776 /* 777 * Switch off LED for corresponding copper 778 * port 779 */ 780 nxge_bcm5464_link_led_off(nxgep); 781 break; 782 default: 783 break; 784 } 785 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "10G %s Xcvr", 786 (nxgep->mac.portmode == PORT_10G_FIBER) ? 787 "Fiber" : "Serdes")); 788 break; 789 790 case PORT_HSP_MODE: 791 nxgep->xcvr = nxge_10G_fiber_table; 792 nxgep->xcvr.xcvr_inuse = HSP_XCVR; 793 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "Neptune 10G Hot " 794 "Swappable Xcvr (not present)")); 795 break; 796 default: 797 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 798 "Unknown port-type: 0x%x", port_type)); 799 return (NXGE_ERROR); 800 } 801 } 802 803 if (nxgep->mac.portmode == PORT_10G_FIBER) { 804 uint32_t pma_pmd_id; 805 pma_pmd_id = nxge_get_cl45_pma_pmd_id(nxgep, 806 nxgep->xcvr_addr); 807 if ((pma_pmd_id & BCM_PHY_ID_MASK) == MARVELL_88X201X_PHY_ID) { 808 chip_id = MRVL88X201X_CHIP_ID; 809 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 810 "nxge_setup_xcvr_table: " 811 "Chip ID MARVELL [0x%x] for 10G xcvr", chip_id)); 812 } else if ((status = nxge_mdio_read(nxgep, nxgep->xcvr_addr, 813 BCM8704_PCS_DEV_ADDR, BCM8704_CHIP_ID_REG, 814 &chip_id)) == NXGE_OK) { 815 816 switch (chip_id) { 817 case BCM8704_CHIP_ID: 818 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 819 "nxge_setup_xcvr_table: " 820 "Chip ID 8704 [0x%x] for 10G xcvr", 821 chip_id)); 822 break; 823 case BCM8706_CHIP_ID: 824 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 825 "nxge_setup_xcvr_table: " 826 "Chip ID 8706 [0x%x] for 10G xcvr", 827 chip_id)); 828 break; 829 default: 830 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 831 "nxge_setup_xcvr_table: " 832 "Unknown Chip ID [0x%x] for 10G xcvr", 833 chip_id)); 834 break; 835 } 836 } 837 } 838 839 nxgep->statsp->mac_stats.xcvr_inuse = nxgep->xcvr.xcvr_inuse; 840 nxgep->statsp->mac_stats.xcvr_portn = nxgep->xcvr_addr; 841 nxgep->chip_id = chip_id; 842 843 /* 844 * Get the actual device ID value returned by MDIO read. 845 */ 846 nxgep->statsp->mac_stats.xcvr_id = 0; 847 848 pma_pmd_id = nxge_get_cl45_pma_pmd_id(nxgep, nxgep->xcvr_addr); 849 if (nxge_is_supported_phy(pma_pmd_id, CLAUSE_45_TYPE)) { 850 nxgep->statsp->mac_stats.xcvr_id = pma_pmd_id; 851 } else { 852 pcs_id = nxge_get_cl45_pcs_id(nxgep, nxgep->xcvr_addr); 853 if (nxge_is_supported_phy(pcs_id, CLAUSE_45_TYPE)) { 854 nxgep->statsp->mac_stats.xcvr_id = pcs_id; 855 } else { 856 phy_id = nxge_get_cl22_phy_id(nxgep, 857 nxgep->xcvr_addr); 858 if (nxge_is_supported_phy(phy_id, CLAUSE_22_TYPE)) { 859 nxgep->statsp->mac_stats.xcvr_id = phy_id; 860 } 861 } 862 } 863 864 nxgep->mac.linkchkmode = LINKCHK_TIMER; 865 866 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "nxge_setup_xcvr_table: niu_type" 867 "[0x%x] platform type[0x%x] xcvr_addr[%d]", nxgep->niu_type, 868 nxgep->platform_type, nxgep->xcvr_addr)); 869 870 return (status); 871 } 872 873 /* Initialize the entire MAC and physical layer */ 874 875 nxge_status_t 876 nxge_mac_init(p_nxge_t nxgep) 877 { 878 uint8_t portn; 879 nxge_status_t status = NXGE_OK; 880 portn = NXGE_GET_PORT_NUM(nxgep->function_num); 881 882 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_mac_init: port<%d>", portn)); 883 884 nxgep->mac.portnum = portn; 885 nxgep->mac.porttype = PORT_TYPE_XMAC; 886 887 if ((portn == BMAC_PORT_0) || (portn == BMAC_PORT_1)) 888 nxgep->mac.porttype = PORT_TYPE_BMAC; 889 890 891 /* Initialize XIF to configure a network mode */ 892 if ((status = nxge_xif_init(nxgep)) != NXGE_OK) { 893 goto fail; 894 } 895 896 if ((status = nxge_pcs_init(nxgep)) != NXGE_OK) { 897 goto fail; 898 } 899 900 /* Initialize TX and RX MACs */ 901 /* 902 * Always perform XIF init first, before TX and RX MAC init 903 */ 904 if ((status = nxge_tx_mac_reset(nxgep)) != NXGE_OK) 905 goto fail; 906 907 if ((status = nxge_tx_mac_init(nxgep)) != NXGE_OK) 908 goto fail; 909 910 if ((status = nxge_rx_mac_reset(nxgep)) != NXGE_OK) 911 goto fail; 912 913 if ((status = nxge_rx_mac_init(nxgep)) != NXGE_OK) 914 goto fail; 915 916 if ((status = nxge_tx_mac_enable(nxgep)) != NXGE_OK) 917 goto fail; 918 919 if ((status = nxge_rx_mac_enable(nxgep)) != NXGE_OK) 920 goto fail; 921 922 /* Initialize MAC control configuration */ 923 if ((status = nxge_mac_ctrl_init(nxgep)) != NXGE_OK) { 924 goto fail; 925 } 926 927 nxgep->statsp->mac_stats.mac_mtu = nxgep->mac.maxframesize; 928 929 /* The Neptune Serdes needs to be reinitialized again */ 930 if ((NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) && 931 ((nxgep->mac.portmode == PORT_1G_SERDES) || 932 (nxgep->mac.portmode == PORT_1G_TN1010) || 933 (nxgep->mac.portmode == PORT_1G_FIBER)) && 934 ((portn == 0) || (portn == 1))) { 935 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 936 "nxge_mac_init: reinit Neptune 1G Serdes ")); 937 if ((status = nxge_1G_serdes_init(nxgep)) != NXGE_OK) { 938 goto fail; 939 } 940 } 941 942 943 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_mac_init: port<%d>", portn)); 944 945 return (NXGE_OK); 946 fail: 947 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 948 "nxge_mac_init: failed to initialize MAC port<%d>", portn)); 949 return (status); 950 } 951 952 /* Initialize the Ethernet Link */ 953 954 nxge_status_t 955 nxge_link_init(p_nxge_t nxgep) 956 { 957 nxge_status_t status = NXGE_OK; 958 nxge_port_mode_t portmode; 959 #ifdef NXGE_DEBUG 960 uint8_t portn; 961 962 portn = nxgep->mac.portnum; 963 964 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_link_init: port<%d>", portn)); 965 #endif 966 if (nxgep->hot_swappable_phy && nxgep->phy_absent) { 967 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_link_init: " 968 "Phy not present, cannot initialize link")); 969 return (status); 970 } 971 972 portmode = nxgep->mac.portmode; 973 974 /* 975 * Workaround to get link up in both NIU ports. Some portmodes require 976 * that the xcvr be initialized twice, the first time before calling 977 * nxge_serdes_init. 978 */ 979 if (nxgep->niu_type == N2_NIU && (portmode != PORT_10G_SERDES) && 980 (portmode != PORT_10G_TN1010) && 981 (portmode != PORT_1G_TN1010) && 982 (portmode != PORT_1G_SERDES)) { 983 if ((status = nxge_xcvr_init(nxgep)) != NXGE_OK) { 984 goto fail; 985 } 986 } 987 988 NXGE_DELAY(200000); 989 /* Initialize internal serdes */ 990 if ((status = nxge_serdes_init(nxgep)) != NXGE_OK) 991 goto fail; 992 NXGE_DELAY(200000); 993 if ((status = nxge_xcvr_init(nxgep)) != NXGE_OK) 994 goto fail; 995 996 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_link_init: port<%d>", portn)); 997 998 return (NXGE_OK); 999 1000 fail: 1001 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "nxge_link_init: ", 1002 "failed to initialize Ethernet link on port<%d>", portn)); 1003 1004 return (status); 1005 } 1006 1007 1008 /* Initialize the XIF sub-block within the MAC */ 1009 1010 nxge_status_t 1011 nxge_xif_init(p_nxge_t nxgep) 1012 { 1013 uint32_t xif_cfg = 0; 1014 npi_attr_t ap; 1015 uint8_t portn; 1016 nxge_port_t portt; 1017 nxge_port_mode_t portmode; 1018 p_nxge_stats_t statsp; 1019 npi_status_t rs = NPI_SUCCESS; 1020 npi_handle_t handle; 1021 1022 portn = NXGE_GET_PORT_NUM(nxgep->function_num); 1023 1024 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_xif_init: port<%d>", portn)); 1025 1026 handle = nxgep->npi_handle; 1027 portmode = nxgep->mac.portmode; 1028 portt = nxgep->mac.porttype; 1029 statsp = nxgep->statsp; 1030 1031 if ((NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) && 1032 ((nxgep->mac.portmode == PORT_1G_SERDES) || 1033 (nxgep->mac.portmode == PORT_1G_TN1010) || 1034 (nxgep->mac.portmode == PORT_1G_FIBER)) && 1035 ((portn == 0) || (portn == 1))) { 1036 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1037 "nxge_xcvr_init: set ATCA mode")); 1038 npi_mac_mif_set_atca_mode(nxgep->npi_handle, B_TRUE); 1039 } 1040 1041 if (portt == PORT_TYPE_XMAC) { 1042 1043 /* Setup XIF Configuration for XMAC */ 1044 1045 if ((portmode == PORT_10G_FIBER) || 1046 (portmode == PORT_10G_COPPER) || 1047 (portmode == PORT_10G_TN1010) || 1048 (portmode == PORT_10G_SERDES)) 1049 xif_cfg |= CFG_XMAC_XIF_LFS; 1050 1051 /* Bypass PCS so that RGMII will be used */ 1052 if (portmode == PORT_1G_COPPER) { 1053 xif_cfg |= CFG_XMAC_XIF_1G_PCS_BYPASS; 1054 } 1055 1056 /* Set MAC Internal Loopback if necessary */ 1057 if (statsp->port_stats.lb_mode == nxge_lb_mac1000) 1058 xif_cfg |= CFG_XMAC_XIF_LOOPBACK; 1059 1060 if (statsp->mac_stats.link_speed == 100) 1061 xif_cfg |= CFG_XMAC_XIF_SEL_CLK_25MHZ; 1062 1063 xif_cfg |= CFG_XMAC_XIF_TX_OUTPUT; 1064 1065 if ((portmode == PORT_10G_FIBER) || 1066 (portmode == PORT_10G_TN1010) || 1067 (portmode == PORT_1G_TN1010) || 1068 (portmode == PORT_10G_SERDES)) { 1069 /* Assume LED same for 1G and 10G */ 1070 if (statsp->mac_stats.link_up) { 1071 xif_cfg |= CFG_XMAC_XIF_LED_POLARITY; 1072 } else { 1073 xif_cfg |= CFG_XMAC_XIF_LED_FORCE; 1074 } 1075 } 1076 1077 rs = npi_xmac_xif_config(handle, INIT, portn, xif_cfg); 1078 if (rs != NPI_SUCCESS) 1079 goto fail; 1080 1081 nxgep->mac.xif_config = xif_cfg; 1082 1083 /* Set Port Mode */ 1084 if ((portmode == PORT_10G_FIBER) || 1085 (portmode == PORT_10G_COPPER) || 1086 (portmode == PORT_10G_TN1010) || 1087 (portmode == PORT_10G_SERDES)) { 1088 SET_MAC_ATTR1(handle, ap, portn, MAC_PORT_MODE, 1089 MAC_XGMII_MODE, rs); 1090 if (rs != NPI_SUCCESS) 1091 goto fail; 1092 if (statsp->mac_stats.link_up) { 1093 if (nxge_10g_link_led_on(nxgep) != NXGE_OK) 1094 goto fail; 1095 } else { 1096 if (nxge_10g_link_led_off(nxgep) != NXGE_OK) 1097 goto fail; 1098 } 1099 } else if ((portmode == PORT_1G_FIBER) || 1100 (portmode == PORT_1G_COPPER) || 1101 (portmode == PORT_1G_SERDES) || 1102 (portmode == PORT_1G_TN1010) || 1103 (portmode == PORT_1G_RGMII_FIBER)) { 1104 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1105 "nxge_xif_init: Port[%d] Mode[%d] Speed[%d]", 1106 portn, portmode, statsp->mac_stats.link_speed)); 1107 if (statsp->mac_stats.link_speed == 1000) { 1108 SET_MAC_ATTR1(handle, ap, portn, MAC_PORT_MODE, 1109 MAC_GMII_MODE, rs); 1110 } else { 1111 SET_MAC_ATTR1(handle, ap, portn, MAC_PORT_MODE, 1112 MAC_MII_MODE, rs); 1113 } 1114 if (rs != NPI_SUCCESS) 1115 goto fail; 1116 } else { 1117 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1118 "nxge_xif_init: Unknown port mode (%d)" 1119 " for port<%d>", portmode, portn)); 1120 goto fail; 1121 } 1122 1123 /* Enable ATCA mode */ 1124 1125 } else if (portt == PORT_TYPE_BMAC) { 1126 1127 /* Setup XIF Configuration for BMAC */ 1128 1129 if ((portmode == PORT_1G_COPPER) || 1130 (portmode == PORT_1G_RGMII_FIBER)) { 1131 if (statsp->mac_stats.link_speed == 100) 1132 xif_cfg |= CFG_BMAC_XIF_SEL_CLK_25MHZ; 1133 } 1134 1135 if (statsp->port_stats.lb_mode == nxge_lb_mac1000) 1136 xif_cfg |= CFG_BMAC_XIF_LOOPBACK; 1137 1138 if (statsp->mac_stats.link_speed == 1000) 1139 xif_cfg |= CFG_BMAC_XIF_GMII_MODE; 1140 1141 xif_cfg |= CFG_BMAC_XIF_TX_OUTPUT; 1142 1143 rs = npi_bmac_xif_config(handle, INIT, portn, xif_cfg); 1144 if (rs != NPI_SUCCESS) 1145 goto fail; 1146 nxgep->mac.xif_config = xif_cfg; 1147 } 1148 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_xif_init: port<%d>", portn)); 1149 return (NXGE_OK); 1150 fail: 1151 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1152 "nxge_xif_init: Failed to initialize XIF port<%d>", portn)); 1153 return (NXGE_ERROR | rs); 1154 } 1155 1156 1157 /* 1158 * Initialize the PCS sub-block in the MAC. Note that PCS does not 1159 * support loopback like XPCS. 1160 */ 1161 nxge_status_t 1162 nxge_pcs_init(p_nxge_t nxgep) 1163 { 1164 pcs_cfg_t pcs_cfg; 1165 uint32_t val; 1166 uint8_t portn; 1167 nxge_port_mode_t portmode; 1168 npi_handle_t handle; 1169 p_nxge_stats_t statsp; 1170 pcs_ctrl_t pcs_ctrl; 1171 npi_status_t rs = NPI_SUCCESS; 1172 uint8_t i; 1173 1174 handle = nxgep->npi_handle; 1175 portmode = nxgep->mac.portmode; 1176 portn = nxgep->mac.portnum; 1177 statsp = nxgep->statsp; 1178 1179 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_pcs_init: port<%d>", portn)); 1180 1181 if (portmode == PORT_1G_FIBER || 1182 portmode == PORT_1G_TN1010 || 1183 portmode == PORT_1G_SERDES) { 1184 if (portmode == PORT_1G_TN1010) { 1185 /* Reset PCS multiple time in PORT_1G_TN1010 mode */ 1186 for (i = 0; i < 6; i ++) { 1187 if ((rs = npi_mac_pcs_reset(handle, portn)) 1188 != NPI_SUCCESS) { 1189 goto fail; 1190 } 1191 } 1192 } else { 1193 if ((rs = npi_mac_pcs_reset(handle, portn)) 1194 != NPI_SUCCESS) 1195 goto fail; 1196 } 1197 1198 /* Initialize port's PCS */ 1199 pcs_cfg.value = 0; 1200 pcs_cfg.bits.w0.enable = 1; 1201 pcs_cfg.bits.w0.mask = 1; 1202 PCS_REG_WR(handle, portn, PCS_CONFIG_REG, pcs_cfg.value); 1203 PCS_REG_WR(handle, portn, PCS_DATAPATH_MODE_REG, 0); 1204 1205 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1206 "==> nxge_pcs_init: (1G) port<%d> write config 0x%llx", 1207 portn, pcs_cfg.value)); 1208 1209 if (portmode == PORT_1G_TN1010) { 1210 /* 1211 * Must disable PCS auto-negotiation when the the driver 1212 * is driving the TN1010 based XAUI card Otherwise the 1213 * autonegotiation between the PCS and the TN1010 PCS 1214 * will never complete and the Neptune/NIU will not work 1215 */ 1216 pcs_ctrl.value = 0; 1217 PCS_REG_WR(handle, portn, PCS_MII_CTRL_REG, 1218 pcs_ctrl.value); 1219 } 1220 } else if (portmode == PORT_10G_FIBER || 1221 portmode == PORT_10G_COPPER || 1222 portmode == PORT_10G_TN1010 || 1223 portmode == PORT_10G_SERDES) { 1224 /* Use internal XPCS, bypass 1G PCS */ 1225 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1226 val &= ~XMAC_XIF_XPCS_BYPASS; 1227 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 1228 1229 if ((rs = npi_xmac_xpcs_reset(handle, portn)) != NPI_SUCCESS) 1230 goto fail; 1231 1232 /* Set XPCS Internal Loopback if necessary */ 1233 if ((rs = npi_xmac_xpcs_read(handle, portn, 1234 XPCS_REG_CONTROL1, &val)) != NPI_SUCCESS) 1235 goto fail; 1236 1237 if ((statsp->port_stats.lb_mode == nxge_lb_mac10g) || 1238 (statsp->port_stats.lb_mode == nxge_lb_mac1000)) 1239 val |= XPCS_CTRL1_LOOPBK; 1240 else 1241 val &= ~XPCS_CTRL1_LOOPBK; 1242 if ((rs = npi_xmac_xpcs_write(handle, portn, 1243 XPCS_REG_CONTROL1, val)) != NPI_SUCCESS) 1244 goto fail; 1245 1246 /* Clear descw errors */ 1247 if ((rs = npi_xmac_xpcs_write(handle, portn, 1248 XPCS_REG_DESCWERR_COUNTER, 0)) != NPI_SUCCESS) 1249 goto fail; 1250 /* Clear symbol errors */ 1251 if ((rs = npi_xmac_xpcs_read(handle, portn, 1252 XPCS_REG_SYMBOL_ERR_L0_1_COUNTER, &val)) != NPI_SUCCESS) 1253 goto fail; 1254 if ((rs = npi_xmac_xpcs_read(handle, portn, 1255 XPCS_REG_SYMBOL_ERR_L2_3_COUNTER, &val)) != NPI_SUCCESS) 1256 goto fail; 1257 1258 } else if ((portmode == PORT_1G_COPPER) || 1259 (portmode == PORT_1G_RGMII_FIBER)) { 1260 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1261 "==> nxge_pcs_init: (1G) copper port<%d>", portn)); 1262 if (portn < 4) { 1263 PCS_REG_WR(handle, portn, PCS_DATAPATH_MODE_REG, 1264 PCS_DATAPATH_MODE_MII); 1265 } 1266 if ((rs = npi_mac_pcs_reset(handle, portn)) != NPI_SUCCESS) 1267 goto fail; 1268 1269 } else { 1270 goto fail; 1271 } 1272 pass: 1273 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_pcs_init: port<%d>", portn)); 1274 return (NXGE_OK); 1275 fail: 1276 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1277 "nxge_pcs_init: Failed to initialize PCS port<%d>", portn)); 1278 return (NXGE_ERROR | rs); 1279 } 1280 1281 /* 1282 * Initialize the MAC CTRL sub-block within the MAC 1283 * Only the receive-pause-cap is supported. 1284 */ 1285 nxge_status_t 1286 nxge_mac_ctrl_init(p_nxge_t nxgep) 1287 { 1288 uint8_t portn; 1289 nxge_port_t portt; 1290 p_nxge_stats_t statsp; 1291 npi_handle_t handle; 1292 uint32_t val; 1293 1294 portn = NXGE_GET_PORT_NUM(nxgep->function_num); 1295 1296 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_mac_ctrl_init: port<%d>", 1297 portn)); 1298 1299 handle = nxgep->npi_handle; 1300 portt = nxgep->mac.porttype; 1301 statsp = nxgep->statsp; 1302 1303 if (portt == PORT_TYPE_XMAC) { 1304 /* Reading the current XMAC Config Register for XMAC */ 1305 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1306 1307 /* 1308 * Setup XMAC Configuration for XMAC 1309 * XMAC only supports receive-pause 1310 */ 1311 if (statsp->mac_stats.adv_cap_asmpause) { 1312 if (!statsp->mac_stats.adv_cap_pause) { 1313 /* 1314 * If adv_cap_asmpause is 1 and adv_cap_pause 1315 * is 0, enable receive pause. 1316 */ 1317 val |= XMAC_RX_CFG_RX_PAUSE_EN; 1318 } else { 1319 /* 1320 * If adv_cap_asmpause is 1 and adv_cap_pause 1321 * is 1, disable receive pause. Send pause is 1322 * not supported. 1323 */ 1324 val &= ~XMAC_RX_CFG_RX_PAUSE_EN; 1325 } 1326 } else { 1327 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1328 "==> nxge_mac_ctrl_init: port<%d>: pause", 1329 portn)); 1330 if (statsp->mac_stats.adv_cap_pause) { 1331 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1332 "==> nxge_mac_ctrl_init: port<%d>: " 1333 "enable pause", portn)); 1334 /* 1335 * If adv_cap_asmpause is 0 and adv_cap_pause 1336 * is 1, enable receive pause. 1337 */ 1338 val |= XMAC_RX_CFG_RX_PAUSE_EN; 1339 } else { 1340 /* 1341 * If adv_cap_asmpause is 0 and adv_cap_pause 1342 * is 0, disable receive pause. Send pause is 1343 * not supported 1344 */ 1345 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1346 "==> nxge_mac_ctrl_init: port<%d>: " 1347 "disable pause", portn)); 1348 val &= ~XMAC_RX_CFG_RX_PAUSE_EN; 1349 } 1350 } 1351 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 1352 } else if (portt == PORT_TYPE_BMAC) { 1353 /* Reading the current MAC CTRL Config Register for BMAC */ 1354 BMAC_REG_RD(handle, portn, MAC_CTRL_CONFIG_REG, &val); 1355 1356 /* Setup MAC CTRL Configuration for BMAC */ 1357 if (statsp->mac_stats.adv_cap_asmpause) { 1358 if (statsp->mac_stats.adv_cap_pause) { 1359 /* 1360 * If adv_cap_asmpause is 1 and adv_cap_pause 1361 * is 1, disable receive pause. Send pause 1362 * is not supported 1363 */ 1364 val &= ~MAC_CTRL_CFG_RECV_PAUSE_EN; 1365 } else { 1366 /* 1367 * If adv_cap_asmpause is 1 and adv_cap_pause 1368 * is 0, enable receive pause and disable 1369 * send pause. 1370 */ 1371 val |= MAC_CTRL_CFG_RECV_PAUSE_EN; 1372 val &= ~MAC_CTRL_CFG_SEND_PAUSE_EN; 1373 } 1374 } else { 1375 if (statsp->mac_stats.adv_cap_pause) { 1376 /* 1377 * If adv_cap_asmpause is 0 and adv_cap_pause 1378 * is 1, enable receive pause. Send pause is 1379 * not supported. 1380 */ 1381 val |= MAC_CTRL_CFG_RECV_PAUSE_EN; 1382 } else { 1383 /* 1384 * If adv_cap_asmpause is 0 and adv_cap_pause 1385 * is 0, pause capability is not available in 1386 * either direction. 1387 */ 1388 val &= (~MAC_CTRL_CFG_SEND_PAUSE_EN & 1389 ~MAC_CTRL_CFG_RECV_PAUSE_EN); 1390 } 1391 } 1392 BMAC_REG_WR(handle, portn, MAC_CTRL_CONFIG_REG, val); 1393 } 1394 1395 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_mac_ctrl_init: port<%d>", 1396 portn)); 1397 1398 return (NXGE_OK); 1399 } 1400 1401 /* Initialize the Internal Serdes */ 1402 1403 nxge_status_t 1404 nxge_serdes_init(p_nxge_t nxgep) 1405 { 1406 p_nxge_stats_t statsp; 1407 #ifdef NXGE_DEBUG 1408 uint8_t portn; 1409 #endif 1410 nxge_status_t status = NXGE_OK; 1411 1412 #ifdef NXGE_DEBUG 1413 portn = nxgep->mac.portnum; 1414 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1415 "==> nxge_serdes_init port<%d>", portn)); 1416 #endif 1417 1418 if (nxgep->xcvr.serdes_init) { 1419 statsp = nxgep->statsp; 1420 status = nxgep->xcvr.serdes_init(nxgep); 1421 if (status != NXGE_OK) 1422 goto fail; 1423 statsp->mac_stats.serdes_inits++; 1424 } 1425 1426 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_serdes_init port<%d>", 1427 portn)); 1428 1429 return (NXGE_OK); 1430 1431 fail: 1432 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1433 "nxge_serdes_init: Failed to initialize serdes for port<%d>", 1434 portn)); 1435 1436 return (status); 1437 } 1438 1439 /* Initialize the TI Hedwig Internal Serdes (N2-NIU only) */ 1440 1441 static nxge_status_t 1442 nxge_n2_serdes_init(p_nxge_t nxgep) 1443 { 1444 uint8_t portn; 1445 int chan; 1446 esr_ti_cfgpll_l_t pll_cfg_l; 1447 esr_ti_cfgpll_l_t pll_sts_l; 1448 esr_ti_cfgrx_l_t rx_cfg_l; 1449 esr_ti_cfgrx_h_t rx_cfg_h; 1450 esr_ti_cfgtx_l_t tx_cfg_l; 1451 esr_ti_cfgtx_h_t tx_cfg_h; 1452 #ifdef NXGE_DEBUG 1453 esr_ti_testcfg_t cfg; 1454 #endif 1455 esr_ti_testcfg_t test_cfg; 1456 nxge_status_t status = NXGE_OK; 1457 1458 portn = nxgep->mac.portnum; 1459 1460 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_n2_serdes_init port<%d>", 1461 portn)); 1462 1463 tx_cfg_l.value = 0; 1464 tx_cfg_h.value = 0; 1465 rx_cfg_l.value = 0; 1466 rx_cfg_h.value = 0; 1467 pll_cfg_l.value = 0; 1468 pll_sts_l.value = 0; 1469 test_cfg.value = 0; 1470 1471 /* 1472 * If the nxge driver has been plumbed without a link, then it will 1473 * detect a link up when a cable connecting to an anto-negotiation 1474 * partner is plugged into the port. Because the TN1010 PHY supports 1475 * both 1G and 10G speeds, the driver must re-configure the 1476 * Neptune/NIU according to the negotiated speed. nxge_n2_serdes_init 1477 * is called at the post-link-up reconfiguration time. Here it calls 1478 * nxge_set_tn1010_param to set portmode before re-initializing 1479 * the serdes. 1480 */ 1481 if (nxgep->mac.portmode == PORT_1G_TN1010 || 1482 nxgep->mac.portmode == PORT_10G_TN1010) { 1483 if (nxge_set_tn1010_param(nxgep) != NXGE_OK) { 1484 goto fail; 1485 } 1486 } 1487 1488 if (nxgep->mac.portmode == PORT_10G_FIBER || 1489 nxgep->mac.portmode == PORT_10G_TN1010 || 1490 nxgep->mac.portmode == PORT_10G_SERDES) { 1491 /* 0x0E01 */ 1492 tx_cfg_l.bits.entx = 1; 1493 tx_cfg_l.bits.swing = CFGTX_SWING_1375MV; 1494 1495 /* 0x9101 */ 1496 rx_cfg_l.bits.enrx = 1; 1497 rx_cfg_l.bits.term = CFGRX_TERM_0P8VDDT; 1498 rx_cfg_l.bits.align = CFGRX_ALIGN_EN; 1499 rx_cfg_l.bits.los = CFGRX_LOS_LOTHRES; 1500 1501 /* 0x0008 */ 1502 rx_cfg_h.bits.eq = CFGRX_EQ_ADAPTIVE_LP_ADAPTIVE_ZF; 1503 1504 /* Set loopback mode if necessary */ 1505 if (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes10g) { 1506 tx_cfg_l.bits.entest = 1; 1507 rx_cfg_l.bits.entest = 1; 1508 test_cfg.bits.loopback = TESTCFG_INNER_CML_DIS_LOOPBACK; 1509 if ((status = nxge_mdio_write(nxgep, portn, 1510 ESR_N2_DEV_ADDR, 1511 ESR_N2_TEST_CFG_REG, test_cfg.value)) != NXGE_OK) 1512 goto fail; 1513 } 1514 1515 /* Initialize PLL for 10G */ 1516 pll_cfg_l.bits.mpy = CFGPLL_MPY_10X; 1517 pll_cfg_l.bits.enpll = 1; 1518 pll_sts_l.bits.enpll = 1; 1519 if ((status = nxge_mdio_write(nxgep, portn, ESR_N2_DEV_ADDR, 1520 ESR_N2_PLL_CFG_L_REG, pll_cfg_l.value)) != NXGE_OK) 1521 goto fail; 1522 1523 if ((status = nxge_mdio_write(nxgep, portn, ESR_N2_DEV_ADDR, 1524 ESR_N2_PLL_STS_L_REG, pll_sts_l.value)) != NXGE_OK) 1525 goto fail; 1526 1527 #ifdef NXGE_DEBUG 1528 nxge_mdio_read(nxgep, portn, ESR_N2_DEV_ADDR, 1529 ESR_N2_PLL_CFG_L_REG, &cfg.value); 1530 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1531 "==> nxge_n2_serdes_init port<%d>: PLL cfg.l 0x%x (0x%x)", 1532 portn, pll_cfg_l.value, cfg.value)); 1533 1534 nxge_mdio_read(nxgep, portn, ESR_N2_DEV_ADDR, 1535 ESR_N2_PLL_STS_L_REG, &cfg.value); 1536 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1537 "==> nxge_n2_serdes_init port<%d>: PLL sts.l 0x%x (0x%x)", 1538 portn, pll_sts_l.value, cfg.value)); 1539 #endif 1540 } else if (nxgep->mac.portmode == PORT_1G_FIBER || 1541 nxgep->mac.portmode == PORT_1G_TN1010 || 1542 nxgep->mac.portmode == PORT_1G_SERDES) { 1543 /* 0x0E21 */ 1544 tx_cfg_l.bits.entx = 1; 1545 tx_cfg_l.bits.rate = CFGTX_RATE_HALF; 1546 tx_cfg_l.bits.swing = CFGTX_SWING_1375MV; 1547 1548 /* 0x9121 */ 1549 rx_cfg_l.bits.enrx = 1; 1550 rx_cfg_l.bits.rate = CFGRX_RATE_HALF; 1551 rx_cfg_l.bits.term = CFGRX_TERM_0P8VDDT; 1552 rx_cfg_l.bits.align = CFGRX_ALIGN_EN; 1553 rx_cfg_l.bits.los = CFGRX_LOS_LOTHRES; 1554 1555 if (portn == 0) { 1556 /* 0x8 */ 1557 rx_cfg_h.bits.eq = CFGRX_EQ_ADAPTIVE_LP_ADAPTIVE_ZF; 1558 } 1559 1560 /* Initialize PLL for 1G */ 1561 pll_cfg_l.bits.mpy = CFGPLL_MPY_8X; 1562 pll_cfg_l.bits.enpll = 1; 1563 pll_sts_l.bits.enpll = 1; 1564 if ((status = nxge_mdio_write(nxgep, portn, ESR_N2_DEV_ADDR, 1565 ESR_N2_PLL_CFG_L_REG, pll_cfg_l.value)) != NXGE_OK) 1566 goto fail; 1567 1568 if ((status = nxge_mdio_write(nxgep, portn, ESR_N2_DEV_ADDR, 1569 ESR_N2_PLL_STS_L_REG, pll_sts_l.value)) != NXGE_OK) 1570 goto fail; 1571 1572 #ifdef NXGE_DEBUG 1573 nxge_mdio_read(nxgep, portn, ESR_N2_DEV_ADDR, 1574 ESR_N2_PLL_CFG_L_REG, &cfg.value); 1575 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1576 "==> nxge_n2_serdes_init port<%d>: PLL cfg.l 0x%x (0x%x)", 1577 portn, pll_cfg_l.value, cfg.value)); 1578 1579 nxge_mdio_read(nxgep, portn, ESR_N2_DEV_ADDR, 1580 ESR_N2_PLL_STS_L_REG, &cfg.value); 1581 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1582 "==> nxge_n2_serdes_init port<%d>: PLL sts.l 0x%x (0x%x)", 1583 portn, pll_sts_l.value, cfg.value)); 1584 #endif 1585 1586 /* Set loopback mode if necessary */ 1587 if (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes1000) { 1588 tx_cfg_l.bits.entest = 1; 1589 rx_cfg_l.bits.entest = 1; 1590 test_cfg.bits.loopback = TESTCFG_INNER_CML_DIS_LOOPBACK; 1591 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1592 "==> nxge_n2_serdes_init port<%d>: loopback 0x%x", 1593 portn, test_cfg.value)); 1594 if ((status = nxge_mdio_write(nxgep, portn, 1595 ESR_N2_DEV_ADDR, 1596 ESR_N2_TEST_CFG_REG, test_cfg.value)) != NXGE_OK) { 1597 goto fail; 1598 } 1599 } 1600 } else { 1601 goto fail; 1602 } 1603 1604 /* MIF_REG_WR(handle, MIF_MASK_REG, ~mask); */ 1605 1606 NXGE_DELAY(20); 1607 1608 /* init TX channels */ 1609 for (chan = 0; chan < 4; chan++) { 1610 if ((status = nxge_mdio_write(nxgep, portn, ESR_N2_DEV_ADDR, 1611 ESR_N2_TX_CFG_L_REG_ADDR(chan), tx_cfg_l.value)) != NXGE_OK) 1612 goto fail; 1613 1614 if ((status = nxge_mdio_write(nxgep, portn, ESR_N2_DEV_ADDR, 1615 ESR_N2_TX_CFG_H_REG_ADDR(chan), tx_cfg_h.value)) != NXGE_OK) 1616 goto fail; 1617 1618 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1619 "==> nxge_n2_serdes_init port<%d>: chan %d tx_cfg_l 0x%x", 1620 portn, chan, tx_cfg_l.value)); 1621 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1622 "==> nxge_n2_serdes_init port<%d>: chan %d tx_cfg_h 0x%x", 1623 portn, chan, tx_cfg_h.value)); 1624 } 1625 1626 /* init RX channels */ 1627 for (chan = 0; chan < 4; chan++) { 1628 if ((status = nxge_mdio_write(nxgep, portn, ESR_N2_DEV_ADDR, 1629 ESR_N2_RX_CFG_L_REG_ADDR(chan), rx_cfg_l.value)) != NXGE_OK) 1630 goto fail; 1631 1632 if ((status = nxge_mdio_write(nxgep, portn, ESR_N2_DEV_ADDR, 1633 ESR_N2_RX_CFG_H_REG_ADDR(chan), rx_cfg_h.value)) != NXGE_OK) 1634 goto fail; 1635 1636 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1637 "==> nxge_n2_serdes_init port<%d>: chan %d rx_cfg_l 0x%x", 1638 portn, chan, rx_cfg_l.value)); 1639 1640 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1641 "==> nxge_n2_serdes_init port<%d>: chan %d rx_cfg_h 0x%x", 1642 portn, chan, rx_cfg_h.value)); 1643 } 1644 1645 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_n2_serdes_init port<%d>", 1646 portn)); 1647 1648 return (NXGE_OK); 1649 fail: 1650 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1651 "nxge_n2_serdes_init: Failed to initialize N2 serdes for port<%d>", 1652 portn)); 1653 1654 return (status); 1655 } 1656 1657 /* Initialize the Neptune Internal Serdes for 10G (Neptune only) */ 1658 1659 static nxge_status_t 1660 nxge_neptune_10G_serdes_init(p_nxge_t nxgep) 1661 { 1662 npi_handle_t handle; 1663 uint8_t portn; 1664 int chan, i; 1665 sr_rx_tx_ctrl_l_t rx_tx_ctrl_l; 1666 sr_rx_tx_ctrl_h_t rx_tx_ctrl_h; 1667 sr_glue_ctrl0_l_t glue_ctrl0_l; 1668 sr_glue_ctrl0_h_t glue_ctrl0_h; 1669 uint64_t val; 1670 uint16_t val16l; 1671 uint16_t val16h; 1672 nxge_status_t status = NXGE_OK; 1673 1674 portn = nxgep->mac.portnum; 1675 1676 if ((portn != 0) && (portn != 1)) 1677 return (NXGE_OK); 1678 1679 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1680 "==> nxge_neptune_10G_serdes_init port<%d>", portn)); 1681 handle = nxgep->npi_handle; 1682 switch (portn) { 1683 case 0: 1684 /* Reset Serdes */ 1685 ESR_REG_WR(handle, ESR_RESET_REG, ESR_RESET_0); 1686 NXGE_DELAY(20); 1687 ESR_REG_WR(handle, ESR_RESET_REG, 0x0); 1688 NXGE_DELAY(2000); 1689 1690 /* Configure Serdes to 10G mode */ 1691 ESR_REG_WR(handle, ESR_0_PLL_CONFIG_REG, 1692 ESR_PLL_CFG_10G_SERDES); 1693 1694 ESR_REG_WR(handle, ESR_0_CONTROL_REG, 1695 ESR_CTL_EN_SYNCDET_0 | ESR_CTL_EN_SYNCDET_1 | 1696 ESR_CTL_EN_SYNCDET_2 | ESR_CTL_EN_SYNCDET_3 | 1697 (0x5 << ESR_CTL_OUT_EMPH_0_SHIFT) | 1698 (0x5 << ESR_CTL_OUT_EMPH_1_SHIFT) | 1699 (0x5 << ESR_CTL_OUT_EMPH_2_SHIFT) | 1700 (0x5 << ESR_CTL_OUT_EMPH_3_SHIFT) | 1701 (0x5 << ESR_CTL_OUT_EMPH_3_SHIFT) | 1702 (0x1 << ESR_CTL_LOSADJ_0_SHIFT) | 1703 (0x1 << ESR_CTL_LOSADJ_1_SHIFT) | 1704 (0x1 << ESR_CTL_LOSADJ_2_SHIFT) | 1705 (0x1 << ESR_CTL_LOSADJ_3_SHIFT)); 1706 1707 /* Set Serdes0 Internal Loopback if necessary */ 1708 if (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes10g) { 1709 ESR_REG_WR(handle, 1710 ESR_0_TEST_CONFIG_REG, 1711 ESR_PAD_LOOPBACK_CH3 | 1712 ESR_PAD_LOOPBACK_CH2 | 1713 ESR_PAD_LOOPBACK_CH1 | 1714 ESR_PAD_LOOPBACK_CH0); 1715 } else { 1716 ESR_REG_WR(handle, ESR_0_TEST_CONFIG_REG, 0); 1717 } 1718 break; 1719 case 1: 1720 /* Reset Serdes */ 1721 ESR_REG_WR(handle, ESR_RESET_REG, ESR_RESET_1); 1722 NXGE_DELAY(20); 1723 ESR_REG_WR(handle, ESR_RESET_REG, 0x0); 1724 NXGE_DELAY(2000); 1725 1726 /* Configure Serdes to 10G mode */ 1727 ESR_REG_WR(handle, ESR_1_PLL_CONFIG_REG, 1728 ESR_PLL_CFG_10G_SERDES); 1729 1730 ESR_REG_WR(handle, ESR_1_CONTROL_REG, 1731 ESR_CTL_EN_SYNCDET_0 | ESR_CTL_EN_SYNCDET_1 | 1732 ESR_CTL_EN_SYNCDET_2 | ESR_CTL_EN_SYNCDET_3 | 1733 (0x5 << ESR_CTL_OUT_EMPH_0_SHIFT) | 1734 (0x5 << ESR_CTL_OUT_EMPH_1_SHIFT) | 1735 (0x5 << ESR_CTL_OUT_EMPH_2_SHIFT) | 1736 (0x5 << ESR_CTL_OUT_EMPH_3_SHIFT) | 1737 (0x5 << ESR_CTL_OUT_EMPH_3_SHIFT) | 1738 (0x1 << ESR_CTL_LOSADJ_0_SHIFT) | 1739 (0x1 << ESR_CTL_LOSADJ_1_SHIFT) | 1740 (0x1 << ESR_CTL_LOSADJ_2_SHIFT) | 1741 (0x1 << ESR_CTL_LOSADJ_3_SHIFT)); 1742 1743 /* Set Serdes1 Internal Loopback if necessary */ 1744 if (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes10g) { 1745 ESR_REG_WR(handle, ESR_1_TEST_CONFIG_REG, 1746 ESR_PAD_LOOPBACK_CH3 | ESR_PAD_LOOPBACK_CH2 | 1747 ESR_PAD_LOOPBACK_CH1 | ESR_PAD_LOOPBACK_CH0); 1748 } else { 1749 ESR_REG_WR(handle, ESR_1_TEST_CONFIG_REG, 0); 1750 } 1751 break; 1752 default: 1753 /* Nothing to do here */ 1754 goto done; 1755 } 1756 1757 /* init TX RX channels */ 1758 for (chan = 0; chan < 4; chan++) { 1759 if ((status = nxge_mdio_read(nxgep, portn, 1760 ESR_NEPTUNE_DEV_ADDR, ESR_NEP_RX_TX_CONTROL_L_ADDR(chan), 1761 &rx_tx_ctrl_l.value)) != NXGE_OK) 1762 goto fail; 1763 if ((status = nxge_mdio_read(nxgep, portn, 1764 ESR_NEPTUNE_DEV_ADDR, ESR_NEP_RX_TX_CONTROL_H_ADDR(chan), 1765 &rx_tx_ctrl_h.value)) != NXGE_OK) 1766 goto fail; 1767 if ((status = nxge_mdio_read(nxgep, portn, 1768 ESR_NEPTUNE_DEV_ADDR, ESR_NEP_GLUE_CONTROL0_L_ADDR(chan), 1769 &glue_ctrl0_l.value)) != NXGE_OK) 1770 goto fail; 1771 if ((status = nxge_mdio_read(nxgep, portn, 1772 ESR_NEPTUNE_DEV_ADDR, ESR_NEP_GLUE_CONTROL0_H_ADDR(chan), 1773 &glue_ctrl0_h.value)) != NXGE_OK) 1774 goto fail; 1775 rx_tx_ctrl_l.bits.enstretch = 1; 1776 rx_tx_ctrl_h.bits.vmuxlo = 2; 1777 rx_tx_ctrl_h.bits.vpulselo = 2; 1778 glue_ctrl0_l.bits.rxlosenable = 1; 1779 glue_ctrl0_l.bits.samplerate = 0xF; 1780 glue_ctrl0_l.bits.thresholdcount = 0xFF; 1781 glue_ctrl0_h.bits.bitlocktime = BITLOCKTIME_300_CYCLES; 1782 if ((status = nxge_mdio_write(nxgep, portn, 1783 ESR_NEPTUNE_DEV_ADDR, ESR_NEP_RX_TX_CONTROL_L_ADDR(chan), 1784 rx_tx_ctrl_l.value)) != NXGE_OK) 1785 goto fail; 1786 if ((status = nxge_mdio_write(nxgep, portn, 1787 ESR_NEPTUNE_DEV_ADDR, ESR_NEP_RX_TX_CONTROL_H_ADDR(chan), 1788 rx_tx_ctrl_h.value)) != NXGE_OK) 1789 goto fail; 1790 if ((status = nxge_mdio_write(nxgep, portn, 1791 ESR_NEPTUNE_DEV_ADDR, ESR_NEP_GLUE_CONTROL0_L_ADDR(chan), 1792 glue_ctrl0_l.value)) != NXGE_OK) 1793 goto fail; 1794 if ((status = nxge_mdio_write(nxgep, portn, 1795 ESR_NEPTUNE_DEV_ADDR, ESR_NEP_GLUE_CONTROL0_H_ADDR(chan), 1796 glue_ctrl0_h.value)) != NXGE_OK) 1797 goto fail; 1798 } 1799 1800 /* Apply Tx core reset */ 1801 if ((status = nxge_mdio_write(nxgep, portn, 1802 ESR_NEPTUNE_DEV_ADDR, ESR_NEP_RX_TX_RESET_CONTROL_L_ADDR(), 1803 (uint16_t)0)) != NXGE_OK) 1804 goto fail; 1805 1806 if ((status = nxge_mdio_write(nxgep, portn, ESR_NEPTUNE_DEV_ADDR, 1807 ESR_NEP_RX_TX_RESET_CONTROL_H_ADDR(), (uint16_t)0xffff)) != 1808 NXGE_OK) 1809 goto fail; 1810 1811 NXGE_DELAY(200); 1812 1813 /* Apply Rx core reset */ 1814 if ((status = nxge_mdio_write(nxgep, portn, ESR_NEPTUNE_DEV_ADDR, 1815 ESR_NEP_RX_TX_RESET_CONTROL_L_ADDR(), (uint16_t)0xffff)) != 1816 NXGE_OK) 1817 goto fail; 1818 1819 NXGE_DELAY(200); 1820 if ((status = nxge_mdio_write(nxgep, portn, ESR_NEPTUNE_DEV_ADDR, 1821 ESR_NEP_RX_TX_RESET_CONTROL_H_ADDR(), (uint16_t)0)) != NXGE_OK) 1822 goto fail; 1823 1824 NXGE_DELAY(200); 1825 if ((status = nxge_mdio_read(nxgep, portn, 1826 ESR_NEPTUNE_DEV_ADDR, ESR_NEP_RX_TX_RESET_CONTROL_L_ADDR(), 1827 &val16l)) != NXGE_OK) 1828 goto fail; 1829 if ((status = nxge_mdio_read(nxgep, portn, ESR_NEPTUNE_DEV_ADDR, 1830 ESR_NEP_RX_TX_RESET_CONTROL_H_ADDR(), &val16h)) != NXGE_OK) 1831 goto fail; 1832 if ((val16l != 0) || (val16h != 0)) { 1833 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1834 "Failed to reset port<%d> XAUI Serdes " 1835 "(val16l 0x%x val16h 0x%x)", 1836 portn, val16l, val16h)); 1837 } 1838 1839 if (portn == 0) { 1840 /* Wait for serdes to be ready */ 1841 for (i = 0; i < MAX_SERDES_RDY_RETRIES; i++) { 1842 ESR_REG_RD(handle, ESR_INTERNAL_SIGNALS_REG, &val); 1843 if ((val & ESR_SIG_P0_BITS_MASK) != 1844 (ESR_SIG_SERDES_RDY0_P0 | ESR_SIG_DETECT0_P0 | 1845 ESR_SIG_XSERDES_RDY_P0 | 1846 ESR_SIG_XDETECT_P0_CH3 | 1847 ESR_SIG_XDETECT_P0_CH2 | 1848 ESR_SIG_XDETECT_P0_CH1 | 1849 ESR_SIG_XDETECT_P0_CH0)) 1850 1851 NXGE_DELAY(SERDES_RDY_WT_INTERVAL); 1852 else 1853 break; 1854 } 1855 1856 if (i == MAX_SERDES_RDY_RETRIES) { 1857 /* 1858 * RDY signal stays low may due to the absent of the 1859 * external PHY, it is not an error condition. But still 1860 * print the message for the debugging purpose when link 1861 * stays down 1862 */ 1863 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1864 "nxge_neptune_10G_serdes_init: " 1865 "Serdes/signal for port<%d> not ready", portn)); 1866 goto done; 1867 } 1868 } else if (portn == 1) { 1869 /* Wait for serdes to be ready */ 1870 for (i = 0; i < MAX_SERDES_RDY_RETRIES; i++) { 1871 ESR_REG_RD(handle, ESR_INTERNAL_SIGNALS_REG, &val); 1872 if ((val & ESR_SIG_P1_BITS_MASK) != 1873 (ESR_SIG_SERDES_RDY0_P1 | ESR_SIG_DETECT0_P1 | 1874 ESR_SIG_XSERDES_RDY_P1 | 1875 ESR_SIG_XDETECT_P1_CH3 | 1876 ESR_SIG_XDETECT_P1_CH2 | 1877 ESR_SIG_XDETECT_P1_CH1 | 1878 ESR_SIG_XDETECT_P1_CH0)) 1879 1880 NXGE_DELAY(SERDES_RDY_WT_INTERVAL); 1881 else 1882 break; 1883 } 1884 1885 if (i == MAX_SERDES_RDY_RETRIES) { 1886 /* 1887 * RDY signal stays low may due to the absent of the 1888 * external PHY, it is not an error condition. But still 1889 * print the message for the debugging purpose when link 1890 * stays down 1891 */ 1892 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1893 "nxge_neptune_10G_serdes_init: " 1894 "Serdes/signal for port<%d> not ready", portn)); 1895 goto done; 1896 } 1897 } 1898 1899 done: 1900 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1901 "<== nxge_neptune_10G_serdes_init port<%d>", portn)); 1902 1903 return (NXGE_OK); 1904 fail: 1905 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1906 "nxge_neptune_10G_serdes_init: " 1907 "Failed to initialize Neptune serdes for port<%d>", portn)); 1908 1909 return (status); 1910 } 1911 1912 /* Initialize Neptune Internal Serdes for 1G (Neptune only) */ 1913 1914 static nxge_status_t 1915 nxge_1G_serdes_init(p_nxge_t nxgep) 1916 { 1917 npi_handle_t handle; 1918 uint8_t portn; 1919 int chan; 1920 sr_rx_tx_ctrl_l_t rx_tx_ctrl_l; 1921 sr_rx_tx_ctrl_h_t rx_tx_ctrl_h; 1922 sr_glue_ctrl0_l_t glue_ctrl0_l; 1923 sr_glue_ctrl0_h_t glue_ctrl0_h; 1924 uint64_t val; 1925 uint16_t val16l; 1926 uint16_t val16h; 1927 nxge_status_t status = NXGE_OK; 1928 1929 portn = nxgep->mac.portnum; 1930 1931 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1932 "==> nxge_1G_serdes_init port<%d>", portn)); 1933 1934 handle = nxgep->npi_handle; 1935 1936 switch (portn) { 1937 case 0: 1938 /* Assert the reset register */ 1939 ESR_REG_RD(handle, ESR_RESET_REG, &val); 1940 val |= ESR_RESET_0; 1941 ESR_REG_WR(handle, ESR_RESET_REG, val); 1942 1943 /* Set the PLL register to 0x79 */ 1944 ESR_REG_WR(handle, ESR_0_PLL_CONFIG_REG, 1945 ESR_PLL_CFG_1G_SERDES); 1946 1947 /* Set the control register to 0x249249f */ 1948 ESR_REG_WR(handle, ESR_0_CONTROL_REG, ESR_CTL_1G_SERDES); 1949 1950 /* Set Serdes0 Internal Loopback if necessary */ 1951 if (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes1000) { 1952 /* Set pad loopback modes 0xaa */ 1953 ESR_REG_WR(handle, ESR_0_TEST_CONFIG_REG, 1954 ESR_TSTCFG_LBTEST_PAD); 1955 } else { 1956 ESR_REG_WR(handle, ESR_0_TEST_CONFIG_REG, 0); 1957 } 1958 1959 /* Deassert the reset register */ 1960 ESR_REG_RD(handle, ESR_RESET_REG, &val); 1961 val &= ~ESR_RESET_0; 1962 ESR_REG_WR(handle, ESR_RESET_REG, val); 1963 break; 1964 1965 case 1: 1966 /* Assert the reset register */ 1967 ESR_REG_RD(handle, ESR_RESET_REG, &val); 1968 val |= ESR_RESET_1; 1969 ESR_REG_WR(handle, ESR_RESET_REG, val); 1970 1971 /* Set PLL register to 0x79 */ 1972 ESR_REG_WR(handle, ESR_1_PLL_CONFIG_REG, 1973 ESR_PLL_CFG_1G_SERDES); 1974 1975 /* Set the control register to 0x249249f */ 1976 ESR_REG_WR(handle, ESR_1_CONTROL_REG, ESR_CTL_1G_SERDES); 1977 1978 /* Set Serdes1 Internal Loopback if necessary */ 1979 if (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes1000) { 1980 /* Set pad loopback mode 0xaa */ 1981 ESR_REG_WR(handle, ESR_1_TEST_CONFIG_REG, 1982 ESR_TSTCFG_LBTEST_PAD); 1983 } else { 1984 ESR_REG_WR(handle, ESR_1_TEST_CONFIG_REG, 0); 1985 } 1986 1987 /* Deassert the reset register */ 1988 ESR_REG_RD(handle, ESR_RESET_REG, &val); 1989 val &= ~ESR_RESET_1; 1990 ESR_REG_WR(handle, ESR_RESET_REG, val); 1991 break; 1992 1993 default: 1994 /* Nothing to do here */ 1995 goto done; 1996 } 1997 1998 /* init TX RX channels */ 1999 for (chan = 0; chan < 4; chan++) { 2000 if ((status = nxge_mdio_read(nxgep, portn, 2001 ESR_NEPTUNE_DEV_ADDR, ESR_NEP_RX_TX_CONTROL_L_ADDR(chan), 2002 &rx_tx_ctrl_l.value)) != NXGE_OK) { 2003 goto fail; 2004 } 2005 if ((status = nxge_mdio_read(nxgep, portn, 2006 ESR_NEPTUNE_DEV_ADDR, ESR_NEP_RX_TX_CONTROL_H_ADDR(chan), 2007 &rx_tx_ctrl_h.value)) != NXGE_OK) { 2008 goto fail; 2009 } 2010 if ((status = nxge_mdio_read(nxgep, portn, 2011 ESR_NEPTUNE_DEV_ADDR, ESR_NEP_GLUE_CONTROL0_L_ADDR(chan), 2012 &glue_ctrl0_l.value)) != NXGE_OK) { 2013 goto fail; 2014 } 2015 if ((status = nxge_mdio_read(nxgep, portn, 2016 ESR_NEPTUNE_DEV_ADDR, ESR_NEP_GLUE_CONTROL0_H_ADDR(chan), 2017 &glue_ctrl0_h.value)) != NXGE_OK) { 2018 goto fail; 2019 } 2020 2021 rx_tx_ctrl_l.bits.enstretch = 1; 2022 rx_tx_ctrl_h.bits.vmuxlo = 2; 2023 rx_tx_ctrl_h.bits.vpulselo = 2; 2024 glue_ctrl0_l.bits.rxlosenable = 1; 2025 glue_ctrl0_l.bits.samplerate = 0xF; 2026 glue_ctrl0_l.bits.thresholdcount = 0xFF; 2027 glue_ctrl0_h.bits.bitlocktime = BITLOCKTIME_300_CYCLES; 2028 if ((status = nxge_mdio_write(nxgep, portn, 2029 ESR_NEPTUNE_DEV_ADDR, ESR_NEP_RX_TX_CONTROL_L_ADDR(chan), 2030 rx_tx_ctrl_l.value)) != NXGE_OK) { 2031 goto fail; 2032 } 2033 if ((status = nxge_mdio_write(nxgep, portn, 2034 ESR_NEPTUNE_DEV_ADDR, ESR_NEP_RX_TX_CONTROL_H_ADDR(chan), 2035 rx_tx_ctrl_h.value)) != NXGE_OK) { 2036 goto fail; 2037 } 2038 if ((status = nxge_mdio_write(nxgep, portn, 2039 ESR_NEPTUNE_DEV_ADDR, ESR_NEP_GLUE_CONTROL0_L_ADDR(chan), 2040 glue_ctrl0_l.value)) != NXGE_OK) { 2041 goto fail; 2042 } 2043 if ((status = nxge_mdio_write(nxgep, portn, 2044 ESR_NEPTUNE_DEV_ADDR, ESR_NEP_GLUE_CONTROL0_H_ADDR(chan), 2045 glue_ctrl0_h.value)) != NXGE_OK) { 2046 goto fail; 2047 } 2048 } 2049 2050 if ((status = nxge_mdio_write(nxgep, portn, ESR_NEPTUNE_DEV_ADDR, 2051 ESR_NEP_RX_POWER_CONTROL_L_ADDR(), 0xfff)) != NXGE_OK) { 2052 goto fail; 2053 } 2054 if ((status = nxge_mdio_write(nxgep, portn, ESR_NEPTUNE_DEV_ADDR, 2055 ESR_NEP_RX_POWER_CONTROL_H_ADDR(), 0xfff)) != NXGE_OK) { 2056 goto fail; 2057 } 2058 if ((status = nxge_mdio_write(nxgep, portn, ESR_NEPTUNE_DEV_ADDR, 2059 ESR_NEP_TX_POWER_CONTROL_L_ADDR(), 0x70)) != NXGE_OK) { 2060 goto fail; 2061 } 2062 if ((status = nxge_mdio_write(nxgep, portn, ESR_NEPTUNE_DEV_ADDR, 2063 ESR_NEP_TX_POWER_CONTROL_H_ADDR(), 0xfff)) != NXGE_OK) { 2064 goto fail; 2065 } 2066 2067 /* Apply Tx core reset */ 2068 if ((status = nxge_mdio_write(nxgep, portn, ESR_NEPTUNE_DEV_ADDR, 2069 ESR_NEP_RX_TX_RESET_CONTROL_L_ADDR(), (uint16_t)0)) != NXGE_OK) { 2070 goto fail; 2071 } 2072 2073 if ((status = nxge_mdio_write(nxgep, portn, ESR_NEPTUNE_DEV_ADDR, 2074 ESR_NEP_RX_TX_RESET_CONTROL_H_ADDR(), (uint16_t)0xffff)) != 2075 NXGE_OK) { 2076 goto fail; 2077 } 2078 2079 NXGE_DELAY(200); 2080 2081 /* Apply Rx core reset */ 2082 if ((status = nxge_mdio_write(nxgep, portn, ESR_NEPTUNE_DEV_ADDR, 2083 ESR_NEP_RX_TX_RESET_CONTROL_L_ADDR(), (uint16_t)0xffff)) != 2084 NXGE_OK) { 2085 goto fail; 2086 } 2087 2088 NXGE_DELAY(200); 2089 if ((status = nxge_mdio_write(nxgep, portn, ESR_NEPTUNE_DEV_ADDR, 2090 ESR_NEP_RX_TX_RESET_CONTROL_H_ADDR(), (uint16_t)0)) != NXGE_OK) { 2091 goto fail; 2092 } 2093 2094 NXGE_DELAY(200); 2095 if ((status = nxge_mdio_read(nxgep, portn, ESR_NEPTUNE_DEV_ADDR, 2096 ESR_NEP_RX_TX_RESET_CONTROL_L_ADDR(), &val16l)) != NXGE_OK) { 2097 goto fail; 2098 } 2099 if ((status = nxge_mdio_read(nxgep, portn, ESR_NEPTUNE_DEV_ADDR, 2100 ESR_NEP_RX_TX_RESET_CONTROL_H_ADDR(), &val16h)) != NXGE_OK) { 2101 goto fail; 2102 } 2103 if ((val16l != 0) || (val16h != 0)) { 2104 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2105 "Failed to reset port<%d> XAUI Serdes " 2106 "(val16l 0x%x val16h 0x%x)", portn, val16l, val16h)); 2107 status = NXGE_ERROR; 2108 goto fail; 2109 } 2110 2111 NXGE_DELAY(200); 2112 ESR_REG_RD(handle, ESR_INTERNAL_SIGNALS_REG, &val); 2113 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 2114 "nxge_neptune_serdes_init: read internal signal reg port<%d> " 2115 "val 0x%x", portn, val)); 2116 if (portn == 0) { 2117 if ((val & ESR_SIG_P0_BITS_MASK_1G) != 2118 (ESR_SIG_SERDES_RDY0_P0 | ESR_SIG_DETECT0_P0)) { 2119 /* 2120 * RDY signal stays low may due to the absent of the 2121 * external PHY, it is not an error condition. But still 2122 * print the message for the debugging purpose when link 2123 * stays down 2124 */ 2125 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2126 "nxge_neptune_1G_serdes_init: " 2127 "Serdes/signal for port<%d> not ready", portn)); 2128 goto done; 2129 } 2130 } else if (portn == 1) { 2131 if ((val & ESR_SIG_P1_BITS_MASK_1G) != 2132 (ESR_SIG_SERDES_RDY0_P1 | ESR_SIG_DETECT0_P1)) { 2133 /* 2134 * RDY signal stays low may due to the absent of the 2135 * external PHY, it is not an error condition. But still 2136 * print the message for the debugging purpose when link 2137 * stays down 2138 */ 2139 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2140 "nxge_neptune_1G_serdes_init: " 2141 "Serdes/signal for port<%d> not ready", portn)); 2142 goto done; 2143 2144 } 2145 } 2146 done: 2147 2148 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 2149 "<== nxge_1G_serdes_init port<%d>", portn)); 2150 return (NXGE_OK); 2151 fail: 2152 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2153 "nxge_1G_serdes_init: " 2154 "Failed to initialize Neptune serdes for port<%d>", 2155 portn)); 2156 2157 return (status); 2158 } 2159 2160 /* Initialize the BCM 8704 xcvr */ 2161 2162 static nxge_status_t 2163 nxge_BCM8704_xcvr_init(p_nxge_t nxgep) 2164 { 2165 uint16_t val; 2166 #ifdef NXGE_DEBUG 2167 uint8_t portn; 2168 uint16_t val1; 2169 #endif 2170 uint8_t phy_port_addr; 2171 pmd_tx_control_t tx_ctl; 2172 control_t ctl; 2173 phyxs_control_t phyxs_ctl; 2174 pcs_control_t pcs_ctl; 2175 uint32_t delay = 0; 2176 optics_dcntr_t op_ctr; 2177 nxge_status_t status = NXGE_OK; 2178 #ifdef NXGE_DEBUG 2179 portn = nxgep->mac.portnum; 2180 #endif 2181 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_BCM8704_xcvr_init: port<%d>", 2182 portn)); 2183 2184 phy_port_addr = nxgep->statsp->mac_stats.xcvr_portn; 2185 2186 /* Reset the transceiver */ 2187 if ((status = nxge_mdio_read(nxgep, phy_port_addr, BCM8704_PHYXS_ADDR, 2188 BCM8704_PHYXS_CONTROL_REG, &phyxs_ctl.value)) != NXGE_OK) 2189 goto fail; 2190 2191 phyxs_ctl.bits.reset = 1; 2192 if ((status = nxge_mdio_write(nxgep, phy_port_addr, BCM8704_PHYXS_ADDR, 2193 BCM8704_PHYXS_CONTROL_REG, phyxs_ctl.value)) != NXGE_OK) 2194 goto fail; 2195 2196 do { 2197 drv_usecwait(500); 2198 if ((status = nxge_mdio_read(nxgep, phy_port_addr, 2199 BCM8704_PHYXS_ADDR, BCM8704_PHYXS_CONTROL_REG, 2200 &phyxs_ctl.value)) != NXGE_OK) 2201 goto fail; 2202 delay++; 2203 } while ((phyxs_ctl.bits.reset) && (delay < 100)); 2204 if (delay == 100) { 2205 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "nxge_xcvr_init: " 2206 "failed to reset Transceiver on port<%d>", portn)); 2207 status = NXGE_ERROR; 2208 goto fail; 2209 } 2210 2211 /* Set to 0x7FBF */ 2212 ctl.value = 0; 2213 ctl.bits.res1 = 0x3F; 2214 ctl.bits.optxon_lvl = 1; 2215 ctl.bits.oprxflt_lvl = 1; 2216 ctl.bits.optrxlos_lvl = 1; 2217 ctl.bits.optxflt_lvl = 1; 2218 ctl.bits.opprflt_lvl = 1; 2219 ctl.bits.obtmpflt_lvl = 1; 2220 ctl.bits.opbiasflt_lvl = 1; 2221 ctl.bits.optxrst_lvl = 1; 2222 if ((status = nxge_mdio_write(nxgep, phy_port_addr, 2223 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL_REG, ctl.value)) 2224 != NXGE_OK) 2225 goto fail; 2226 2227 /* Set to 0x164 */ 2228 tx_ctl.value = 0; 2229 tx_ctl.bits.tsck_lpwren = 1; 2230 tx_ctl.bits.tx_dac_txck = 0x2; 2231 tx_ctl.bits.tx_dac_txd = 0x1; 2232 tx_ctl.bits.xfp_clken = 1; 2233 if ((status = nxge_mdio_write(nxgep, phy_port_addr, 2234 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL_REG, 2235 tx_ctl.value)) != NXGE_OK) 2236 goto fail; 2237 /* 2238 * According to Broadcom's instruction, SW needs to read 2239 * back these registers twice after written. 2240 */ 2241 if ((status = nxge_mdio_read(nxgep, phy_port_addr, 2242 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL_REG, &val)) 2243 != NXGE_OK) 2244 goto fail; 2245 2246 if ((status = nxge_mdio_read(nxgep, phy_port_addr, 2247 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL_REG, &val)) 2248 != NXGE_OK) 2249 goto fail; 2250 2251 if ((status = nxge_mdio_read(nxgep, phy_port_addr, 2252 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL_REG, &val)) 2253 != NXGE_OK) 2254 goto fail; 2255 2256 if ((status = nxge_mdio_read(nxgep, phy_port_addr, 2257 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL_REG, &val)) 2258 != NXGE_OK) 2259 goto fail; 2260 2261 /* Enable Tx and Rx LEDs to be driven by traffic */ 2262 if ((status = nxge_mdio_read(nxgep, phy_port_addr, 2263 BCM8704_USER_DEV3_ADDR, BCM8704_USER_OPTICS_DIGITAL_CTRL_REG, 2264 &op_ctr.value)) != NXGE_OK) 2265 goto fail; 2266 if (NXGE_IS_XAUI_PLATFORM(nxgep)) { 2267 op_ctr.bits.gpio_sel = 0x1; 2268 } else { 2269 op_ctr.bits.gpio_sel = 0x3; 2270 } 2271 if ((status = nxge_mdio_write(nxgep, phy_port_addr, 2272 BCM8704_USER_DEV3_ADDR, BCM8704_USER_OPTICS_DIGITAL_CTRL_REG, 2273 op_ctr.value)) != NXGE_OK) 2274 goto fail; 2275 2276 NXGE_DELAY(1000000); 2277 2278 /* Set BCM8704 Internal Loopback mode if necessary */ 2279 if ((status = nxge_mdio_read(nxgep, phy_port_addr, 2280 BCM8704_PCS_DEV_ADDR, BCM8704_PCS_CONTROL_REG, &pcs_ctl.value)) 2281 != NXGE_OK) 2282 goto fail; 2283 if (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy10g) 2284 pcs_ctl.bits.loopback = 1; 2285 else 2286 pcs_ctl.bits.loopback = 0; 2287 if ((status = nxge_mdio_write(nxgep, phy_port_addr, 2288 BCM8704_PCS_DEV_ADDR, BCM8704_PCS_CONTROL_REG, pcs_ctl.value)) 2289 != NXGE_OK) 2290 goto fail; 2291 2292 status = nxge_mdio_read(nxgep, phy_port_addr, 0x1, 0xA, &val); 2293 if (status != NXGE_OK) 2294 goto fail; 2295 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 2296 "BCM8704 port<%d> Dev 1 Reg 0xA = 0x%x\n", portn, val)); 2297 status = nxge_mdio_read(nxgep, phy_port_addr, 0x3, 0x20, &val); 2298 if (status != NXGE_OK) 2299 goto fail; 2300 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 2301 "BCM8704 port<%d> Dev 3 Reg 0x20 = 0x%x\n", portn, val)); 2302 status = nxge_mdio_read(nxgep, phy_port_addr, 0x4, 0x18, &val); 2303 if (status != NXGE_OK) 2304 goto fail; 2305 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 2306 "BCM8704 port<%d> Dev 4 Reg 0x18 = 0x%x\n", portn, val)); 2307 2308 #ifdef NXGE_DEBUG 2309 /* Diagnose link issue if link is not up */ 2310 status = nxge_mdio_read(nxgep, phy_port_addr, BCM8704_USER_DEV3_ADDR, 2311 BCM8704_USER_ANALOG_STATUS0_REG, 2312 &val); 2313 if (status != NXGE_OK) 2314 goto fail; 2315 2316 status = nxge_mdio_read(nxgep, phy_port_addr, 2317 BCM8704_USER_DEV3_ADDR, BCM8704_USER_ANALOG_STATUS0_REG, &val); 2318 if (status != NXGE_OK) 2319 goto fail; 2320 2321 status = nxge_mdio_read(nxgep, phy_port_addr, 2322 BCM8704_USER_DEV3_ADDR, BCM8704_USER_TX_ALARM_STATUS_REG, &val1); 2323 if (status != NXGE_OK) 2324 goto fail; 2325 2326 status = nxge_mdio_read(nxgep, phy_port_addr, 2327 BCM8704_USER_DEV3_ADDR, BCM8704_USER_TX_ALARM_STATUS_REG, &val1); 2328 if (status != NXGE_OK) 2329 goto fail; 2330 2331 if (val != 0x3FC) { 2332 if ((val == 0x43BC) && (val1 != 0)) { 2333 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 2334 "Cable not connected to peer or bad" 2335 " cable on port<%d>\n", portn)); 2336 } else if (val == 0x639C) { 2337 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2338 "Optical module (XFP) is bad or absent" 2339 " on port<%d>\n", portn)); 2340 } 2341 } 2342 #endif 2343 2344 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_BCM8704_xcvr_init: port<%d>", 2345 portn)); 2346 return (NXGE_OK); 2347 2348 fail: 2349 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2350 "nxge_BCM8704_xcvr_init: failed to initialize transceiver for " 2351 "port<%d>", nxgep->mac.portnum)); 2352 return (NXGE_ERROR); 2353 } 2354 2355 /* Initialize the BCM 8706 Transceiver */ 2356 2357 static nxge_status_t 2358 nxge_BCM8706_xcvr_init(p_nxge_t nxgep) 2359 { 2360 uint8_t phy_port_addr; 2361 phyxs_control_t phyxs_ctl; 2362 pcs_control_t pcs_ctl; 2363 uint32_t delay = 0; 2364 optics_dcntr_t op_ctr; 2365 nxge_status_t status = NXGE_OK; 2366 #ifdef NXGE_DEBUG 2367 uint8_t portn = nxgep->mac.portnum; 2368 #endif 2369 2370 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_BCM8706_xcvr_init: port<%d>", 2371 portn)); 2372 2373 phy_port_addr = nxgep->statsp->mac_stats.xcvr_portn; 2374 2375 /* Reset the transceiver */ 2376 if ((status = nxge_mdio_read(nxgep, phy_port_addr, BCM8704_PHYXS_ADDR, 2377 BCM8704_PHYXS_CONTROL_REG, &phyxs_ctl.value)) != NXGE_OK) 2378 goto fail; 2379 2380 phyxs_ctl.bits.reset = 1; 2381 if ((status = nxge_mdio_write(nxgep, phy_port_addr, BCM8704_PHYXS_ADDR, 2382 BCM8704_PHYXS_CONTROL_REG, phyxs_ctl.value)) != NXGE_OK) 2383 goto fail; 2384 do { 2385 drv_usecwait(500); 2386 if ((status = nxge_mdio_read(nxgep, phy_port_addr, 2387 BCM8704_PHYXS_ADDR, BCM8704_PHYXS_CONTROL_REG, 2388 &phyxs_ctl.value)) != NXGE_OK) 2389 goto fail; 2390 delay++; 2391 } while ((phyxs_ctl.bits.reset) && (delay < 100)); 2392 2393 if (delay == 100) { 2394 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "nxge_xcvr_init: " 2395 "failed to reset Transceiver on port<%d>", portn)); 2396 status = NXGE_ERROR; 2397 goto fail; 2398 } 2399 2400 NXGE_DELAY(1000000); 2401 2402 /* Set BCM8706 Internal Loopback mode if necessary */ 2403 if ((status = nxge_mdio_read(nxgep, phy_port_addr, 2404 BCM8704_PCS_DEV_ADDR, BCM8704_PCS_CONTROL_REG, &pcs_ctl.value)) 2405 != NXGE_OK) 2406 goto fail; 2407 if (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy10g) 2408 pcs_ctl.bits.loopback = 1; 2409 else 2410 pcs_ctl.bits.loopback = 0; 2411 if ((status = nxge_mdio_write(nxgep, phy_port_addr, 2412 BCM8704_PCS_DEV_ADDR, BCM8704_PCS_CONTROL_REG, pcs_ctl.value)) 2413 != NXGE_OK) 2414 goto fail; 2415 2416 /* Enable Tx and Rx LEDs to be driven by traffic */ 2417 if ((status = nxge_mdio_read(nxgep, phy_port_addr, 2418 BCM8704_USER_DEV3_ADDR, BCM8704_USER_OPTICS_DIGITAL_CTRL_REG, 2419 &op_ctr.value)) != NXGE_OK) 2420 goto fail; 2421 op_ctr.bits.gpio_sel = 0x3; 2422 op_ctr.bits.res2 = 0x1; 2423 2424 if ((status = nxge_mdio_write(nxgep, phy_port_addr, 2425 BCM8704_USER_DEV3_ADDR, BCM8704_USER_OPTICS_DIGITAL_CTRL_REG, 2426 op_ctr.value)) != NXGE_OK) 2427 goto fail; 2428 2429 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_BCM8706_xcvr_init: port<%d>", 2430 portn)); 2431 return (NXGE_OK); 2432 2433 fail: 2434 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2435 "nxge_BCM8706_xcvr_init: failed to initialize transceiver for " 2436 "port<%d>", nxgep->mac.portnum)); 2437 return (status); 2438 } 2439 2440 #define CHK_STAT(x) status = (x); if (status != NXGE_OK) goto fail 2441 2442 #define MRVL88X2011_RD(nxgep, port, d, r, p) \ 2443 CHK_STAT(nxge_mdio_read(nxgep, port, d, r, p)) 2444 2445 #define MRVL88X2011_WR(nxgep, port, d, r, p) \ 2446 CHK_STAT(nxge_mdio_write(nxgep, port, d, r, p)) 2447 2448 2449 static void 2450 nxge_mrvl88x2011_led_blink_rate(p_nxge_t nxgep, uint16_t rate) 2451 { 2452 uint16_t value; 2453 uint8_t phy = nxgep->statsp->mac_stats.xcvr_portn; 2454 2455 if (nxge_mdio_read(nxgep, phy, MRVL_88X2011_USER_DEV2_ADDR, 2456 MRVL_88X2011_LED_BLINK_CTL, &value) == NXGE_OK) { 2457 value &= ~MRVL_88X2011_LED_BLK_MASK; 2458 value |= (rate << MRVL_88X2011_LED_BLK_SHIFT); 2459 (void) nxge_mdio_write(nxgep, phy, 2460 MRVL_88X2011_USER_DEV2_ADDR, MRVL_88X2011_LED_BLINK_CTL, 2461 value); 2462 } 2463 } 2464 2465 static nxge_status_t 2466 nxge_mrvl88x2011_setup_lb(p_nxge_t nxgep) 2467 { 2468 nxge_status_t status; 2469 pcs_control_t pcs_ctl; 2470 uint8_t phy = nxgep->statsp->mac_stats.xcvr_portn; 2471 2472 MRVL88X2011_RD(nxgep, phy, MRVL_88X2011_USER_DEV3_ADDR, 2473 MRVL_88X2011_PMA_PMD_CTL_1, &pcs_ctl.value); 2474 2475 if (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy10g) 2476 pcs_ctl.bits.loopback = 1; 2477 else 2478 pcs_ctl.bits.loopback = 0; 2479 2480 MRVL88X2011_WR(nxgep, phy, MRVL_88X2011_USER_DEV3_ADDR, 2481 MRVL_88X2011_PMA_PMD_CTL_1, pcs_ctl.value); 2482 2483 fail: 2484 return (status); 2485 } 2486 2487 2488 static void 2489 nxge_mrvl88x2011_led(p_nxge_t nxgep, uint16_t val) 2490 { 2491 uint16_t val2; 2492 uint8_t phy = nxgep->statsp->mac_stats.xcvr_portn; 2493 2494 val2 = MRVL_88X2011_LED(MRVL_88X2011_LED_ACT, val); 2495 val2 &= ~MRVL_88X2011_LED(MRVL_88X2011_LED_ACT, 2496 MRVL_88X2011_LED_CTL_MASK); 2497 val2 |= MRVL_88X2011_LED(MRVL_88X2011_LED_ACT, val); 2498 2499 if (nxge_mdio_write(nxgep, phy, MRVL_88X2011_USER_DEV2_ADDR, 2500 MRVL_88X2011_LED_8_TO_11_CTL, val2) != NXGE_OK) { 2501 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2502 "nxge_mrvl88x2011_led: nxge_mdio_write failed!!")); 2503 } 2504 } 2505 2506 2507 static nxge_status_t 2508 nxge_mrvl88x2011_xcvr_init(p_nxge_t nxgep) 2509 { 2510 uint8_t phy; 2511 nxge_status_t status; 2512 uint16_t clk; 2513 2514 phy = nxgep->statsp->mac_stats.xcvr_portn; 2515 2516 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 2517 "==> nxge_mrvl88x2011_xcvr_init: port<%d> addr<0x%x>", 2518 nxgep->mac.portnum, phy)); 2519 2520 /* Set LED functions */ 2521 nxge_mrvl88x2011_led_blink_rate(nxgep, MRVL_88X2011_LED_BLK134MS); 2522 /* PCS activity */ 2523 nxge_mrvl88x2011_led(nxgep, MRVL_88X2011_LED_ACT); 2524 2525 MRVL88X2011_RD(nxgep, phy, MRVL_88X2011_USER_DEV3_ADDR, 2526 MRVL_88X2011_GEN_CTL, &clk); 2527 clk |= MRVL_88X2011_ENA_XFPREFCLK; 2528 MRVL88X2011_WR(nxgep, phy, MRVL_88X2011_USER_DEV3_ADDR, 2529 MRVL_88X2011_GEN_CTL, clk); 2530 2531 /* Set internal loopback mode if necessary */ 2532 2533 CHK_STAT(nxge_mrvl88x2011_setup_lb(nxgep)); 2534 2535 /* Enable PMD */ 2536 MRVL88X2011_WR(nxgep, phy, MRVL_88X2011_USER_DEV1_ADDR, 2537 MRVL_88X2011_10G_PMD_TX_DIS, MRVL_88X2011_ENA_PMDTX); 2538 2539 NXGE_DEBUG_MSG((nxgep, MAC_CTL, " nxge_mrvl88x2011_reset: OK")); 2540 2541 fail: 2542 return (status); 2543 } 2544 2545 2546 2547 /* Initialize the 10G Transceiver */ 2548 2549 static nxge_status_t 2550 nxge_10G_xcvr_init(p_nxge_t nxgep) 2551 { 2552 p_nxge_stats_t statsp; 2553 p_nxge_param_t param_arr = nxgep->param_arr; 2554 nxge_status_t status = NXGE_OK; 2555 #ifdef NXGE_DEBUG 2556 uint8_t portn = nxgep->mac.portnum; 2557 #endif 2558 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_10G_xcvr_init: port<%d>", 2559 portn)); 2560 2561 statsp = nxgep->statsp; 2562 2563 if (nxgep->mac.portmode == PORT_10G_SERDES) { 2564 goto done; 2565 } 2566 2567 /* Disable Link LEDs */ 2568 if (nxge_10g_link_led_off(nxgep) != NXGE_OK) 2569 goto fail; 2570 2571 /* Set Clause 45 */ 2572 npi_mac_mif_set_indirect_mode(nxgep->npi_handle, B_TRUE); 2573 2574 switch (nxgep->chip_id) { 2575 case BCM8704_CHIP_ID: 2576 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "nxge_10G_xcvr_init: " 2577 "Chip ID 8704 [0x%x] for 10G xcvr", nxgep->chip_id)); 2578 status = nxge_BCM8704_xcvr_init(nxgep); 2579 break; 2580 case BCM8706_CHIP_ID: 2581 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "nxge_10G_xcvr_init: " 2582 "Chip ID 8706 [0x%x] for 10G xcvr", nxgep->chip_id)); 2583 status = nxge_BCM8706_xcvr_init(nxgep); 2584 break; 2585 case MRVL88X201X_CHIP_ID: 2586 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "nxge_10G_xcvr_init: " 2587 "Chip ID 8706 [0x%x] for 10G xcvr", nxgep->chip_id)); 2588 status = nxge_mrvl88x2011_xcvr_init(nxgep); 2589 break; 2590 default: 2591 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_xcvr_init: " 2592 "Unknown chip ID 0x%x for 10G xcvr addr[%d]", 2593 nxgep->chip_id, nxgep->statsp->mac_stats.xcvr_portn)); 2594 goto fail; 2595 } 2596 2597 if (status != NXGE_OK) { 2598 goto fail; 2599 } 2600 done: 2601 statsp->mac_stats.cap_10gfdx = 1; 2602 statsp->mac_stats.lp_cap_10gfdx = 1; 2603 statsp->mac_stats.adv_cap_asmpause = 2604 param_arr[param_anar_asmpause].value; 2605 statsp->mac_stats.adv_cap_pause = param_arr[param_anar_pause].value; 2606 2607 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_10G_xcvr_init: port<%d>", 2608 portn)); 2609 return (NXGE_OK); 2610 2611 fail: 2612 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2613 "nxge_10G_xcvr_init: failed to initialize transceiver for " 2614 "port<%d>", nxgep->mac.portnum)); 2615 return (NXGE_ERROR); 2616 } 2617 2618 /* Initialize the 1G copper (BCM 5464) Transceiver */ 2619 2620 static nxge_status_t 2621 nxge_1G_xcvr_init(p_nxge_t nxgep) 2622 { 2623 p_nxge_param_t param_arr = nxgep->param_arr; 2624 p_nxge_stats_t statsp = nxgep->statsp; 2625 nxge_status_t status = NXGE_OK; 2626 2627 if (nxgep->mac.portmode == PORT_1G_SERDES) { 2628 statsp->mac_stats.cap_1000fdx = 2629 param_arr[param_anar_1000fdx].value; 2630 goto done; 2631 } 2632 2633 /* Set Clause 22 */ 2634 npi_mac_mif_set_indirect_mode(nxgep->npi_handle, B_FALSE); 2635 2636 /* Set capability flags */ 2637 statsp->mac_stats.cap_1000fdx = param_arr[param_anar_1000fdx].value; 2638 if ((nxgep->mac.portmode == PORT_1G_COPPER) || 2639 (nxgep->mac.portmode == PORT_1G_FIBER)) { 2640 statsp->mac_stats.cap_100fdx = 2641 param_arr[param_anar_100fdx].value; 2642 statsp->mac_stats.cap_10fdx = 2643 param_arr[param_anar_10fdx].value; 2644 } 2645 2646 status = nxge_mii_xcvr_init(nxgep); 2647 done: 2648 return (status); 2649 } 2650 2651 /* 2652 * Although the Teranetics copper transceiver (TN1010) does not need 2653 * to be initialized by the driver for passing packets, this funtion 2654 * initializes the members of nxgep->statsp->mac_stats struct for 2655 * kstat based on the value of nxgep->statsp->ports_stats.lb_mode. 2656 * It also configures the TN1010 for PHY loopback to support SunVTS. 2657 * 2658 * TN1010 only has the option to disable advertisement for the 10G 2659 * mode. So we can set it to either Dual Mode or 1G Only mode but 2660 * can't set it to 10G Only mode. 2661 * 2662 * ndd -set command can set the following 6 speed/duplex related parameters. 2663 * 2664 * ---------------------------------------------------------------- 2665 * ndd -set /dev/nxgeX param n kstat nxge:X | grep param 2666 * ---------------------------------------------------------------- 2667 * adv_autoneg_cap kstat nxge:1 | grep adv_cap_autoneg 2668 * adv_10gfdx_cap 2669 * adv_1000fdx_cap kstat nxge:1 | grep adv_cap_1000fdx 2670 * adv_100fdx_cap kstat nxge:1 | grep adv_cap_100fdx 2671 * adv_10fdx_cap kstat nxge:1 | grep adv_cap_10fdx 2672 * adv_pause_cap kstat nxge:1 | grep adv_cap_pause 2673 * ---------------------------------------------------------------- 2674 */ 2675 static nxge_status_t 2676 nxge_tn1010_xcvr_init(p_nxge_t nxgep) 2677 { 2678 p_nxge_param_t param_arr; 2679 p_nxge_stats_t statsp; 2680 tn1010_pcs_ctrl_t tn1010_pcs_ctrl; 2681 uint16_t speed; 2682 uint8_t phy_port_addr; 2683 uint8_t portn = NXGE_GET_PORT_NUM(nxgep->function_num); 2684 int status = NXGE_OK; 2685 2686 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_1G_tn1010_xcvr_init")); 2687 2688 param_arr = nxgep->param_arr; 2689 statsp = nxgep->statsp; 2690 2691 /* 2692 * Initialize the xcvr statistics which are NOT controlled by ndd 2693 */ 2694 statsp->mac_stats.cap_autoneg = 1; /* TN1010 autoneg is always on */ 2695 statsp->mac_stats.cap_100T4 = 0; 2696 2697 /* 2698 * Read the TN1010 link speed and initialize capabilities kstat. Note 2699 * that function nxge_check_tn1010_link repeatedly invoked by the 2700 * timer will update link_speed real time. 2701 */ 2702 if (nxge_get_tn1010_speed(nxgep, &speed) != NXGE_OK) { 2703 goto fail; 2704 } 2705 if (speed == TN1010_SPEED_1G) { 2706 statsp->mac_stats.cap_10gfdx = 0; 2707 } else { 2708 statsp->mac_stats.cap_10gfdx = 1; 2709 } 2710 2711 /* Whether we are in 1G or 10G mode, we always have the 1G capability */ 2712 statsp->mac_stats.cap_1000fdx = 1; 2713 2714 /* TN1010 is not able to operate in the following states */ 2715 statsp->mac_stats.cap_1000hdx = 0; 2716 statsp->mac_stats.cap_100fdx = 0; 2717 statsp->mac_stats.cap_100hdx = 0; 2718 statsp->mac_stats.cap_10fdx = 0; 2719 statsp->mac_stats.cap_10hdx = 0; 2720 2721 /* param_anar_pause can be modified by ndd -set */ 2722 statsp->mac_stats.cap_pause = param_arr[param_anar_pause].value; 2723 2724 /* 2725 * The following 4 lines actually overwrites what ever the ndd command 2726 * has set. For example, by command 2727 * ndd -set /dev/nxge1 adv_autoneg_cap n (n = 0 or 1) 2728 * we could set param_arr[param_autoneg].value to n. However, because 2729 * here we assign constants to these parameters, whatever we set with 2730 * the "ndd -set" command will be replaced. So command 2731 * kstat nxge:X | grep param 2732 * will always show those constant values. In other words, the 2733 * "ndd -set" command can NOT change the values of these 4 parameters 2734 * even though the command appears to be successful. 2735 * 2736 * Note: TN1010 auto negotiation is always enabled. 2737 */ 2738 statsp->mac_stats.adv_cap_autoneg 2739 = param_arr[param_autoneg].value = 1; 2740 statsp->mac_stats.adv_cap_1000fdx 2741 = param_arr[param_anar_1000fdx].value = 1; 2742 statsp->mac_stats.adv_cap_100fdx 2743 = param_arr[param_anar_100fdx].value = 0; 2744 statsp->mac_stats.adv_cap_10fdx 2745 = param_arr[param_anar_10fdx].value = 0; 2746 2747 /* 2748 * The following 4 ndd params have type NXGE_PARAM_MAC_DONT_SHOW as 2749 * defined in nxge_param_arr[], therefore they are not seen by the 2750 * "ndd -get" command and can not be changed by ndd. We just set 2751 * them (both ndd param and kstat values) to constant 0 because TN1010 2752 * does not support those speeds. 2753 */ 2754 statsp->mac_stats.adv_cap_100T4 2755 = param_arr[param_anar_100T4].value = 0; 2756 statsp->mac_stats.adv_cap_1000hdx 2757 = param_arr[param_anar_1000hdx].value = 0; 2758 statsp->mac_stats.adv_cap_100hdx 2759 = param_arr[param_anar_100hdx].value = 0; 2760 statsp->mac_stats.adv_cap_10hdx 2761 = param_arr[param_anar_10hdx].value = 0; 2762 2763 /* 2764 * adv_cap_pause has type NXGE_PARAM_MAC_RW, so it can be modified 2765 * by ndd 2766 */ 2767 statsp->mac_stats.adv_cap_pause = param_arr[param_anar_pause].value; 2768 2769 /* 2770 * nxge_param_arr[] defines the adv_cap_asmpause with type 2771 * NXGE_PARAM_DONT_SHOW, therefore they are NOT seen by the 2772 * "ndd -get" command and can not be changed by ndd. Here we do not 2773 * assign a constant to it so the default value defined in 2774 * nxge_param_arr[] will be used to set the parameter and 2775 * will be shown by the kstat. 2776 */ 2777 statsp->mac_stats.adv_cap_asmpause 2778 = param_arr[param_anar_asmpause].value; 2779 2780 /* 2781 * Initialize the link statistics. 2782 */ 2783 statsp->mac_stats.link_T4 = 0; 2784 statsp->mac_stats.link_asmpause = 0; 2785 statsp->mac_stats.link_pause = 0; 2786 if (speed == TN1010_SPEED_1G) { 2787 statsp->mac_stats.link_speed = 1000; 2788 statsp->mac_stats.link_duplex = 2; /* Full duplex */ 2789 statsp->mac_stats.link_up = 1; 2790 } else { 2791 statsp->mac_stats.link_speed = 10000; 2792 statsp->mac_stats.link_duplex = 2; 2793 statsp->mac_stats.link_up = 1; 2794 } 2795 2796 /* 2797 * Because TN1010 does not have a link partner register, to 2798 * figure out the link partner's capabilities is tricky. Here we 2799 * just set the kstat based on our knowledge about the partner 2800 * (The partner must support auto-neg because auto-negotiation 2801 * has completed, it must support 1G or 10G because that is the 2802 * negotiated speed we are using.) 2803 * 2804 * Note: Current kstat does not show lp_cap_10gfdx and 2805 * lp_cap_10ghdx. 2806 */ 2807 if (speed == TN1010_SPEED_1G) { 2808 statsp->mac_stats.lp_cap_1000fdx = 1; 2809 statsp->mac_stats.lp_cap_10gfdx = 0; 2810 } else { 2811 statsp->mac_stats.lp_cap_1000fdx = 0; 2812 statsp->mac_stats.lp_cap_10gfdx = 1; 2813 } 2814 statsp->mac_stats.lp_cap_10ghdx = 0; 2815 statsp->mac_stats.lp_cap_1000hdx = 0; 2816 statsp->mac_stats.lp_cap_100fdx = 0; 2817 statsp->mac_stats.lp_cap_100hdx = 0; 2818 statsp->mac_stats.lp_cap_10fdx = 0; 2819 statsp->mac_stats.lp_cap_10hdx = 0; 2820 statsp->mac_stats.lp_cap_10gfdx = 0; 2821 statsp->mac_stats.lp_cap_10ghdx = 0; 2822 statsp->mac_stats.lp_cap_100T4 = 0; 2823 statsp->mac_stats.lp_cap_autoneg = 1; 2824 statsp->mac_stats.lp_cap_asmpause = 0; 2825 statsp->mac_stats.lp_cap_pause = 0; 2826 2827 /* Handle PHY loopback for SunVTS loopback test */ 2828 npi_mac_mif_set_indirect_mode(nxgep->npi_handle, B_TRUE); 2829 phy_port_addr = nxgep->nxge_hw_p->xcvr_addr[portn]; 2830 2831 if ((status = nxge_mdio_read(nxgep, phy_port_addr, 2832 TN1010_PCS_DEV_ADDR, TN1010_PCS_CONTROL_REG, 2833 &tn1010_pcs_ctrl.value)) != NXGE_OK) { 2834 goto fail; 2835 } 2836 if ((statsp->port_stats.lb_mode == nxge_lb_phy1000) || 2837 (statsp->port_stats.lb_mode == nxge_lb_phy10g)) { 2838 tn1010_pcs_ctrl.bits.loopback = 1; 2839 } else { 2840 tn1010_pcs_ctrl.bits.loopback = 0; 2841 } 2842 if ((status = nxge_mdio_write(nxgep, phy_port_addr, 2843 TN1010_PCS_DEV_ADDR, TN1010_PCS_CONTROL_REG, 2844 tn1010_pcs_ctrl.value)) != NXGE_OK) { 2845 goto fail; 2846 } 2847 2848 statsp->mac_stats.xcvr_inits++; 2849 2850 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 2851 "<== nxge_1G_tn1010_xcvr_init status 0x%x", status)); 2852 return (status); 2853 fail: 2854 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2855 "<== nxge_1G_tn1010_xcvr_init status 0x%x", status)); 2856 return (status); 2857 } 2858 2859 /* Initialize transceiver */ 2860 2861 nxge_status_t 2862 nxge_xcvr_init(p_nxge_t nxgep) 2863 { 2864 p_nxge_stats_t statsp; 2865 #ifdef NXGE_DEBUG 2866 uint8_t portn; 2867 #endif 2868 2869 nxge_status_t status = NXGE_OK; 2870 #ifdef NXGE_DEBUG 2871 portn = nxgep->mac.portnum; 2872 #endif 2873 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_xcvr_init: port<%d>", portn)); 2874 statsp = nxgep->statsp; 2875 2876 /* 2877 * Initialize the xcvr statistics. nxgep->xcvr.xcvr_init will 2878 * modify mac_stats. 2879 */ 2880 statsp->mac_stats.cap_autoneg = 0; 2881 statsp->mac_stats.cap_100T4 = 0; 2882 statsp->mac_stats.cap_100fdx = 0; 2883 statsp->mac_stats.cap_100hdx = 0; 2884 statsp->mac_stats.cap_10fdx = 0; 2885 statsp->mac_stats.cap_10hdx = 0; 2886 statsp->mac_stats.cap_asmpause = 0; 2887 statsp->mac_stats.cap_pause = 0; 2888 statsp->mac_stats.cap_1000fdx = 0; 2889 statsp->mac_stats.cap_1000hdx = 0; 2890 statsp->mac_stats.cap_10gfdx = 0; 2891 statsp->mac_stats.cap_10ghdx = 0; 2892 2893 /* 2894 * Initialize the link statistics. 2895 */ 2896 statsp->mac_stats.link_T4 = 0; 2897 statsp->mac_stats.link_asmpause = 0; 2898 statsp->mac_stats.link_pause = 0; 2899 2900 if (nxgep->xcvr.xcvr_init) { 2901 status = nxgep->xcvr.xcvr_init(nxgep); 2902 if (status != NXGE_OK) 2903 goto fail; 2904 statsp->mac_stats.xcvr_inits++; 2905 } 2906 2907 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_xcvr_init: port<%d>", 2908 portn)); 2909 return (NXGE_OK); 2910 2911 fail: 2912 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 2913 "nxge_xcvr_init: failed to initialize transceiver for port<%d>", 2914 portn)); 2915 return (status); 2916 } 2917 2918 /* Look for transceiver type */ 2919 2920 nxge_status_t 2921 nxge_xcvr_find(p_nxge_t nxgep) 2922 { 2923 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_xcvr_find: port<%d>", 2924 nxgep->mac.portnum)); 2925 2926 if (nxge_get_xcvr_type(nxgep) != NXGE_OK) 2927 return (NXGE_ERROR); 2928 2929 if (nxge_setup_xcvr_table(nxgep) != NXGE_OK) 2930 return (NXGE_ERROR); 2931 2932 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_xcvr_find: xcvr_inuse = %d", 2933 nxgep->statsp->mac_stats.xcvr_inuse)); 2934 return (NXGE_OK); 2935 } 2936 2937 /* Initialize the TxMAC sub-block */ 2938 2939 nxge_status_t 2940 nxge_tx_mac_init(p_nxge_t nxgep) 2941 { 2942 npi_attr_t ap; 2943 uint8_t portn; 2944 nxge_port_mode_t portmode; 2945 nxge_port_t portt; 2946 npi_handle_t handle; 2947 npi_status_t rs = NPI_SUCCESS; 2948 2949 portn = NXGE_GET_PORT_NUM(nxgep->function_num); 2950 portt = nxgep->mac.porttype; 2951 handle = nxgep->npi_handle; 2952 portmode = nxgep->mac.portmode; 2953 2954 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_tx_mac_init: port<%d>", 2955 portn)); 2956 /* Set Max and Min Frame Size */ 2957 /* 2958 * Use maxframesize to configure the hardware maxframe size 2959 * and minframesize to configure the hardware minframe size. 2960 */ 2961 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 2962 "==> nxge_tx_mac_init: port<%d> " 2963 "min framesize %d max framesize %d ", 2964 nxgep->mac.minframesize, 2965 nxgep->mac.maxframesize, 2966 portn)); 2967 2968 SET_MAC_ATTR2(handle, ap, portn, 2969 MAC_PORT_FRAME_SIZE, 2970 nxgep->mac.minframesize, 2971 nxgep->mac.maxframesize, 2972 rs); 2973 if (rs != NPI_SUCCESS) 2974 goto fail; 2975 2976 if (portt == PORT_TYPE_XMAC) { 2977 if ((rs = npi_xmac_tx_iconfig(handle, INIT, portn, 2978 0)) != NPI_SUCCESS) 2979 goto fail; 2980 nxgep->mac.tx_iconfig = NXGE_XMAC_TX_INTRS; 2981 if ((portmode == PORT_10G_FIBER) || 2982 (portmode == PORT_10G_COPPER) || 2983 (portmode == PORT_10G_TN1010) || 2984 (portmode == PORT_10G_SERDES)) { 2985 SET_MAC_ATTR1(handle, ap, portn, XMAC_10G_PORT_IPG, 2986 XGMII_IPG_12_15, rs); 2987 if (rs != NPI_SUCCESS) 2988 goto fail; 2989 nxgep->mac.ipg[0] = XGMII_IPG_12_15; 2990 } else { 2991 SET_MAC_ATTR1(handle, ap, portn, XMAC_PORT_IPG, 2992 MII_GMII_IPG_12, rs); 2993 if (rs != NPI_SUCCESS) 2994 goto fail; 2995 nxgep->mac.ipg[0] = MII_GMII_IPG_12; 2996 } 2997 if ((rs = npi_xmac_tx_config(handle, INIT, portn, 2998 CFG_XMAC_TX_CRC | CFG_XMAC_TX)) != NPI_SUCCESS) 2999 goto fail; 3000 nxgep->mac.tx_config = CFG_XMAC_TX_CRC | CFG_XMAC_TX; 3001 nxgep->mac.maxburstsize = 0; /* not programmable */ 3002 nxgep->mac.ctrltype = 0; /* not programmable */ 3003 nxgep->mac.pa_size = 0; /* not programmable */ 3004 3005 if ((rs = npi_xmac_zap_tx_counters(handle, portn)) 3006 != NPI_SUCCESS) 3007 goto fail; 3008 3009 } else { 3010 if ((rs = npi_bmac_tx_iconfig(handle, INIT, portn, 3011 0)) != NPI_SUCCESS) 3012 goto fail; 3013 nxgep->mac.tx_iconfig = NXGE_BMAC_TX_INTRS; 3014 3015 SET_MAC_ATTR1(handle, ap, portn, BMAC_PORT_CTRL_TYPE, 0x8808, 3016 rs); 3017 if (rs != NPI_SUCCESS) 3018 goto fail; 3019 nxgep->mac.ctrltype = 0x8808; 3020 3021 SET_MAC_ATTR1(handle, ap, portn, BMAC_PORT_PA_SIZE, 0x7, rs); 3022 if (rs != NPI_SUCCESS) 3023 goto fail; 3024 nxgep->mac.pa_size = 0x7; 3025 3026 if ((rs = npi_bmac_tx_config(handle, INIT, portn, 3027 CFG_BMAC_TX_CRC | CFG_BMAC_TX)) != NPI_SUCCESS) 3028 goto fail; 3029 nxgep->mac.tx_config = CFG_BMAC_TX_CRC | CFG_BMAC_TX; 3030 } 3031 3032 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_tx_mac_init: port<%d>", 3033 portn)); 3034 3035 return (NXGE_OK); 3036 fail: 3037 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 3038 "nxge_tx_mac_init: failed to initialize port<%d> TXMAC", portn)); 3039 3040 return (NXGE_ERROR | rs); 3041 } 3042 3043 int 3044 nxge_hio_hostinfo_get_rdc_table(p_nxge_t nxgep) 3045 { 3046 int rdc_tbl; 3047 3048 /* 3049 * Get an RDC table (version 0). 3050 */ 3051 if ((rdc_tbl = nxge_fzc_rdc_tbl_bind(nxgep, -1, B_FALSE)) < 0) { 3052 NXGE_ERROR_MSG((nxgep, OBP_CTL, 3053 "nxge_hio_hostinfo_get_rdc_table: " 3054 "there are no free RDC tables!")); 3055 return (EBUSY); 3056 } 3057 3058 return (rdc_tbl); 3059 } 3060 3061 /* 3062 * nxge_hio_hostinfo_init 3063 * 3064 * Initialize an alternate MAC address, and bind a macrdctbln to it. 3065 * 3066 * Arguments: 3067 * nxge 3068 * vr The Virtualization Region 3069 * macaddr The alternate MAC address 3070 * 3071 * Notes: 3072 * 1. Find & bind an RDC table to <nxge>. 3073 * 2. Program an alternate MAC address (<macaddr>). 3074 * 3. Bind the RDC table to <macaddr>. 3075 * 3076 * Context: 3077 * Service domain 3078 * 3079 * Side Effects: 3080 * nxge->class_config.mac_host_info[slot].rdctbl 3081 * vr->slot & vr->altmac 3082 * 3083 */ 3084 int 3085 nxge_hio_hostinfo_init(nxge_t *nxge, nxge_hio_vr_t *vr, ether_addr_t *macaddr) 3086 { 3087 int slot, error; 3088 uint8_t rdc_tbl; 3089 nxge_mmac_t *mmac_info; 3090 nxge_rdc_grp_t *group; 3091 uint8_t *addr = (uint8_t *)macaddr; 3092 3093 mutex_enter(nxge->genlock); 3094 3095 rdc_tbl = (uint8_t)vr->rdc_tbl; 3096 3097 /* Initialize the NXGE RDC table data structure. */ 3098 group = &nxge->pt_config.rdc_grps[rdc_tbl]; 3099 group->port = NXGE_GET_PORT_NUM(nxge->function_num); 3100 group->config_method = RDC_TABLE_ENTRY_METHOD_REP; 3101 group->flag = 1; /* This group has been configured. */ 3102 3103 mmac_info = &nxge->nxge_mmac_info; 3104 3105 /* 3106 * Are there free slots. 3107 */ 3108 if (mmac_info->naddrfree == 0) { 3109 mutex_exit(nxge->genlock); 3110 return (ENOSPC); 3111 } 3112 3113 /* 3114 * Find a slot for the VR to use for Hybrid I/O. 3115 */ 3116 if (mmac_info->num_factory_mmac < mmac_info->num_mmac) { 3117 for (slot = mmac_info->num_factory_mmac + 1; 3118 slot <= mmac_info->num_mmac; slot++) { 3119 if (!(mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED)) 3120 break; 3121 } 3122 if (slot > mmac_info->num_mmac) { 3123 for (slot = 1; slot <= mmac_info->num_factory_mmac; 3124 slot++) { 3125 if (!(mmac_info->mac_pool[slot].flags 3126 & MMAC_SLOT_USED)) 3127 break; 3128 } 3129 } 3130 } else { 3131 for (slot = 1; slot <= mmac_info->num_mmac; slot++) { 3132 if (!(mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED)) 3133 break; 3134 } 3135 } 3136 ASSERT(slot <= mmac_info->num_mmac); 3137 vr->slot = slot; 3138 3139 error = nxge_altmac_set(nxge, addr, slot, rdc_tbl); 3140 if (error != 0) { 3141 mutex_exit(nxge->genlock); 3142 return (EIO); 3143 } 3144 3145 bcopy(macaddr, vr->altmac, sizeof (vr->altmac)); 3146 3147 /* 3148 * Update mmac 3149 */ 3150 bcopy(addr, mmac_info->mac_pool[vr->slot].addr, ETHERADDRL); 3151 mmac_info->mac_pool[vr->slot].flags |= MMAC_SLOT_USED; 3152 mmac_info->mac_pool[vr->slot].flags &= ~MMAC_VENDOR_ADDR; 3153 mmac_info->naddrfree--; 3154 nxge_mmac_kstat_update(nxge, vr->slot, B_FALSE); 3155 3156 mutex_exit(nxge->genlock); 3157 return (0); 3158 } 3159 3160 /* 3161 * nxge_hio_hostinfo_uninit 3162 * 3163 * Uninitialize an alternate MAC address. 3164 * 3165 * Arguments: 3166 * nxge 3167 * vr The Virtualization Region 3168 * 3169 * Notes: 3170 * Remove the VR's alternate MAC address. 3171 * 3172 * Context: 3173 * Service domain 3174 * 3175 * Side Effects: 3176 * nxge->class_config.mac_host_info[slot].rdctbl 3177 * 3178 */ 3179 void 3180 nxge_hio_hostinfo_uninit(nxge_t *nxge, nxge_hio_vr_t *vr) 3181 { 3182 nxge_class_pt_cfg_t *class; 3183 uint8_t addrn; 3184 3185 addrn = vr->slot - 1; 3186 (void) npi_mac_altaddr_disable(nxge->npi_handle, 3187 nxge->mac.portnum, addrn); 3188 3189 /* Set this variable to its default. */ 3190 class = (p_nxge_class_pt_cfg_t)&nxge->class_config; 3191 class->mac_host_info[addrn].rdctbl = 3192 nxge->pt_config.hw_config.def_mac_rxdma_grpid; 3193 3194 (void) nxge_m_mmac_remove(nxge, vr->slot); 3195 vr->slot = -1; 3196 } 3197 3198 /* Initialize the RxMAC sub-block */ 3199 3200 nxge_status_t 3201 nxge_rx_mac_init(p_nxge_t nxgep) 3202 { 3203 npi_attr_t ap; 3204 uint32_t i; 3205 uint16_t hashtab_e; 3206 p_hash_filter_t hash_filter; 3207 nxge_port_t portt; 3208 uint8_t portn; 3209 npi_handle_t handle; 3210 npi_status_t rs = NPI_SUCCESS; 3211 uint16_t *addr16p; 3212 uint16_t addr0, addr1, addr2; 3213 xmac_rx_config_t xconfig; 3214 bmac_rx_config_t bconfig; 3215 3216 portn = NXGE_GET_PORT_NUM(nxgep->function_num); 3217 3218 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_rx_mac_init: port<%d>\n", 3219 portn)); 3220 handle = nxgep->npi_handle; 3221 portt = nxgep->mac.porttype; 3222 3223 addr16p = (uint16_t *)nxgep->ouraddr.ether_addr_octet; 3224 addr0 = ntohs(addr16p[2]); 3225 addr1 = ntohs(addr16p[1]); 3226 addr2 = ntohs(addr16p[0]); 3227 SET_MAC_ATTR3(handle, ap, portn, MAC_PORT_ADDR, addr0, addr1, addr2, 3228 rs); 3229 3230 if (rs != NPI_SUCCESS) 3231 goto fail; 3232 SET_MAC_ATTR3(handle, ap, portn, MAC_PORT_ADDR_FILTER, 0, 0, 0, rs); 3233 if (rs != NPI_SUCCESS) 3234 goto fail; 3235 SET_MAC_ATTR2(handle, ap, portn, MAC_PORT_ADDR_FILTER_MASK, 0, 0, rs); 3236 if (rs != NPI_SUCCESS) 3237 goto fail; 3238 3239 /* 3240 * Load the multicast hash filter bits. 3241 */ 3242 hash_filter = nxgep->hash_filter; 3243 for (i = 0; i < MAC_MAX_HASH_ENTRY; i++) { 3244 if (hash_filter != NULL) { 3245 hashtab_e = (uint16_t)hash_filter->hash_filter_regs[ 3246 (NMCFILTER_REGS - 1) - i]; 3247 } else { 3248 hashtab_e = 0; 3249 } 3250 3251 if ((rs = npi_mac_hashtab_entry(handle, OP_SET, portn, i, 3252 (uint16_t *)&hashtab_e)) != NPI_SUCCESS) 3253 goto fail; 3254 } 3255 3256 if (portt == PORT_TYPE_XMAC) { 3257 if ((rs = npi_xmac_rx_iconfig(handle, INIT, portn, 3258 0)) != NPI_SUCCESS) 3259 goto fail; 3260 nxgep->mac.rx_iconfig = NXGE_XMAC_RX_INTRS; 3261 3262 (void) nxge_fflp_init_hostinfo(nxgep); 3263 3264 xconfig = CFG_XMAC_RX_ERRCHK | CFG_XMAC_RX_CRC_CHK | 3265 CFG_XMAC_RX | CFG_XMAC_RX_CODE_VIO_CHK & 3266 ~CFG_XMAC_RX_STRIP_CRC; 3267 3268 if (nxgep->filter.all_phys_cnt != 0) 3269 xconfig |= CFG_XMAC_RX_PROMISCUOUS; 3270 3271 if (nxgep->filter.all_multicast_cnt != 0) 3272 xconfig |= CFG_XMAC_RX_PROMISCUOUSGROUP; 3273 3274 xconfig |= CFG_XMAC_RX_HASH_FILTER; 3275 3276 if ((rs = npi_xmac_rx_config(handle, INIT, portn, 3277 xconfig)) != NPI_SUCCESS) 3278 goto fail; 3279 nxgep->mac.rx_config = xconfig; 3280 3281 /* Comparison of mac unique address is always enabled on XMAC */ 3282 3283 if ((rs = npi_xmac_zap_rx_counters(handle, portn)) 3284 != NPI_SUCCESS) 3285 goto fail; 3286 } else { 3287 (void) nxge_fflp_init_hostinfo(nxgep); 3288 3289 if (npi_bmac_rx_iconfig(nxgep->npi_handle, INIT, portn, 3290 0) != NPI_SUCCESS) 3291 goto fail; 3292 nxgep->mac.rx_iconfig = NXGE_BMAC_RX_INTRS; 3293 3294 bconfig = CFG_BMAC_RX_DISCARD_ON_ERR | CFG_BMAC_RX & 3295 ~CFG_BMAC_RX_STRIP_CRC; 3296 3297 if (nxgep->filter.all_phys_cnt != 0) 3298 bconfig |= CFG_BMAC_RX_PROMISCUOUS; 3299 3300 if (nxgep->filter.all_multicast_cnt != 0) 3301 bconfig |= CFG_BMAC_RX_PROMISCUOUSGROUP; 3302 3303 bconfig |= CFG_BMAC_RX_HASH_FILTER; 3304 if ((rs = npi_bmac_rx_config(handle, INIT, portn, 3305 bconfig)) != NPI_SUCCESS) 3306 goto fail; 3307 nxgep->mac.rx_config = bconfig; 3308 3309 /* Always enable comparison of mac unique address */ 3310 if ((rs = npi_mac_altaddr_enable(handle, portn, 0)) 3311 != NPI_SUCCESS) 3312 goto fail; 3313 } 3314 3315 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_rx_mac_init: port<%d>\n", 3316 portn)); 3317 3318 return (NXGE_OK); 3319 3320 fail: 3321 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3322 "nxge_rx_mac_init: Failed to Initialize port<%d> RxMAC", portn)); 3323 3324 return (NXGE_ERROR | rs); 3325 } 3326 3327 /* Enable TXMAC */ 3328 3329 nxge_status_t 3330 nxge_tx_mac_enable(p_nxge_t nxgep) 3331 { 3332 npi_handle_t handle; 3333 npi_status_t rs = NPI_SUCCESS; 3334 nxge_status_t status = NXGE_OK; 3335 3336 handle = nxgep->npi_handle; 3337 3338 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_tx_mac_enable: port<%d>", 3339 nxgep->mac.portnum)); 3340 3341 if ((status = nxge_tx_mac_init(nxgep)) != NXGE_OK) 3342 goto fail; 3343 3344 /* based on speed */ 3345 nxgep->msg_min = ETHERMIN; 3346 3347 if (nxgep->mac.porttype == PORT_TYPE_XMAC) { 3348 if ((rs = npi_xmac_tx_config(handle, ENABLE, nxgep->mac.portnum, 3349 CFG_XMAC_TX)) != NPI_SUCCESS) 3350 goto fail; 3351 } else { 3352 if ((rs = npi_bmac_tx_config(handle, ENABLE, nxgep->mac.portnum, 3353 CFG_BMAC_TX)) != NPI_SUCCESS) 3354 goto fail; 3355 } 3356 3357 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_tx_mac_enable: port<%d>", 3358 nxgep->mac.portnum)); 3359 3360 return (NXGE_OK); 3361 fail: 3362 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3363 "nxgep_tx_mac_enable: Failed to enable port<%d> TxMAC", 3364 nxgep->mac.portnum)); 3365 if (rs != NPI_SUCCESS) 3366 return (NXGE_ERROR | rs); 3367 else 3368 return (status); 3369 } 3370 3371 /* Disable TXMAC */ 3372 3373 nxge_status_t 3374 nxge_tx_mac_disable(p_nxge_t nxgep) 3375 { 3376 npi_handle_t handle; 3377 npi_status_t rs = NPI_SUCCESS; 3378 3379 if (isLDOMguest(nxgep)) 3380 return (NXGE_OK); 3381 3382 handle = nxgep->npi_handle; 3383 3384 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_tx_mac_disable: port<%d>", 3385 nxgep->mac.portnum)); 3386 3387 if (nxgep->mac.porttype == PORT_TYPE_XMAC) { 3388 if ((rs = npi_xmac_tx_config(handle, DISABLE, 3389 nxgep->mac.portnum, CFG_XMAC_TX)) != NPI_SUCCESS) 3390 goto fail; 3391 } else { 3392 if ((rs = npi_bmac_tx_config(handle, DISABLE, 3393 nxgep->mac.portnum, CFG_BMAC_TX)) != NPI_SUCCESS) 3394 goto fail; 3395 } 3396 3397 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_tx_mac_disable: port<%d>", 3398 nxgep->mac.portnum)); 3399 return (NXGE_OK); 3400 fail: 3401 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3402 "nxge_tx_mac_disable: Failed to disable port<%d> TxMAC", 3403 nxgep->mac.portnum)); 3404 return (NXGE_ERROR | rs); 3405 } 3406 3407 /* Enable RXMAC */ 3408 3409 nxge_status_t 3410 nxge_rx_mac_enable(p_nxge_t nxgep) 3411 { 3412 npi_handle_t handle; 3413 uint8_t portn; 3414 npi_status_t rs = NPI_SUCCESS; 3415 nxge_status_t status = NXGE_OK; 3416 3417 /* This is a service-domain-only activity. */ 3418 if (isLDOMguest(nxgep)) 3419 return (status); 3420 3421 handle = nxgep->npi_handle; 3422 portn = nxgep->mac.portnum; 3423 3424 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_rx_mac_enable: port<%d>", 3425 portn)); 3426 3427 if ((status = nxge_rx_mac_init(nxgep)) != NXGE_OK) 3428 goto fail; 3429 3430 if (nxgep->mac.porttype == PORT_TYPE_XMAC) { 3431 if ((rs = npi_xmac_rx_config(handle, ENABLE, portn, 3432 CFG_XMAC_RX)) != NPI_SUCCESS) 3433 goto fail; 3434 } else { 3435 if ((rs = npi_bmac_rx_config(handle, ENABLE, portn, 3436 CFG_BMAC_RX)) != NPI_SUCCESS) 3437 goto fail; 3438 } 3439 3440 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 3441 "<== nxge_rx_mac_enable: port<%d>", portn)); 3442 3443 return (NXGE_OK); 3444 fail: 3445 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3446 "nxgep_rx_mac_enable: Failed to enable port<%d> RxMAC", portn)); 3447 3448 if (rs != NPI_SUCCESS) 3449 return (NXGE_ERROR | rs); 3450 else 3451 return (status); 3452 } 3453 3454 /* Disable RXMAC */ 3455 3456 nxge_status_t 3457 nxge_rx_mac_disable(p_nxge_t nxgep) 3458 { 3459 npi_handle_t handle; 3460 uint8_t portn; 3461 npi_status_t rs = NPI_SUCCESS; 3462 3463 /* If we are a guest domain driver, don't bother. */ 3464 if (isLDOMguest(nxgep)) 3465 return (NXGE_OK); 3466 3467 handle = nxgep->npi_handle; 3468 portn = nxgep->mac.portnum; 3469 3470 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_rx_mac_disable: port<%d>", 3471 portn)); 3472 3473 if (nxgep->mac.porttype == PORT_TYPE_XMAC) { 3474 if ((rs = npi_xmac_rx_config(handle, DISABLE, portn, 3475 CFG_XMAC_RX)) != NPI_SUCCESS) 3476 goto fail; 3477 } else { 3478 if ((rs = npi_bmac_rx_config(handle, DISABLE, portn, 3479 CFG_BMAC_RX)) != NPI_SUCCESS) 3480 goto fail; 3481 } 3482 3483 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_rx_mac_disable: port<%d>", 3484 portn)); 3485 return (NXGE_OK); 3486 fail: 3487 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3488 "nxgep_rx_mac_disable: Failed to disable port<%d> RxMAC", portn)); 3489 3490 return (NXGE_ERROR | rs); 3491 } 3492 3493 /* Reset TXMAC */ 3494 3495 nxge_status_t 3496 nxge_tx_mac_reset(p_nxge_t nxgep) 3497 { 3498 npi_handle_t handle; 3499 uint8_t portn; 3500 npi_status_t rs = NPI_SUCCESS; 3501 3502 handle = nxgep->npi_handle; 3503 portn = nxgep->mac.portnum; 3504 3505 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_tx_mac_reset: port<%d>", 3506 portn)); 3507 3508 if (nxgep->mac.porttype == PORT_TYPE_XMAC) { 3509 if ((rs = npi_xmac_reset(handle, portn, XTX_MAC_RESET_ALL)) 3510 != NPI_SUCCESS) 3511 goto fail; 3512 } else { 3513 if ((rs = npi_bmac_reset(handle, portn, TX_MAC_RESET)) 3514 != NPI_SUCCESS) 3515 goto fail; 3516 } 3517 3518 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_tx_mac_reset: port<%d>", 3519 portn)); 3520 3521 return (NXGE_OK); 3522 fail: 3523 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3524 "nxge_tx_mac_reset: Failed to Reset TxMAC port<%d>", portn)); 3525 3526 return (NXGE_ERROR | rs); 3527 } 3528 3529 /* Reset RXMAC */ 3530 3531 nxge_status_t 3532 nxge_rx_mac_reset(p_nxge_t nxgep) 3533 { 3534 npi_handle_t handle; 3535 uint8_t portn; 3536 npi_status_t rs = NPI_SUCCESS; 3537 3538 handle = nxgep->npi_handle; 3539 portn = nxgep->mac.portnum; 3540 3541 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_rx_mac_reset: port<%d>", 3542 portn)); 3543 3544 if (nxgep->mac.porttype == PORT_TYPE_XMAC) { 3545 if ((rs = npi_xmac_reset(handle, portn, XRX_MAC_RESET_ALL)) 3546 != NPI_SUCCESS) 3547 goto fail; 3548 } else { 3549 if ((rs = npi_bmac_reset(handle, portn, RX_MAC_RESET)) 3550 != NPI_SUCCESS) 3551 goto fail; 3552 } 3553 3554 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_rx_mac_reset: port<%d>", 3555 portn)); 3556 3557 return (NXGE_OK); 3558 fail: 3559 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3560 "nxge_rx_mac_reset: Failed to Reset RxMAC port<%d>", portn)); 3561 return (NXGE_ERROR | rs); 3562 } 3563 3564 /* 10G fiber link interrupt start routine */ 3565 3566 static nxge_status_t 3567 nxge_10G_link_intr_start(p_nxge_t nxgep) 3568 { 3569 npi_status_t rs = NPI_SUCCESS; 3570 uint8_t portn = nxgep->mac.portnum; 3571 3572 rs = npi_xmac_xpcs_link_intr_enable(nxgep->npi_handle, portn); 3573 3574 if (rs != NPI_SUCCESS) 3575 return (NXGE_ERROR | rs); 3576 else 3577 return (NXGE_OK); 3578 } 3579 3580 /* 10G fiber link interrupt stop routine */ 3581 3582 static nxge_status_t 3583 nxge_10G_link_intr_stop(p_nxge_t nxgep) 3584 { 3585 npi_status_t rs = NPI_SUCCESS; 3586 uint8_t portn = nxgep->mac.portnum; 3587 3588 rs = npi_xmac_xpcs_link_intr_disable(nxgep->npi_handle, portn); 3589 3590 if (rs != NPI_SUCCESS) 3591 return (NXGE_ERROR | rs); 3592 else 3593 return (NXGE_OK); 3594 } 3595 3596 /* 1G fiber link interrupt start routine */ 3597 3598 static nxge_status_t 3599 nxge_1G_fiber_link_intr_start(p_nxge_t nxgep) 3600 { 3601 npi_status_t rs = NPI_SUCCESS; 3602 uint8_t portn = nxgep->mac.portnum; 3603 3604 rs = npi_mac_pcs_link_intr_enable(nxgep->npi_handle, portn); 3605 if (rs != NPI_SUCCESS) 3606 return (NXGE_ERROR | rs); 3607 else 3608 return (NXGE_OK); 3609 } 3610 3611 /* 1G fiber link interrupt stop routine */ 3612 3613 static nxge_status_t 3614 nxge_1G_fiber_link_intr_stop(p_nxge_t nxgep) 3615 { 3616 npi_status_t rs = NPI_SUCCESS; 3617 uint8_t portn = nxgep->mac.portnum; 3618 3619 rs = npi_mac_pcs_link_intr_disable(nxgep->npi_handle, portn); 3620 3621 if (rs != NPI_SUCCESS) 3622 return (NXGE_ERROR | rs); 3623 else 3624 return (NXGE_OK); 3625 } 3626 3627 /* 1G copper link interrupt start routine */ 3628 3629 static nxge_status_t 3630 nxge_1G_copper_link_intr_start(p_nxge_t nxgep) 3631 { 3632 npi_status_t rs = NPI_SUCCESS; 3633 uint8_t portn = nxgep->mac.portnum; 3634 3635 rs = npi_mac_mif_link_intr_enable(nxgep->npi_handle, portn, 3636 MII_STATUS, MII_STATUS_LINKUP); 3637 3638 if (rs != NPI_SUCCESS) 3639 return (NXGE_ERROR | rs); 3640 else 3641 return (NXGE_OK); 3642 } 3643 3644 /* 1G copper link interrupt stop routine */ 3645 3646 static nxge_status_t 3647 nxge_1G_copper_link_intr_stop(p_nxge_t nxgep) 3648 { 3649 npi_status_t rs = NPI_SUCCESS; 3650 uint8_t portn = nxgep->mac.portnum; 3651 3652 rs = npi_mac_mif_link_intr_disable(nxgep->npi_handle, portn); 3653 3654 if (rs != NPI_SUCCESS) 3655 return (NXGE_ERROR | rs); 3656 else 3657 return (NXGE_OK); 3658 } 3659 3660 /* Enable/Disable Link Status change interrupt */ 3661 3662 nxge_status_t 3663 nxge_link_intr(p_nxge_t nxgep, link_intr_enable_t enable) 3664 { 3665 uint8_t portn; 3666 nxge_status_t status = NXGE_OK; 3667 3668 portn = nxgep->mac.portnum; 3669 3670 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_link_intr: port<%d>", portn)); 3671 if (!nxgep->xcvr.link_intr_stop || !nxgep->xcvr.link_intr_start) 3672 return (NXGE_OK); 3673 3674 if (enable == LINK_INTR_START) 3675 status = nxgep->xcvr.link_intr_start(nxgep); 3676 else if (enable == LINK_INTR_STOP) 3677 status = nxgep->xcvr.link_intr_stop(nxgep); 3678 if (status != NXGE_OK) 3679 goto fail; 3680 3681 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_link_intr: port<%d>", portn)); 3682 3683 return (NXGE_OK); 3684 fail: 3685 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3686 "nxge_link_intr: Failed to set port<%d> mif intr mode", portn)); 3687 3688 return (status); 3689 } 3690 3691 /* Initialize 1G Fiber / Copper transceiver using Clause 22 */ 3692 3693 nxge_status_t 3694 nxge_mii_xcvr_init(p_nxge_t nxgep) 3695 { 3696 p_nxge_param_t param_arr; 3697 p_nxge_stats_t statsp; 3698 uint8_t xcvr_portn; 3699 p_mii_regs_t mii_regs; 3700 mii_bmcr_t bmcr; 3701 mii_bmsr_t bmsr; 3702 mii_anar_t anar; 3703 mii_gcr_t gcr; 3704 mii_esr_t esr; 3705 mii_aux_ctl_t bcm5464r_aux; 3706 int status = NXGE_OK; 3707 3708 uint_t delay; 3709 3710 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_mii_xcvr_init")); 3711 3712 param_arr = nxgep->param_arr; 3713 statsp = nxgep->statsp; 3714 xcvr_portn = statsp->mac_stats.xcvr_portn; 3715 3716 mii_regs = NULL; 3717 3718 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 3719 "nxge_param_autoneg = 0x%02x", param_arr[param_autoneg].value)); 3720 3721 /* 3722 * The mif phy mode may be connected to either a copper link 3723 * or fiber link. Read the mode control register to get the fiber 3724 * configuration if it is hard-wired to fiber link. 3725 */ 3726 (void) nxge_mii_get_link_mode(nxgep); 3727 if (nxgep->mac.portmode == PORT_1G_RGMII_FIBER) { 3728 return (nxge_mii_xcvr_fiber_init(nxgep)); 3729 } 3730 3731 /* 3732 * Reset the transceiver. 3733 */ 3734 delay = 0; 3735 bmcr.value = 0; 3736 bmcr.bits.reset = 1; 3737 if ((status = nxge_mii_write(nxgep, xcvr_portn, 3738 #if defined(__i386) 3739 (uint8_t)(uint32_t)&mii_regs->bmcr, 3740 #else 3741 (uint8_t)(uint64_t)&mii_regs->bmcr, 3742 #endif 3743 bmcr.value)) != NXGE_OK) 3744 goto fail; 3745 do { 3746 drv_usecwait(500); 3747 if ((status = nxge_mii_read(nxgep, xcvr_portn, 3748 #if defined(__i386) 3749 (uint8_t)(uint32_t)&mii_regs->bmcr, 3750 #else 3751 (uint8_t)(uint64_t)&mii_regs->bmcr, 3752 #endif 3753 &bmcr.value)) != NXGE_OK) 3754 goto fail; 3755 delay++; 3756 } while ((bmcr.bits.reset) && (delay < 1000)); 3757 if (delay == 1000) { 3758 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "Xcvr reset failed.")); 3759 goto fail; 3760 } 3761 3762 if ((status = nxge_mii_read(nxgep, xcvr_portn, 3763 #if defined(__i386) 3764 (uint8_t)(uint32_t)(&mii_regs->bmsr), 3765 #else 3766 (uint8_t)(uint64_t)(&mii_regs->bmsr), 3767 #endif 3768 &bmsr.value)) != NXGE_OK) 3769 goto fail; 3770 3771 param_arr[param_autoneg].value &= bmsr.bits.auto_neg_able; 3772 param_arr[param_anar_100T4].value &= bmsr.bits.link_100T4; 3773 param_arr[param_anar_100fdx].value &= bmsr.bits.link_100fdx; 3774 param_arr[param_anar_100hdx].value = 0; 3775 param_arr[param_anar_10fdx].value &= bmsr.bits.link_10fdx; 3776 param_arr[param_anar_10hdx].value = 0; 3777 3778 /* 3779 * Initialize the xcvr statistics. 3780 */ 3781 statsp->mac_stats.cap_autoneg = bmsr.bits.auto_neg_able; 3782 statsp->mac_stats.cap_100T4 = bmsr.bits.link_100T4; 3783 statsp->mac_stats.cap_100fdx = bmsr.bits.link_100fdx; 3784 statsp->mac_stats.cap_100hdx = 0; 3785 statsp->mac_stats.cap_10fdx = bmsr.bits.link_10fdx; 3786 statsp->mac_stats.cap_10hdx = 0; 3787 statsp->mac_stats.cap_asmpause = param_arr[param_anar_asmpause].value; 3788 statsp->mac_stats.cap_pause = param_arr[param_anar_pause].value; 3789 3790 /* 3791 * Initialize the xcvr advertised capability statistics. 3792 */ 3793 statsp->mac_stats.adv_cap_autoneg = param_arr[param_autoneg].value; 3794 statsp->mac_stats.adv_cap_1000fdx = param_arr[param_anar_1000fdx].value; 3795 statsp->mac_stats.adv_cap_1000hdx = param_arr[param_anar_1000hdx].value; 3796 statsp->mac_stats.adv_cap_100T4 = param_arr[param_anar_100T4].value; 3797 statsp->mac_stats.adv_cap_100fdx = param_arr[param_anar_100fdx].value; 3798 statsp->mac_stats.adv_cap_100hdx = param_arr[param_anar_100hdx].value; 3799 statsp->mac_stats.adv_cap_10fdx = param_arr[param_anar_10fdx].value; 3800 statsp->mac_stats.adv_cap_10hdx = param_arr[param_anar_10hdx].value; 3801 statsp->mac_stats.adv_cap_asmpause = 3802 param_arr[param_anar_asmpause].value; 3803 statsp->mac_stats.adv_cap_pause = param_arr[param_anar_pause].value; 3804 3805 3806 /* 3807 * Check for extended status just in case we're 3808 * running a Gigibit phy. 3809 */ 3810 if (bmsr.bits.extend_status) { 3811 if ((status = nxge_mii_read(nxgep, xcvr_portn, 3812 #if defined(__i386) 3813 (uint8_t)(uint32_t)(&mii_regs->esr), 3814 #else 3815 (uint8_t)(uint64_t)(&mii_regs->esr), 3816 #endif 3817 &esr.value)) != NXGE_OK) 3818 goto fail; 3819 param_arr[param_anar_1000fdx].value &= esr.bits.link_1000fdx; 3820 param_arr[param_anar_1000hdx].value = 0; 3821 3822 statsp->mac_stats.cap_1000fdx = 3823 (esr.bits.link_1000Xfdx || esr.bits.link_1000fdx); 3824 statsp->mac_stats.cap_1000hdx = 0; 3825 } else { 3826 param_arr[param_anar_1000fdx].value = 0; 3827 param_arr[param_anar_1000hdx].value = 0; 3828 } 3829 3830 /* 3831 * Initialize 1G Statistics once the capability is established. 3832 */ 3833 statsp->mac_stats.adv_cap_1000fdx = param_arr[param_anar_1000fdx].value; 3834 statsp->mac_stats.adv_cap_1000hdx = param_arr[param_anar_1000hdx].value; 3835 3836 /* 3837 * Initialize the link statistics. 3838 */ 3839 statsp->mac_stats.link_T4 = 0; 3840 statsp->mac_stats.link_asmpause = 0; 3841 statsp->mac_stats.link_pause = 0; 3842 statsp->mac_stats.link_speed = 0; 3843 statsp->mac_stats.link_duplex = 0; 3844 statsp->mac_stats.link_up = 0; 3845 3846 /* 3847 * Switch off Auto-negotiation, 100M and full duplex. 3848 */ 3849 bmcr.value = 0; 3850 if ((status = nxge_mii_write(nxgep, xcvr_portn, 3851 #if defined(__i386) 3852 (uint8_t)(uint32_t)(&mii_regs->bmcr), 3853 #else 3854 (uint8_t)(uint64_t)(&mii_regs->bmcr), 3855 #endif 3856 bmcr.value)) != NXGE_OK) 3857 goto fail; 3858 3859 if ((statsp->port_stats.lb_mode == nxge_lb_phy) || 3860 (statsp->port_stats.lb_mode == nxge_lb_phy1000)) { 3861 bmcr.bits.loopback = 1; 3862 bmcr.bits.enable_autoneg = 0; 3863 if (statsp->port_stats.lb_mode == nxge_lb_phy1000) 3864 bmcr.bits.speed_1000_sel = 1; 3865 bmcr.bits.duplex_mode = 1; 3866 param_arr[param_autoneg].value = 0; 3867 } else { 3868 bmcr.bits.loopback = 0; 3869 } 3870 3871 if ((statsp->port_stats.lb_mode == nxge_lb_ext1000) || 3872 (statsp->port_stats.lb_mode == nxge_lb_ext100) || 3873 (statsp->port_stats.lb_mode == nxge_lb_ext10)) { 3874 param_arr[param_autoneg].value = 0; 3875 bcm5464r_aux.value = 0; 3876 bcm5464r_aux.bits.ext_lb = 1; 3877 bcm5464r_aux.bits.write_1 = 1; 3878 if ((status = nxge_mii_write(nxgep, xcvr_portn, 3879 BCM5464R_AUX_CTL, bcm5464r_aux.value)) != NXGE_OK) 3880 goto fail; 3881 } 3882 3883 /* If auto-negotiation is desired */ 3884 if (param_arr[param_autoneg].value) { 3885 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 3886 "Restarting Auto-negotiation.")); 3887 /* 3888 * Setup our Auto-negotiation advertisement register. 3889 */ 3890 anar.value = 0; 3891 anar.bits.selector = 1; 3892 anar.bits.cap_100T4 = param_arr[param_anar_100T4].value; 3893 anar.bits.cap_100fdx = param_arr[param_anar_100fdx].value; 3894 anar.bits.cap_100hdx = param_arr[param_anar_100hdx].value; 3895 anar.bits.cap_10fdx = param_arr[param_anar_10fdx].value; 3896 anar.bits.cap_10hdx = param_arr[param_anar_10hdx].value; 3897 anar.bits.cap_asmpause = 0; 3898 anar.bits.cap_pause = 0; 3899 if (param_arr[param_anar_1000fdx].value || 3900 param_arr[param_anar_100fdx].value || 3901 param_arr[param_anar_10fdx].value) { 3902 anar.bits.cap_asmpause = statsp->mac_stats.cap_asmpause; 3903 anar.bits.cap_pause = statsp->mac_stats.cap_pause; 3904 } 3905 3906 /* Write to the auto-negotiation advertisement register */ 3907 if ((status = nxge_mii_write(nxgep, xcvr_portn, 3908 #if defined(__i386) 3909 (uint8_t)(uint32_t)(&mii_regs->anar), 3910 #else 3911 (uint8_t)(uint64_t)(&mii_regs->anar), 3912 #endif 3913 anar.value)) != NXGE_OK) 3914 goto fail; 3915 if (bmsr.bits.extend_status) { 3916 gcr.value = 0; 3917 gcr.bits.ms_mode_en = 3918 param_arr[param_master_cfg_enable].value; 3919 gcr.bits.master = 3920 param_arr[param_master_cfg_value].value; 3921 gcr.bits.link_1000fdx = 3922 param_arr[param_anar_1000fdx].value; 3923 gcr.bits.link_1000hdx = 3924 param_arr[param_anar_1000hdx].value; 3925 if ((status = nxge_mii_write(nxgep, xcvr_portn, 3926 #if defined(__i386) 3927 (uint8_t)(uint32_t)(&mii_regs->gcr), 3928 #else 3929 (uint8_t)(uint64_t)(&mii_regs->gcr), 3930 #endif 3931 gcr.value)) != NXGE_OK) 3932 goto fail; 3933 } 3934 3935 bmcr.bits.enable_autoneg = 1; 3936 bmcr.bits.restart_autoneg = 1; 3937 3938 } else { 3939 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "Going into forced mode.")); 3940 bmcr.bits.speed_1000_sel = 3941 param_arr[param_anar_1000fdx].value | 3942 param_arr[param_anar_1000hdx].value; 3943 bmcr.bits.speed_sel = (~bmcr.bits.speed_1000_sel) & 3944 (param_arr[param_anar_100fdx].value | 3945 param_arr[param_anar_100hdx].value); 3946 3947 /* Force to 1G */ 3948 if (bmcr.bits.speed_1000_sel) { 3949 statsp->mac_stats.link_speed = 1000; 3950 gcr.value = 0; 3951 gcr.bits.ms_mode_en = 3952 param_arr[param_master_cfg_enable].value; 3953 gcr.bits.master = 3954 param_arr[param_master_cfg_value].value; 3955 if ((status = nxge_mii_write(nxgep, xcvr_portn, 3956 #if defined(__i386) 3957 (uint8_t)(uint32_t)(&mii_regs->gcr), 3958 #else 3959 (uint8_t)(uint64_t)(&mii_regs->gcr), 3960 #endif 3961 gcr.value)) != NXGE_OK) 3962 goto fail; 3963 if (param_arr[param_anar_1000fdx].value) { 3964 bmcr.bits.duplex_mode = 1; 3965 statsp->mac_stats.link_duplex = 2; 3966 } else 3967 statsp->mac_stats.link_duplex = 1; 3968 3969 /* Force to 100M */ 3970 } else if (bmcr.bits.speed_sel) { 3971 statsp->mac_stats.link_speed = 100; 3972 if (param_arr[param_anar_100fdx].value) { 3973 bmcr.bits.duplex_mode = 1; 3974 statsp->mac_stats.link_duplex = 2; 3975 } else 3976 statsp->mac_stats.link_duplex = 1; 3977 3978 /* Force to 10M */ 3979 } else { 3980 statsp->mac_stats.link_speed = 10; 3981 if (param_arr[param_anar_10fdx].value) { 3982 bmcr.bits.duplex_mode = 1; 3983 statsp->mac_stats.link_duplex = 2; 3984 } else 3985 statsp->mac_stats.link_duplex = 1; 3986 } 3987 if (statsp->mac_stats.link_duplex != 1) { 3988 statsp->mac_stats.link_asmpause = 3989 statsp->mac_stats.cap_asmpause; 3990 statsp->mac_stats.link_pause = 3991 statsp->mac_stats.cap_pause; 3992 } 3993 3994 if ((statsp->port_stats.lb_mode == nxge_lb_ext1000) || 3995 (statsp->port_stats.lb_mode == nxge_lb_ext100) || 3996 (statsp->port_stats.lb_mode == nxge_lb_ext10)) { 3997 if (statsp->port_stats.lb_mode == nxge_lb_ext1000) { 3998 /* BCM5464R 1000mbps external loopback mode */ 3999 gcr.value = 0; 4000 gcr.bits.ms_mode_en = 1; 4001 gcr.bits.master = 1; 4002 if ((status = nxge_mii_write(nxgep, xcvr_portn, 4003 #if defined(__i386) 4004 (uint8_t)(uint32_t)(&mii_regs->gcr), 4005 #else 4006 (uint8_t)(uint64_t)(&mii_regs->gcr), 4007 #endif 4008 gcr.value)) != NXGE_OK) 4009 goto fail; 4010 bmcr.value = 0; 4011 bmcr.bits.speed_1000_sel = 1; 4012 statsp->mac_stats.link_speed = 1000; 4013 } else if (statsp->port_stats.lb_mode 4014 == nxge_lb_ext100) { 4015 /* BCM5464R 100mbps external loopback mode */ 4016 bmcr.value = 0; 4017 bmcr.bits.speed_sel = 1; 4018 bmcr.bits.duplex_mode = 1; 4019 statsp->mac_stats.link_speed = 100; 4020 } else if (statsp->port_stats.lb_mode 4021 == nxge_lb_ext10) { 4022 /* BCM5464R 10mbps external loopback mode */ 4023 bmcr.value = 0; 4024 bmcr.bits.duplex_mode = 1; 4025 statsp->mac_stats.link_speed = 10; 4026 } 4027 } 4028 } 4029 4030 if ((status = nxge_mii_write(nxgep, xcvr_portn, 4031 #if defined(__i386) 4032 (uint8_t)(uint32_t)(&mii_regs->bmcr), 4033 #else 4034 (uint8_t)(uint64_t)(&mii_regs->bmcr), 4035 #endif 4036 bmcr.value)) != NXGE_OK) 4037 goto fail; 4038 4039 if ((status = nxge_mii_read(nxgep, xcvr_portn, 4040 #if defined(__i386) 4041 (uint8_t)(uint32_t)(&mii_regs->bmcr), 4042 #else 4043 (uint8_t)(uint64_t)(&mii_regs->bmcr), 4044 #endif 4045 &bmcr.value)) != NXGE_OK) 4046 goto fail; 4047 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "bmcr = 0x%04X", bmcr.value)); 4048 4049 /* 4050 * Initialize the xcvr status kept in the context structure. 4051 */ 4052 nxgep->soft_bmsr.value = 0; 4053 4054 if ((status = nxge_mii_read(nxgep, xcvr_portn, 4055 #if defined(__i386) 4056 (uint8_t)(uint32_t)(&mii_regs->bmsr), 4057 #else 4058 (uint8_t)(uint64_t)(&mii_regs->bmsr), 4059 #endif 4060 &nxgep->bmsr.value)) != NXGE_OK) 4061 goto fail; 4062 4063 statsp->mac_stats.xcvr_inits++; 4064 nxgep->bmsr.value = 0; 4065 4066 fail: 4067 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 4068 "<== nxge_mii_xcvr_init status 0x%x", status)); 4069 return (status); 4070 } 4071 4072 nxge_status_t 4073 nxge_mii_xcvr_fiber_init(p_nxge_t nxgep) 4074 { 4075 p_nxge_param_t param_arr; 4076 p_nxge_stats_t statsp; 4077 uint8_t xcvr_portn; 4078 p_mii_regs_t mii_regs; 4079 mii_bmcr_t bmcr; 4080 mii_bmsr_t bmsr; 4081 mii_gcr_t gcr; 4082 mii_esr_t esr; 4083 mii_aux_ctl_t bcm5464r_aux; 4084 int status = NXGE_OK; 4085 4086 uint_t delay; 4087 4088 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_mii_xcvr_fiber_init")); 4089 4090 param_arr = nxgep->param_arr; 4091 statsp = nxgep->statsp; 4092 xcvr_portn = statsp->mac_stats.xcvr_portn; 4093 4094 mii_regs = NULL; 4095 4096 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 4097 "nxge_mii_xcvr_fiber_init: " 4098 "nxge_param_autoneg = 0x%02x", param_arr[param_autoneg].value)); 4099 4100 /* 4101 * Reset the transceiver. 4102 */ 4103 delay = 0; 4104 bmcr.value = 0; 4105 bmcr.bits.reset = 1; 4106 4107 #if defined(__i386) 4108 4109 if ((status = nxge_mii_write(nxgep, xcvr_portn, 4110 (uint8_t)(uint32_t)(&mii_regs->bmcr), bmcr.value)) != NXGE_OK) 4111 goto fail; 4112 #else 4113 if ((status = nxge_mii_write(nxgep, xcvr_portn, 4114 (uint8_t)(uint64_t)(&mii_regs->bmcr), bmcr.value)) != NXGE_OK) 4115 goto fail; 4116 #endif 4117 do { 4118 drv_usecwait(500); 4119 #if defined(__i386) 4120 if ((status = nxge_mii_read(nxgep, xcvr_portn, 4121 (uint8_t)(uint32_t)(&mii_regs->bmcr), &bmcr.value)) 4122 != NXGE_OK) 4123 goto fail; 4124 #else 4125 if ((status = nxge_mii_read(nxgep, xcvr_portn, 4126 (uint8_t)(uint64_t)(&mii_regs->bmcr), &bmcr.value)) 4127 != NXGE_OK) 4128 goto fail; 4129 #endif 4130 delay++; 4131 } while ((bmcr.bits.reset) && (delay < 1000)); 4132 if (delay == 1000) { 4133 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "Xcvr reset failed.")); 4134 goto fail; 4135 } 4136 4137 #if defined(__i386) 4138 if ((status = nxge_mii_read(nxgep, xcvr_portn, 4139 (uint8_t)(uint32_t)(&mii_regs->bmsr), &bmsr.value)) != NXGE_OK) 4140 goto fail; 4141 #else 4142 if ((status = nxge_mii_read(nxgep, xcvr_portn, 4143 (uint8_t)(uint64_t)(&mii_regs->bmsr), &bmsr.value)) != NXGE_OK) 4144 goto fail; 4145 #endif 4146 4147 param_arr[param_autoneg].value &= bmsr.bits.auto_neg_able; 4148 param_arr[param_anar_100T4].value = 0; 4149 param_arr[param_anar_100fdx].value = 0; 4150 param_arr[param_anar_100hdx].value = 0; 4151 param_arr[param_anar_10fdx].value = 0; 4152 param_arr[param_anar_10hdx].value = 0; 4153 4154 /* 4155 * Initialize the xcvr statistics. 4156 */ 4157 statsp->mac_stats.cap_autoneg = bmsr.bits.auto_neg_able; 4158 statsp->mac_stats.cap_100T4 = 0; 4159 statsp->mac_stats.cap_100fdx = 0; 4160 statsp->mac_stats.cap_100hdx = 0; 4161 statsp->mac_stats.cap_10fdx = 0; 4162 statsp->mac_stats.cap_10hdx = 0; 4163 statsp->mac_stats.cap_asmpause = param_arr[param_anar_asmpause].value; 4164 statsp->mac_stats.cap_pause = param_arr[param_anar_pause].value; 4165 4166 /* 4167 * Initialize the xcvr advertised capability statistics. 4168 */ 4169 statsp->mac_stats.adv_cap_autoneg = param_arr[param_autoneg].value; 4170 statsp->mac_stats.adv_cap_1000fdx = param_arr[param_anar_1000fdx].value; 4171 statsp->mac_stats.adv_cap_1000hdx = param_arr[param_anar_1000hdx].value; 4172 statsp->mac_stats.adv_cap_100T4 = param_arr[param_anar_100T4].value; 4173 statsp->mac_stats.adv_cap_100fdx = param_arr[param_anar_100fdx].value; 4174 statsp->mac_stats.adv_cap_100hdx = param_arr[param_anar_100hdx].value; 4175 statsp->mac_stats.adv_cap_10fdx = param_arr[param_anar_10fdx].value; 4176 statsp->mac_stats.adv_cap_10hdx = param_arr[param_anar_10hdx].value; 4177 statsp->mac_stats.adv_cap_asmpause = 4178 param_arr[param_anar_asmpause].value; 4179 statsp->mac_stats.adv_cap_pause = param_arr[param_anar_pause].value; 4180 4181 /* 4182 * Check for extended status just in case we're 4183 * running a Gigibit phy. 4184 */ 4185 if (bmsr.bits.extend_status) { 4186 #if defined(__i386) 4187 if ((status = nxge_mii_read(nxgep, xcvr_portn, 4188 (uint8_t)(uint32_t)(&mii_regs->esr), &esr.value)) != 4189 NXGE_OK) 4190 goto fail; 4191 #else 4192 if ((status = nxge_mii_read(nxgep, xcvr_portn, 4193 (uint8_t)(uint64_t)(&mii_regs->esr), &esr.value)) != 4194 NXGE_OK) 4195 goto fail; 4196 #endif 4197 param_arr[param_anar_1000fdx].value &= 4198 esr.bits.link_1000fdx; 4199 param_arr[param_anar_1000hdx].value = 0; 4200 4201 statsp->mac_stats.cap_1000fdx = 4202 (esr.bits.link_1000Xfdx || esr.bits.link_1000fdx); 4203 statsp->mac_stats.cap_1000hdx = 0; 4204 } else { 4205 param_arr[param_anar_1000fdx].value = 0; 4206 param_arr[param_anar_1000hdx].value = 0; 4207 } 4208 4209 /* 4210 * Initialize 1G Statistics once the capability is established. 4211 */ 4212 statsp->mac_stats.adv_cap_1000fdx = param_arr[param_anar_1000fdx].value; 4213 statsp->mac_stats.adv_cap_1000hdx = param_arr[param_anar_1000hdx].value; 4214 4215 /* 4216 * Initialize the link statistics. 4217 */ 4218 statsp->mac_stats.link_T4 = 0; 4219 statsp->mac_stats.link_asmpause = 0; 4220 statsp->mac_stats.link_pause = 0; 4221 statsp->mac_stats.link_speed = 0; 4222 statsp->mac_stats.link_duplex = 0; 4223 statsp->mac_stats.link_up = 0; 4224 4225 /* 4226 * Switch off Auto-negotiation, 100M and full duplex. 4227 */ 4228 bmcr.value = 0; 4229 #if defined(__i386) 4230 if ((status = nxge_mii_write(nxgep, xcvr_portn, 4231 (uint8_t)(uint32_t)(&mii_regs->bmcr), bmcr.value)) != NXGE_OK) 4232 goto fail; 4233 #else 4234 if ((status = nxge_mii_write(nxgep, xcvr_portn, 4235 (uint8_t)(uint64_t)(&mii_regs->bmcr), bmcr.value)) != NXGE_OK) 4236 goto fail; 4237 #endif 4238 4239 if ((statsp->port_stats.lb_mode == nxge_lb_phy) || 4240 (statsp->port_stats.lb_mode == nxge_lb_phy1000)) { 4241 bmcr.bits.loopback = 1; 4242 bmcr.bits.enable_autoneg = 0; 4243 if (statsp->port_stats.lb_mode == nxge_lb_phy1000) 4244 bmcr.bits.speed_1000_sel = 1; 4245 bmcr.bits.duplex_mode = 1; 4246 param_arr[param_autoneg].value = 0; 4247 } else { 4248 bmcr.bits.loopback = 0; 4249 } 4250 4251 if (statsp->port_stats.lb_mode == nxge_lb_ext1000) { 4252 param_arr[param_autoneg].value = 0; 4253 bcm5464r_aux.value = 0; 4254 bcm5464r_aux.bits.ext_lb = 1; 4255 bcm5464r_aux.bits.write_1 = 1; 4256 if ((status = nxge_mii_write(nxgep, xcvr_portn, 4257 BCM5464R_AUX_CTL, bcm5464r_aux.value)) != NXGE_OK) 4258 goto fail; 4259 } 4260 4261 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "Going into forced mode.")); 4262 bmcr.bits.speed_1000_sel = 1; 4263 bmcr.bits.speed_sel = 0; 4264 bmcr.bits.duplex_mode = 1; 4265 statsp->mac_stats.link_speed = 1000; 4266 statsp->mac_stats.link_duplex = 2; 4267 4268 if ((statsp->port_stats.lb_mode == nxge_lb_ext1000)) { 4269 /* BCM5464R 1000mbps external loopback mode */ 4270 gcr.value = 0; 4271 gcr.bits.ms_mode_en = 1; 4272 gcr.bits.master = 1; 4273 #if defined(__i386) 4274 if ((status = nxge_mii_write(nxgep, xcvr_portn, 4275 (uint8_t)(uint32_t)(&mii_regs->gcr), 4276 gcr.value)) != NXGE_OK) 4277 goto fail; 4278 #else 4279 if ((status = nxge_mii_write(nxgep, xcvr_portn, 4280 (uint8_t)(uint64_t)(&mii_regs->gcr), 4281 gcr.value)) != NXGE_OK) 4282 goto fail; 4283 #endif 4284 bmcr.value = 0; 4285 bmcr.bits.speed_1000_sel = 1; 4286 statsp->mac_stats.link_speed = 1000; 4287 } 4288 4289 #if defined(__i386) 4290 if ((status = nxge_mii_write(nxgep, xcvr_portn, 4291 (uint8_t)(uint32_t)(&mii_regs->bmcr), 4292 bmcr.value)) != NXGE_OK) 4293 goto fail; 4294 #else 4295 if ((status = nxge_mii_write(nxgep, xcvr_portn, 4296 (uint8_t)(uint64_t)(&mii_regs->bmcr), 4297 bmcr.value)) != NXGE_OK) 4298 goto fail; 4299 #endif 4300 4301 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 4302 "nxge_mii_xcvr_fiber_init: value wrote bmcr = 0x%x", 4303 bmcr.value)); 4304 4305 #if defined(__i386) 4306 if ((status = nxge_mii_read(nxgep, xcvr_portn, 4307 (uint8_t)(uint32_t)(&mii_regs->bmcr), &bmcr.value)) != NXGE_OK) 4308 goto fail; 4309 #else 4310 if ((status = nxge_mii_read(nxgep, xcvr_portn, 4311 (uint8_t)(uint64_t)(&mii_regs->bmcr), &bmcr.value)) != NXGE_OK) 4312 goto fail; 4313 #endif 4314 4315 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 4316 "nxge_mii_xcvr_fiber_init: read bmcr = 0x%04X", bmcr.value)); 4317 4318 /* 4319 * Initialize the xcvr status kept in the context structure. 4320 */ 4321 nxgep->soft_bmsr.value = 0; 4322 #if defined(__i386) 4323 if ((status = nxge_mii_read(nxgep, xcvr_portn, 4324 (uint8_t)(uint32_t)(&mii_regs->bmsr), 4325 &nxgep->bmsr.value)) != NXGE_OK) 4326 goto fail; 4327 #else 4328 if ((status = nxge_mii_read(nxgep, xcvr_portn, 4329 (uint8_t)(uint64_t)(&mii_regs->bmsr), 4330 &nxgep->bmsr.value)) != NXGE_OK) 4331 goto fail; 4332 #endif 4333 4334 statsp->mac_stats.xcvr_inits++; 4335 nxgep->bmsr.value = 0; 4336 4337 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 4338 "<== nxge_mii_xcvr_fiber_init status 0x%x", status)); 4339 return (status); 4340 4341 fail: 4342 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4343 "<== nxge_mii_xcvr_fiber_init status 0x%x", status)); 4344 return (status); 4345 } 4346 4347 /* Read from a MII compliant register */ 4348 4349 nxge_status_t 4350 nxge_mii_read(p_nxge_t nxgep, uint8_t xcvr_portn, uint8_t xcvr_reg, 4351 uint16_t *value) 4352 { 4353 npi_status_t rs = NPI_SUCCESS; 4354 4355 NXGE_DEBUG_MSG((nxgep, MIF_CTL, "==> nxge_mii_read: xcvr_port<%d>" 4356 "xcvr_reg<%d>", xcvr_portn, xcvr_reg)); 4357 4358 MUTEX_ENTER(&nxgep->nxge_hw_p->nxge_mdio_lock); 4359 4360 if ((nxgep->mac.portmode == PORT_1G_COPPER) || 4361 (nxgep->mac.portmode == PORT_1G_RGMII_FIBER)) { 4362 if ((rs = npi_mac_mif_mii_read(nxgep->npi_handle, 4363 xcvr_portn, xcvr_reg, value)) != NPI_SUCCESS) 4364 goto fail; 4365 } else if ((nxgep->mac.portmode == PORT_1G_FIBER) || 4366 (nxgep->mac.portmode == PORT_1G_SERDES)) { 4367 if ((rs = npi_mac_pcs_mii_read(nxgep->npi_handle, 4368 xcvr_portn, xcvr_reg, value)) != NPI_SUCCESS) 4369 goto fail; 4370 } else 4371 goto fail; 4372 4373 MUTEX_EXIT(&nxgep->nxge_hw_p->nxge_mdio_lock); 4374 4375 NXGE_DEBUG_MSG((nxgep, MIF_CTL, "<== nxge_mii_read: xcvr_port<%d>" 4376 "xcvr_reg<%d> value=0x%x", xcvr_portn, xcvr_reg, *value)); 4377 return (NXGE_OK); 4378 fail: 4379 MUTEX_EXIT(&nxgep->nxge_hw_p->nxge_mdio_lock); 4380 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4381 "nxge_mii_read: Failed to read mii on xcvr %d", xcvr_portn)); 4382 4383 return (NXGE_ERROR | rs); 4384 } 4385 4386 /* Write to a MII compliant Register */ 4387 4388 nxge_status_t 4389 nxge_mii_write(p_nxge_t nxgep, uint8_t xcvr_portn, uint8_t xcvr_reg, 4390 uint16_t value) 4391 { 4392 npi_status_t rs = NPI_SUCCESS; 4393 4394 NXGE_DEBUG_MSG((nxgep, MIF_CTL, "==> nxge_mii_write: xcvr_port<%d>" 4395 "xcvr_reg<%d> value=0x%x", xcvr_portn, xcvr_reg, value)); 4396 4397 MUTEX_ENTER(&nxgep->nxge_hw_p->nxge_mdio_lock); 4398 4399 if ((nxgep->mac.portmode == PORT_1G_COPPER) || 4400 (nxgep->mac.portmode == PORT_1G_RGMII_FIBER)) { 4401 if ((rs = npi_mac_mif_mii_write(nxgep->npi_handle, 4402 xcvr_portn, xcvr_reg, value)) != NPI_SUCCESS) 4403 goto fail; 4404 } else if ((nxgep->mac.portmode == PORT_1G_FIBER) || 4405 (nxgep->mac.portmode == PORT_1G_SERDES)) { 4406 if ((rs = npi_mac_pcs_mii_write(nxgep->npi_handle, 4407 xcvr_portn, xcvr_reg, value)) != NPI_SUCCESS) 4408 goto fail; 4409 } else 4410 goto fail; 4411 4412 MUTEX_EXIT(&nxgep->nxge_hw_p->nxge_mdio_lock); 4413 4414 NXGE_DEBUG_MSG((nxgep, MIF_CTL, "<== nxge_mii_write: xcvr_port<%d>" 4415 "xcvr_reg<%d>", xcvr_portn, xcvr_reg)); 4416 return (NXGE_OK); 4417 fail: 4418 MUTEX_EXIT(&nxgep->nxge_hw_p->nxge_mdio_lock); 4419 4420 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4421 "nxge_mii_write: Failed to write mii on xcvr %d", xcvr_portn)); 4422 4423 return (NXGE_ERROR | rs); 4424 } 4425 4426 /* 4427 * Perform write to Clause45 serdes / transceiver device 4428 * Arguments: 4429 * xcvr_portn: The IEEE 802.3 Clause45 PHYAD, it is the same as port 4430 * number if nxge_mdio_write is used for accessing the 4431 * internal LSIL serdes. Otherwise PHYAD is different 4432 * for different platforms. 4433 * device: With each PHYAD, the driver can use MDIO to control 4434 * multiple devices inside the PHY, here "device" is an 4435 * MMD (MDIO managable device). 4436 * xcvr_reg: Each device has multiple registers. xcvr_reg specifies 4437 * the register which the driver will write value to. 4438 * value: The register value will be filled in. 4439 */ 4440 nxge_status_t 4441 nxge_mdio_read(p_nxge_t nxgep, uint8_t xcvr_portn, uint8_t device, 4442 uint16_t xcvr_reg, uint16_t *value) 4443 { 4444 npi_status_t rs = NPI_SUCCESS; 4445 4446 NXGE_DEBUG_MSG((nxgep, MIF_CTL, "==> nxge_mdio_read: xcvr_port<%d>", 4447 xcvr_portn)); 4448 4449 MUTEX_ENTER(&nxgep->nxge_hw_p->nxge_mdio_lock); 4450 4451 if ((rs = npi_mac_mif_mdio_read(nxgep->npi_handle, 4452 xcvr_portn, device, xcvr_reg, value)) != NPI_SUCCESS) 4453 goto fail; 4454 4455 MUTEX_EXIT(&nxgep->nxge_hw_p->nxge_mdio_lock); 4456 4457 NXGE_DEBUG_MSG((nxgep, MIF_CTL, "<== nxge_mdio_read: xcvr_port<%d>", 4458 xcvr_portn)); 4459 return (NXGE_OK); 4460 fail: 4461 MUTEX_EXIT(&nxgep->nxge_hw_p->nxge_mdio_lock); 4462 4463 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4464 "nxge_mdio_read: Failed to read mdio on xcvr %d", xcvr_portn)); 4465 4466 return (NXGE_ERROR | rs); 4467 } 4468 4469 /* Perform write to Clause45 serdes / transceiver device */ 4470 4471 nxge_status_t 4472 nxge_mdio_write(p_nxge_t nxgep, uint8_t xcvr_portn, uint8_t device, 4473 uint16_t xcvr_reg, uint16_t value) 4474 { 4475 npi_status_t rs = NPI_SUCCESS; 4476 4477 NXGE_DEBUG_MSG((nxgep, MIF_CTL, "==> nxge_mdio_write: xcvr_port<%d>", 4478 xcvr_portn)); 4479 4480 MUTEX_ENTER(&nxgep->nxge_hw_p->nxge_mdio_lock); 4481 4482 if ((rs = npi_mac_mif_mdio_write(nxgep->npi_handle, 4483 xcvr_portn, device, xcvr_reg, value)) != NPI_SUCCESS) 4484 goto fail; 4485 4486 MUTEX_EXIT(&nxgep->nxge_hw_p->nxge_mdio_lock); 4487 4488 NXGE_DEBUG_MSG((nxgep, MIF_CTL, "<== nxge_mdio_write: xcvr_port<%d>", 4489 xcvr_portn)); 4490 return (NXGE_OK); 4491 fail: 4492 MUTEX_EXIT(&nxgep->nxge_hw_p->nxge_mdio_lock); 4493 4494 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4495 "nxge_mdio_write: Failed to write mdio on xcvr %d", xcvr_portn)); 4496 4497 return (NXGE_ERROR | rs); 4498 } 4499 4500 4501 /* Check MII to see if there is any link status change */ 4502 4503 nxge_status_t 4504 nxge_mii_check(p_nxge_t nxgep, mii_bmsr_t bmsr, mii_bmsr_t bmsr_ints, 4505 nxge_link_state_t *link_up) 4506 { 4507 p_nxge_param_t param_arr; 4508 p_nxge_stats_t statsp; 4509 p_mii_regs_t mii_regs; 4510 p_mii_bmsr_t soft_bmsr; 4511 mii_anar_t anar; 4512 mii_anlpar_t anlpar; 4513 mii_anar_t an_common; 4514 mii_aner_t aner; 4515 mii_gsr_t gsr; 4516 nxge_status_t status = NXGE_OK; 4517 4518 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_mii_check")); 4519 4520 mii_regs = NULL; 4521 param_arr = nxgep->param_arr; 4522 statsp = nxgep->statsp; 4523 soft_bmsr = &nxgep->soft_bmsr; 4524 *link_up = LINK_NO_CHANGE; 4525 4526 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 4527 "==> nxge_mii_check bmsr 0x%x bmsr_int 0x%x", 4528 bmsr.value, bmsr_ints.value)); 4529 4530 if (bmsr_ints.bits.link_status) { 4531 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 4532 "==> nxge_mii_check (link up) bmsr 0x%x bmsr_int 0x%x", 4533 bmsr.value, bmsr_ints.value)); 4534 if (bmsr.bits.link_status) { 4535 soft_bmsr->bits.link_status = 1; 4536 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 4537 "==> nxge_mii_check (link up) soft bmsr 0x%x bmsr_int " 4538 "0x%x", bmsr.value, bmsr_ints.value)); 4539 } else { 4540 statsp->mac_stats.link_up = 0; 4541 soft_bmsr->bits.link_status = 0; 4542 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 4543 "Link down cable problem")); 4544 *link_up = LINK_IS_DOWN; 4545 } 4546 } 4547 4548 if (nxgep->mac.portmode == PORT_1G_COPPER && 4549 param_arr[param_autoneg].value) { 4550 if (bmsr_ints.bits.auto_neg_complete) { 4551 if (bmsr.bits.auto_neg_complete) 4552 soft_bmsr->bits.auto_neg_complete = 1; 4553 else 4554 soft_bmsr->bits.auto_neg_complete = 0; 4555 } 4556 if (soft_bmsr->bits.link_status == 0) { 4557 statsp->mac_stats.link_T4 = 0; 4558 statsp->mac_stats.link_speed = 0; 4559 statsp->mac_stats.link_duplex = 0; 4560 statsp->mac_stats.link_asmpause = 0; 4561 statsp->mac_stats.link_pause = 0; 4562 statsp->mac_stats.lp_cap_autoneg = 0; 4563 statsp->mac_stats.lp_cap_100T4 = 0; 4564 statsp->mac_stats.lp_cap_1000fdx = 0; 4565 statsp->mac_stats.lp_cap_1000hdx = 0; 4566 statsp->mac_stats.lp_cap_100fdx = 0; 4567 statsp->mac_stats.lp_cap_100hdx = 0; 4568 statsp->mac_stats.lp_cap_10fdx = 0; 4569 statsp->mac_stats.lp_cap_10hdx = 0; 4570 statsp->mac_stats.lp_cap_10gfdx = 0; 4571 statsp->mac_stats.lp_cap_10ghdx = 0; 4572 statsp->mac_stats.lp_cap_asmpause = 0; 4573 statsp->mac_stats.lp_cap_pause = 0; 4574 } 4575 } else 4576 soft_bmsr->bits.auto_neg_complete = 1; 4577 4578 if ((bmsr_ints.bits.link_status || 4579 bmsr_ints.bits.auto_neg_complete) && 4580 soft_bmsr->bits.link_status && 4581 soft_bmsr->bits.auto_neg_complete) { 4582 statsp->mac_stats.link_up = 1; 4583 4584 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 4585 "==> nxge_mii_check " 4586 "(auto negotiation complete or link up) " 4587 "soft bmsr 0x%x bmsr_int 0x%x", 4588 bmsr.value, bmsr_ints.value)); 4589 4590 if (nxgep->mac.portmode == PORT_1G_COPPER && 4591 param_arr[param_autoneg].value) { 4592 if ((status = nxge_mii_read(nxgep, 4593 statsp->mac_stats.xcvr_portn, 4594 #if defined(__i386) 4595 (uint8_t)(uint32_t)(&mii_regs->anar), 4596 #else 4597 (uint8_t)(uint64_t)(&mii_regs->anar), 4598 #endif 4599 &anar.value)) != NXGE_OK) 4600 goto fail; 4601 if ((status = nxge_mii_read(nxgep, 4602 statsp->mac_stats.xcvr_portn, 4603 #if defined(__i386) 4604 (uint8_t)(uint32_t)(&mii_regs->anlpar), 4605 #else 4606 (uint8_t)(uint64_t)(&mii_regs->anlpar), 4607 #endif 4608 &anlpar.value)) != NXGE_OK) 4609 goto fail; 4610 if ((status = nxge_mii_read(nxgep, 4611 statsp->mac_stats.xcvr_portn, 4612 #if defined(__i386) 4613 (uint8_t)(uint32_t)(&mii_regs->aner), 4614 #else 4615 (uint8_t)(uint64_t)(&mii_regs->aner), 4616 #endif 4617 &aner.value)) != NXGE_OK) 4618 goto fail; 4619 statsp->mac_stats.lp_cap_autoneg = aner.bits.lp_an_able; 4620 statsp->mac_stats.lp_cap_100T4 = anlpar.bits.cap_100T4; 4621 statsp->mac_stats.lp_cap_100fdx = 4622 anlpar.bits.cap_100fdx; 4623 statsp->mac_stats.lp_cap_100hdx = 4624 anlpar.bits.cap_100hdx; 4625 statsp->mac_stats.lp_cap_10fdx = anlpar.bits.cap_10fdx; 4626 statsp->mac_stats.lp_cap_10hdx = anlpar.bits.cap_10hdx; 4627 statsp->mac_stats.lp_cap_asmpause = 4628 anlpar.bits.cap_asmpause; 4629 statsp->mac_stats.lp_cap_pause = anlpar.bits.cap_pause; 4630 an_common.value = anar.value & anlpar.value; 4631 if (param_arr[param_anar_1000fdx].value || 4632 param_arr[param_anar_1000hdx].value) { 4633 if ((status = nxge_mii_read(nxgep, 4634 statsp->mac_stats.xcvr_portn, 4635 #if defined(__i386) 4636 (uint8_t)(uint32_t)(&mii_regs->gsr), 4637 #else 4638 (uint8_t)(uint64_t)(&mii_regs->gsr), 4639 #endif 4640 &gsr.value)) != NXGE_OK) 4641 goto fail; 4642 statsp->mac_stats.lp_cap_1000fdx = 4643 gsr.bits.link_1000fdx; 4644 statsp->mac_stats.lp_cap_1000hdx = 4645 gsr.bits.link_1000hdx; 4646 if (param_arr[param_anar_1000fdx].value && 4647 gsr.bits.link_1000fdx) { 4648 statsp->mac_stats.link_speed = 1000; 4649 statsp->mac_stats.link_duplex = 2; 4650 } else if ( 4651 param_arr[param_anar_1000hdx].value && 4652 gsr.bits.link_1000hdx) { 4653 statsp->mac_stats.link_speed = 1000; 4654 statsp->mac_stats.link_duplex = 1; 4655 } 4656 } 4657 if ((an_common.value != 0) && 4658 !(statsp->mac_stats.link_speed)) { 4659 if (an_common.bits.cap_100T4) { 4660 statsp->mac_stats.link_T4 = 1; 4661 statsp->mac_stats.link_speed = 100; 4662 statsp->mac_stats.link_duplex = 1; 4663 } else if (an_common.bits.cap_100fdx) { 4664 statsp->mac_stats.link_speed = 100; 4665 statsp->mac_stats.link_duplex = 2; 4666 } else if (an_common.bits.cap_100hdx) { 4667 statsp->mac_stats.link_speed = 100; 4668 statsp->mac_stats.link_duplex = 1; 4669 } else if (an_common.bits.cap_10fdx) { 4670 statsp->mac_stats.link_speed = 10; 4671 statsp->mac_stats.link_duplex = 2; 4672 } else if (an_common.bits.cap_10hdx) { 4673 statsp->mac_stats.link_speed = 10; 4674 statsp->mac_stats.link_duplex = 1; 4675 } else { 4676 goto fail; 4677 } 4678 } 4679 if (statsp->mac_stats.link_duplex != 1) { 4680 int link_pause; 4681 int cp, lcp; 4682 4683 statsp->mac_stats.link_asmpause = 4684 an_common.bits.cap_asmpause; 4685 cp = statsp->mac_stats.cap_pause; 4686 lcp = statsp->mac_stats.lp_cap_pause; 4687 if (statsp->mac_stats.link_asmpause) { 4688 if ((cp == 0) && (lcp == 1)) { 4689 link_pause = 0; 4690 } else { 4691 link_pause = 1; 4692 } 4693 } else { 4694 link_pause = an_common.bits.cap_pause; 4695 } 4696 statsp->mac_stats.link_pause = link_pause; 4697 } 4698 } else if (nxgep->mac.portmode == PORT_1G_RGMII_FIBER) { 4699 statsp->mac_stats.link_speed = 1000; 4700 statsp->mac_stats.link_duplex = 2; 4701 } 4702 *link_up = LINK_IS_UP; 4703 } 4704 4705 if (nxgep->link_notify) { 4706 *link_up = ((statsp->mac_stats.link_up) ? LINK_IS_UP : 4707 LINK_IS_DOWN); 4708 nxgep->link_notify = B_FALSE; 4709 } 4710 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_mii_check")); 4711 return (NXGE_OK); 4712 fail: 4713 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4714 "nxge_mii_check: Unable to check MII")); 4715 return (status); 4716 } 4717 4718 /* 4719 * Check PCS to see if there is any link status change. 4720 * This function is called by PORT_1G_SERDES only. 4721 */ 4722 void 4723 nxge_pcs_check(p_nxge_t nxgep, uint8_t portn, nxge_link_state_t *link_up) 4724 { 4725 p_nxge_stats_t statsp; 4726 boolean_t linkup; 4727 4728 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_pcs_check")); 4729 4730 statsp = nxgep->statsp; 4731 *link_up = LINK_NO_CHANGE; 4732 4733 (void) npi_mac_get_link_status(nxgep->npi_handle, portn, &linkup); 4734 if (linkup) { 4735 if (nxgep->link_notify || 4736 nxgep->statsp->mac_stats.link_up == 0) { 4737 statsp->mac_stats.link_up = 1; 4738 statsp->mac_stats.link_speed = 1000; 4739 statsp->mac_stats.link_duplex = 2; 4740 *link_up = LINK_IS_UP; 4741 nxgep->link_notify = B_FALSE; 4742 } 4743 } else { 4744 if (nxgep->link_notify || 4745 nxgep->statsp->mac_stats.link_up == 1) { 4746 statsp->mac_stats.link_up = 0; 4747 statsp->mac_stats.link_speed = 0; 4748 statsp->mac_stats.link_duplex = 0; 4749 *link_up = LINK_IS_DOWN; 4750 nxgep->link_notify = B_FALSE; 4751 } 4752 } 4753 4754 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_pcs_check")); 4755 } 4756 4757 /* Add a multicast address entry into the HW hash table */ 4758 4759 nxge_status_t 4760 nxge_add_mcast_addr(p_nxge_t nxgep, struct ether_addr *addrp) 4761 { 4762 uint32_t mchash; 4763 p_hash_filter_t hash_filter; 4764 uint16_t hash_bit; 4765 boolean_t rx_init = B_FALSE; 4766 uint_t j; 4767 nxge_status_t status = NXGE_OK; 4768 4769 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_add_mcast_addr")); 4770 4771 RW_ENTER_WRITER(&nxgep->filter_lock); 4772 mchash = crc32_mchash(addrp); 4773 if (nxgep->hash_filter == NULL) { 4774 NXGE_DEBUG_MSG((NULL, STR_CTL, 4775 "Allocating hash filter storage.")); 4776 nxgep->hash_filter = KMEM_ZALLOC(sizeof (hash_filter_t), 4777 KM_SLEEP); 4778 } 4779 hash_filter = nxgep->hash_filter; 4780 j = mchash / HASH_REG_WIDTH; 4781 hash_bit = (1 << (mchash % HASH_REG_WIDTH)); 4782 hash_filter->hash_filter_regs[j] |= hash_bit; 4783 hash_filter->hash_bit_ref_cnt[mchash]++; 4784 if (hash_filter->hash_bit_ref_cnt[mchash] == 1) { 4785 hash_filter->hash_ref_cnt++; 4786 rx_init = B_TRUE; 4787 } 4788 if (rx_init) { 4789 if ((status = nxge_rx_mac_disable(nxgep)) != NXGE_OK) 4790 goto fail; 4791 if ((status = nxge_rx_mac_enable(nxgep)) != NXGE_OK) 4792 goto fail; 4793 } 4794 4795 RW_EXIT(&nxgep->filter_lock); 4796 4797 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_add_mcast_addr")); 4798 4799 return (NXGE_OK); 4800 fail: 4801 RW_EXIT(&nxgep->filter_lock); 4802 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_add_mcast_addr: " 4803 "Unable to add multicast address")); 4804 return (status); 4805 } 4806 4807 /* Remove a multicast address entry from the HW hash table */ 4808 4809 nxge_status_t 4810 nxge_del_mcast_addr(p_nxge_t nxgep, struct ether_addr *addrp) 4811 { 4812 uint32_t mchash; 4813 p_hash_filter_t hash_filter; 4814 uint16_t hash_bit; 4815 boolean_t rx_init = B_FALSE; 4816 uint_t j; 4817 nxge_status_t status = NXGE_OK; 4818 4819 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_del_mcast_addr")); 4820 RW_ENTER_WRITER(&nxgep->filter_lock); 4821 mchash = crc32_mchash(addrp); 4822 if (nxgep->hash_filter == NULL) { 4823 NXGE_DEBUG_MSG((NULL, STR_CTL, 4824 "Hash filter already de_allocated.")); 4825 RW_EXIT(&nxgep->filter_lock); 4826 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_del_mcast_addr")); 4827 return (NXGE_OK); 4828 } 4829 hash_filter = nxgep->hash_filter; 4830 hash_filter->hash_bit_ref_cnt[mchash]--; 4831 if (hash_filter->hash_bit_ref_cnt[mchash] == 0) { 4832 j = mchash / HASH_REG_WIDTH; 4833 hash_bit = (1 << (mchash % HASH_REG_WIDTH)); 4834 hash_filter->hash_filter_regs[j] &= ~hash_bit; 4835 hash_filter->hash_ref_cnt--; 4836 rx_init = B_TRUE; 4837 } 4838 if (hash_filter->hash_ref_cnt == 0) { 4839 NXGE_DEBUG_MSG((NULL, STR_CTL, 4840 "De-allocating hash filter storage.")); 4841 KMEM_FREE(hash_filter, sizeof (hash_filter_t)); 4842 nxgep->hash_filter = NULL; 4843 } 4844 4845 if (rx_init) { 4846 if ((status = nxge_rx_mac_disable(nxgep)) != NXGE_OK) 4847 goto fail; 4848 if ((status = nxge_rx_mac_enable(nxgep)) != NXGE_OK) 4849 goto fail; 4850 } 4851 RW_EXIT(&nxgep->filter_lock); 4852 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_del_mcast_addr")); 4853 4854 return (NXGE_OK); 4855 fail: 4856 RW_EXIT(&nxgep->filter_lock); 4857 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_del_mcast_addr: " 4858 "Unable to remove multicast address")); 4859 4860 return (status); 4861 } 4862 4863 /* Set MAC address into MAC address HW registers */ 4864 4865 nxge_status_t 4866 nxge_set_mac_addr(p_nxge_t nxgep, struct ether_addr *addrp) 4867 { 4868 nxge_status_t status = NXGE_OK; 4869 4870 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_set_mac_addr")); 4871 4872 MUTEX_ENTER(&nxgep->ouraddr_lock); 4873 /* 4874 * Exit if the address is same as ouraddr or multicast or broadcast 4875 */ 4876 if (((addrp->ether_addr_octet[0] & 01) == 1) || 4877 (ether_cmp(addrp, ðerbroadcastaddr) == 0) || 4878 (ether_cmp(addrp, &nxgep->ouraddr) == 0)) { 4879 goto nxge_set_mac_addr_exit; 4880 } 4881 nxgep->ouraddr = *addrp; 4882 /* 4883 * Set new interface local address and re-init device. 4884 * This is destructive to any other streams attached 4885 * to this device. 4886 */ 4887 RW_ENTER_WRITER(&nxgep->filter_lock); 4888 if ((status = nxge_rx_mac_disable(nxgep)) != NXGE_OK) 4889 goto fail; 4890 if ((status = nxge_rx_mac_enable(nxgep)) != NXGE_OK) 4891 goto fail; 4892 4893 RW_EXIT(&nxgep->filter_lock); 4894 MUTEX_EXIT(&nxgep->ouraddr_lock); 4895 goto nxge_set_mac_addr_end; 4896 nxge_set_mac_addr_exit: 4897 MUTEX_EXIT(&nxgep->ouraddr_lock); 4898 nxge_set_mac_addr_end: 4899 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_set_mac_addr")); 4900 4901 return (NXGE_OK); 4902 fail: 4903 MUTEX_EXIT(&nxgep->ouraddr_lock); 4904 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_set_mac_addr: " 4905 "Unable to set mac address")); 4906 return (status); 4907 } 4908 4909 static 4910 check_link_state_t 4911 nxge_check_link_stop(nxge_t *nxge) 4912 { 4913 /* If the poll has been cancelled, return STOP. */ 4914 MUTEX_ENTER(&nxge->poll_lock); 4915 if (nxge->suspended || nxge->poll_state == LINK_MONITOR_STOPPING) { 4916 nxge->poll_state = LINK_MONITOR_STOP; 4917 nxge->nxge_link_poll_timerid = 0; 4918 cv_broadcast(&nxge->poll_cv); 4919 MUTEX_EXIT(&nxge->poll_lock); 4920 4921 NXGE_DEBUG_MSG((nxge, MAC_CTL, 4922 "nxge_check_%s_link(port<%d>) stopped.", 4923 nxge->mac.portmode == PORT_10G_FIBER ? "10g" : "mii", 4924 nxge->mac.portnum)); 4925 return (CHECK_LINK_STOP); 4926 } 4927 MUTEX_EXIT(&nxge->poll_lock); 4928 4929 return (CHECK_LINK_RESCHEDULE); 4930 } 4931 4932 /* 4933 * Check status of MII (MIF or PCS) link. 4934 * This function is called once per second, that is because this function 4935 * calls nxge_link_monitor with LINK_MONITOR_START, which starts a timer to 4936 * call this function recursively. 4937 */ 4938 static nxge_status_t 4939 nxge_check_mii_link(p_nxge_t nxgep) 4940 { 4941 mii_bmsr_t bmsr_ints, bmsr_data; 4942 mii_anlpar_t anlpar; 4943 mii_gsr_t gsr; 4944 p_mii_regs_t mii_regs; 4945 nxge_status_t status = NXGE_OK; 4946 uint8_t portn; 4947 nxge_link_state_t link_up; 4948 4949 if (nxgep->nxge_magic != NXGE_MAGIC) 4950 return (NXGE_ERROR); 4951 4952 if (nxge_check_link_stop(nxgep) == CHECK_LINK_STOP) 4953 return (NXGE_OK); 4954 4955 portn = nxgep->mac.portnum; 4956 4957 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_check_mii_link port<%d>", 4958 portn)); 4959 4960 mii_regs = NULL; 4961 4962 RW_ENTER_WRITER(&nxgep->filter_lock); 4963 4964 if (nxgep->statsp->port_stats.lb_mode > nxge_lb_ext10) 4965 goto nxge_check_mii_link_exit; 4966 4967 switch (nxgep->mac.portmode) { 4968 default: 4969 bmsr_data.value = 0; 4970 if ((status = nxge_mii_read(nxgep, 4971 nxgep->statsp->mac_stats.xcvr_portn, 4972 #if defined(__i386) 4973 (uint8_t)(uint32_t)(&mii_regs->bmsr), 4974 #else 4975 (uint8_t)(uint64_t)(&mii_regs->bmsr), 4976 #endif 4977 &bmsr_data.value)) != NXGE_OK) { 4978 goto fail; 4979 } 4980 4981 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 4982 "==> nxge_check_mii_link port<0x%x> " 4983 "RIGHT AFTER READ bmsr_data 0x%x (nxgep->bmsr 0x%x ", 4984 portn, bmsr_data.value, nxgep->bmsr.value)); 4985 4986 if (nxgep->param_arr[param_autoneg].value) { 4987 if ((status = nxge_mii_read(nxgep, 4988 nxgep->statsp->mac_stats.xcvr_portn, 4989 #if defined(__i386) 4990 (uint8_t)(uint32_t)(&mii_regs->gsr), 4991 #else 4992 (uint8_t)(uint64_t)(&mii_regs->gsr), 4993 #endif 4994 &gsr.value)) != NXGE_OK) 4995 goto fail; 4996 if ((status = nxge_mii_read(nxgep, 4997 nxgep->statsp->mac_stats.xcvr_portn, 4998 #if defined(__i386) 4999 (uint8_t)(uint32_t)(&mii_regs->anlpar), 5000 #else 5001 (uint8_t)(uint64_t)(&mii_regs->anlpar), 5002 #endif 5003 &anlpar.value)) != NXGE_OK) 5004 goto fail; 5005 if (nxgep->mac.portmode != PORT_1G_RGMII_FIBER) { 5006 5007 if (nxgep->statsp->mac_stats.link_up && 5008 ((nxgep->statsp->mac_stats.lp_cap_1000fdx ^ 5009 gsr.bits.link_1000fdx) || 5010 (nxgep->statsp->mac_stats.lp_cap_1000hdx ^ 5011 gsr.bits.link_1000hdx) || 5012 (nxgep->statsp->mac_stats.lp_cap_100T4 ^ 5013 anlpar.bits.cap_100T4) || 5014 (nxgep->statsp->mac_stats.lp_cap_100fdx ^ 5015 anlpar.bits.cap_100fdx) || 5016 (nxgep->statsp->mac_stats.lp_cap_100hdx ^ 5017 anlpar.bits.cap_100hdx) || 5018 (nxgep->statsp->mac_stats.lp_cap_10fdx ^ 5019 anlpar.bits.cap_10fdx) || 5020 (nxgep->statsp->mac_stats.lp_cap_10hdx ^ 5021 anlpar.bits.cap_10hdx))) { 5022 bmsr_data.bits.link_status = 0; 5023 } 5024 } 5025 } 5026 5027 /* Workaround for link down issue */ 5028 if (bmsr_data.value == 0) { 5029 cmn_err(CE_NOTE, "!LINK DEBUG: Read zero bmsr\n"); 5030 goto nxge_check_mii_link_exit; 5031 } 5032 5033 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 5034 "==> nxge_check_mii_link port<0x%x> :" 5035 "BEFORE BMSR ^ nxgep->bmsr 0x%x bmsr_data 0x%x", 5036 portn, nxgep->bmsr.value, bmsr_data.value)); 5037 5038 bmsr_ints.value = nxgep->bmsr.value ^ bmsr_data.value; 5039 nxgep->bmsr.value = bmsr_data.value; 5040 5041 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 5042 "==> nxge_check_mii_link port<0x%x> CALLING " 5043 "bmsr_data 0x%x bmsr_ints.value 0x%x", 5044 portn, bmsr_data.value, bmsr_ints.value)); 5045 5046 if ((status = nxge_mii_check(nxgep, bmsr_data, bmsr_ints, 5047 &link_up)) != NXGE_OK) { 5048 goto fail; 5049 } 5050 break; 5051 5052 case PORT_1G_SERDES: 5053 /* 5054 * Above default is for all cases except PORT_1G_SERDES. 5055 * The default case gets information from the PHY, but a 5056 * nxge whose portmode equals PORT_1G_SERDES does not 5057 * have a PHY. 5058 */ 5059 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 5060 "==> nxge_check_mii_link port<%d> (SERDES)", portn)); 5061 nxge_pcs_check(nxgep, portn, &link_up); 5062 break; 5063 } 5064 5065 nxge_check_mii_link_exit: 5066 RW_EXIT(&nxgep->filter_lock); 5067 if (link_up == LINK_IS_UP) { 5068 nxge_link_is_up(nxgep); 5069 } else if (link_up == LINK_IS_DOWN) { 5070 nxge_link_is_down(nxgep); 5071 } 5072 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 5073 5074 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_check_mii_link port<%d>", 5075 portn)); 5076 return (NXGE_OK); 5077 5078 fail: 5079 RW_EXIT(&nxgep->filter_lock); 5080 5081 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 5082 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5083 "nxge_check_mii_link: Failed to check link port<%d>", portn)); 5084 return (status); 5085 } 5086 5087 /*ARGSUSED*/ 5088 static nxge_status_t 5089 nxge_check_10g_link(p_nxge_t nxgep) 5090 { 5091 uint8_t portn; 5092 nxge_status_t status = NXGE_OK; 5093 boolean_t link_up; 5094 uint32_t val; 5095 npi_status_t rs; 5096 5097 if (nxgep->nxge_magic != NXGE_MAGIC) 5098 return (NXGE_ERROR); 5099 5100 if (nxge_check_link_stop(nxgep) == CHECK_LINK_STOP) 5101 return (NXGE_OK); 5102 5103 portn = nxgep->mac.portnum; 5104 val = 0; 5105 rs = NPI_SUCCESS; 5106 5107 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_check_10g_link port<%d>", 5108 portn)); 5109 5110 switch (nxgep->mac.portmode) { 5111 default: 5112 /* 5113 * Check if the phy is present in case of hot swappable phy 5114 */ 5115 if (nxgep->hot_swappable_phy) { 5116 boolean_t phy_present_now = B_FALSE; 5117 5118 /* 5119 * If this is the 2nd Goa port, then check 2 addresses 5120 * to take care of the Goa NEM card requirements. 5121 */ 5122 if (portn == 1) { 5123 if (nxge_is_phy_present(nxgep, 5124 ALT_GOA_CLAUSE45_PORT1_ADDR, 5125 BCM8706_DEV_ID, BCM_PHY_ID_MASK)) { 5126 phy_present_now = B_TRUE; 5127 nxgep->xcvr_addr = 5128 ALT_GOA_CLAUSE45_PORT1_ADDR; 5129 goto phy_check_done; 5130 } 5131 } 5132 if (nxge_is_phy_present(nxgep, 5133 (GOA_CLAUSE45_PORT_ADDR_BASE) + portn, 5134 BCM8706_DEV_ID, BCM_PHY_ID_MASK)) { 5135 nxgep->xcvr_addr = 5136 (GOA_CLAUSE45_PORT_ADDR_BASE) + portn; 5137 phy_present_now = B_TRUE; 5138 } 5139 5140 phy_check_done: 5141 if (nxgep->phy_absent) { 5142 if (phy_present_now) { 5143 /* 5144 * Detect, Initialize phy and do link up 5145 * set xcvr vals, link_init, nxge_init 5146 */ 5147 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 5148 "Hot swappable phy DETECTED!!")); 5149 nxgep->phy_absent = B_FALSE; 5150 (void) nxge_xcvr_find(nxgep); 5151 (void) nxge_link_init(nxgep); 5152 if (!(nxgep->drv_state & 5153 STATE_HW_INITIALIZED)) { 5154 status = nxge_init(nxgep); 5155 if (status != NXGE_OK) { 5156 NXGE_ERROR_MSG((nxgep, 5157 NXGE_ERR_CTL, 5158 "Hot swappable " 5159 "phy present, but" 5160 " driver init" 5161 " failed...")); 5162 goto fail; 5163 } 5164 } 5165 } 5166 5167 goto start_link_check; 5168 5169 } else if (!phy_present_now) { 5170 /* 5171 * Phy gone, bring link down reset xcvr vals 5172 */ 5173 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 5174 "Hot swappable phy REMOVED!!")); 5175 nxgep->phy_absent = B_TRUE; 5176 nxgep->statsp->mac_stats.link_up = 0; 5177 nxgep->statsp->mac_stats.link_speed = 0; 5178 nxgep->statsp->mac_stats.link_duplex = 0; 5179 nxge_link_is_down(nxgep); 5180 nxgep->link_notify = B_FALSE; 5181 5182 (void) nxge_xcvr_find(nxgep); 5183 5184 goto start_link_check; 5185 5186 } 5187 } 5188 if (nxgep->chip_id == MRVL88X201X_CHIP_ID) { 5189 status = nxge_check_mrvl88x2011_link(nxgep, &link_up); 5190 } else { 5191 status = nxge_check_bcm8704_link(nxgep, &link_up); 5192 } 5193 if (status != NXGE_OK) 5194 goto fail; 5195 break; 5196 case PORT_10G_SERDES: 5197 rs = npi_xmac_xpcs_read(nxgep->npi_handle, nxgep->mac.portnum, 5198 XPCS_REG_STATUS, &val); 5199 if (rs != 0) 5200 goto fail; 5201 5202 link_up = B_FALSE; 5203 if (val & XPCS_STATUS_LANE_ALIGN) { 5204 link_up = B_TRUE; 5205 } 5206 5207 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 5208 "==> nxge_check_10g_link port<%d> " 5209 "XPCS_REG_STATUS2 0x%x link_up %d", 5210 portn, val, link_up)); 5211 5212 break; 5213 } 5214 5215 if (link_up) { 5216 if (nxgep->link_notify || 5217 nxgep->statsp->mac_stats.link_up == 0) { 5218 if (nxge_10g_link_led_on(nxgep) != NXGE_OK) 5219 goto fail; 5220 nxgep->statsp->mac_stats.link_up = 1; 5221 nxgep->statsp->mac_stats.link_speed = 10000; 5222 nxgep->statsp->mac_stats.link_duplex = 2; 5223 5224 nxge_link_is_up(nxgep); 5225 nxgep->link_notify = B_FALSE; 5226 } 5227 } else { 5228 if (nxgep->link_notify || 5229 nxgep->statsp->mac_stats.link_up == 1) { 5230 if (nxge_10g_link_led_off(nxgep) != NXGE_OK) 5231 goto fail; 5232 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 5233 "Link down cable problem")); 5234 nxgep->statsp->mac_stats.link_up = 0; 5235 nxgep->statsp->mac_stats.link_speed = 0; 5236 nxgep->statsp->mac_stats.link_duplex = 0; 5237 5238 nxge_link_is_down(nxgep); 5239 nxgep->link_notify = B_FALSE; 5240 } 5241 } 5242 5243 start_link_check: 5244 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 5245 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_check_10g_link port<%d>", 5246 portn)); 5247 return (NXGE_OK); 5248 5249 fail: 5250 (void) nxge_check_link_stop(nxgep); 5251 5252 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5253 "nxge_check_10g_link: Failed to check link port<%d>", 5254 portn)); 5255 return (status); 5256 } 5257 5258 5259 /* Declare link down */ 5260 5261 void 5262 nxge_link_is_down(p_nxge_t nxgep) 5263 { 5264 p_nxge_stats_t statsp; 5265 char link_stat_msg[64]; 5266 5267 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_link_is_down")); 5268 5269 statsp = nxgep->statsp; 5270 (void) sprintf(link_stat_msg, "xcvr addr:0x%02x - link is down", 5271 statsp->mac_stats.xcvr_portn); 5272 5273 if (nxge_no_msg == B_FALSE) { 5274 NXGE_ERROR_MSG((nxgep, NXGE_NOTE, "%s", link_stat_msg)); 5275 } 5276 5277 mac_link_update(nxgep->mach, LINK_STATE_DOWN); 5278 5279 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_link_is_down")); 5280 } 5281 5282 /* Declare link up */ 5283 5284 void 5285 nxge_link_is_up(p_nxge_t nxgep) 5286 { 5287 p_nxge_stats_t statsp; 5288 char link_stat_msg[64]; 5289 uint32_t val; 5290 5291 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_link_is_up")); 5292 5293 statsp = nxgep->statsp; 5294 (void) sprintf(link_stat_msg, "xcvr addr:0x%02x - link is up %d Mbps ", 5295 statsp->mac_stats.xcvr_portn, 5296 statsp->mac_stats.link_speed); 5297 5298 if (statsp->mac_stats.link_T4) 5299 (void) strcat(link_stat_msg, "T4"); 5300 else if (statsp->mac_stats.link_duplex == 2) 5301 (void) strcat(link_stat_msg, "full duplex"); 5302 else 5303 (void) strcat(link_stat_msg, "half duplex"); 5304 5305 5306 /* Clean up symbol errors incurred during link transition */ 5307 if ((nxgep->mac.portmode == PORT_10G_FIBER) || 5308 (nxgep->mac.portmode == PORT_10G_SERDES)) { 5309 (void) npi_xmac_xpcs_read(nxgep->npi_handle, nxgep->mac.portnum, 5310 XPCS_REG_SYMBOL_ERR_L0_1_COUNTER, &val); 5311 (void) npi_xmac_xpcs_read(nxgep->npi_handle, nxgep->mac.portnum, 5312 XPCS_REG_SYMBOL_ERR_L2_3_COUNTER, &val); 5313 } 5314 5315 /* 5316 * If the driver was plumbed without a link (therefore auto-negotiation 5317 * could not complete), the driver will detect a link up when a cable 5318 * conneting to a link partner is plugged into the port. By the time 5319 * link-up is detected, auto-negotiation should have completed (The 5320 * TN1010 tries to contact a link partner every 8~24ms). Here we re- 5321 * configure the Neptune/NIU according to the newly negotiated speed. 5322 * This is necessary only for the TN1010 basad device because only the 5323 * TN1010 supports dual speeds. 5324 */ 5325 if (nxgep->mac.portmode == PORT_1G_TN1010 || 5326 nxgep->mac.portmode == PORT_10G_TN1010) { 5327 5328 (void) nxge_set_tn1010_param(nxgep); 5329 5330 /* 5331 * nxge_xcvr_find calls nxge_get_xcvr_type (which sets 5332 * nxgep->portmode) and nxge_setup_xcvr_table (which sets 5333 * the nxgep->xcvr to the proper nxge_xcvr_table_t struct). 5334 */ 5335 if (nxge_xcvr_find(nxgep) != NXGE_OK) { 5336 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5337 "nxge_link_is_up: nxge_xcvr_find failed")); 5338 } 5339 5340 /* nxge_link_init calls nxge_xcvr_init and nxge_serdes_init */ 5341 if (nxge_link_init(nxgep) != NXGE_OK) { 5342 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5343 "nxge_link_is_up: nxge_link_init failed")); 5344 } 5345 5346 /* 5347 * nxge_mac_init calls many subroutines including 5348 * nxge_xif_init which sets XGMII or GMII mode 5349 */ 5350 if (nxge_mac_init(nxgep) != NXGE_OK) { 5351 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5352 "nxge_link_is_up: nxge_mac_init failed")); 5353 } 5354 } else { 5355 (void) nxge_xif_init(nxgep); 5356 } 5357 5358 if (nxge_no_msg == B_FALSE) { 5359 NXGE_ERROR_MSG((nxgep, NXGE_NOTE, "%s", link_stat_msg)); 5360 } 5361 5362 mac_link_update(nxgep->mach, LINK_STATE_UP); 5363 5364 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_link_is_up")); 5365 } 5366 5367 #ifdef NXGE_DEBUG 5368 /* Dump all TN1010 Status registers */ 5369 static void 5370 nxge_dump_tn1010_status_regs(p_nxge_t nxgep) 5371 { 5372 uint16_t val; 5373 5374 nxge_mdio_read(nxgep, nxgep->xcvr_addr, 5375 TN1010_PMA_PMD_DEV_ADDR, 1, &val); 5376 cmn_err(CE_NOTE, "PMA status1 = 0x%x", val); 5377 5378 nxge_mdio_read(nxgep, nxgep->xcvr_addr, 5379 TN1010_PMA_PMD_DEV_ADDR, 8, &val); 5380 cmn_err(CE_NOTE, "PMA status2 = 0x%x", val); 5381 5382 nxge_mdio_read(nxgep, nxgep->xcvr_addr, 5383 TN1010_PMA_PMD_DEV_ADDR, 129, &val); 5384 cmn_err(CE_NOTE, "10BASET-T status = 0x%x", val); 5385 5386 nxge_mdio_read(nxgep, nxgep->xcvr_addr, 5387 TN1010_PCS_DEV_ADDR, 1, &val); 5388 cmn_err(CE_NOTE, "PCS status1 = 0x%x", val); 5389 5390 nxge_mdio_read(nxgep, nxgep->xcvr_addr, 5391 TN1010_PCS_DEV_ADDR, 8, &val); 5392 cmn_err(CE_NOTE, "PCS status2 = 0x%x", val); 5393 5394 nxge_mdio_read(nxgep, nxgep->xcvr_addr, 5395 TN1010_PCS_DEV_ADDR, 32, &val); 5396 cmn_err(CE_NOTE, "10GBASE-R status1 = 0x%x", val); 5397 5398 nxge_mdio_read(nxgep, nxgep->xcvr_addr, 5399 TN1010_PCS_DEV_ADDR, 33, &val); 5400 cmn_err(CE_NOTE, "10GBASE-R Status2 = 0x%x", val); 5401 5402 nxge_mdio_read(nxgep, nxgep->xcvr_addr, 5403 TN1010_PHYXS_DEV_ADDR, 1, &val); 5404 cmn_err(CE_NOTE, "PHYXS status1 = 0x%x", val); 5405 5406 nxge_mdio_read(nxgep, nxgep->xcvr_addr, 5407 TN1010_PHYXS_DEV_ADDR, 8, &val); 5408 cmn_err(CE_NOTE, "PHYXS status2 = 0x%x", val); 5409 5410 nxge_mdio_read(nxgep, nxgep->xcvr_addr, 5411 TN1010_PHYXS_DEV_ADDR, 24, &val); 5412 cmn_err(CE_NOTE, "XGXS Lane status = 0x%x", val); 5413 5414 nxge_mdio_read(nxgep, nxgep->xcvr_addr, 5415 TN1010_AUTONEG_DEV_ADDR, 1, &val); 5416 cmn_err(CE_NOTE, "Autoneg status = 0x%x", val); 5417 5418 nxge_mdio_read(nxgep, nxgep->xcvr_addr, 5419 TN1010_AUTONEG_DEV_ADDR, 33, &val); 5420 cmn_err(CE_NOTE, "10Gbase-T An status = 0x%x", val); 5421 5422 nxge_mdio_read(nxgep, nxgep->xcvr_addr, 5423 TN1010_VENDOR_MMD1_DEV_ADDR, 1, &val); 5424 cmn_err(CE_NOTE, "TN1010 status = 0x%x", val); 5425 5426 nxge_mdio_read(nxgep, nxgep->xcvr_addr, 5427 TN1010_VENDOR_MMD1_DEV_ADDR, 8, &val); 5428 cmn_err(CE_NOTE, "Device status = 0x%x", val); 5429 5430 nxge_mdio_read(nxgep, nxgep->xcvr_addr, 5431 TN1010_VENDOR_MMD1_DEV_ADDR, 16, &val); 5432 cmn_err(CE_NOTE, "DDR status = 0x%x", val); 5433 5434 nxge_mdio_read(nxgep, nxgep->xcvr_addr, 5435 TN1010_VENDOR_MMD1_DEV_ADDR, 17, &val); 5436 cmn_err(CE_NOTE, "DDR fault status = 0x%x", val); 5437 5438 nxge_mdio_read(nxgep, nxgep->xcvr_addr, 5439 TN1010_VENDOR_MMD1_DEV_ADDR, 11, &val); 5440 cmn_err(CE_NOTE, "Firmware Revision = 0x%x Major = 0x%x Minor = 0x%x", 5441 val, (val & 0xFF00) >> 8, val & 0x00FF); 5442 } 5443 #endif 5444 5445 /* 5446 * Calculate the bit in the multicast address filter 5447 * that selects the given * address. 5448 * Note: For GEM, the last 8-bits are used. 5449 */ 5450 uint32_t 5451 crc32_mchash(p_ether_addr_t addr) 5452 { 5453 uint8_t *cp; 5454 uint32_t crc; 5455 uint32_t c; 5456 int byte; 5457 int bit; 5458 5459 cp = (uint8_t *)addr; 5460 crc = (uint32_t)0xffffffff; 5461 for (byte = 0; byte < 6; byte++) { 5462 c = (uint32_t)cp[byte]; 5463 for (bit = 0; bit < 8; bit++) { 5464 if ((c & 0x1) ^ (crc & 0x1)) 5465 crc = (crc >> 1)^0xedb88320; 5466 else 5467 crc = (crc >> 1); 5468 c >>= 1; 5469 } 5470 } 5471 return ((~crc) >> (32 - HASH_BITS)); 5472 } 5473 5474 /* Reset serdes */ 5475 5476 nxge_status_t 5477 nxge_serdes_reset(p_nxge_t nxgep) 5478 { 5479 npi_handle_t handle; 5480 5481 handle = nxgep->npi_handle; 5482 5483 ESR_REG_WR(handle, ESR_RESET_REG, ESR_RESET_0 | ESR_RESET_1); 5484 drv_usecwait(500); 5485 ESR_REG_WR(handle, ESR_CONFIG_REG, 0); 5486 5487 return (NXGE_OK); 5488 } 5489 5490 /* 5491 * This function monitors link status using interrupt or polling. 5492 * It calls nxgep->xcvr.check_link, a member function of 5493 * nxge_xcvr_table_t. But nxgep->xcvr.check_link calls this 5494 * function back, that is why the check_link routine is 5495 * executed periodically. 5496 */ 5497 nxge_status_t 5498 nxge_link_monitor(p_nxge_t nxgep, link_mon_enable_t enable) 5499 { 5500 nxge_status_t status = NXGE_OK; 5501 5502 /* If we are a guest domain driver, don't bother. */ 5503 if (isLDOMguest(nxgep)) 5504 return (status); 5505 5506 /* 5507 * Return immediately if this is an imaginary XMAC port. 5508 * (At least, we don't have 4-port XMAC cards yet.) 5509 */ 5510 if ((nxgep->mac.portmode == PORT_10G_FIBER || 5511 nxgep->mac.portmode == PORT_10G_SERDES) && 5512 (nxgep->mac.portnum > 1)) 5513 return (NXGE_OK); 5514 5515 if (nxgep->statsp == NULL) { 5516 /* stats has not been allocated. */ 5517 return (NXGE_OK); 5518 } 5519 /* Don't check link if we're in internal loopback mode */ 5520 if (nxgep->statsp->port_stats.lb_mode >= nxge_lb_serdes10g) 5521 return (NXGE_OK); 5522 5523 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 5524 "==> nxge_link_monitor port<%d> enable=%d", 5525 nxgep->mac.portnum, enable)); 5526 if (enable == LINK_MONITOR_START) { 5527 if (nxgep->mac.linkchkmode == LINKCHK_INTR) { 5528 if ((status = nxge_link_intr(nxgep, LINK_INTR_START)) 5529 != NXGE_OK) 5530 goto fail; 5531 } else { 5532 timeout_id_t timerid; 5533 /* 5534 * check_link_stop means "Stop the link check", so 5535 * we return without starting the timer. 5536 */ 5537 if (nxge_check_link_stop(nxgep) == CHECK_LINK_STOP) 5538 return (NXGE_OK); 5539 5540 /* 5541 * Otherwise fire the timer for the nxge to check 5542 * the link using the check_link function 5543 * of the nxge_xcvr_table and pass "nxgep" as the 5544 * argument to the check_link function. 5545 */ 5546 if (nxgep->xcvr.check_link) { 5547 timerid = timeout( 5548 (fptrv_t)(nxgep->xcvr.check_link), 5549 nxgep, 5550 drv_usectohz(LINK_MONITOR_PERIOD)); 5551 MUTEX_ENTER(&nxgep->poll_lock); 5552 nxgep->nxge_link_poll_timerid = timerid; 5553 MUTEX_EXIT(&nxgep->poll_lock); 5554 } else { 5555 return (NXGE_ERROR); 5556 } 5557 } 5558 } else { 5559 if (nxgep->mac.linkchkmode == LINKCHK_INTR) { 5560 if ((status = nxge_link_intr(nxgep, LINK_INTR_STOP)) 5561 != NXGE_OK) 5562 goto fail; 5563 } else { 5564 clock_t rv; 5565 5566 MUTEX_ENTER(&nxgep->poll_lock); 5567 5568 /* If <timerid> == 0, the link monitor has */ 5569 /* never been started, or just now stopped. */ 5570 if (nxgep->nxge_link_poll_timerid == 0) { 5571 MUTEX_EXIT(&nxgep->poll_lock); 5572 return (NXGE_OK); 5573 } 5574 5575 nxgep->poll_state = LINK_MONITOR_STOPPING; 5576 rv = cv_timedwait(&nxgep->poll_cv, 5577 &nxgep->poll_lock, 5578 ddi_get_lbolt() + 5579 drv_usectohz(LM_WAIT_MULTIPLIER * 5580 LINK_MONITOR_PERIOD)); 5581 if (rv == -1) { 5582 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 5583 "==> stopping port %d: " 5584 "cv_timedwait(%d) timed out", 5585 nxgep->mac.portnum, nxgep->poll_state)); 5586 nxgep->poll_state = LINK_MONITOR_STOP; 5587 nxgep->nxge_link_poll_timerid = 0; 5588 } 5589 5590 MUTEX_EXIT(&nxgep->poll_lock); 5591 } 5592 } 5593 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 5594 "<== nxge_link_monitor port<%d> enable=%d", 5595 nxgep->mac.portnum, enable)); 5596 5597 return (NXGE_OK); 5598 fail: 5599 return (status); 5600 5601 } 5602 5603 nxge_status_t 5604 nxge_check_tn1010_link(p_nxge_t nxgep) 5605 { 5606 nxge_status_t status = NXGE_OK; 5607 nxge_link_state_t link_up; 5608 5609 if (nxgep->nxge_magic != NXGE_MAGIC) { 5610 /* magic is 0 if driver is not attached */ 5611 return (NXGE_ERROR); 5612 } 5613 5614 /* Link has been stopped, no need to continue */ 5615 if (nxge_check_link_stop(nxgep) == CHECK_LINK_STOP) { 5616 return (NXGE_OK); 5617 } 5618 5619 if (nxgep->statsp->port_stats.lb_mode > nxge_lb_ext10) 5620 goto nxge_check_tn1010_link_exit; 5621 5622 if ((status = nxge_tn1010_check(nxgep, &link_up)) != NXGE_OK) 5623 goto fail; 5624 5625 nxge_check_tn1010_link_exit: 5626 if (link_up == LINK_IS_UP) 5627 nxge_link_is_up(nxgep); 5628 else if (link_up == LINK_IS_DOWN) 5629 nxge_link_is_down(nxgep); 5630 5631 /* 5632 * nxge_link_monitor will call (nxgep->xcvr.check_link) 5633 * which could be THIS function. 5634 */ 5635 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 5636 5637 return (NXGE_OK); 5638 5639 fail: 5640 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 5641 5642 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5643 "nxge_check_tn1010_link: Failed to check link")); 5644 return (status); 5645 } 5646 5647 5648 /* 5649 * Fill variable "link_up" with either LINK_IS_UP or LINK_IS_DOWN. 5650 */ 5651 static nxge_status_t 5652 nxge_tn1010_check(p_nxge_t nxgep, nxge_link_state_t *link_up) 5653 { 5654 nxge_status_t status = NXGE_OK; 5655 p_nxge_stats_t statsp; 5656 uint8_t phy_port_addr, portn; 5657 uint16_t val; 5658 5659 *link_up = LINK_NO_CHANGE; 5660 5661 portn = NXGE_GET_PORT_NUM(nxgep->function_num); 5662 phy_port_addr = nxgep->nxge_hw_p->xcvr_addr[portn]; 5663 statsp = nxgep->statsp; 5664 5665 /* Check if link is up */ 5666 if ((status = nxge_mdio_read(nxgep, phy_port_addr, 5667 TN1010_AUTONEG_DEV_ADDR, TN1010_AUTONEG_STATUS_REG, &val)) 5668 != NXGE_OK) { 5669 goto fail; 5670 } 5671 /* 5672 * nxge_link_is_up has called nxge_set_tn1010_param and set 5673 * portmode and link_speed 5674 */ 5675 if (val & TN1010_AN_LINK_STAT_BIT) { 5676 if (nxgep->link_notify || 5677 nxgep->statsp->mac_stats.link_up == 0) { 5678 statsp->mac_stats.link_up = 1; 5679 statsp->mac_stats.link_duplex = 2; 5680 *link_up = LINK_IS_UP; 5681 nxgep->link_notify = B_FALSE; 5682 } 5683 } else { 5684 if (nxgep->link_notify || 5685 nxgep->statsp->mac_stats.link_up == 1) { 5686 statsp->mac_stats.link_up = 0; 5687 statsp->mac_stats.link_speed = 0; 5688 statsp->mac_stats.link_duplex = 0; 5689 *link_up = LINK_IS_DOWN; 5690 nxgep->link_notify = B_FALSE; 5691 } 5692 } 5693 return (NXGE_OK); 5694 5695 fail: 5696 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5697 "nxge_tn1010_check: Unable to check TN1010")); 5698 return (status); 5699 } 5700 5701 5702 /* Set promiscous mode */ 5703 5704 nxge_status_t 5705 nxge_set_promisc(p_nxge_t nxgep, boolean_t on) 5706 { 5707 nxge_status_t status = NXGE_OK; 5708 5709 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_set_promisc: on %d", on)); 5710 5711 nxgep->filter.all_phys_cnt = ((on) ? 1 : 0); 5712 5713 RW_ENTER_WRITER(&nxgep->filter_lock); 5714 5715 if ((status = nxge_rx_mac_disable(nxgep)) != NXGE_OK) { 5716 goto fail; 5717 } 5718 if ((status = nxge_rx_mac_enable(nxgep)) != NXGE_OK) { 5719 goto fail; 5720 } 5721 5722 RW_EXIT(&nxgep->filter_lock); 5723 5724 if (on) 5725 nxgep->statsp->mac_stats.promisc = B_TRUE; 5726 else 5727 nxgep->statsp->mac_stats.promisc = B_FALSE; 5728 5729 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_set_promisc")); 5730 5731 return (NXGE_OK); 5732 fail: 5733 RW_EXIT(&nxgep->filter_lock); 5734 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_set_promisc: " 5735 "Unable to set promisc (%d)", on)); 5736 5737 return (status); 5738 } 5739 5740 /*ARGSUSED*/ 5741 uint_t 5742 nxge_mif_intr(void *arg1, void *arg2) 5743 { 5744 #ifdef NXGE_DEBUG 5745 p_nxge_t nxgep = (p_nxge_t)arg2; 5746 #endif 5747 #if NXGE_MIF 5748 p_nxge_ldv_t ldvp = (p_nxge_ldv_t)arg1; 5749 uint32_t status; 5750 npi_handle_t handle; 5751 uint8_t portn; 5752 p_nxge_stats_t statsp; 5753 #endif 5754 5755 #ifdef NXGE_MIF 5756 if (arg2 == NULL || (void *)ldvp->nxgep != arg2) { 5757 nxgep = ldvp->nxgep; 5758 } 5759 nxgep = ldvp->nxgep; 5760 #endif 5761 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_mif_intr")); 5762 5763 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_mif_intr")); 5764 return (DDI_INTR_CLAIMED); 5765 5766 mif_intr_fail: 5767 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_mif_intr")); 5768 return (DDI_INTR_UNCLAIMED); 5769 } 5770 5771 /*ARGSUSED*/ 5772 uint_t 5773 nxge_mac_intr(void *arg1, void *arg2) 5774 { 5775 p_nxge_t nxgep = (p_nxge_t)arg2; 5776 p_nxge_ldv_t ldvp = (p_nxge_ldv_t)arg1; 5777 p_nxge_ldg_t ldgp; 5778 uint32_t status; 5779 npi_handle_t handle; 5780 uint8_t portn; 5781 p_nxge_stats_t statsp; 5782 npi_status_t rs = NPI_SUCCESS; 5783 5784 if (arg2 == NULL || (void *)ldvp->nxgep != arg2) { 5785 nxgep = ldvp->nxgep; 5786 } 5787 5788 ldgp = ldvp->ldgp; 5789 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_mac_intr: " 5790 "group %d", ldgp->ldg)); 5791 5792 handle = NXGE_DEV_NPI_HANDLE(nxgep); 5793 /* 5794 * This interrupt handler is for a specific 5795 * mac port. 5796 */ 5797 statsp = (p_nxge_stats_t)nxgep->statsp; 5798 portn = nxgep->mac.portnum; 5799 5800 NXGE_DEBUG_MSG((nxgep, INT_CTL, 5801 "==> nxge_mac_intr: reading mac stats: port<%d>", portn)); 5802 5803 if (nxgep->mac.porttype == PORT_TYPE_XMAC) { 5804 rs = npi_xmac_tx_get_istatus(handle, portn, 5805 (xmac_tx_iconfig_t *)&status); 5806 if (rs != NPI_SUCCESS) 5807 goto npi_fail; 5808 if (status & ICFG_XMAC_TX_ALL) { 5809 if (status & ICFG_XMAC_TX_UNDERRUN) { 5810 statsp->xmac_stats.tx_underflow_err++; 5811 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 5812 NXGE_FM_EREPORT_TXMAC_UNDERFLOW); 5813 } 5814 if (status & ICFG_XMAC_TX_MAX_PACKET_ERR) { 5815 statsp->xmac_stats.tx_maxpktsize_err++; 5816 /* 5817 * Do not send FMA ereport because this 5818 * error does not indicate HW failure. 5819 */ 5820 } 5821 if (status & ICFG_XMAC_TX_OVERFLOW) { 5822 statsp->xmac_stats.tx_overflow_err++; 5823 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 5824 NXGE_FM_EREPORT_TXMAC_OVERFLOW); 5825 } 5826 if (status & ICFG_XMAC_TX_FIFO_XFR_ERR) { 5827 statsp->xmac_stats.tx_fifo_xfr_err++; 5828 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 5829 NXGE_FM_EREPORT_TXMAC_TXFIFO_XFR_ERR); 5830 } 5831 if (status & ICFG_XMAC_TX_BYTE_CNT_EXP) { 5832 statsp->xmac_stats.tx_byte_cnt += 5833 XTXMAC_BYTE_CNT_MASK; 5834 } 5835 if (status & ICFG_XMAC_TX_FRAME_CNT_EXP) { 5836 statsp->xmac_stats.tx_frame_cnt += 5837 XTXMAC_FRM_CNT_MASK; 5838 } 5839 } 5840 5841 rs = npi_xmac_rx_get_istatus(handle, portn, 5842 (xmac_rx_iconfig_t *)&status); 5843 if (rs != NPI_SUCCESS) 5844 goto npi_fail; 5845 if (status & ICFG_XMAC_RX_ALL) { 5846 if (status & ICFG_XMAC_RX_OVERFLOW) 5847 statsp->xmac_stats.rx_overflow_err++; 5848 if (status & ICFG_XMAC_RX_UNDERFLOW) { 5849 statsp->xmac_stats.rx_underflow_err++; 5850 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 5851 NXGE_FM_EREPORT_RXMAC_UNDERFLOW); 5852 } 5853 /* 5854 * Do not send FMA ereport for the following 3 errors 5855 * because they do not indicate HW failures. 5856 */ 5857 if (status & ICFG_XMAC_RX_CRC_ERR_CNT_EXP) { 5858 statsp->xmac_stats.rx_crc_err_cnt += 5859 XRXMAC_CRC_ER_CNT_MASK; 5860 } 5861 if (status & ICFG_XMAC_RX_LEN_ERR_CNT_EXP) { 5862 statsp->xmac_stats.rx_len_err_cnt += 5863 MAC_LEN_ER_CNT_MASK; 5864 } 5865 if (status & ICFG_XMAC_RX_VIOL_ERR_CNT_EXP) { 5866 statsp->xmac_stats.rx_viol_err_cnt += 5867 XRXMAC_CD_VIO_CNT_MASK; 5868 } 5869 if (status & ICFG_XMAC_RX_OCT_CNT_EXP) { 5870 statsp->xmac_stats.rx_byte_cnt += 5871 XRXMAC_BT_CNT_MASK; 5872 } 5873 if (status & ICFG_XMAC_RX_HST_CNT1_EXP) { 5874 statsp->xmac_stats.rx_hist1_cnt += 5875 XRXMAC_HIST_CNT1_MASK; 5876 } 5877 if (status & ICFG_XMAC_RX_HST_CNT2_EXP) { 5878 statsp->xmac_stats.rx_hist2_cnt += 5879 XRXMAC_HIST_CNT2_MASK; 5880 } 5881 if (status & ICFG_XMAC_RX_HST_CNT3_EXP) { 5882 statsp->xmac_stats.rx_hist3_cnt += 5883 XRXMAC_HIST_CNT3_MASK; 5884 } 5885 if (status & ICFG_XMAC_RX_HST_CNT4_EXP) { 5886 statsp->xmac_stats.rx_hist4_cnt += 5887 XRXMAC_HIST_CNT4_MASK; 5888 } 5889 if (status & ICFG_XMAC_RX_HST_CNT5_EXP) { 5890 statsp->xmac_stats.rx_hist5_cnt += 5891 XRXMAC_HIST_CNT5_MASK; 5892 } 5893 if (status & ICFG_XMAC_RX_HST_CNT6_EXP) { 5894 statsp->xmac_stats.rx_hist6_cnt += 5895 XRXMAC_HIST_CNT6_MASK; 5896 } 5897 if (status & ICFG_XMAC_RX_BCAST_CNT_EXP) { 5898 statsp->xmac_stats.rx_broadcast_cnt += 5899 XRXMAC_BC_FRM_CNT_MASK; 5900 } 5901 if (status & ICFG_XMAC_RX_MCAST_CNT_EXP) { 5902 statsp->xmac_stats.rx_mult_cnt += 5903 XRXMAC_MC_FRM_CNT_MASK; 5904 } 5905 /* 5906 * Do not send FMA ereport for the following 3 errors 5907 * because they do not indicate HW failures. 5908 */ 5909 if (status & ICFG_XMAC_RX_FRAG_CNT_EXP) { 5910 statsp->xmac_stats.rx_frag_cnt += 5911 XRXMAC_FRAG_CNT_MASK; 5912 } 5913 if (status & ICFG_XMAC_RX_ALIGNERR_CNT_EXP) { 5914 statsp->xmac_stats.rx_frame_align_err_cnt += 5915 XRXMAC_AL_ER_CNT_MASK; 5916 } 5917 if (status & ICFG_XMAC_RX_LINK_FLT_CNT_EXP) { 5918 statsp->xmac_stats.rx_linkfault_err_cnt += 5919 XMAC_LINK_FLT_CNT_MASK; 5920 } 5921 if (status & ICFG_XMAC_RX_REMOTE_FLT_DET) { 5922 statsp->xmac_stats.rx_remotefault_err++; 5923 } 5924 if (status & ICFG_XMAC_RX_LOCAL_FLT_DET) { 5925 statsp->xmac_stats.rx_localfault_err++; 5926 } 5927 } 5928 5929 rs = npi_xmac_ctl_get_istatus(handle, portn, 5930 (xmac_ctl_iconfig_t *)&status); 5931 if (rs != NPI_SUCCESS) 5932 goto npi_fail; 5933 if (status & ICFG_XMAC_CTRL_ALL) { 5934 if (status & ICFG_XMAC_CTRL_PAUSE_RCVD) 5935 statsp->xmac_stats.rx_pause_cnt++; 5936 if (status & ICFG_XMAC_CTRL_PAUSE_STATE) 5937 statsp->xmac_stats.tx_pause_state++; 5938 if (status & ICFG_XMAC_CTRL_NOPAUSE_STATE) 5939 statsp->xmac_stats.tx_nopause_state++; 5940 } 5941 } else if (nxgep->mac.porttype == PORT_TYPE_BMAC) { 5942 rs = npi_bmac_tx_get_istatus(handle, portn, 5943 (bmac_tx_iconfig_t *)&status); 5944 if (rs != NPI_SUCCESS) 5945 goto npi_fail; 5946 if (status & ICFG_BMAC_TX_ALL) { 5947 if (status & ICFG_BMAC_TX_UNDERFLOW) { 5948 statsp->bmac_stats.tx_underrun_err++; 5949 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 5950 NXGE_FM_EREPORT_TXMAC_UNDERFLOW); 5951 } 5952 if (status & ICFG_BMAC_TX_MAXPKTSZ_ERR) { 5953 statsp->bmac_stats.tx_max_pkt_err++; 5954 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 5955 NXGE_FM_EREPORT_TXMAC_MAX_PKT_ERR); 5956 } 5957 if (status & ICFG_BMAC_TX_BYTE_CNT_EXP) { 5958 statsp->bmac_stats.tx_byte_cnt += 5959 BTXMAC_BYTE_CNT_MASK; 5960 } 5961 if (status & ICFG_BMAC_TX_FRAME_CNT_EXP) { 5962 statsp->bmac_stats.tx_frame_cnt += 5963 BTXMAC_FRM_CNT_MASK; 5964 } 5965 } 5966 5967 rs = npi_bmac_rx_get_istatus(handle, portn, 5968 (bmac_rx_iconfig_t *)&status); 5969 if (rs != NPI_SUCCESS) 5970 goto npi_fail; 5971 if (status & ICFG_BMAC_RX_ALL) { 5972 if (status & ICFG_BMAC_RX_OVERFLOW) { 5973 statsp->bmac_stats.rx_overflow_err++; 5974 } 5975 if (status & ICFG_BMAC_RX_FRAME_CNT_EXP) { 5976 statsp->bmac_stats.rx_frame_cnt += 5977 RXMAC_FRM_CNT_MASK; 5978 } 5979 if (status & ICFG_BMAC_RX_CRC_ERR_CNT_EXP) { 5980 statsp->bmac_stats.rx_crc_err_cnt += 5981 BMAC_CRC_ER_CNT_MASK; 5982 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 5983 NXGE_FM_EREPORT_RXMAC_CRC_ERRCNT_EXP); 5984 } 5985 if (status & ICFG_BMAC_RX_LEN_ERR_CNT_EXP) { 5986 statsp->bmac_stats.rx_len_err_cnt += 5987 MAC_LEN_ER_CNT_MASK; 5988 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 5989 NXGE_FM_EREPORT_RXMAC_LENGTH_ERRCNT_EXP); 5990 } 5991 if (status & ICFG_BMAC_RX_VIOL_ERR_CNT_EXP) 5992 statsp->bmac_stats.rx_viol_err_cnt += 5993 BMAC_CD_VIO_CNT_MASK; 5994 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 5995 NXGE_FM_EREPORT_RXMAC_VIOL_ERRCNT_EXP); 5996 } 5997 if (status & ICFG_BMAC_RX_BYTE_CNT_EXP) { 5998 statsp->bmac_stats.rx_byte_cnt += 5999 BRXMAC_BYTE_CNT_MASK; 6000 } 6001 if (status & ICFG_BMAC_RX_ALIGNERR_CNT_EXP) { 6002 statsp->bmac_stats.rx_align_err_cnt += 6003 BMAC_AL_ER_CNT_MASK; 6004 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 6005 NXGE_FM_EREPORT_RXMAC_ALIGN_ECNT_EXP); 6006 } 6007 6008 rs = npi_bmac_ctl_get_istatus(handle, portn, 6009 (bmac_ctl_iconfig_t *)&status); 6010 if (rs != NPI_SUCCESS) 6011 goto npi_fail; 6012 6013 if (status & ICFG_BMAC_CTL_ALL) { 6014 if (status & ICFG_BMAC_CTL_RCVPAUSE) 6015 statsp->bmac_stats.rx_pause_cnt++; 6016 if (status & ICFG_BMAC_CTL_INPAUSE_ST) 6017 statsp->bmac_stats.tx_pause_state++; 6018 if (status & ICFG_BMAC_CTL_INNOTPAUSE_ST) 6019 statsp->bmac_stats.tx_nopause_state++; 6020 } 6021 } 6022 6023 if (ldgp->nldvs == 1) { 6024 (void) npi_intr_ldg_mgmt_set(handle, ldgp->ldg, 6025 B_TRUE, ldgp->ldg_timer); 6026 } 6027 6028 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_mac_intr")); 6029 return (DDI_INTR_CLAIMED); 6030 6031 npi_fail: 6032 NXGE_ERROR_MSG((nxgep, INT_CTL, "<== nxge_mac_intr")); 6033 return (DDI_INTR_UNCLAIMED); 6034 } 6035 6036 nxge_status_t 6037 nxge_check_bcm8704_link(p_nxge_t nxgep, boolean_t *link_up) 6038 { 6039 uint8_t phy_port_addr; 6040 nxge_status_t status = NXGE_OK; 6041 boolean_t rx_sig_ok; 6042 boolean_t pcs_blk_lock; 6043 boolean_t link_align; 6044 uint16_t val1, val2, val3; 6045 #ifdef NXGE_DEBUG_SYMBOL_ERR 6046 uint16_t val_debug; 6047 uint16_t val; 6048 #endif 6049 6050 phy_port_addr = nxgep->statsp->mac_stats.xcvr_portn; 6051 6052 #ifdef NXGE_DEBUG_SYMBOL_ERR 6053 /* Check Device 3 Register Device 3 0xC809 */ 6054 (void) nxge_mdio_read(nxgep, phy_port_addr, 0x3, 0xC809, &val_debug); 6055 if ((val_debug & ~0x200) != 0) { 6056 cmn_err(CE_NOTE, "!Port%d BCM8704 Dev3 Reg 0xc809 = 0x%x\n", 6057 nxgep->mac.portnum, val_debug); 6058 (void) nxge_mdio_read(nxgep, phy_port_addr, 0x4, 0x18, 6059 &val_debug); 6060 cmn_err(CE_NOTE, "!Port%d BCM8704 Dev4 Reg 0x18 = 0x%x\n", 6061 nxgep->mac.portnum, val_debug); 6062 } 6063 6064 (void) npi_xmac_xpcs_read(nxgep->npi_handle, nxgep->mac.portnum, 6065 XPCS_REG_DESCWERR_COUNTER, &val); 6066 if (val != 0) 6067 cmn_err(CE_NOTE, "!XPCS DESCWERR = 0x%x\n", val); 6068 6069 (void) npi_xmac_xpcs_read(nxgep->npi_handle, nxgep->mac.portnum, 6070 XPCS_REG_SYMBOL_ERR_L0_1_COUNTER, &val); 6071 if (val != 0) 6072 cmn_err(CE_NOTE, "!XPCS SYMBOL_ERR_L0_1 = 0x%x\n", val); 6073 6074 (void) npi_xmac_xpcs_read(nxgep->npi_handle, nxgep->mac.portnum, 6075 XPCS_REG_SYMBOL_ERR_L2_3_COUNTER, &val); 6076 if (val != 0) 6077 cmn_err(CE_NOTE, "!XPCS SYMBOL_ERR_L2_3 = 0x%x\n", val); 6078 #endif 6079 6080 /* Check from BCM8704 if 10G link is up or down */ 6081 6082 /* Check Device 1 Register 0xA bit0 */ 6083 status = nxge_mdio_read(nxgep, phy_port_addr, BCM8704_PMA_PMD_DEV_ADDR, 6084 BCM8704_PMD_RECEIVE_SIG_DETECT, &val1); 6085 if (status != NXGE_OK) 6086 goto fail; 6087 rx_sig_ok = ((val1 & GLOB_PMD_RX_SIG_OK) ? B_TRUE : B_FALSE); 6088 6089 /* Check Device 3 Register 0x20 bit0 */ 6090 if ((status = nxge_mdio_read(nxgep, phy_port_addr, BCM8704_PCS_DEV_ADDR, 6091 BCM8704_10GBASE_R_PCS_STATUS_REG, &val2)) != NPI_SUCCESS) 6092 goto fail; 6093 pcs_blk_lock = ((val2 & PCS_10GBASE_R_PCS_BLK_LOCK) ? B_TRUE : B_FALSE); 6094 6095 /* Check Device 4 Register 0x18 bit12 */ 6096 status = nxge_mdio_read(nxgep, phy_port_addr, BCM8704_PHYXS_ADDR, 6097 BCM8704_PHYXS_XGXS_LANE_STATUS_REG, &val3); 6098 if (status != NXGE_OK) 6099 goto fail; 6100 6101 switch (nxgep->chip_id) { 6102 case BCM8704_CHIP_ID: 6103 link_align = (val3 == (XGXS_LANE_ALIGN_STATUS | 6104 XGXS_LANE3_SYNC | XGXS_LANE2_SYNC | XGXS_LANE1_SYNC | 6105 XGXS_LANE0_SYNC | 0x400)) ? B_TRUE : B_FALSE; 6106 break; 6107 case BCM8706_CHIP_ID: 6108 link_align = ((val3 & XGXS_LANE_ALIGN_STATUS) && 6109 (val3 & XGXS_LANE3_SYNC) && (val3 & XGXS_LANE2_SYNC) && 6110 (val3 & XGXS_LANE1_SYNC) && (val3 & XGXS_LANE0_SYNC)) ? 6111 B_TRUE : B_FALSE; 6112 break; 6113 default: 6114 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_check_bcm8704_link:" 6115 "Unknown chip ID [0x%x]", nxgep->chip_id)); 6116 goto fail; 6117 } 6118 6119 6120 #ifdef NXGE_DEBUG_ALIGN_ERR 6121 /* Temp workaround for link down issue */ 6122 if (pcs_blk_lock == B_FALSE) { 6123 if (val2 != 0x4) { 6124 pcs_blk_lock = B_TRUE; 6125 cmn_err(CE_NOTE, "!LINK DEBUG: port%d PHY Dev3 " 6126 "Reg 0x20 = 0x%x\n", nxgep->mac.portnum, val2); 6127 } 6128 } 6129 6130 if (link_align == B_FALSE) { 6131 if (val3 != 0x140f) { 6132 link_align = B_TRUE; 6133 cmn_err(CE_NOTE, "!LINK DEBUG: port%d PHY Dev4 " 6134 "Reg 0x18 = 0x%x\n", nxgep->mac.portnum, val3); 6135 } 6136 } 6137 6138 if (rx_sig_ok == B_FALSE) { 6139 if ((val2 == 0) || (val3 == 0)) { 6140 rx_sig_ok = B_TRUE; 6141 cmn_err(CE_NOTE, 6142 "!LINK DEBUG: port %d Dev3 or Dev4 read zero\n", 6143 nxgep->mac.portnum); 6144 } 6145 } 6146 #endif 6147 6148 *link_up = ((rx_sig_ok == B_TRUE) && (pcs_blk_lock == B_TRUE) && 6149 (link_align == B_TRUE)) ? B_TRUE : B_FALSE; 6150 6151 return (NXGE_OK); 6152 fail: 6153 return (status); 6154 } 6155 6156 static nxge_status_t 6157 nxge_check_mrvl88x2011_link(p_nxge_t nxgep, boolean_t *link_up) 6158 { 6159 uint8_t phy; 6160 nxge_status_t status = NXGE_OK; 6161 boolean_t pma_status; 6162 boolean_t pcs_status; 6163 boolean_t xgxs_status; 6164 uint16_t val; 6165 6166 phy = nxgep->statsp->mac_stats.xcvr_portn; 6167 6168 MRVL88X2011_RD(nxgep, phy, MRVL_88X2011_USER_DEV1_ADDR, 6169 MRVL_88X2011_10G_PMD_STAT_2, &val); 6170 6171 *link_up = B_FALSE; 6172 6173 /* Check from Marvell 88X2011 if 10G link is up or down */ 6174 6175 /* Check PMA/PMD Register: 1.0001.2 == 1 */ 6176 MRVL88X2011_RD(nxgep, phy, MRVL_88X2011_USER_DEV1_ADDR, 6177 MRVL_88X2011_PMA_PMD_STAT_1, &val); 6178 6179 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6180 "nxge_check_mrvl88x2011_link: pmd=0x%x", val)); 6181 6182 pma_status = ((val & MRVL_88X2011_LNK_STATUS_OK) ? B_TRUE : B_FALSE); 6183 6184 /* Check PMC Register : 3.0001.2 == 1: read twice */ 6185 MRVL88X2011_RD(nxgep, phy, MRVL_88X2011_USER_DEV3_ADDR, 6186 MRVL_88X2011_PMA_PMD_STAT_1, &val); 6187 MRVL88X2011_RD(nxgep, phy, MRVL_88X2011_USER_DEV3_ADDR, 6188 MRVL_88X2011_PMA_PMD_STAT_1, &val); 6189 6190 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6191 "nxge_check_mrvl88x2011_link: pcs=0x%x", val)); 6192 6193 pcs_status = ((val & MRVL_88X2011_LNK_STATUS_OK) ? B_TRUE : B_FALSE); 6194 6195 /* Check XGXS Register : 4.0018.[0-3,12] */ 6196 MRVL88X2011_RD(nxgep, phy, MRVL_88X2011_USER_DEV4_ADDR, 6197 MRVL_88X2011_10G_XGXS_LANE_STAT, &val); 6198 6199 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6200 "nxge_check_mrvl88x2011_link: xgxs=0x%x", val)); 6201 6202 xgxs_status = (val == (XGXS_LANE_ALIGN_STATUS | XGXS_LANE3_SYNC | 6203 XGXS_LANE2_SYNC | XGXS_LANE1_SYNC | 6204 XGXS_LANE0_SYNC | XGXS_PATTERN_TEST_ABILITY | 6205 XGXS_LANE_STAT_MAGIC)) ? B_TRUE : B_FALSE; 6206 6207 *link_up = (pma_status && pcs_status && xgxs_status) ? 6208 B_TRUE : B_FALSE; 6209 6210 fail: 6211 6212 if (*link_up == B_FALSE) { 6213 /* PCS OFF */ 6214 nxge_mrvl88x2011_led(nxgep, MRVL_88X2011_LED_CTL_OFF); 6215 } else { 6216 /* PCS Activity */ 6217 nxge_mrvl88x2011_led(nxgep, MRVL_88X2011_LED_CTL_PCS_ACT); 6218 } 6219 6220 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6221 " <== nxge_check_mrvl88x2011_link: up=%d", *link_up)); 6222 6223 return (status); 6224 } 6225 6226 nxge_status_t 6227 nxge_10g_link_led_on(p_nxge_t nxgep) 6228 { 6229 if (npi_xmac_xif_led(nxgep->npi_handle, nxgep->mac.portnum, B_TRUE) 6230 != NPI_SUCCESS) 6231 return (NXGE_ERROR); 6232 else 6233 return (NXGE_OK); 6234 } 6235 6236 nxge_status_t 6237 nxge_10g_link_led_off(p_nxge_t nxgep) 6238 { 6239 if (npi_xmac_xif_led(nxgep->npi_handle, nxgep->mac.portnum, B_FALSE) 6240 != NPI_SUCCESS) 6241 return (NXGE_ERROR); 6242 else 6243 return (NXGE_OK); 6244 } 6245 6246 static boolean_t 6247 nxge_is_phy_present(p_nxge_t nxgep, int addr, uint32_t id, uint32_t mask) 6248 { 6249 uint32_t pma_pmd_id = 0; 6250 uint32_t pcs_id = 0; 6251 uint32_t phy_id = 0; 6252 6253 pma_pmd_id = nxge_get_cl45_pma_pmd_id(nxgep, addr); 6254 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6255 "nxge_is_phy_present: pma_pmd_id[0x%x]", pma_pmd_id)); 6256 if ((pma_pmd_id & mask) == (id & mask)) 6257 goto found_phy; 6258 pcs_id = nxge_get_cl45_pcs_id(nxgep, addr); 6259 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6260 "nxge_is_phy_present: pcs_id[0x%x]", pcs_id)); 6261 if ((pcs_id & mask) == (id & mask)) 6262 goto found_phy; 6263 phy_id = nxge_get_cl22_phy_id(nxgep, addr); 6264 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6265 "nxge_is_phy_present: phy_id[0x%x]", phy_id)); 6266 if ((phy_id & mask) == (id & mask)) 6267 goto found_phy; 6268 6269 return (B_FALSE); 6270 6271 found_phy: 6272 return (B_TRUE); 6273 } 6274 6275 /* Check if the given id read using the given MDIO Clause is supported */ 6276 6277 static boolean_t 6278 nxge_is_supported_phy(uint32_t id, uint8_t type) 6279 { 6280 int i; 6281 boolean_t found = B_FALSE; 6282 6283 switch (type) { 6284 case CLAUSE_45_TYPE: 6285 for (i = 0; i < NUM_CLAUSE_45_IDS; i++) { 6286 if (((nxge_supported_cl45_ids[i] & BCM_PHY_ID_MASK) == 6287 (id & BCM_PHY_ID_MASK)) || 6288 (TN1010_DEV_ID == (id & TN1010_DEV_ID_MASK))) { 6289 found = B_TRUE; 6290 break; 6291 } 6292 } 6293 break; 6294 case CLAUSE_22_TYPE: 6295 for (i = 0; i < NUM_CLAUSE_22_IDS; i++) { 6296 if ((nxge_supported_cl22_ids[i] & BCM_PHY_ID_MASK) == 6297 (id & BCM_PHY_ID_MASK)) { 6298 found = B_TRUE; 6299 break; 6300 } 6301 } 6302 break; 6303 default: 6304 break; 6305 } 6306 6307 return (found); 6308 } 6309 6310 static uint32_t 6311 nxge_get_cl45_pma_pmd_id(p_nxge_t nxgep, int phy_port) 6312 { 6313 uint16_t val1 = 0; 6314 uint16_t val2 = 0; 6315 uint32_t pma_pmd_dev_id = 0; 6316 npi_handle_t handle = NXGE_DEV_NPI_HANDLE(nxgep); 6317 6318 MUTEX_ENTER(&nxgep->nxge_hw_p->nxge_mdio_lock); 6319 (void) npi_mac_mif_mdio_read(handle, phy_port, NXGE_PMA_PMD_DEV_ADDR, 6320 NXGE_DEV_ID_REG_1, &val1); 6321 (void) npi_mac_mif_mdio_read(handle, phy_port, NXGE_PMA_PMD_DEV_ADDR, 6322 NXGE_DEV_ID_REG_2, &val2); 6323 MUTEX_EXIT(&nxgep->nxge_hw_p->nxge_mdio_lock); 6324 6325 /* Concatenate the Device ID stored in two registers. */ 6326 pma_pmd_dev_id = val1; 6327 pma_pmd_dev_id = (pma_pmd_dev_id << 16); 6328 pma_pmd_dev_id |= val2; 6329 6330 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "port[%d] PMA/PMD " 6331 "devid[0x%llx]", phy_port, pma_pmd_dev_id)); 6332 6333 return (pma_pmd_dev_id); 6334 } 6335 6336 static uint32_t 6337 nxge_get_cl45_pcs_id(p_nxge_t nxgep, int phy_port) 6338 { 6339 uint16_t val1 = 0; 6340 uint16_t val2 = 0; 6341 uint32_t pcs_dev_id = 0; 6342 npi_handle_t handle = NXGE_DEV_NPI_HANDLE(nxgep); 6343 6344 MUTEX_ENTER(&nxgep->nxge_hw_p->nxge_mdio_lock); 6345 (void) npi_mac_mif_mdio_read(handle, phy_port, NXGE_PCS_DEV_ADDR, 6346 NXGE_DEV_ID_REG_1, &val1); 6347 (void) npi_mac_mif_mdio_read(handle, phy_port, NXGE_PCS_DEV_ADDR, 6348 NXGE_DEV_ID_REG_2, &val2); 6349 MUTEX_EXIT(&nxgep->nxge_hw_p->nxge_mdio_lock); 6350 6351 pcs_dev_id = val1; 6352 pcs_dev_id = (pcs_dev_id << 16); 6353 pcs_dev_id |= val2; 6354 6355 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "port[%d] PCS " 6356 "devid[0x%llx]", phy_port, pcs_dev_id)); 6357 6358 return (pcs_dev_id); 6359 } 6360 6361 static uint32_t 6362 nxge_get_cl22_phy_id(p_nxge_t nxgep, int phy_port) 6363 { 6364 uint16_t val1 = 0; 6365 uint16_t val2 = 0; 6366 uint32_t phy_id = 0; 6367 npi_handle_t handle = NXGE_DEV_NPI_HANDLE(nxgep); 6368 npi_status_t npi_status = NPI_SUCCESS; 6369 6370 MUTEX_ENTER(&nxgep->nxge_hw_p->nxge_mdio_lock); 6371 npi_status = npi_mac_mif_mii_read(handle, phy_port, NXGE_PHY_ID_REG_1, 6372 &val1); 6373 if (npi_status != NPI_SUCCESS) { 6374 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "port[%d] " 6375 "clause 22 read to reg 2 failed!!!")); 6376 goto exit; 6377 } 6378 npi_status = npi_mac_mif_mii_read(handle, phy_port, NXGE_PHY_ID_REG_2, 6379 &val2); 6380 if (npi_status != 0) { 6381 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "port[%d] " 6382 "clause 22 read to reg 3 failed!!!")); 6383 goto exit; 6384 } 6385 phy_id = val1; 6386 phy_id = (phy_id << 16); 6387 phy_id |= val2; 6388 6389 exit: 6390 MUTEX_EXIT(&nxgep->nxge_hw_p->nxge_mdio_lock); 6391 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "port[%d] PHY ID [0x%llx]", 6392 phy_port, phy_id)); 6393 6394 return (phy_id); 6395 } 6396 6397 /* 6398 * Scan the PHY ports 0 through 31 to get the PHY ID using Clause 22 MDIO 6399 * read and the PMA/PMD device ID and the PCS device ID using Clause 45 MDIO 6400 * read. Then use the values obtained to determine the phy type of each port 6401 * and the Neptune type. 6402 * 6403 * This function sets hw_p->xcvr_addr[i] for future MDIO access and set 6404 * hw_p->niu_type for each nxge instance to figure out nxgep->mac.portmode 6405 * in case the portmode information is not available via OBP, nxge.conf, 6406 * VPD or SEEPROM. 6407 */ 6408 nxge_status_t 6409 nxge_scan_ports_phy(p_nxge_t nxgep, p_nxge_hw_list_t hw_p) 6410 { 6411 int i, j, l; 6412 uint32_t pma_pmd_dev_id = 0; 6413 uint32_t pcs_dev_id = 0; 6414 uint32_t phy_id = 0; 6415 uint32_t port_pma_pmd_dev_id[NXGE_PORTS_NEPTUNE]; 6416 uint32_t port_pcs_dev_id[NXGE_PORTS_NEPTUNE]; 6417 uint32_t port_phy_id[NXGE_PORTS_NEPTUNE]; 6418 uint8_t pma_pmd_dev_fd[NXGE_MAX_PHY_PORTS]; 6419 uint8_t pcs_dev_fd[NXGE_MAX_PHY_PORTS]; 6420 uint8_t phy_fd_arr[NXGE_MAX_PHY_PORTS]; 6421 uint8_t port_fd_arr[NXGE_MAX_PHY_PORTS]; 6422 uint8_t total_port_fd, total_phy_fd; 6423 uint8_t num_xaui; 6424 nxge_status_t status = NXGE_OK; 6425 6426 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_scan_ports_phy: ")); 6427 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6428 "==> nxge_scan_ports_phy: nxge niu_type[0x%x]", 6429 nxgep->niu_type)); 6430 6431 if (isLDOMguest(nxgep)) { 6432 hw_p->niu_type = NIU_TYPE_NONE; 6433 hw_p->platform_type = P_NEPTUNE_NONE; 6434 return (NXGE_OK); 6435 } 6436 6437 j = l = 0; 6438 total_port_fd = total_phy_fd = 0; 6439 /* 6440 * Clause 45 and Clause 22 port/phy addresses 0 through 5 are reserved 6441 * for on chip serdes usages. "i" in the following for loop starts at 6. 6442 */ 6443 for (i = NXGE_EXT_PHY_PORT_ST; i < NXGE_MAX_PHY_PORTS; i++) { 6444 6445 pma_pmd_dev_id = nxge_get_cl45_pma_pmd_id(nxgep, i); 6446 6447 if (nxge_is_supported_phy(pma_pmd_dev_id, CLAUSE_45_TYPE)) { 6448 pma_pmd_dev_fd[i] = 1; 6449 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "port[%d] " 6450 "PMA/PMD dev %x found", i, pma_pmd_dev_id)); 6451 if (j < NXGE_PORTS_NEPTUNE) { 6452 if ((pma_pmd_dev_id & TN1010_DEV_ID_MASK) 6453 == TN1010_DEV_ID) { 6454 port_pma_pmd_dev_id[j] = TN1010_DEV_ID; 6455 } else { 6456 port_pma_pmd_dev_id[j] = 6457 pma_pmd_dev_id & BCM_PHY_ID_MASK; 6458 } 6459 port_fd_arr[j] = (uint8_t)i; 6460 j++; 6461 } 6462 } else { 6463 pma_pmd_dev_fd[i] = 0; 6464 } 6465 6466 pcs_dev_id = nxge_get_cl45_pcs_id(nxgep, i); 6467 6468 if (nxge_is_supported_phy(pcs_dev_id, CLAUSE_45_TYPE)) { 6469 pcs_dev_fd[i] = 1; 6470 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "port[%d] PCS " 6471 "dev %x found", i, pcs_dev_id)); 6472 if (pma_pmd_dev_fd[i] == 1) { 6473 if ((pcs_dev_id & TN1010_DEV_ID_MASK) 6474 == TN1010_DEV_ID) { 6475 port_pcs_dev_id[j - 1] = 6476 TN1010_DEV_ID; 6477 } else { 6478 port_pcs_dev_id[j - 1] = 6479 pcs_dev_id & 6480 BCM_PHY_ID_MASK; 6481 } 6482 } else { 6483 if (j < NXGE_PORTS_NEPTUNE) { 6484 if ((pcs_dev_id & TN1010_DEV_ID_MASK) 6485 == TN1010_DEV_ID) { 6486 port_pcs_dev_id[j] = 6487 TN1010_DEV_ID; 6488 } else { 6489 port_pcs_dev_id[j] = 6490 pcs_dev_id & 6491 BCM_PHY_ID_MASK; 6492 } 6493 port_fd_arr[j] = (uint8_t)i; 6494 j++; 6495 } 6496 } 6497 } else { 6498 pcs_dev_fd[i] = 0; 6499 } 6500 6501 if (pcs_dev_fd[i] || pma_pmd_dev_fd[i]) { 6502 total_port_fd ++; 6503 } 6504 6505 phy_id = nxge_get_cl22_phy_id(nxgep, i); 6506 if (nxge_is_supported_phy(phy_id, CLAUSE_22_TYPE)) { 6507 total_phy_fd ++; 6508 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "port[%d] PHY ID" 6509 "%x found", i, phy_id)); 6510 if (l < NXGE_PORTS_NEPTUNE) { 6511 if ((phy_id & TN1010_DEV_ID_MASK) 6512 == TN1010_DEV_ID) { 6513 port_phy_id[l] = TN1010_DEV_ID; 6514 } else { 6515 port_phy_id[l] 6516 = phy_id & BCM_PHY_ID_MASK; 6517 } 6518 phy_fd_arr[l] = (uint8_t)i; 6519 l++; 6520 } 6521 } 6522 } 6523 6524 switch (total_port_fd) { 6525 case 2: 6526 switch (total_phy_fd) { 6527 case 2: 6528 /* 2 10G, 2 1G RGMII Fiber / copper */ 6529 if ((((port_pcs_dev_id[0] == PHY_BCM8704_FAMILY) && 6530 (port_pcs_dev_id[1] == PHY_BCM8704_FAMILY)) || 6531 ((port_pma_pmd_dev_id[0] == PHY_BCM8704_FAMILY) && 6532 (port_pma_pmd_dev_id[1] == PHY_BCM8704_FAMILY))) && 6533 ((port_phy_id[0] == PHY_BCM5482_FAMILY) && 6534 (port_phy_id[1] == PHY_BCM5482_FAMILY))) { 6535 6536 switch (hw_p->platform_type) { 6537 case P_NEPTUNE_ROCK: 6538 hw_p->niu_type = NEPTUNE_2_10GF_2_1GC; 6539 /* 6540 * ROCK platform has assigned a lower 6541 * addr to port 1. (port 0 = 0x9 and 6542 * port 1 = 0x8). 6543 */ 6544 hw_p->xcvr_addr[1] = port_fd_arr[0]; 6545 hw_p->xcvr_addr[0] = port_fd_arr[1]; 6546 6547 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6548 "Rock with 2 10G, 2 1GC")); 6549 break; 6550 6551 case P_NEPTUNE_NONE: 6552 default: 6553 hw_p->platform_type = 6554 P_NEPTUNE_GENERIC; 6555 hw_p->niu_type = NEPTUNE_2_10GF_2_1GRF; 6556 6557 hw_p->xcvr_addr[0] = port_fd_arr[0]; 6558 hw_p->xcvr_addr[1] = port_fd_arr[1]; 6559 6560 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6561 "ARTM card with 2 10G, 2 1GF")); 6562 break; 6563 } 6564 6565 hw_p->xcvr_addr[2] = phy_fd_arr[0]; 6566 hw_p->xcvr_addr[3] = phy_fd_arr[1]; 6567 6568 } else { 6569 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6570 "Unsupported neptune type 1")); 6571 goto error_exit; 6572 } 6573 break; 6574 6575 case 1: 6576 /* TODO - 2 10G, 1 1G */ 6577 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6578 "Unsupported neptune type 2 10G, 1 1G")); 6579 goto error_exit; 6580 case 0: 6581 /* 6582 * 2 10G: 2XGF NIC, Marvell, Goa, Huron with 2 XAUI 6583 * cards, etc. 6584 */ 6585 if (((port_pcs_dev_id[0] == PHY_BCM8704_FAMILY) && 6586 (port_pcs_dev_id[1] == PHY_BCM8704_FAMILY)) || 6587 ((port_pma_pmd_dev_id[0] == PHY_BCM8704_FAMILY) && 6588 (port_pma_pmd_dev_id[1] == PHY_BCM8704_FAMILY)) || 6589 ((port_pcs_dev_id[0] == MARVELL_88X201X_PHY_ID) && 6590 (port_pcs_dev_id[1] == MARVELL_88X201X_PHY_ID)) || 6591 ((port_pma_pmd_dev_id[0] == 6592 MARVELL_88X201X_PHY_ID) && 6593 (port_pma_pmd_dev_id[1] == 6594 MARVELL_88X201X_PHY_ID))) { 6595 6596 /* 6597 * Check the first phy port address against 6598 * the known phy start addresses to determine 6599 * the platform type. 6600 */ 6601 6602 switch (port_fd_arr[0]) { 6603 case NEPTUNE_CLAUSE45_PORT_ADDR_BASE: 6604 /* 6605 * The Marvell case also falls into 6606 * this case as 6607 * MRVL88X2011_NEPTUNE_PORT_ADDR_BASE 6608 * == NEPTUNE_CLAUSE45_PORT_ADDR_BASE. 6609 * This is OK for the 2 10G case. 6610 */ 6611 hw_p->niu_type = NEPTUNE_2_10GF; 6612 hw_p->platform_type = 6613 P_NEPTUNE_ATLAS_2PORT; 6614 break; 6615 case GOA_CLAUSE45_PORT_ADDR_BASE: 6616 if (hw_p->platform_type != 6617 P_NEPTUNE_NIU) { 6618 hw_p->platform_type = 6619 P_NEPTUNE_GENERIC; 6620 hw_p->niu_type = 6621 NEPTUNE_2_10GF; 6622 } 6623 break; 6624 default: 6625 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6626 "Unsupported neptune type 2 - 1")); 6627 goto error_exit; 6628 } 6629 6630 for (i = 0; i < 2; i++) { 6631 hw_p->xcvr_addr[i] = port_fd_arr[i]; 6632 } 6633 6634 /* Both XAUI slots have copper XAUI cards */ 6635 } else if ((((port_pcs_dev_id[0] & TN1010_DEV_ID_MASK) 6636 == TN1010_DEV_ID) && 6637 ((port_pcs_dev_id[1] & TN1010_DEV_ID_MASK) 6638 == TN1010_DEV_ID)) || 6639 (((port_pma_pmd_dev_id[0] & TN1010_DEV_ID_MASK) 6640 == TN1010_DEV_ID) && 6641 ((port_pma_pmd_dev_id[1] & TN1010_DEV_ID_MASK) 6642 == TN1010_DEV_ID))) { 6643 hw_p->niu_type = NEPTUNE_2_TN1010; 6644 hw_p->xcvr_addr[0] = port_fd_arr[0]; 6645 hw_p->xcvr_addr[1] = port_fd_arr[1]; 6646 6647 /* Slot0 has fiber XAUI, slot1 has copper XAUI */ 6648 } else if ((port_pcs_dev_id[0] == PHY_BCM8704_FAMILY && 6649 (port_pcs_dev_id[1] & TN1010_DEV_ID_MASK) 6650 == TN1010_DEV_ID) || 6651 (port_pma_pmd_dev_id[0] == PHY_BCM8704_FAMILY && 6652 (port_pma_pmd_dev_id[1] & TN1010_DEV_ID_MASK) == 6653 TN1010_DEV_ID)) { 6654 hw_p->niu_type = NEPTUNE_1_10GF_1_TN1010; 6655 hw_p->xcvr_addr[0] = port_fd_arr[0]; 6656 hw_p->xcvr_addr[1] = port_fd_arr[1]; 6657 6658 /* Slot0 has copper XAUI, slot1 has fiber XAUI */ 6659 } else if ((port_pcs_dev_id[1] == PHY_BCM8704_FAMILY && 6660 (port_pcs_dev_id[0] & TN1010_DEV_ID_MASK) 6661 == TN1010_DEV_ID) || 6662 (port_pma_pmd_dev_id[1] == PHY_BCM8704_FAMILY && 6663 (port_pma_pmd_dev_id[0] & TN1010_DEV_ID_MASK) 6664 == TN1010_DEV_ID)) { 6665 hw_p->niu_type = NEPTUNE_1_TN1010_1_10GF; 6666 hw_p->xcvr_addr[0] = port_fd_arr[0]; 6667 hw_p->xcvr_addr[1] = port_fd_arr[1]; 6668 6669 } else { 6670 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6671 "Unsupported neptune type 2")); 6672 goto error_exit; 6673 } 6674 break; 6675 6676 case 4: 6677 if (nxge_get_num_of_xaui( 6678 port_pma_pmd_dev_id, port_pcs_dev_id, 6679 port_phy_id, &num_xaui) == NXGE_ERROR) { 6680 goto error_exit; 6681 } 6682 if (num_xaui != 2) 6683 goto error_exit; 6684 6685 /* 6686 * Maramba with 2 XAUIs (either fiber or copper) 6687 * 6688 * Check the first phy port address against 6689 * the known phy start addresses to determine 6690 * the platform type. 6691 */ 6692 switch (phy_fd_arr[0]) { 6693 case MARAMBA_P0_CLAUSE22_PORT_ADDR_BASE: 6694 hw_p->platform_type = 6695 P_NEPTUNE_MARAMBA_P0; 6696 break; 6697 case MARAMBA_P1_CLAUSE22_PORT_ADDR_BASE: 6698 hw_p->platform_type = 6699 P_NEPTUNE_MARAMBA_P1; 6700 break; 6701 default: 6702 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6703 "Unknown port %d...Cannot " 6704 "determine platform type", i)); 6705 goto error_exit; 6706 } 6707 6708 hw_p->xcvr_addr[0] = port_fd_arr[0]; 6709 hw_p->xcvr_addr[1] = port_fd_arr[1]; 6710 hw_p->xcvr_addr[2] = phy_fd_arr[2]; 6711 hw_p->xcvr_addr[3] = phy_fd_arr[3]; 6712 6713 /* slot0 has fiber XAUI, slot1 has Cu XAUI */ 6714 if (port_pcs_dev_id[0] == PHY_BCM8704_FAMILY && 6715 (port_pcs_dev_id[1] & TN1010_DEV_ID_MASK) 6716 == TN1010_DEV_ID) { 6717 hw_p->niu_type = NEPTUNE_1_10GF_1_TN1010_2_1GC; 6718 6719 /* slot0 has Cu XAUI, slot1 has fiber XAUI */ 6720 } else if (((port_pcs_dev_id[0] & TN1010_DEV_ID_MASK) 6721 == TN1010_DEV_ID) && 6722 port_pcs_dev_id[1] == PHY_BCM8704_FAMILY) { 6723 hw_p->niu_type = NEPTUNE_1_TN1010_1_10GF_2_1GC; 6724 6725 /* Both slots have fiber XAUI */ 6726 } else if (port_pcs_dev_id[0] == PHY_BCM8704_FAMILY && 6727 port_pcs_dev_id[1] == PHY_BCM8704_FAMILY) { 6728 hw_p->niu_type = NEPTUNE_2_10GF_2_1GC; 6729 6730 /* Both slots have copper XAUI */ 6731 } else if (((port_pcs_dev_id[0] & TN1010_DEV_ID_MASK) 6732 == TN1010_DEV_ID) && 6733 (port_pcs_dev_id[1] & TN1010_DEV_ID_MASK) 6734 == TN1010_DEV_ID) { 6735 hw_p->niu_type = NEPTUNE_2_TN1010_2_1GC; 6736 6737 } else { 6738 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6739 "Unsupported neptune type 3")); 6740 goto error_exit; 6741 } 6742 break; 6743 default: 6744 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6745 "Unsupported neptune type 5")); 6746 goto error_exit; 6747 } 6748 break; 6749 case 1: /* Only one clause45 port */ 6750 switch (total_phy_fd) { /* Number of clause22 ports */ 6751 case 3: 6752 /* 6753 * TODO 3 1G, 1 10G mode. 6754 * Differentiate between 1_1G_1_10G_2_1G and 6755 * 1_10G_3_1G 6756 */ 6757 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6758 "Unsupported neptune type 7")); 6759 goto error_exit; 6760 case 2: 6761 /* 6762 * TODO 2 1G, 1 10G mode. 6763 * Differentiate between 1_1G_1_10G_1_1G and 6764 * 1_10G_2_1G 6765 */ 6766 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6767 "Unsupported neptune type 8")); 6768 goto error_exit; 6769 case 1: 6770 /* 6771 * TODO 1 1G, 1 10G mode. 6772 * Differentiate between 1_1G_1_10G and 6773 * 1_10G_1_1G 6774 */ 6775 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6776 "Unsupported neptune type 9")); 6777 goto error_exit; 6778 case 0: /* N2 with 1 XAUI (fiber or copper) */ 6779 /* Fiber XAUI */ 6780 if (port_pcs_dev_id[0] == PHY_BCM8704_FAMILY || 6781 port_pma_pmd_dev_id[0] == PHY_BCM8704_FAMILY) { 6782 6783 /* 6784 * Check the first phy port address against 6785 * the known phy start addresses to determine 6786 * the platform type. 6787 */ 6788 6789 switch (port_fd_arr[0]) { 6790 case N2_CLAUSE45_PORT_ADDR_BASE: 6791 case (N2_CLAUSE45_PORT_ADDR_BASE + 1): 6792 case ALT_GOA_CLAUSE45_PORT1_ADDR: 6793 /* 6794 * If hw_p->platform_type == 6795 * P_NEPTUNE_NIU, then portmode 6796 * is already known, so there is 6797 * no need to figure out hw_p-> 6798 * platform_type because 6799 * platform_type is only for 6800 * figuring out portmode. 6801 */ 6802 if (hw_p->platform_type != 6803 P_NEPTUNE_NIU) { 6804 hw_p->platform_type = 6805 P_NEPTUNE_GENERIC; 6806 hw_p->niu_type = 6807 NEPTUNE_2_10GF; 6808 } 6809 break; 6810 default: 6811 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6812 "Unsupported neptune type 10")); 6813 goto error_exit; 6814 } 6815 /* 6816 * For GOA, which is a hot swappable PHY, the 6817 * phy address to function number mapping 6818 * should be preserved, i.e., addr 16 is 6819 * assigned to function 0 and 20 to function 1 6820 * But for Huron XAUI, the assignment should 6821 * be by function number, i.e., whichever 6822 * function number attaches should be 6823 * assigned the available PHY (this is required 6824 * primarily to support pre-production Huron 6825 * boards where function 0 is mapped to addr 17 6826 */ 6827 if (port_fd_arr[0] == 6828 ALT_GOA_CLAUSE45_PORT1_ADDR) { 6829 hw_p->xcvr_addr[1] = port_fd_arr[0]; 6830 } else { 6831 hw_p->xcvr_addr[nxgep->function_num] = 6832 port_fd_arr[0]; 6833 } 6834 6835 /* A 10G copper XAUI in either slot0 or slot1 */ 6836 } else if ((port_pcs_dev_id[0] & TN1010_DEV_ID_MASK) 6837 == TN1010_DEV_ID || 6838 (port_pma_pmd_dev_id[0] & TN1010_DEV_ID_MASK) 6839 == TN1010_DEV_ID) { 6840 switch (port_fd_arr[0]) { 6841 /* The XAUI is in slot0 */ 6842 case N2_CLAUSE45_PORT_ADDR_BASE: 6843 hw_p->niu_type = NEPTUNE_1_TN1010; 6844 break; 6845 6846 /* The XAUI is in slot1 */ 6847 case (N2_CLAUSE45_PORT_ADDR_BASE + 1): 6848 hw_p->niu_type 6849 = NEPTUNE_1_NONE_1_TN1010; 6850 break; 6851 default: 6852 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6853 "Unsupported XAUI port address")); 6854 goto error_exit; 6855 } 6856 hw_p->xcvr_addr[nxgep->function_num] 6857 = port_fd_arr[0]; 6858 6859 } else { 6860 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6861 "Unsupported PHY type")); 6862 goto error_exit; 6863 } 6864 break; 6865 case 4: /* Maramba always have 4 clause 45 ports */ 6866 6867 /* Maramba with 1 XAUI */ 6868 if ((port_pcs_dev_id[0] != PHY_BCM8704_FAMILY) && 6869 (port_pma_pmd_dev_id[0] != PHY_BCM8704_FAMILY) && 6870 ((port_pcs_dev_id[0] & TN1010_DEV_ID_MASK) 6871 != TN1010_DEV_ID) && 6872 ((port_pma_pmd_dev_id[0] & TN1010_DEV_ID_MASK) 6873 != TN1010_DEV_ID)) { 6874 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6875 "Unsupported neptune type 12")); 6876 goto error_exit; 6877 } 6878 6879 /* 6880 * Check the first phy port address against 6881 * the known phy start addresses to determine 6882 * the platform type. 6883 */ 6884 switch (phy_fd_arr[0]) { 6885 case MARAMBA_P0_CLAUSE22_PORT_ADDR_BASE: 6886 hw_p->platform_type = 6887 P_NEPTUNE_MARAMBA_P0; 6888 break; 6889 case MARAMBA_P1_CLAUSE22_PORT_ADDR_BASE: 6890 hw_p->platform_type = 6891 P_NEPTUNE_MARAMBA_P1; 6892 break; 6893 default: 6894 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6895 "Unknown port %d...Cannot " 6896 "determine platform type 10 - 2", 6897 i)); 6898 goto error_exit; 6899 } 6900 6901 /* 6902 * Check the clause45 address to determine 6903 * if XAUI is in port 0 or port 1. 6904 */ 6905 switch (port_fd_arr[0]) { 6906 case MARAMBA_CLAUSE45_PORT_ADDR_BASE: 6907 if (port_pcs_dev_id[0] 6908 == PHY_BCM8704_FAMILY || 6909 port_pma_pmd_dev_id[0] 6910 == PHY_BCM8704_FAMILY) { 6911 hw_p->niu_type 6912 = NEPTUNE_1_10GF_3_1GC; 6913 } else { 6914 hw_p->niu_type 6915 = NEPTUNE_1_TN1010_3_1GC; 6916 } 6917 hw_p->xcvr_addr[0] = port_fd_arr[0]; 6918 for (i = 1; i < NXGE_MAX_PORTS; i++) { 6919 hw_p->xcvr_addr[i] = 6920 phy_fd_arr[i]; 6921 } 6922 break; 6923 case (MARAMBA_CLAUSE45_PORT_ADDR_BASE + 1): 6924 if (port_pcs_dev_id[0] 6925 == PHY_BCM8704_FAMILY || 6926 port_pma_pmd_dev_id[0] 6927 == PHY_BCM8704_FAMILY) { 6928 hw_p->niu_type = 6929 NEPTUNE_1_1GC_1_10GF_2_1GC; 6930 } else { 6931 hw_p->niu_type = 6932 NEPTUNE_1_1GC_1_TN1010_2_1GC; 6933 } 6934 hw_p->xcvr_addr[0] = phy_fd_arr[0]; 6935 hw_p->xcvr_addr[1] = port_fd_arr[0]; 6936 hw_p->xcvr_addr[2] = phy_fd_arr[2]; 6937 hw_p->xcvr_addr[3] = phy_fd_arr[3]; 6938 break; 6939 default: 6940 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6941 "Unsupported neptune type 11")); 6942 goto error_exit; 6943 } 6944 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6945 "Maramba with 1 XAUI (fiber or copper)")); 6946 break; 6947 default: 6948 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6949 "Unsupported neptune type 13")); 6950 goto error_exit; 6951 } 6952 break; 6953 case 0: /* 4 ports Neptune based NIC */ 6954 switch (total_phy_fd) { 6955 case 4: 6956 if ((port_phy_id[0] == PHY_BCM5464R_FAMILY) && 6957 (port_phy_id[1] == PHY_BCM5464R_FAMILY) && 6958 (port_phy_id[2] == PHY_BCM5464R_FAMILY) && 6959 (port_phy_id[3] == PHY_BCM5464R_FAMILY)) { 6960 6961 /* 6962 * Check the first phy port address against 6963 * the known phy start addresses to determine 6964 * the platform type. 6965 */ 6966 switch (phy_fd_arr[0]) { 6967 case MARAMBA_P1_CLAUSE22_PORT_ADDR_BASE: 6968 hw_p->platform_type = 6969 P_NEPTUNE_MARAMBA_P1; 6970 break; 6971 case NEPTUNE_CLAUSE22_PORT_ADDR_BASE: 6972 hw_p->platform_type = 6973 P_NEPTUNE_ATLAS_4PORT; 6974 break; 6975 default: 6976 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6977 "Unknown port %d...Cannot " 6978 "determine platform type", i)); 6979 goto error_exit; 6980 } 6981 hw_p->niu_type = NEPTUNE_4_1GC; 6982 for (i = 0; i < NXGE_MAX_PORTS; i++) { 6983 hw_p->xcvr_addr[i] = phy_fd_arr[i]; 6984 } 6985 } else { 6986 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6987 "Unsupported neptune type 14")); 6988 goto error_exit; 6989 } 6990 break; 6991 case 3: 6992 /* TODO 3 1G mode */ 6993 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6994 "Unsupported neptune type 15")); 6995 goto error_exit; 6996 case 2: 6997 /* TODO 2 1G mode */ 6998 if ((port_phy_id[0] == PHY_BCM5482_FAMILY) && 6999 (port_phy_id[1] == PHY_BCM5482_FAMILY)) { 7000 hw_p->platform_type = P_NEPTUNE_GENERIC; 7001 hw_p->niu_type = NEPTUNE_2_1GRF; 7002 hw_p->xcvr_addr[2] = phy_fd_arr[0]; 7003 hw_p->xcvr_addr[3] = phy_fd_arr[1]; 7004 } else { 7005 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 7006 "Unsupported neptune type 16")); 7007 goto error_exit; 7008 } 7009 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 7010 "2 RGMII Fiber ports - RTM")); 7011 break; 7012 7013 case 1: 7014 /* TODO 1 1G mode */ 7015 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 7016 "Unsupported neptune type 17")); 7017 goto error_exit; 7018 default: 7019 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 7020 "Unsupported neptune type 18, total phy fd %d", 7021 total_phy_fd)); 7022 goto error_exit; 7023 } 7024 break; 7025 default: 7026 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 7027 "Unsupported neptune type 19")); 7028 goto error_exit; 7029 } 7030 7031 scan_exit: 7032 7033 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_scan_ports_phy, " 7034 "niu type [0x%x]\n", hw_p->niu_type)); 7035 return (status); 7036 7037 error_exit: 7038 return (NXGE_ERROR); 7039 } 7040 7041 boolean_t 7042 nxge_is_valid_local_mac(ether_addr_st mac_addr) 7043 { 7044 if ((mac_addr.ether_addr_octet[0] & 0x01) || 7045 (ether_cmp(&mac_addr, ðerbroadcastaddr) == 0) || 7046 (ether_cmp(&mac_addr, ðerzeroaddr) == 0)) 7047 return (B_FALSE); 7048 else 7049 return (B_TRUE); 7050 } 7051 7052 static void 7053 nxge_bcm5464_link_led_off(p_nxge_t nxgep) { 7054 7055 npi_status_t rs = NPI_SUCCESS; 7056 uint8_t xcvr_portn; 7057 uint8_t portn = NXGE_GET_PORT_NUM(nxgep->function_num); 7058 7059 NXGE_DEBUG_MSG((nxgep, MIF_CTL, "==> nxge_bcm5464_link_led_off")); 7060 7061 if (nxgep->nxge_hw_p->platform_type == P_NEPTUNE_MARAMBA_P1) { 7062 xcvr_portn = MARAMBA_P1_CLAUSE22_PORT_ADDR_BASE; 7063 } else if (nxgep->nxge_hw_p->platform_type == P_NEPTUNE_MARAMBA_P0) { 7064 xcvr_portn = MARAMBA_P0_CLAUSE22_PORT_ADDR_BASE; 7065 } 7066 /* 7067 * For Altas 4-1G copper, Xcvr port numbers are 7068 * swapped with ethernet port number. This is 7069 * designed for better signal integrity in routing. 7070 */ 7071 switch (portn) { 7072 case 0: 7073 xcvr_portn += 3; 7074 break; 7075 case 1: 7076 xcvr_portn += 2; 7077 break; 7078 case 2: 7079 xcvr_portn += 1; 7080 break; 7081 case 3: 7082 default: 7083 break; 7084 } 7085 7086 MUTEX_ENTER(&nxgep->nxge_hw_p->nxge_mdio_lock); 7087 rs = npi_mac_mif_mii_write(nxgep->npi_handle, 7088 xcvr_portn, BCM5464R_MISC, 0xb4ee); 7089 if (rs != NPI_SUCCESS) { 7090 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 7091 "<== nxge_bcm5464_link_led_off: npi_mac_mif_mii_write " 7092 "returned error 0x[%x]", rs)); 7093 MUTEX_EXIT(&nxgep->nxge_hw_p->nxge_mdio_lock); 7094 return; 7095 } 7096 7097 rs = npi_mac_mif_mii_write(nxgep->npi_handle, 7098 xcvr_portn, BCM5464R_MISC, 0xb8ee); 7099 if (rs != NPI_SUCCESS) { 7100 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 7101 "<== nxge_bcm5464_link_led_off: npi_mac_mif_mii_write " 7102 "returned error 0x[%x]", rs)); 7103 } 7104 7105 MUTEX_EXIT(&nxgep->nxge_hw_p->nxge_mdio_lock); 7106 } 7107 7108 static nxge_status_t 7109 nxge_mii_get_link_mode(p_nxge_t nxgep) 7110 { 7111 p_nxge_stats_t statsp; 7112 uint8_t xcvr_portn; 7113 p_mii_regs_t mii_regs; 7114 mii_mode_control_stat_t mode; 7115 int status = NXGE_OK; 7116 7117 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_mii_get_link_mode")); 7118 7119 statsp = nxgep->statsp; 7120 xcvr_portn = statsp->mac_stats.xcvr_portn; 7121 mii_regs = NULL; 7122 mode.value = 0; 7123 mode.bits.shadow = NXGE_MII_MODE_CONTROL_REG; 7124 #if defined(__i386) 7125 if ((status = nxge_mii_write(nxgep, xcvr_portn, 7126 (uint8_t)(uint32_t)(&mii_regs->shadow), 7127 mode.value)) != NXGE_OK) { 7128 goto fail; 7129 #else 7130 if ((status = nxge_mii_write(nxgep, xcvr_portn, 7131 (uint8_t)(uint64_t)(&mii_regs->shadow), 7132 mode.value)) != NXGE_OK) { 7133 goto fail; 7134 #endif 7135 } 7136 #if defined(__i386) 7137 if ((status = nxge_mii_read(nxgep, xcvr_portn, 7138 (uint8_t)(uint32_t)(&mii_regs->shadow), 7139 &mode.value)) != NXGE_OK) { 7140 goto fail; 7141 } 7142 #else 7143 if ((status = nxge_mii_read(nxgep, xcvr_portn, 7144 (uint8_t)(uint64_t)(&mii_regs->shadow), 7145 &mode.value)) != NXGE_OK) { 7146 goto fail; 7147 } 7148 #endif 7149 7150 if (mode.bits.mode == NXGE_MODE_SELECT_FIBER) { 7151 nxgep->mac.portmode = PORT_1G_RGMII_FIBER; 7152 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 7153 "nxge_mii_get_link_mode: fiber mode")); 7154 } 7155 7156 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 7157 "nxge_mii_get_link_mode: " 7158 "(address 0x%x) port 0x%x mode value 0x%x link mode 0x%x", 7159 NXGE_MII_MODE_CONTROL_REG, xcvr_portn, 7160 mode.value, nxgep->mac.portmode)); 7161 7162 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 7163 "<== nxge_mii_get_link_mode")); 7164 return (status); 7165 fail: 7166 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 7167 "<== nxge_mii_get_link_mode (failed)")); 7168 return (NXGE_ERROR); 7169 } 7170 7171 nxge_status_t 7172 nxge_mac_set_framesize(p_nxge_t nxgep) 7173 { 7174 npi_attr_t ap; 7175 uint8_t portn; 7176 npi_handle_t handle; 7177 npi_status_t rs = NPI_SUCCESS; 7178 7179 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_mac_set_framesize")); 7180 7181 portn = NXGE_GET_PORT_NUM(nxgep->function_num); 7182 handle = nxgep->npi_handle; 7183 7184 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 7185 "==> nxge_mac_sec_framesize: port<%d> " 7186 "min framesize %d max framesize %d ", 7187 portn, 7188 nxgep->mac.minframesize, 7189 nxgep->mac.maxframesize)); 7190 7191 SET_MAC_ATTR2(handle, ap, portn, 7192 MAC_PORT_FRAME_SIZE, 7193 nxgep->mac.minframesize, 7194 nxgep->mac.maxframesize, 7195 rs); 7196 if (rs != NPI_SUCCESS) { 7197 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 7198 "<== nxge_mac_set_framesize: failed to configure " 7199 "max/min frame size port %d", portn)); 7200 7201 return (NXGE_ERROR | rs); 7202 } 7203 7204 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 7205 "<== nxge_mac_set_framesize: port<%d>", portn)); 7206 7207 return (NXGE_OK); 7208 } 7209 7210 static nxge_status_t 7211 nxge_get_num_of_xaui(uint32_t *port_pma_pmd_dev_id, 7212 uint32_t *port_pcs_dev_id, uint32_t *port_phy_id, uint8_t *num_xaui) 7213 { 7214 uint8_t i; 7215 7216 for (i = 0; i < 4; i++) { 7217 if (port_phy_id[i] != PHY_BCM5464R_FAMILY) 7218 return (NXGE_ERROR); 7219 } 7220 7221 *num_xaui = 0; 7222 if ((port_pma_pmd_dev_id[0] == PHY_BCM8704_FAMILY && 7223 port_pcs_dev_id[0] == PHY_BCM8704_FAMILY) || 7224 (((port_pma_pmd_dev_id[0] & TN1010_DEV_ID_MASK) 7225 == TN1010_DEV_ID) && 7226 ((port_pcs_dev_id[0] & TN1010_DEV_ID_MASK) 7227 == TN1010_DEV_ID))) { 7228 (*num_xaui) ++; 7229 } 7230 if ((port_pma_pmd_dev_id[1] == PHY_BCM8704_FAMILY && 7231 port_pcs_dev_id[1] == PHY_BCM8704_FAMILY) || 7232 (((port_pma_pmd_dev_id[1] & TN1010_DEV_ID_MASK) 7233 == TN1010_DEV_ID) && 7234 ((port_pcs_dev_id[1] & TN1010_DEV_ID_MASK) 7235 == TN1010_DEV_ID))) { 7236 (*num_xaui) ++; 7237 } 7238 return (NXGE_OK); 7239 } 7240 7241 /* 7242 * Instruction from Teranetics: Once you detect link is up, go 7243 * read Reg 30.1.4 for link speed: '1' for 1G and '0' for 10G. You 7244 * may want to qualify it by first checking Register 30.1.7:6 and 7245 * making sure it reads "01" (Auto-Neg Complete). 7246 * 7247 * If this function is called when the link is down or before auto- 7248 * negotiation has completed, then the speed of the PHY is not certain. 7249 * In such cases, this function returns 1G as the default speed with 7250 * NXGE_OK status instead of NXGE_ERROR. It is OK to initialize the 7251 * driver based on a default speed because this function will be called 7252 * again when the link comes up. Returning NXGE_ERROR, which may 7253 * cause brutal chain reaction in caller functions, is not necessary. 7254 */ 7255 static nxge_status_t 7256 nxge_get_tn1010_speed(p_nxge_t nxgep, uint16_t *speed) 7257 { 7258 uint8_t phy_port_addr, autoneg_stat, link_up; 7259 nxge_status_t status = NXGE_OK; 7260 uint16_t val; 7261 uint8_t portn = NXGE_GET_PORT_NUM(nxgep->function_num); 7262 7263 /* Set default speed to 10G */ 7264 *speed = TN1010_SPEED_10G; 7265 7266 /* Set Clause 45 */ 7267 npi_mac_mif_set_indirect_mode(nxgep->npi_handle, B_TRUE); 7268 7269 phy_port_addr = nxgep->nxge_hw_p->xcvr_addr[portn]; 7270 7271 /* Check Device 1 Register 0xA bit0 for link up status */ 7272 status = nxge_mdio_read(nxgep, phy_port_addr, 7273 TN1010_AUTONEG_DEV_ADDR, TN1010_AUTONEG_STATUS_REG, &val); 7274 if (status != NXGE_OK) 7275 goto fail; 7276 7277 link_up = ((val & TN1010_AN_LINK_STAT_BIT) 7278 ? B_TRUE : B_FALSE); 7279 if (link_up == B_FALSE) { 7280 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 7281 "nxge_get_tn1010_speed: link is down")); 7282 goto nxge_get_tn1010_speed_exit; 7283 } 7284 7285 if ((status = nxge_mdio_read(nxgep, phy_port_addr, 7286 TN1010_VENDOR_MMD1_DEV_ADDR, TN1010_VENDOR_MMD1_STATUS_REG, 7287 &val)) != NXGE_OK) { 7288 goto fail; 7289 } 7290 autoneg_stat = (val & TN1010_VENDOR_MMD1_AN_STAT_BITS) >> 7291 TN1010_VENDOR_MMD1_AN_STAT_SHIFT; 7292 7293 /* 7294 * Return NXGE_OK even when we can not get a settled speed. In 7295 * such case, the speed reported should not be trusted but that 7296 * is OK, we will call this function periodically and will get 7297 * the correct speed after the link is up. 7298 */ 7299 switch (autoneg_stat) { 7300 case TN1010_AN_IN_PROG: 7301 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 7302 "nxge_get_tn1010_speed: Auto-negotiation in progress")); 7303 break; 7304 case TN1010_AN_COMPLETE: 7305 if ((status = nxge_mdio_read(nxgep, phy_port_addr, 7306 TN1010_VENDOR_MMD1_DEV_ADDR, 7307 TN1010_VENDOR_MMD1_STATUS_REG, 7308 &val)) != NXGE_OK) { 7309 goto fail; 7310 } 7311 *speed = (val & TN1010_VENDOR_MMD1_AN_SPEED_BIT) >> 7312 TN1010_VENDOR_MMD1_AN_SPEED_SHIFT; 7313 break; 7314 case TN1010_AN_RSVD: 7315 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 7316 "nxge_get_tn1010_speed: Autoneg status undefined")); 7317 break; 7318 case TN1010_AN_FAILED: 7319 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 7320 "nxge_get_tn1010_speed: Auto-negotiation failed")); 7321 break; 7322 default: 7323 break; 7324 } 7325 nxge_get_tn1010_speed_exit: 7326 return (NXGE_OK); 7327 fail: 7328 return (status); 7329 } 7330 7331 7332 /* 7333 * Teranetics TN1010 PHY chip supports both 1G and 10G modes, this function 7334 * figures out the speed of the PHY determined by the autonegotiation 7335 * process and sets the following 3 parameters, 7336 * nxgep->mac.portmode 7337 * nxgep->statsp->mac_stats.link_speed 7338 * nxgep->statsp->mac_stats.xcvr_inuse 7339 */ 7340 static nxge_status_t 7341 nxge_set_tn1010_param(p_nxge_t nxgep) 7342 { 7343 uint16_t speed; 7344 7345 if (nxge_get_tn1010_speed(nxgep, &speed) != NXGE_OK) { 7346 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 7347 "nxge_set_tn1010_param: " 7348 "Failed to get TN1010 speed")); 7349 return (NXGE_ERROR); 7350 } 7351 if (speed == TN1010_SPEED_1G) { 7352 nxgep->mac.portmode = PORT_1G_TN1010; 7353 nxgep->statsp->mac_stats.link_speed = 1000; 7354 nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR; 7355 } else { 7356 nxgep->mac.portmode = PORT_10G_TN1010; 7357 nxgep->statsp->mac_stats.link_speed = 10000; 7358 nxgep->statsp->mac_stats.xcvr_inuse = XPCS_XCVR; 7359 } 7360 return (NXGE_OK); 7361 } 7362 7363 #ifdef NXGE_DEBUG 7364 static void 7365 nxge_mii_dump(p_nxge_t nxgep) 7366 { 7367 p_nxge_stats_t statsp; 7368 uint8_t xcvr_portn; 7369 p_mii_regs_t mii_regs; 7370 mii_bmcr_t bmcr; 7371 mii_bmsr_t bmsr; 7372 mii_idr1_t idr1; 7373 mii_idr2_t idr2; 7374 mii_mode_control_stat_t mode; 7375 p_nxge_param_t param_arr; 7376 7377 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "==> nxge_mii_dump")); 7378 7379 statsp = nxgep->statsp; 7380 xcvr_portn = statsp->mac_stats.xcvr_portn; 7381 7382 mii_regs = NULL; 7383 7384 #if defined(__i386) 7385 (void) nxge_mii_read(nxgep, nxgep->statsp->mac_stats.xcvr_portn, 7386 (uint8_t)(uint32_t)(&mii_regs->bmcr), &bmcr.value); 7387 #else 7388 (void) nxge_mii_read(nxgep, nxgep->statsp->mac_stats.xcvr_portn, 7389 (uint8_t)(uint64_t)(&mii_regs->bmcr), &bmcr.value); 7390 #endif 7391 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 7392 "nxge_mii_dump: bmcr (0) xcvr 0x%x value 0x%x", 7393 xcvr_portn, bmcr.value)); 7394 7395 #if defined(__i386) 7396 (void) nxge_mii_read(nxgep, 7397 nxgep->statsp->mac_stats.xcvr_portn, 7398 (uint8_t)(uint32_t)(&mii_regs->bmsr), &bmsr.value); 7399 #else 7400 (void) nxge_mii_read(nxgep, 7401 nxgep->statsp->mac_stats.xcvr_portn, 7402 (uint8_t)(uint64_t)(&mii_regs->bmsr), &bmsr.value); 7403 #endif 7404 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 7405 "nxge_mii_dump: bmsr (1) xcvr 0x%x value 0x%x", 7406 xcvr_portn, bmsr.value)); 7407 7408 #if defined(__i386) 7409 (void) nxge_mii_read(nxgep, 7410 nxgep->statsp->mac_stats.xcvr_portn, 7411 (uint8_t)(uint32_t)(&mii_regs->idr1), &idr1.value); 7412 #else 7413 (void) nxge_mii_read(nxgep, 7414 nxgep->statsp->mac_stats.xcvr_portn, 7415 (uint8_t)(uint64_t)(&mii_regs->idr1), &idr1.value); 7416 #endif 7417 7418 7419 #if defined(__i386) 7420 (void) nxge_mii_read(nxgep, 7421 nxgep->statsp->mac_stats.xcvr_portn, 7422 (uint8_t)(uint32_t)(&mii_regs->idr2), &idr2.value); 7423 #else 7424 (void) nxge_mii_read(nxgep, 7425 nxgep->statsp->mac_stats.xcvr_portn, 7426 (uint8_t)(uint64_t)(&mii_regs->idr2), &idr2.value); 7427 #endif 7428 7429 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 7430 "nxge_mii_dump: idr1 (2) xcvr 0x%x value 0x%x", 7431 xcvr_portn, idr1.value)); 7432 7433 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 7434 "nxge_mii_dump: idr2 (3) xcvr 0x%x value 0x%x", 7435 xcvr_portn, idr2.value)); 7436 7437 mode.value = 0; 7438 mode.bits.shadow = NXGE_MII_MODE_CONTROL_REG; 7439 7440 #if defined(__i386) 7441 (void) nxge_mii_write(nxgep, xcvr_portn, 7442 (uint8_t)(uint32_t)(&mii_regs->shadow), mode.value); 7443 7444 (void) nxge_mii_read(nxgep, xcvr_portn, 7445 (uint8_t)(uint32_t)(&mii_regs->shadow), &mode.value); 7446 #else 7447 (void) nxge_mii_write(nxgep, xcvr_portn, 7448 (uint8_t)(uint64_t)(&mii_regs->shadow), mode.value); 7449 7450 (void) nxge_mii_read(nxgep, xcvr_portn, 7451 (uint8_t)(uint64_t)(&mii_regs->shadow), &mode.value); 7452 #endif 7453 7454 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 7455 "nxge_mii_dump: mode control xcvr 0x%x value 0x%x", 7456 xcvr_portn, mode.value)); 7457 } 7458 #endif 7459