xref: /titanic_50/usr/src/uts/common/io/nxge/nxge_hw.c (revision 66ea84940ca8687745ad2a165ef9bf49ec13996f)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #include <sys/nxge/nxge_impl.h>
27 
28 /*
29  * Tunable Receive Completion Ring Configuration B parameters.
30  */
31 uint16_t nxge_rx_pkt_thres;	/* 16 bits */
32 uint8_t nxge_rx_pkt_timeout;	/* 6 bits based on DMA clock divider */
33 
34 lb_property_t lb_normal = {normal, "normal", nxge_lb_normal};
35 lb_property_t lb_external10g = {external, "external10g", nxge_lb_ext10g};
36 lb_property_t lb_external1000 = {external, "external1000", nxge_lb_ext1000};
37 lb_property_t lb_external100 = {external, "external100", nxge_lb_ext100};
38 lb_property_t lb_external10 = {external, "external10", nxge_lb_ext10};
39 lb_property_t lb_phy10g = {internal, "phy10g", nxge_lb_phy10g};
40 lb_property_t lb_phy1000 = {internal, "phy1000", nxge_lb_phy1000};
41 lb_property_t lb_phy = {internal, "phy", nxge_lb_phy};
42 lb_property_t lb_serdes10g = {internal, "serdes10g", nxge_lb_serdes10g};
43 lb_property_t lb_serdes1000 = {internal, "serdes", nxge_lb_serdes1000};
44 lb_property_t lb_mac10g = {internal, "mac10g", nxge_lb_mac10g};
45 lb_property_t lb_mac1000 = {internal, "mac1000", nxge_lb_mac1000};
46 lb_property_t lb_mac = {internal, "mac10/100", nxge_lb_mac};
47 
48 uint32_t nxge_lb_dbg = 1;
49 void nxge_get_mii(p_nxge_t nxgep, p_mblk_t mp);
50 void nxge_put_mii(p_nxge_t nxgep, p_mblk_t mp);
51 static nxge_status_t nxge_check_xaui_xfp(p_nxge_t nxgep);
52 
53 extern uint32_t nxge_rx_mode;
54 extern uint32_t nxge_jumbo_mtu;
55 extern boolean_t nxge_jumbo_enable;
56 
57 static void
58 nxge_rtrace_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *);
59 
60 /* ARGSUSED */
61 nxge_status_t
62 nxge_global_reset(p_nxge_t nxgep)
63 {
64 	nxge_status_t	status = NXGE_OK;
65 
66 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_global_reset"));
67 
68 	if ((status = nxge_link_monitor(nxgep, LINK_MONITOR_STOP)) != NXGE_OK)
69 		return (status);
70 	(void) nxge_intr_hw_disable(nxgep);
71 
72 	if ((nxgep->suspended) ||
73 	    ((nxgep->statsp->port_stats.lb_mode ==
74 	    nxge_lb_phy1000) ||
75 	    (nxgep->statsp->port_stats.lb_mode ==
76 	    nxge_lb_phy10g) ||
77 	    (nxgep->statsp->port_stats.lb_mode ==
78 	    nxge_lb_serdes1000) ||
79 	    (nxgep->statsp->port_stats.lb_mode ==
80 	    nxge_lb_serdes10g))) {
81 		if ((status = nxge_link_init(nxgep)) != NXGE_OK)
82 			return (status);
83 	}
84 
85 	if ((status = nxge_link_monitor(nxgep, LINK_MONITOR_START)) != NXGE_OK)
86 		return (status);
87 	if ((status = nxge_mac_init(nxgep)) != NXGE_OK)
88 		return (status);
89 	(void) nxge_intr_hw_enable(nxgep);
90 
91 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_global_reset"));
92 	return (status);
93 }
94 
95 /* ARGSUSED */
96 void
97 nxge_hw_id_init(p_nxge_t nxgep)
98 {
99 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_id_init"));
100 	/*
101 	 * Set up initial hardware parameters required such as mac mtu size.
102 	 */
103 	nxgep->mac.is_jumbo = B_FALSE;
104 	/*
105 	 * Set the maxframe size to 1522 (1518 + 4) to account for
106 	 * VLAN tagged packets.
107 	 */
108 	nxgep->mac.minframesize = NXGE_MIN_MAC_FRAMESIZE; /* 64   */
109 	nxgep->mac.maxframesize = NXGE_MAX_MAC_FRAMESIZE; /* 1522 */
110 	if (nxgep->param_arr[param_accept_jumbo].value || nxge_jumbo_enable) {
111 		nxgep->mac.maxframesize = (uint16_t)nxge_jumbo_mtu;
112 		nxgep->mac.is_jumbo = B_TRUE;
113 	}
114 	NXGE_DEBUG_MSG((nxgep, DDI_CTL,
115 	    "==> nxge_hw_id_init: maxframesize %d",
116 	    nxgep->mac.maxframesize));
117 
118 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_id_init"));
119 }
120 
121 /* ARGSUSED */
122 void
123 nxge_hw_init_niu_common(p_nxge_t nxgep)
124 {
125 	p_nxge_hw_list_t hw_p;
126 
127 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_init_niu_common"));
128 
129 	if ((hw_p = nxgep->nxge_hw_p) == NULL) {
130 		return;
131 	}
132 	MUTEX_ENTER(&hw_p->nxge_cfg_lock);
133 	if (hw_p->flags & COMMON_INIT_DONE) {
134 		NXGE_DEBUG_MSG((nxgep, MOD_CTL,
135 		    "nxge_hw_init_niu_common"
136 		    " already done for dip $%p function %d exiting",
137 		    hw_p->parent_devp, nxgep->function_num));
138 		MUTEX_EXIT(&hw_p->nxge_cfg_lock);
139 		return;
140 	}
141 
142 	hw_p->flags = COMMON_INIT_START;
143 	NXGE_DEBUG_MSG((nxgep, MOD_CTL, "nxge_hw_init_niu_common"
144 	    " Started for device id %x with function %d",
145 	    hw_p->parent_devp, nxgep->function_num));
146 
147 	/* per neptune common block init */
148 	(void) nxge_fflp_hw_reset(nxgep);
149 
150 	hw_p->flags = COMMON_INIT_DONE;
151 	MUTEX_EXIT(&hw_p->nxge_cfg_lock);
152 
153 	NXGE_DEBUG_MSG((nxgep, MOD_CTL, "nxge_hw_init_niu_common"
154 	    " Done for device id %x with function %d",
155 	    hw_p->parent_devp, nxgep->function_num));
156 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_init_niu_common"));
157 }
158 
159 /* ARGSUSED */
160 uint_t
161 nxge_intr(void *arg1, void *arg2)
162 {
163 	p_nxge_ldv_t ldvp = (p_nxge_ldv_t)arg1;
164 	p_nxge_t nxgep = (p_nxge_t)arg2;
165 	uint_t serviced = DDI_INTR_UNCLAIMED;
166 	uint8_t ldv;
167 	npi_handle_t handle;
168 	p_nxge_ldgv_t ldgvp;
169 	p_nxge_ldg_t ldgp, t_ldgp;
170 	p_nxge_ldv_t t_ldvp;
171 	uint64_t vector0 = 0, vector1 = 0, vector2 = 0;
172 	int i, j, nldvs, nintrs = 1;
173 	npi_status_t rs = NPI_SUCCESS;
174 
175 	/* DDI interface returns second arg as NULL (n2 niumx driver) !!! */
176 	if (arg2 == NULL || (void *) ldvp->nxgep != arg2) {
177 		nxgep = ldvp->nxgep;
178 	}
179 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr"));
180 
181 	if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) {
182 		NXGE_ERROR_MSG((nxgep, INT_CTL,
183 		    "<== nxge_intr: not initialized 0x%x", serviced));
184 		return (serviced);
185 	}
186 
187 	ldgvp = nxgep->ldgvp;
188 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: ldgvp $%p", ldgvp));
189 	if (ldvp == NULL && ldgvp) {
190 		t_ldvp = ldvp = ldgvp->ldvp;
191 	}
192 	if (ldvp) {
193 		ldgp = t_ldgp = ldvp->ldgp;
194 	}
195 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: "
196 	    "ldgvp $%p ldvp $%p ldgp $%p", ldgvp, ldvp, ldgp));
197 	if (ldgvp == NULL || ldvp == NULL || ldgp == NULL) {
198 		NXGE_ERROR_MSG((nxgep, INT_CTL, "==> nxge_intr: "
199 		    "ldgvp $%p ldvp $%p ldgp $%p", ldgvp, ldvp, ldgp));
200 		NXGE_ERROR_MSG((nxgep, INT_CTL, "<== nxge_intr: not ready"));
201 		return (DDI_INTR_UNCLAIMED);
202 	}
203 	/*
204 	 * This interrupt handler will have to go through all the logical
205 	 * devices to find out which logical device interrupts us and then call
206 	 * its handler to process the events.
207 	 */
208 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
209 	t_ldgp = ldgp;
210 	t_ldvp = ldgp->ldvp;
211 
212 	nldvs = ldgp->nldvs;
213 
214 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: #ldvs %d #intrs %d",
215 	    nldvs, ldgvp->ldg_intrs));
216 
217 	serviced = DDI_INTR_CLAIMED;
218 	for (i = 0; i < nintrs; i++, t_ldgp++) {
219 		NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr(%d): #ldvs %d "
220 		    " #intrs %d", i, nldvs, nintrs));
221 		/* Get this group's flag bits.  */
222 		rs = npi_ldsv_ldfs_get(handle, t_ldgp->ldg,
223 		    &vector0, &vector1, &vector2);
224 		if (rs) {
225 			continue;
226 		}
227 		if (!vector0 && !vector1 && !vector2) {
228 			NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: "
229 			    "no interrupts on group %d", t_ldgp->ldg));
230 			continue;
231 		}
232 		NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: "
233 		    "vector0 0x%llx vector1 0x%llx vector2 0x%llx",
234 		    vector0, vector1, vector2));
235 		nldvs = t_ldgp->nldvs;
236 		for (j = 0; j < nldvs; j++, t_ldvp++) {
237 			/*
238 			 * Call device's handler if flag bits are on.
239 			 */
240 			ldv = t_ldvp->ldv;
241 			if (((ldv < NXGE_MAC_LD_START) &&
242 			    (LDV_ON(ldv, vector0) |
243 			    (LDV_ON(ldv, vector1)))) ||
244 			    (ldv >= NXGE_MAC_LD_START &&
245 			    ((LDV2_ON_1(ldv, vector2)) ||
246 			    (LDV2_ON_2(ldv, vector2))))) {
247 				(void) (t_ldvp->ldv_intr_handler)(
248 				    (caddr_t)t_ldvp, arg2);
249 				NXGE_DEBUG_MSG((nxgep, INT_CTL,
250 				    "==> nxge_intr: "
251 				    "calling device %d #ldvs %d #intrs %d",
252 				    j, nldvs, nintrs));
253 			}
254 		}
255 	}
256 
257 	t_ldgp = ldgp;
258 	for (i = 0; i < nintrs; i++, t_ldgp++) {
259 		/* rearm group interrupts */
260 		NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: arm "
261 		    "group %d", t_ldgp->ldg));
262 		(void) npi_intr_ldg_mgmt_set(handle, t_ldgp->ldg,
263 		    t_ldgp->arm, t_ldgp->ldg_timer);
264 	}
265 
266 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr: serviced 0x%x",
267 	    serviced));
268 	return (serviced);
269 }
270 
271 
272 /*
273  * XFP Related Status Register Values Under 3 Different Conditions
274  *
275  * -------------+-------------------------+-------------------------
276  * 		|   Intel XFP and Avago   |	 Picolight XFP
277  * -------------+---------+---------------+---------+---------------
278  *		| STATUS0 | TX_ALARM_STAT | STATUS0 | TX_ALARM_STAT
279  * -------------+---------+---------------+---------+---------------
280  *	No XFP  | 0x639C  |      0x40     | 0x639C  |      0x40
281  * -------------+---------+---------------+---------+---------------
282  * XFP,linkdown | 0x43BC  |      0x40     | 0x639C  |      0x40
283  * -------------+---------+---------------+---------+---------------
284  * XFP,linkup   | 0x03FC  |      0x0      | 0x03FC  |      0x0
285  * -------------+---------+---------------+---------+---------------
286  * Note:
287  *      STATUS0         = BCM8704_USER_ANALOG_STATUS0_REG
288  *      TX_ALARM_STAT   = BCM8704_USER_TX_ALARM_STATUS_REG
289  */
290 /* ARGSUSED */
291 static nxge_status_t
292 nxge_check_xaui_xfp(p_nxge_t nxgep)
293 {
294 	nxge_status_t	status = NXGE_OK;
295 	uint8_t		phy_port_addr;
296 	uint16_t	val;
297 	uint16_t	val1;
298 	uint8_t		portn;
299 
300 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_check_xaui_xfp"));
301 
302 	portn = nxgep->mac.portnum;
303 	phy_port_addr = nxgep->statsp->mac_stats.xcvr_portn;
304 
305 	/*
306 	 * Keep the val1 code even though it is not used. Could be
307 	 * used to differenciate the "No XFP" case and "XFP,linkdown"
308 	 * case when a Intel XFP is used.
309 	 */
310 	if ((status = nxge_mdio_read(nxgep, phy_port_addr,
311 	    BCM8704_USER_DEV3_ADDR,
312 	    BCM8704_USER_ANALOG_STATUS0_REG, &val)) == NXGE_OK) {
313 		status = nxge_mdio_read(nxgep, phy_port_addr,
314 		    BCM8704_USER_DEV3_ADDR,
315 		    BCM8704_USER_TX_ALARM_STATUS_REG, &val1);
316 	}
317 
318 	if (status != NXGE_OK) {
319 		NXGE_FM_REPORT_ERROR(nxgep, portn, NULL,
320 		    NXGE_FM_EREPORT_XAUI_ERR);
321 		if (DDI_FM_EREPORT_CAP(nxgep->fm_capabilities)) {
322 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
323 			    "XAUI is bad or absent on port<%d>\n", portn));
324 		}
325 #ifdef NXGE_DEBUG
326 	/*
327 	 * As a workaround for CR6693529, do not execute this block of
328 	 * code for non-debug driver. When a Picolight XFP transceiver
329 	 * is used, register BCM8704_USER_ANALOG_STATUS0_REG returns
330 	 * the same 0x639C value in normal link down case, which causes
331 	 * false FMA messages and link reconnection problem.
332 	 */
333 	} else if (nxgep->mac.portmode == PORT_10G_FIBER) {
334 		/*
335 		 * 0x03FC = 0000 0011 1111 1100 (XFP is normal)
336 		 * 0x639C = 0110 0011 1001 1100 (XFP has problem)
337 		 * bit14 = 1: PDM loss-of-light indicator
338 		 * bit13 = 1: PDM Rx loss-of-signal
339 		 * bit6  = 0: Light is NOT ok
340 		 * bit5  = 0: PMD Rx signal is NOT ok
341 		 */
342 		if (val == 0x639C) {
343 			NXGE_FM_REPORT_ERROR(nxgep, portn, NULL,
344 			    NXGE_FM_EREPORT_XFP_ERR);
345 			if (DDI_FM_EREPORT_CAP(nxgep->fm_capabilities)) {
346 				NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
347 				    "XFP is bad or absent on port<%d>\n",
348 				    portn));
349 			}
350 			status = NXGE_ERROR;
351 		}
352 #endif
353 	}
354 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_check_xaui_xfp"));
355 	return (status);
356 }
357 
358 
359 /* ARGSUSED */
360 uint_t
361 nxge_syserr_intr(void *arg1, void *arg2)
362 {
363 	p_nxge_ldv_t ldvp = (p_nxge_ldv_t)arg1;
364 	p_nxge_t nxgep = (p_nxge_t)arg2;
365 	p_nxge_ldg_t ldgp = NULL;
366 	npi_handle_t handle;
367 	sys_err_stat_t estat;
368 	uint_t serviced = DDI_INTR_UNCLAIMED;
369 
370 	if (arg1 == NULL && arg2 == NULL) {
371 		return (serviced);
372 	}
373 	if (arg2 == NULL || ((ldvp != NULL && (void *) ldvp->nxgep != arg2))) {
374 		if (ldvp != NULL) {
375 			nxgep = ldvp->nxgep;
376 		}
377 	}
378 	NXGE_DEBUG_MSG((nxgep, SYSERR_CTL,
379 	    "==> nxge_syserr_intr: arg2 $%p arg1 $%p", nxgep, ldvp));
380 	if (ldvp != NULL && ldvp->use_timer == B_FALSE) {
381 		ldgp = ldvp->ldgp;
382 		if (ldgp == NULL) {
383 			NXGE_ERROR_MSG((nxgep, SYSERR_CTL,
384 			    "<== nxge_syserrintr(no logical group): "
385 			    "arg2 $%p arg1 $%p", nxgep, ldvp));
386 			return (DDI_INTR_UNCLAIMED);
387 		}
388 		/*
389 		 * Get the logical device state if the function uses interrupt.
390 		 */
391 	}
392 
393 	/* This interrupt handler is for system error interrupts.  */
394 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
395 	estat.value = 0;
396 	(void) npi_fzc_sys_err_stat_get(handle, &estat);
397 	NXGE_DEBUG_MSG((nxgep, SYSERR_CTL,
398 	    "==> nxge_syserr_intr: device error 0x%016llx", estat.value));
399 
400 	if (estat.bits.ldw.smx) {
401 		/* SMX */
402 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
403 		    "==> nxge_syserr_intr: device error - SMX"));
404 	} else if (estat.bits.ldw.mac) {
405 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
406 		    "==> nxge_syserr_intr: device error - MAC"));
407 		/*
408 		 * There is nothing to be done here. All MAC errors go to per
409 		 * MAC port interrupt. MIF interrupt is the only MAC sub-block
410 		 * that can generate status here. MIF status reported will be
411 		 * ignored here. It is checked by per port timer instead.
412 		 */
413 	} else if (estat.bits.ldw.ipp) {
414 		NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL,
415 		    "==> nxge_syserr_intr: device error - IPP"));
416 		(void) nxge_ipp_handle_sys_errors(nxgep);
417 	} else if (estat.bits.ldw.zcp) {
418 		/* ZCP */
419 		NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL,
420 		    "==> nxge_syserr_intr: device error - ZCP"));
421 		(void) nxge_zcp_handle_sys_errors(nxgep);
422 	} else if (estat.bits.ldw.tdmc) {
423 		/* TDMC */
424 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
425 		    "==> nxge_syserr_intr: device error - TDMC"));
426 		/*
427 		 * There is no TDMC system errors defined in the PRM. All TDMC
428 		 * channel specific errors are reported on a per channel basis.
429 		 */
430 	} else if (estat.bits.ldw.rdmc) {
431 		/* RDMC */
432 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
433 		    "==> nxge_syserr_intr: device error - RDMC"));
434 		(void) nxge_rxdma_handle_sys_errors(nxgep);
435 	} else if (estat.bits.ldw.txc) {
436 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
437 		    "==> nxge_syserr_intr: device error - TXC"));
438 		(void) nxge_txc_handle_sys_errors(nxgep);
439 	} else if ((nxgep->niu_type != N2_NIU) && estat.bits.ldw.peu) {
440 		/* PCI-E */
441 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
442 		    "==> nxge_syserr_intr: device error - PCI-E"));
443 	} else if (estat.bits.ldw.meta1) {
444 		/* META1 */
445 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
446 		    "==> nxge_syserr_intr: device error - META1"));
447 	} else if (estat.bits.ldw.meta2) {
448 		/* META2 */
449 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
450 		    "==> nxge_syserr_intr: device error - META2"));
451 	} else if (estat.bits.ldw.fflp) {
452 		/* FFLP */
453 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
454 		    "==> nxge_syserr_intr: device error - FFLP"));
455 		(void) nxge_fflp_handle_sys_errors(nxgep);
456 	}
457 
458 	/*
459 	 * nxge_check_xaui_xfg checks XAUI for all of the following
460 	 * portmodes, but checks XFP only if portmode == PORT_10G_FIBER.
461 	 */
462 	if (nxgep->mac.portmode == PORT_10G_FIBER ||
463 	    nxgep->mac.portmode == PORT_10G_COPPER ||
464 	    nxgep->mac.portmode == PORT_10G_TN1010 ||
465 	    nxgep->mac.portmode == PORT_1G_TN1010) {
466 		if (nxge_check_xaui_xfp(nxgep) != NXGE_OK) {
467 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
468 			    "==> nxge_syserr_intr: device error - XAUI"));
469 		}
470 	}
471 
472 	serviced = DDI_INTR_CLAIMED;
473 
474 	if (ldgp != NULL && ldvp != NULL && ldgp->nldvs == 1 &&
475 	    !ldvp->use_timer) {
476 		(void) npi_intr_ldg_mgmt_set(handle, ldgp->ldg,
477 		    B_TRUE, ldgp->ldg_timer);
478 	}
479 	NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, "<== nxge_syserr_intr"));
480 	return (serviced);
481 }
482 
483 /* ARGSUSED */
484 void
485 nxge_intr_hw_enable(p_nxge_t nxgep)
486 {
487 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_hw_enable"));
488 	(void) nxge_intr_mask_mgmt_set(nxgep, B_TRUE);
489 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_hw_enable"));
490 }
491 
492 /* ARGSUSED */
493 void
494 nxge_intr_hw_disable(p_nxge_t nxgep)
495 {
496 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_hw_disable"));
497 	(void) nxge_intr_mask_mgmt_set(nxgep, B_FALSE);
498 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_hw_disable"));
499 }
500 
501 /* ARGSUSED */
502 void
503 nxge_rx_hw_blank(void *arg, time_t ticks, uint_t count)
504 {
505 	p_nxge_t nxgep = (p_nxge_t)arg;
506 	uint8_t channel;
507 	npi_handle_t handle;
508 	p_nxge_ldgv_t ldgvp;
509 	p_nxge_ldv_t ldvp;
510 	int i;
511 
512 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_rx_hw_blank"));
513 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
514 
515 	if ((ldgvp = nxgep->ldgvp) == NULL) {
516 		NXGE_ERROR_MSG((nxgep, INT_CTL,
517 		    "<== nxge_rx_hw_blank (not enabled)"));
518 		return;
519 	}
520 	ldvp = nxgep->ldgvp->ldvp;
521 	if (ldvp == NULL) {
522 		return;
523 	}
524 	for (i = 0; i < ldgvp->nldvs; i++, ldvp++) {
525 		if (ldvp->is_rxdma) {
526 			channel = ldvp->channel;
527 			(void) npi_rxdma_cfg_rdc_rcr_threshold(handle,
528 			    channel, count);
529 			(void) npi_rxdma_cfg_rdc_rcr_timeout(handle,
530 			    channel, ticks);
531 		}
532 	}
533 
534 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_rx_hw_blank"));
535 }
536 
537 /* ARGSUSED */
538 void
539 nxge_hw_stop(p_nxge_t nxgep)
540 {
541 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_stop"));
542 
543 	(void) nxge_tx_mac_disable(nxgep);
544 	(void) nxge_rx_mac_disable(nxgep);
545 	(void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_STOP);
546 	(void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP);
547 
548 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_stop"));
549 }
550 
551 /* ARGSUSED */
552 void
553 nxge_hw_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp)
554 {
555 	int cmd;
556 
557 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_hw_ioctl"));
558 
559 	if (nxgep == NULL) {
560 		miocnak(wq, mp, 0, EINVAL);
561 		return;
562 	}
563 	iocp->ioc_error = 0;
564 	cmd = iocp->ioc_cmd;
565 
566 	switch (cmd) {
567 	default:
568 		miocnak(wq, mp, 0, EINVAL);
569 		return;
570 
571 	case NXGE_GET_MII:
572 		nxge_get_mii(nxgep, mp->b_cont);
573 		miocack(wq, mp, sizeof (uint16_t), 0);
574 		break;
575 
576 	case NXGE_PUT_MII:
577 		nxge_put_mii(nxgep, mp->b_cont);
578 		miocack(wq, mp, 0, 0);
579 		break;
580 
581 	case NXGE_GET64:
582 		nxge_get64(nxgep, mp->b_cont);
583 		miocack(wq, mp, sizeof (uint32_t), 0);
584 		break;
585 
586 	case NXGE_PUT64:
587 		nxge_put64(nxgep, mp->b_cont);
588 		miocack(wq, mp, 0, 0);
589 		break;
590 
591 	case NXGE_PUT_TCAM:
592 		nxge_put_tcam(nxgep, mp->b_cont);
593 		miocack(wq, mp, 0, 0);
594 		break;
595 
596 	case NXGE_GET_TCAM:
597 		nxge_get_tcam(nxgep, mp->b_cont);
598 		miocack(wq, mp, 0, 0);
599 		break;
600 
601 	case NXGE_TX_REGS_DUMP:
602 		nxge_txdma_regs_dump_channels(nxgep);
603 		miocack(wq, mp, 0, 0);
604 		break;
605 	case NXGE_RX_REGS_DUMP:
606 		nxge_rxdma_regs_dump_channels(nxgep);
607 		miocack(wq, mp, 0, 0);
608 		break;
609 	case NXGE_VIR_INT_REGS_DUMP:
610 	case NXGE_INT_REGS_DUMP:
611 		nxge_virint_regs_dump(nxgep);
612 		miocack(wq, mp, 0, 0);
613 		break;
614 	case NXGE_RTRACE:
615 		nxge_rtrace_ioctl(nxgep, wq, mp, iocp);
616 		break;
617 	}
618 }
619 
620 /* ARGSUSED */
621 void
622 nxge_loopback_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp,
623 	struct iocblk *iocp)
624 {
625 	p_lb_property_t lb_props;
626 
627 	size_t size;
628 	int i;
629 
630 	if (mp->b_cont == NULL) {
631 		miocnak(wq, mp, 0, EINVAL);
632 	}
633 	switch (iocp->ioc_cmd) {
634 	case LB_GET_MODE:
635 		NXGE_DEBUG_MSG((nxgep, IOC_CTL, "NXGE_GET_LB_MODE command"));
636 		if (nxgep != NULL) {
637 			*(lb_info_sz_t *)mp->b_cont->b_rptr =
638 			    nxgep->statsp->port_stats.lb_mode;
639 			miocack(wq, mp, sizeof (nxge_lb_t), 0);
640 		} else {
641 			miocnak(wq, mp, 0, EINVAL);
642 		}
643 		break;
644 	case LB_SET_MODE:
645 		NXGE_DEBUG_MSG((nxgep, IOC_CTL, "NXGE_SET_LB_MODE command"));
646 		if (iocp->ioc_count != sizeof (uint32_t)) {
647 			miocack(wq, mp, 0, 0);
648 			break;
649 		}
650 		if ((nxgep != NULL) && nxge_set_lb(nxgep, wq, mp->b_cont)) {
651 			miocack(wq, mp, 0, 0);
652 		} else {
653 			miocnak(wq, mp, 0, EPROTO);
654 		}
655 		break;
656 	case LB_GET_INFO_SIZE:
657 		NXGE_DEBUG_MSG((nxgep, IOC_CTL, "LB_GET_INFO_SIZE command"));
658 		if (nxgep != NULL) {
659 			size = sizeof (lb_normal);
660 			if (nxgep->statsp->mac_stats.cap_10gfdx) {
661 				/* TN1010 does not support external loopback */
662 				if (nxgep->mac.portmode != PORT_1G_TN1010 &&
663 				    nxgep->mac.portmode != PORT_10G_TN1010) {
664 					size += sizeof (lb_external10g);
665 				}
666 				size += sizeof (lb_mac10g);
667 				/* Publish PHY loopback if PHY is present */
668 				if (nxgep->mac.portmode == PORT_10G_COPPER ||
669 				    nxgep->mac.portmode == PORT_10G_TN1010 ||
670 				    nxgep->mac.portmode == PORT_10G_FIBER)
671 					size += sizeof (lb_phy10g);
672 			}
673 
674 			/*
675 			 * Even if cap_10gfdx is false, we still do 10G
676 			 * serdes loopback as a part of SunVTS xnetlbtest
677 			 * internal loopback test.
678 			 */
679 			if (nxgep->mac.portmode == PORT_10G_FIBER ||
680 			    nxgep->mac.portmode == PORT_10G_TN1010 ||
681 			    nxgep->mac.portmode == PORT_10G_SERDES)
682 				size += sizeof (lb_serdes10g);
683 
684 			if (nxgep->statsp->mac_stats.cap_1000fdx) {
685 				/* TN1010 does not support external loopback */
686 				if (nxgep->mac.portmode != PORT_1G_TN1010 &&
687 				    nxgep->mac.portmode != PORT_10G_TN1010) {
688 					size += sizeof (lb_external1000);
689 				}
690 				size += sizeof (lb_mac1000);
691 				if (nxgep->mac.portmode == PORT_1G_COPPER ||
692 				    nxgep->mac.portmode == PORT_1G_TN1010 ||
693 				    nxgep->mac.portmode ==
694 				    PORT_1G_RGMII_FIBER)
695 					size += sizeof (lb_phy1000);
696 			}
697 			if (nxgep->statsp->mac_stats.cap_100fdx)
698 				size += sizeof (lb_external100);
699 			if (nxgep->statsp->mac_stats.cap_10fdx)
700 				size += sizeof (lb_external10);
701 			if (nxgep->mac.portmode == PORT_1G_FIBER ||
702 			    nxgep->mac.portmode == PORT_1G_TN1010 ||
703 			    nxgep->mac.portmode == PORT_1G_SERDES)
704 				size += sizeof (lb_serdes1000);
705 
706 			*(lb_info_sz_t *)mp->b_cont->b_rptr = size;
707 
708 			NXGE_DEBUG_MSG((nxgep, IOC_CTL,
709 			    "NXGE_GET_LB_INFO command: size %d", size));
710 			miocack(wq, mp, sizeof (lb_info_sz_t), 0);
711 		} else
712 			miocnak(wq, mp, 0, EINVAL);
713 		break;
714 
715 	case LB_GET_INFO:
716 		NXGE_DEBUG_MSG((nxgep, IOC_CTL, "NXGE_GET_LB_INFO command"));
717 		if (nxgep != NULL) {
718 			size = sizeof (lb_normal);
719 			if (nxgep->statsp->mac_stats.cap_10gfdx) {
720 				/* TN1010 does not support external loopback */
721 				if (nxgep->mac.portmode != PORT_1G_TN1010 &&
722 				    nxgep->mac.portmode != PORT_10G_TN1010) {
723 					size += sizeof (lb_external10g);
724 				}
725 				size += sizeof (lb_mac10g);
726 				/* Publish PHY loopback if PHY is present */
727 				if (nxgep->mac.portmode == PORT_10G_COPPER ||
728 				    nxgep->mac.portmode == PORT_10G_TN1010 ||
729 				    nxgep->mac.portmode == PORT_10G_FIBER)
730 					size += sizeof (lb_phy10g);
731 			}
732 			if (nxgep->mac.portmode == PORT_10G_FIBER ||
733 			    nxgep->mac.portmode == PORT_10G_TN1010 ||
734 			    nxgep->mac.portmode == PORT_10G_SERDES)
735 				size += sizeof (lb_serdes10g);
736 
737 			if (nxgep->statsp->mac_stats.cap_1000fdx) {
738 				/* TN1010 does not support external loopback */
739 				if (nxgep->mac.portmode != PORT_1G_TN1010 &&
740 				    nxgep->mac.portmode != PORT_10G_TN1010) {
741 					size += sizeof (lb_external1000);
742 				}
743 				size += sizeof (lb_mac1000);
744 				if (nxgep->mac.portmode == PORT_1G_COPPER ||
745 				    nxgep->mac.portmode == PORT_1G_TN1010 ||
746 				    nxgep->mac.portmode ==
747 				    PORT_1G_RGMII_FIBER)
748 					size += sizeof (lb_phy1000);
749 			}
750 			if (nxgep->statsp->mac_stats.cap_100fdx)
751 				size += sizeof (lb_external100);
752 
753 			if (nxgep->statsp->mac_stats.cap_10fdx)
754 				size += sizeof (lb_external10);
755 
756 			if (nxgep->mac.portmode == PORT_1G_FIBER ||
757 			    nxgep->mac.portmode == PORT_1G_TN1010 ||
758 			    nxgep->mac.portmode == PORT_1G_SERDES)
759 				size += sizeof (lb_serdes1000);
760 
761 			NXGE_DEBUG_MSG((nxgep, IOC_CTL,
762 			    "NXGE_GET_LB_INFO command: size %d", size));
763 			if (size == iocp->ioc_count) {
764 				i = 0;
765 				lb_props = (p_lb_property_t)mp->b_cont->b_rptr;
766 				lb_props[i++] = lb_normal;
767 
768 				if (nxgep->statsp->mac_stats.cap_10gfdx) {
769 					lb_props[i++] = lb_mac10g;
770 					if (nxgep->mac.portmode ==
771 					    PORT_10G_COPPER ||
772 					    nxgep->mac.portmode ==
773 					    PORT_10G_TN1010 ||
774 					    nxgep->mac.portmode ==
775 					    PORT_10G_FIBER) {
776 						lb_props[i++] = lb_phy10g;
777 					}
778 					/* TN1010 does not support ext lb */
779 					if (nxgep->mac.portmode !=
780 					    PORT_10G_TN1010 &&
781 					    nxgep->mac.portmode !=
782 					    PORT_1G_TN1010) {
783 						lb_props[i++] = lb_external10g;
784 					}
785 				}
786 
787 				if (nxgep->mac.portmode == PORT_10G_FIBER ||
788 				    nxgep->mac.portmode == PORT_10G_TN1010 ||
789 				    nxgep->mac.portmode == PORT_10G_SERDES)
790 					lb_props[i++] = lb_serdes10g;
791 
792 				if (nxgep->statsp->mac_stats.cap_1000fdx) {
793 					/* TN1010 does not support ext lb */
794 					if (nxgep->mac.portmode !=
795 					    PORT_10G_TN1010 &&
796 					    nxgep->mac.portmode !=
797 					    PORT_1G_TN1010) {
798 						lb_props[i++] = lb_external1000;
799 					}
800 				}
801 
802 				if (nxgep->statsp->mac_stats.cap_100fdx)
803 					lb_props[i++] = lb_external100;
804 
805 				if (nxgep->statsp->mac_stats.cap_10fdx)
806 					lb_props[i++] = lb_external10;
807 
808 				if (nxgep->statsp->mac_stats.cap_1000fdx)
809 					lb_props[i++] = lb_mac1000;
810 
811 				if (nxgep->mac.portmode == PORT_1G_COPPER ||
812 				    nxgep->mac.portmode == PORT_1G_TN1010 ||
813 				    nxgep->mac.portmode ==
814 				    PORT_1G_RGMII_FIBER) {
815 					if (nxgep->statsp->mac_stats.
816 					    cap_1000fdx)
817 						lb_props[i++] = lb_phy1000;
818 				} else if (nxgep->mac.portmode ==
819 				    PORT_1G_FIBER ||
820 				    nxgep->mac.portmode == PORT_1G_TN1010 ||
821 				    nxgep->mac.portmode == PORT_1G_SERDES) {
822 					lb_props[i++] = lb_serdes1000;
823 				}
824 				miocack(wq, mp, size, 0);
825 			} else
826 				miocnak(wq, mp, 0, EINVAL);
827 		} else {
828 			miocnak(wq, mp, 0, EINVAL);
829 			cmn_err(CE_NOTE, "!nxge_hw_ioctl: invalid command 0x%x",
830 			    iocp->ioc_cmd);
831 		}
832 		break;
833 	}
834 }
835 
836 /*
837  * DMA channel interfaces to access various channel specific
838  * hardware functions.
839  */
840 /* ARGSUSED */
841 void
842 nxge_rxdma_channel_put64(nxge_os_acc_handle_t handle, void *reg_addrp,
843 	uint32_t reg_base, uint16_t channel, uint64_t reg_data)
844 {
845 	uint64_t reg_offset;
846 
847 	NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_channel_put64"));
848 
849 	/*
850 	 * Channel is assumed to be from 0 to the maximum DMA channel #. If we
851 	 * use the virtual DMA CSR address space from the config space (in PCI
852 	 * case), then the following code need to be use different offset
853 	 * computation macro.
854 	 */
855 	reg_offset = reg_base + DMC_OFFSET(channel);
856 	NXGE_PIO_WRITE64(handle, reg_addrp, reg_offset, reg_data);
857 
858 	NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_channel_put64"));
859 }
860 
861 /* ARGSUSED */
862 uint64_t
863 nxge_rxdma_channel_get64(nxge_os_acc_handle_t handle, void *reg_addrp,
864 	uint32_t reg_base, uint16_t channel)
865 {
866 	uint64_t reg_offset;
867 
868 	NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_channel_get64"));
869 
870 	/*
871 	 * Channel is assumed to be from 0 to the maximum DMA channel #. If we
872 	 * use the virtual DMA CSR address space from the config space (in PCI
873 	 * case), then the following code need to be use different offset
874 	 * computation macro.
875 	 */
876 	reg_offset = reg_base + DMC_OFFSET(channel);
877 
878 	NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_channel_get64"));
879 
880 	return (NXGE_PIO_READ64(handle, reg_addrp, reg_offset));
881 }
882 
883 /* ARGSUSED */
884 void
885 nxge_get32(p_nxge_t nxgep, p_mblk_t mp)
886 {
887 	nxge_os_acc_handle_t nxge_regh;
888 
889 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "nxge_get32"));
890 	nxge_regh = nxgep->dev_regs->nxge_regh;
891 
892 	*(uint32_t *)mp->b_rptr = NXGE_PIO_READ32(nxge_regh,
893 	    nxgep->dev_regs->nxge_regp, *(uint32_t *)mp->b_rptr);
894 
895 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "value = 0x%08X",
896 	    *(uint32_t *)mp->b_rptr));
897 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "nxge_get32"));
898 }
899 
900 /* ARGSUSED */
901 void
902 nxge_put32(p_nxge_t nxgep, p_mblk_t mp)
903 {
904 	nxge_os_acc_handle_t nxge_regh;
905 	uint32_t *buf;
906 	uint8_t *reg;
907 
908 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "nxge_put32"));
909 	nxge_regh = nxgep->dev_regs->nxge_regh;
910 
911 	buf = (uint32_t *)mp->b_rptr;
912 	reg = (uint8_t *)(nxgep->dev_regs->nxge_regp) + buf[0];
913 	NXGE_DEBUG_MSG((nxgep, IOC_CTL,
914 	    "reg = 0x%016llX index = 0x%08X value = 0x%08X",
915 	    reg, buf[0], buf[1]));
916 	NXGE_PIO_WRITE32(nxge_regh, (uint32_t *)reg, 0, buf[1]);
917 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "nxge_put32"));
918 }
919 
920 /*ARGSUSED*/
921 boolean_t
922 nxge_set_lb(p_nxge_t nxgep, queue_t *wq, p_mblk_t mp)
923 {
924 	boolean_t status = B_TRUE;
925 	uint32_t lb_mode;
926 	lb_property_t *lb_info;
927 
928 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_set_lb"));
929 	lb_mode = nxgep->statsp->port_stats.lb_mode;
930 	if (lb_mode == *(uint32_t *)mp->b_rptr) {
931 		cmn_err(CE_NOTE,
932 		    "!nxge%d: Loopback mode already set (lb_mode %d).\n",
933 		    nxgep->instance, lb_mode);
934 		status = B_FALSE;
935 		goto nxge_set_lb_exit;
936 	}
937 	lb_mode = *(uint32_t *)mp->b_rptr;
938 	lb_info = NULL;
939 	if (lb_mode == lb_normal.value)
940 		lb_info = &lb_normal;
941 	else if ((lb_mode == lb_external10g.value) &&
942 	    (nxgep->statsp->mac_stats.cap_10gfdx))
943 		lb_info = &lb_external10g;
944 	else if ((lb_mode == lb_external1000.value) &&
945 	    (nxgep->statsp->mac_stats.cap_1000fdx))
946 		lb_info = &lb_external1000;
947 	else if ((lb_mode == lb_external100.value) &&
948 	    (nxgep->statsp->mac_stats.cap_100fdx))
949 		lb_info = &lb_external100;
950 	else if ((lb_mode == lb_external10.value) &&
951 	    (nxgep->statsp->mac_stats.cap_10fdx))
952 		lb_info = &lb_external10;
953 	else if ((lb_mode == lb_phy10g.value) &&
954 	    (nxgep->mac.portmode == PORT_10G_COPPER ||
955 	    nxgep->mac.portmode == PORT_10G_TN1010 ||
956 	    nxgep->mac.portmode == PORT_10G_FIBER))
957 		lb_info = &lb_phy10g;
958 	else if ((lb_mode == lb_phy1000.value) &&
959 	    (nxgep->mac.portmode == PORT_1G_COPPER ||
960 	    nxgep->mac.portmode == PORT_1G_TN1010 ||
961 	    nxgep->mac.portmode == PORT_1G_RGMII_FIBER))
962 		lb_info = &lb_phy1000;
963 	else if ((lb_mode == lb_phy.value) &&
964 	    (nxgep->mac.portmode == PORT_1G_COPPER))
965 		lb_info = &lb_phy;
966 	else if ((lb_mode == lb_serdes10g.value) &&
967 	    (nxgep->mac.portmode == PORT_10G_FIBER ||
968 	    nxgep->mac.portmode == PORT_10G_COPPER ||
969 	    nxgep->mac.portmode == PORT_10G_TN1010 ||
970 	    nxgep->mac.portmode == PORT_10G_SERDES))
971 		lb_info = &lb_serdes10g;
972 	else if ((lb_mode == lb_serdes1000.value) &&
973 	    (nxgep->mac.portmode == PORT_1G_FIBER ||
974 	    nxgep->mac.portmode == PORT_1G_TN1010 ||
975 	    nxgep->mac.portmode == PORT_1G_SERDES))
976 		lb_info = &lb_serdes1000;
977 	else if (lb_mode == lb_mac10g.value)
978 		lb_info = &lb_mac10g;
979 	else if (lb_mode == lb_mac1000.value)
980 		lb_info = &lb_mac1000;
981 	else if (lb_mode == lb_mac.value)
982 		lb_info = &lb_mac;
983 	else {
984 		cmn_err(CE_NOTE,
985 		    "!nxge%d: Loopback mode not supported(mode %d).\n",
986 		    nxgep->instance, lb_mode);
987 		status = B_FALSE;
988 		goto nxge_set_lb_exit;
989 	}
990 
991 	if (lb_mode == nxge_lb_normal) {
992 		if (nxge_lb_dbg) {
993 			cmn_err(CE_NOTE,
994 			    "!nxge%d: Returning to normal operation",
995 			    nxgep->instance);
996 		}
997 		if (nxge_set_lb_normal(nxgep) != NXGE_OK) {
998 			status = B_FALSE;
999 			cmn_err(CE_NOTE,
1000 			    "!nxge%d: Failed to return to normal operation",
1001 			    nxgep->instance);
1002 		}
1003 		goto nxge_set_lb_exit;
1004 	}
1005 	nxgep->statsp->port_stats.lb_mode = lb_mode;
1006 
1007 	if (nxge_lb_dbg)
1008 		cmn_err(CE_NOTE,
1009 		    "!nxge%d: Adapter now in %s loopback mode",
1010 		    nxgep->instance, lb_info->key);
1011 	nxgep->param_arr[param_autoneg].value = 0;
1012 	nxgep->param_arr[param_anar_10gfdx].value =
1013 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext10g) ||
1014 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_mac10g) ||
1015 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy10g) ||
1016 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes10g);
1017 	nxgep->param_arr[param_anar_10ghdx].value = 0;
1018 	nxgep->param_arr[param_anar_1000fdx].value =
1019 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext1000) ||
1020 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_mac1000) ||
1021 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy1000) ||
1022 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes1000);
1023 	nxgep->param_arr[param_anar_1000hdx].value = 0;
1024 	nxgep->param_arr[param_anar_100fdx].value =
1025 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy) ||
1026 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_mac) ||
1027 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext100);
1028 	nxgep->param_arr[param_anar_100hdx].value = 0;
1029 	nxgep->param_arr[param_anar_10fdx].value =
1030 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_mac) ||
1031 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext10);
1032 	if (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext1000) {
1033 		nxgep->param_arr[param_master_cfg_enable].value = 1;
1034 		nxgep->param_arr[param_master_cfg_value].value = 1;
1035 	}
1036 	if ((nxgep->statsp->port_stats.lb_mode == nxge_lb_ext10g) ||
1037 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext1000) ||
1038 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext100) ||
1039 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext10) ||
1040 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy10g) ||
1041 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy1000) ||
1042 	    (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy)) {
1043 
1044 		if (nxge_link_monitor(nxgep, LINK_MONITOR_STOP) != NXGE_OK)
1045 			goto nxge_set_lb_err;
1046 		if (nxge_xcvr_find(nxgep) != NXGE_OK)
1047 			goto nxge_set_lb_err;
1048 		if (nxge_link_init(nxgep) != NXGE_OK)
1049 			goto nxge_set_lb_err;
1050 		if (nxge_link_monitor(nxgep, LINK_MONITOR_START) != NXGE_OK)
1051 			goto nxge_set_lb_err;
1052 	}
1053 	if (lb_info->lb_type == internal) {
1054 		if ((nxgep->statsp->port_stats.lb_mode == nxge_lb_mac10g) ||
1055 		    (nxgep->statsp->port_stats.lb_mode ==
1056 		    nxge_lb_phy10g) ||
1057 		    (nxgep->statsp->port_stats.lb_mode ==
1058 		    nxge_lb_serdes10g)) {
1059 			nxgep->statsp->mac_stats.link_speed = 10000;
1060 		} else if ((nxgep->statsp->port_stats.lb_mode
1061 		    == nxge_lb_mac1000) ||
1062 		    (nxgep->statsp->port_stats.lb_mode ==
1063 		    nxge_lb_phy1000) ||
1064 		    (nxgep->statsp->port_stats.lb_mode ==
1065 		    nxge_lb_serdes1000)) {
1066 			nxgep->statsp->mac_stats.link_speed = 1000;
1067 		} else {
1068 			nxgep->statsp->mac_stats.link_speed = 100;
1069 		}
1070 		nxgep->statsp->mac_stats.link_duplex = 2;
1071 		nxgep->statsp->mac_stats.link_up = 1;
1072 	}
1073 	if (nxge_global_reset(nxgep) != NXGE_OK)
1074 		goto nxge_set_lb_err;
1075 
1076 nxge_set_lb_exit:
1077 	NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1078 	    "<== nxge_set_lb status = 0x%08x", status));
1079 	return (status);
1080 nxge_set_lb_err:
1081 	status = B_FALSE;
1082 	cmn_err(CE_NOTE,
1083 	    "!nxge%d: Failed to put adapter in %s loopback mode",
1084 	    nxgep->instance, lb_info->key);
1085 	return (status);
1086 }
1087 
1088 /* Return to normal (no loopback) mode */
1089 /* ARGSUSED */
1090 nxge_status_t
1091 nxge_set_lb_normal(p_nxge_t nxgep)
1092 {
1093 	nxge_status_t	status = NXGE_OK;
1094 
1095 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_set_lb_normal"));
1096 
1097 	nxgep->statsp->port_stats.lb_mode = nxge_lb_normal;
1098 	nxgep->param_arr[param_autoneg].value =
1099 	    nxgep->param_arr[param_autoneg].old_value;
1100 	nxgep->param_arr[param_anar_1000fdx].value =
1101 	    nxgep->param_arr[param_anar_1000fdx].old_value;
1102 	nxgep->param_arr[param_anar_1000hdx].value =
1103 	    nxgep->param_arr[param_anar_1000hdx].old_value;
1104 	nxgep->param_arr[param_anar_100fdx].value =
1105 	    nxgep->param_arr[param_anar_100fdx].old_value;
1106 	nxgep->param_arr[param_anar_100hdx].value =
1107 	    nxgep->param_arr[param_anar_100hdx].old_value;
1108 	nxgep->param_arr[param_anar_10fdx].value =
1109 	    nxgep->param_arr[param_anar_10fdx].old_value;
1110 	nxgep->param_arr[param_master_cfg_enable].value =
1111 	    nxgep->param_arr[param_master_cfg_enable].old_value;
1112 	nxgep->param_arr[param_master_cfg_value].value =
1113 	    nxgep->param_arr[param_master_cfg_value].old_value;
1114 
1115 	if ((status = nxge_global_reset(nxgep)) != NXGE_OK)
1116 		return (status);
1117 
1118 	if ((status = nxge_link_monitor(nxgep, LINK_MONITOR_STOP)) != NXGE_OK)
1119 		return (status);
1120 	if ((status = nxge_xcvr_find(nxgep)) != NXGE_OK)
1121 		return (status);
1122 	if ((status = nxge_link_init(nxgep)) != NXGE_OK)
1123 		return (status);
1124 	status = nxge_link_monitor(nxgep, LINK_MONITOR_START);
1125 
1126 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_set_lb_normal"));
1127 
1128 	return (status);
1129 }
1130 
1131 /* ARGSUSED */
1132 void
1133 nxge_get_mii(p_nxge_t nxgep, p_mblk_t mp)
1134 {
1135 	uint16_t reg;
1136 
1137 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_get_mii"));
1138 
1139 	reg = *(uint16_t *)mp->b_rptr;
1140 	(void) nxge_mii_read(nxgep, nxgep->statsp->mac_stats.xcvr_portn, reg,
1141 	    (uint16_t *)mp->b_rptr);
1142 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "reg = 0x%08X value = 0x%04X",
1143 	    reg, *(uint16_t *)mp->b_rptr));
1144 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_get_mii"));
1145 }
1146 
1147 /* ARGSUSED */
1148 void
1149 nxge_put_mii(p_nxge_t nxgep, p_mblk_t mp)
1150 {
1151 	uint16_t *buf;
1152 	uint8_t reg;
1153 
1154 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_put_mii"));
1155 	buf = (uint16_t *)mp->b_rptr;
1156 	reg = (uint8_t)buf[0];
1157 	NXGE_DEBUG_MSG((nxgep, IOC_CTL,
1158 	    "reg = 0x%08X index = 0x%08X value = 0x%08X",
1159 	    reg, buf[0], buf[1]));
1160 	(void) nxge_mii_write(nxgep, nxgep->statsp->mac_stats.xcvr_portn,
1161 	    reg, buf[1]);
1162 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_put_mii"));
1163 }
1164 
1165 /* ARGSUSED */
1166 void
1167 nxge_check_hw_state(p_nxge_t nxgep)
1168 {
1169 	p_nxge_ldgv_t ldgvp;
1170 	p_nxge_ldv_t t_ldvp;
1171 
1172 	NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, "==> nxge_check_hw_state"));
1173 
1174 	MUTEX_ENTER(nxgep->genlock);
1175 	nxgep->nxge_timerid = 0;
1176 	if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) {
1177 		goto nxge_check_hw_state_exit;
1178 	}
1179 	nxge_check_tx_hang(nxgep);
1180 
1181 	ldgvp = nxgep->ldgvp;
1182 	if (ldgvp == NULL || (ldgvp->ldvp_syserr == NULL)) {
1183 		NXGE_ERROR_MSG((nxgep, SYSERR_CTL, "<== nxge_check_hw_state: "
1184 		    "NULL ldgvp (interrupt not ready)."));
1185 		goto nxge_check_hw_state_exit;
1186 	}
1187 	t_ldvp = ldgvp->ldvp_syserr;
1188 	if (!t_ldvp->use_timer) {
1189 		NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, "<== nxge_check_hw_state: "
1190 		    "ldgvp $%p t_ldvp $%p use_timer flag %d",
1191 		    ldgvp, t_ldvp, t_ldvp->use_timer));
1192 		goto nxge_check_hw_state_exit;
1193 	}
1194 	if (fm_check_acc_handle(nxgep->dev_regs->nxge_regh) != DDI_FM_OK) {
1195 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1196 		    "port%d Bad register acc handle", nxgep->mac.portnum));
1197 	}
1198 	(void) nxge_syserr_intr((void *) t_ldvp, (void *) nxgep);
1199 
1200 	nxgep->nxge_timerid = nxge_start_timer(nxgep, nxge_check_hw_state,
1201 	    NXGE_CHECK_TIMER);
1202 
1203 nxge_check_hw_state_exit:
1204 	MUTEX_EXIT(nxgep->genlock);
1205 	NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, "<== nxge_check_hw_state"));
1206 }
1207 
1208 /*ARGSUSED*/
1209 static void
1210 nxge_rtrace_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp,
1211 	struct iocblk *iocp)
1212 {
1213 	ssize_t size;
1214 	rtrace_t *rtp;
1215 	mblk_t *nmp;
1216 	uint32_t i, j;
1217 	uint32_t start_blk;
1218 	uint32_t base_entry;
1219 	uint32_t num_entries;
1220 
1221 	NXGE_DEBUG_MSG((nxgep, STR_CTL, "==> nxge_rtrace_ioctl"));
1222 
1223 	size = 1024;
1224 	if (mp->b_cont == NULL || MBLKL(mp->b_cont) < size) {
1225 		NXGE_DEBUG_MSG((nxgep, STR_CTL,
1226 		    "malformed M_IOCTL MBLKL = %d size = %d",
1227 		    MBLKL(mp->b_cont), size));
1228 		miocnak(wq, mp, 0, EINVAL);
1229 		return;
1230 	}
1231 	nmp = mp->b_cont;
1232 	rtp = (rtrace_t *)nmp->b_rptr;
1233 	start_blk = rtp->next_idx;
1234 	num_entries = rtp->last_idx;
1235 	base_entry = start_blk * MAX_RTRACE_IOC_ENTRIES;
1236 
1237 	NXGE_DEBUG_MSG((nxgep, STR_CTL, "start_blk = %d\n", start_blk));
1238 	NXGE_DEBUG_MSG((nxgep, STR_CTL, "num_entries = %d\n", num_entries));
1239 	NXGE_DEBUG_MSG((nxgep, STR_CTL, "base_entry = %d\n", base_entry));
1240 
1241 	rtp->next_idx = npi_rtracebuf.next_idx;
1242 	rtp->last_idx = npi_rtracebuf.last_idx;
1243 	rtp->wrapped = npi_rtracebuf.wrapped;
1244 	for (i = 0, j = base_entry; i < num_entries; i++, j++) {
1245 		rtp->buf[i].ctl_addr = npi_rtracebuf.buf[j].ctl_addr;
1246 		rtp->buf[i].val_l32 = npi_rtracebuf.buf[j].val_l32;
1247 		rtp->buf[i].val_h32 = npi_rtracebuf.buf[j].val_h32;
1248 	}
1249 
1250 	nmp->b_wptr = nmp->b_rptr + size;
1251 	NXGE_DEBUG_MSG((nxgep, STR_CTL, "<== nxge_rtrace_ioctl"));
1252 	miocack(wq, mp, (int)size, 0);
1253 }
1254