1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 NetXen, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 #ifndef __UNM_INC_H 26 #define __UNM_INC_H 27 28 #include "nx_errorcode.h" 29 30 #define PREALIGN(x) 31 #define POSTALIGN(x) 32 33 typedef char __int8_t; 34 typedef short __int16_t; 35 typedef int __int32_t; 36 typedef long long __int64_t; 37 typedef unsigned char __uint8_t; 38 typedef unsigned short __uint16_t; 39 typedef unsigned int __uint32_t; 40 typedef unsigned long long __uint64_t; 41 typedef __uint64_t jiffies_t; 42 43 typedef uint8_t u8; 44 typedef uint8_t U8; 45 typedef uint16_t U16; 46 typedef uint32_t u32; 47 typedef uint32_t U32; 48 typedef unsigned long long u64; 49 typedef unsigned long long U64; 50 51 #define UNUSED __attribute__((unused)) 52 #define NOINLINE __attribute__((noinline)) 53 54 #include "nx_hw_pci_regs.h" 55 56 #define UNM_CONF_X86 3 57 58 #define bzero(A, B) memset((A), 0, (B)) 59 60 /* 61 * MAX_RCV_CTX : The number of receive contexts that are available on 62 * the phantom. 63 */ 64 #define MAX_RCV_CTX 1 65 66 /* ------------------------------------------------------------------------ */ 67 /* CRB Hub and Agent addressing */ 68 /* ------------------------------------------------------------------------ */ 69 /* 70 * WARNING: pex_tgt_adr.v assumes if MSB of hub adr is set then it is an 71 * ILLEGAL hub!!!!! 72 */ 73 #define UNM_HW_H0_CH_HUB_ADR 0x05 74 #define UNM_HW_H1_CH_HUB_ADR 0x0E 75 #define UNM_HW_H2_CH_HUB_ADR 0x03 76 #define UNM_HW_H3_CH_HUB_ADR 0x01 77 #define UNM_HW_H4_CH_HUB_ADR 0x06 78 #define UNM_HW_H5_CH_HUB_ADR 0x07 79 #define UNM_HW_H6_CH_HUB_ADR 0x08 80 /* 81 * WARNING: pex_tgt_adr.v assumes if MSB of hub adr is set then it is an 82 * ILLEGAL hub!!!!! 83 */ 84 85 /* Hub 0 */ 86 #define UNM_HW_MN_CRB_AGT_ADR 0x15 87 #define UNM_HW_MS_CRB_AGT_ADR 0x25 88 89 /* Hub 1 */ 90 #define UNM_HW_PS_CRB_AGT_ADR 0x73 91 #define UNM_HW_SS_CRB_AGT_ADR 0x20 92 #define UNM_HW_RPMX3_CRB_AGT_ADR 0x0b 93 #define UNM_HW_QMS_CRB_AGT_ADR 0x00 94 #define UNM_HW_SQGS0_CRB_AGT_ADR 0x01 95 #define UNM_HW_SQGS1_CRB_AGT_ADR 0x02 96 #define UNM_HW_SQGS2_CRB_AGT_ADR 0x03 97 #define UNM_HW_SQGS3_CRB_AGT_ADR 0x04 98 #define UNM_HW_C2C0_CRB_AGT_ADR 0x58 99 #define UNM_HW_C2C1_CRB_AGT_ADR 0x59 100 #define UNM_HW_C2C2_CRB_AGT_ADR 0x5a 101 #define UNM_HW_RPMX2_CRB_AGT_ADR 0x0a 102 #define UNM_HW_RPMX4_CRB_AGT_ADR 0x0c 103 #define UNM_HW_RPMX7_CRB_AGT_ADR 0x0f 104 #define UNM_HW_RPMX9_CRB_AGT_ADR 0x12 105 #define UNM_HW_SMB_CRB_AGT_ADR 0x18 106 107 /* Hub 2 */ 108 #define UNM_HW_NIU_CRB_AGT_ADR 0x31 109 #define UNM_HW_I2C0_CRB_AGT_ADR 0x19 110 #define UNM_HW_I2C1_CRB_AGT_ADR 0x29 111 112 #define UNM_HW_SN_CRB_AGT_ADR 0x10 113 #define UNM_HW_I2Q_CRB_AGT_ADR 0x20 114 #define UNM_HW_LPC_CRB_AGT_ADR 0x22 115 #define UNM_HW_ROMUSB_CRB_AGT_ADR 0x21 116 #define UNM_HW_QM_CRB_AGT_ADR 0x66 117 #define UNM_HW_SQG0_CRB_AGT_ADR 0x60 118 #define UNM_HW_SQG1_CRB_AGT_ADR 0x61 119 #define UNM_HW_SQG2_CRB_AGT_ADR 0x62 120 #define UNM_HW_SQG3_CRB_AGT_ADR 0x63 121 #define UNM_HW_RPMX1_CRB_AGT_ADR 0x09 122 #define UNM_HW_RPMX5_CRB_AGT_ADR 0x0d 123 #define UNM_HW_RPMX6_CRB_AGT_ADR 0x0e 124 #define UNM_HW_RPMX8_CRB_AGT_ADR 0x11 125 126 /* Hub 3 */ 127 #define UNM_HW_PH_CRB_AGT_ADR 0x1A 128 #define UNM_HW_SRE_CRB_AGT_ADR 0x50 129 #define UNM_HW_EG_CRB_AGT_ADR 0x51 130 #define UNM_HW_RPMX0_CRB_AGT_ADR 0x08 131 132 /* Hub 4 */ 133 #define UNM_HW_PEGN0_CRB_AGT_ADR 0x40 134 #define UNM_HW_PEGN1_CRB_AGT_ADR 0x41 135 #define UNM_HW_PEGN2_CRB_AGT_ADR 0x42 136 #define UNM_HW_PEGN3_CRB_AGT_ADR 0x43 137 #define UNM_HW_PEGNI_CRB_AGT_ADR 0x44 138 #define UNM_HW_PEGND_CRB_AGT_ADR 0x45 139 #define UNM_HW_PEGNC_CRB_AGT_ADR 0x46 140 #define UNM_HW_PEGR0_CRB_AGT_ADR 0x47 141 #define UNM_HW_PEGR1_CRB_AGT_ADR 0x48 142 #define UNM_HW_PEGR2_CRB_AGT_ADR 0x49 143 #define UNM_HW_PEGR3_CRB_AGT_ADR 0x4a 144 #define UNM_HW_PEGN4_CRB_AGT_ADR 0x4b 145 146 /* Hub 5 */ 147 #define UNM_HW_PEGS0_CRB_AGT_ADR 0x40 148 #define UNM_HW_PEGS1_CRB_AGT_ADR 0x41 149 #define UNM_HW_PEGS2_CRB_AGT_ADR 0x42 150 #define UNM_HW_PEGS3_CRB_AGT_ADR 0x43 151 #define UNM_HW_PEGSI_CRB_AGT_ADR 0x44 152 #define UNM_HW_PEGSD_CRB_AGT_ADR 0x45 153 #define UNM_HW_PEGSC_CRB_AGT_ADR 0x46 154 155 /* Hub 6 */ 156 #define UNM_HW_CAS0_CRB_AGT_ADR 0x46 157 #define UNM_HW_CAS1_CRB_AGT_ADR 0x47 158 #define UNM_HW_CAS2_CRB_AGT_ADR 0x48 159 #define UNM_HW_CAS3_CRB_AGT_ADR 0x49 160 #define UNM_HW_NCM_CRB_AGT_ADR 0x16 161 #define UNM_HW_TMR_CRB_AGT_ADR 0x17 162 #define UNM_HW_XDMA_CRB_AGT_ADR 0x05 163 #define UNM_HW_OCM0_CRB_AGT_ADR 0x06 164 #define UNM_HW_OCM1_CRB_AGT_ADR 0x07 165 166 /* This field defines PCI/X adr [25:20] of agents on the CRB */ 167 /* */ 168 #define UNM_HW_PX_MAP_CRB_PH 0 169 #define UNM_HW_PX_MAP_CRB_PS 1 170 #define UNM_HW_PX_MAP_CRB_MN 2 171 #define UNM_HW_PX_MAP_CRB_MS 3 172 #define UNM_HW_PX_MAP_CRB_SRE 5 173 #define UNM_HW_PX_MAP_CRB_NIU 6 174 #define UNM_HW_PX_MAP_CRB_QMN 7 175 #define UNM_HW_PX_MAP_CRB_SQN0 8 176 #define UNM_HW_PX_MAP_CRB_SQN1 9 177 #define UNM_HW_PX_MAP_CRB_SQN2 10 178 #define UNM_HW_PX_MAP_CRB_SQN3 11 179 #define UNM_HW_PX_MAP_CRB_QMS 12 180 #define UNM_HW_PX_MAP_CRB_SQS0 13 181 #define UNM_HW_PX_MAP_CRB_SQS1 14 182 #define UNM_HW_PX_MAP_CRB_SQS2 15 183 #define UNM_HW_PX_MAP_CRB_SQS3 16 184 #define UNM_HW_PX_MAP_CRB_PGN0 17 185 #define UNM_HW_PX_MAP_CRB_PGN1 18 186 #define UNM_HW_PX_MAP_CRB_PGN2 19 187 #define UNM_HW_PX_MAP_CRB_PGN3 20 188 #define UNM_HW_PX_MAP_CRB_PGND 21 189 #define UNM_HW_PX_MAP_CRB_PGNI 22 190 #define UNM_HW_PX_MAP_CRB_PGS0 23 191 #define UNM_HW_PX_MAP_CRB_PGS1 24 192 #define UNM_HW_PX_MAP_CRB_PGS2 25 193 #define UNM_HW_PX_MAP_CRB_PGS3 26 194 #define UNM_HW_PX_MAP_CRB_PGSD 27 195 #define UNM_HW_PX_MAP_CRB_PGSI 28 196 #define UNM_HW_PX_MAP_CRB_SN 29 197 #define UNM_HW_PX_MAP_CRB_EG 31 198 #define UNM_HW_PX_MAP_CRB_PH2 32 199 #define UNM_HW_PX_MAP_CRB_PS2 33 200 #define UNM_HW_PX_MAP_CRB_CAM 34 201 #define UNM_HW_PX_MAP_CRB_CAS0 35 202 #define UNM_HW_PX_MAP_CRB_CAS1 36 203 #define UNM_HW_PX_MAP_CRB_CAS2 37 204 #define UNM_HW_PX_MAP_CRB_C2C0 38 205 #define UNM_HW_PX_MAP_CRB_C2C1 39 206 #define UNM_HW_PX_MAP_CRB_TIMR 40 207 /* N/A: Not use in either Phantom1 or Phantom2 => use for TIMR */ 208 /* #define PX_MAP_CRB_C2C2 40 */ 209 /* #define PX_MAP_CRB_SS 41 */ 210 #define UNM_HW_PX_MAP_CRB_RPMX1 42 211 #define UNM_HW_PX_MAP_CRB_RPMX2 43 212 #define UNM_HW_PX_MAP_CRB_RPMX3 44 213 #define UNM_HW_PX_MAP_CRB_RPMX4 45 214 #define UNM_HW_PX_MAP_CRB_RPMX5 46 215 #define UNM_HW_PX_MAP_CRB_RPMX6 47 216 #define UNM_HW_PX_MAP_CRB_RPMX7 48 217 #define UNM_HW_PX_MAP_CRB_XDMA 49 218 #define UNM_HW_PX_MAP_CRB_I2Q 50 219 #define UNM_HW_PX_MAP_CRB_ROMUSB 51 220 #define UNM_HW_PX_MAP_CRB_CAS3 52 221 #define UNM_HW_PX_MAP_CRB_RPMX0 53 222 #define UNM_HW_PX_MAP_CRB_RPMX8 54 223 #define UNM_HW_PX_MAP_CRB_RPMX9 55 224 #define UNM_HW_PX_MAP_CRB_OCM0 56 225 #define UNM_HW_PX_MAP_CRB_OCM1 57 226 #define UNM_HW_PX_MAP_CRB_SMB 58 227 #define UNM_HW_PX_MAP_CRB_I2C0 59 228 #define UNM_HW_PX_MAP_CRB_I2C1 60 229 #define UNM_HW_PX_MAP_CRB_LPC 61 230 #define UNM_HW_PX_MAP_CRB_PGNC 62 231 #define UNM_HW_PX_MAP_CRB_PGR0 63 232 #define UNM_HW_PX_MAP_CRB_PGR1 4 233 #define UNM_HW_PX_MAP_CRB_PGR2 30 234 #define UNM_HW_PX_MAP_CRB_PGR3 41 235 236 /* This field defines CRB adr [31:20] of the agents */ 237 /* */ 238 239 #define UNM_HW_CRB_HUB_AGT_ADR_MN ((UNM_HW_H0_CH_HUB_ADR << 7) \ 240 | UNM_HW_MN_CRB_AGT_ADR) 241 #define UNM_HW_CRB_HUB_AGT_ADR_PH ((UNM_HW_H0_CH_HUB_ADR << 7) \ 242 | UNM_HW_PH_CRB_AGT_ADR) 243 #define UNM_HW_CRB_HUB_AGT_ADR_MS ((UNM_HW_H0_CH_HUB_ADR << 7) \ 244 | UNM_HW_MS_CRB_AGT_ADR) 245 246 #define UNM_HW_CRB_HUB_AGT_ADR_PS ((UNM_HW_H1_CH_HUB_ADR << 7) \ 247 | UNM_HW_PS_CRB_AGT_ADR) 248 #define UNM_HW_CRB_HUB_AGT_ADR_SS ((UNM_HW_H1_CH_HUB_ADR << 7) \ 249 | UNM_HW_SS_CRB_AGT_ADR) 250 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX3 ((UNM_HW_H1_CH_HUB_ADR << 7) \ 251 | UNM_HW_RPMX3_CRB_AGT_ADR) 252 #define UNM_HW_CRB_HUB_AGT_ADR_QMS ((UNM_HW_H1_CH_HUB_ADR << 7) \ 253 | UNM_HW_QMS_CRB_AGT_ADR) 254 #define UNM_HW_CRB_HUB_AGT_ADR_SQS0 ((UNM_HW_H1_CH_HUB_ADR << 7) \ 255 | UNM_HW_SQGS0_CRB_AGT_ADR) 256 #define UNM_HW_CRB_HUB_AGT_ADR_SQS1 ((UNM_HW_H1_CH_HUB_ADR << 7) \ 257 | UNM_HW_SQGS1_CRB_AGT_ADR) 258 #define UNM_HW_CRB_HUB_AGT_ADR_SQS2 ((UNM_HW_H1_CH_HUB_ADR << 7) \ 259 | UNM_HW_SQGS2_CRB_AGT_ADR) 260 #define UNM_HW_CRB_HUB_AGT_ADR_SQS3 ((UNM_HW_H1_CH_HUB_ADR << 7) \ 261 | UNM_HW_SQGS3_CRB_AGT_ADR) 262 #define UNM_HW_CRB_HUB_AGT_ADR_C2C0 ((UNM_HW_H1_CH_HUB_ADR << 7) \ 263 | UNM_HW_C2C0_CRB_AGT_ADR) 264 #define UNM_HW_CRB_HUB_AGT_ADR_C2C1 ((UNM_HW_H1_CH_HUB_ADR << 7) \ 265 | UNM_HW_C2C1_CRB_AGT_ADR) 266 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX2 ((UNM_HW_H1_CH_HUB_ADR << 7) \ 267 | UNM_HW_RPMX2_CRB_AGT_ADR) 268 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX4 ((UNM_HW_H1_CH_HUB_ADR << 7) \ 269 | UNM_HW_RPMX4_CRB_AGT_ADR) 270 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX7 ((UNM_HW_H1_CH_HUB_ADR << 7) \ 271 | UNM_HW_RPMX7_CRB_AGT_ADR) 272 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX9 ((UNM_HW_H1_CH_HUB_ADR << 7) \ 273 | UNM_HW_RPMX9_CRB_AGT_ADR) 274 #define UNM_HW_CRB_HUB_AGT_ADR_SMB ((UNM_HW_H1_CH_HUB_ADR << 7) \ 275 | UNM_HW_SMB_CRB_AGT_ADR) 276 277 #define UNM_HW_CRB_HUB_AGT_ADR_NIU ((UNM_HW_H2_CH_HUB_ADR << 7) \ 278 | UNM_HW_NIU_CRB_AGT_ADR) 279 #define UNM_HW_CRB_HUB_AGT_ADR_I2C0 ((UNM_HW_H2_CH_HUB_ADR << 7) \ 280 | UNM_HW_I2C0_CRB_AGT_ADR) 281 #define UNM_HW_CRB_HUB_AGT_ADR_I2C1 ((UNM_HW_H2_CH_HUB_ADR << 7) \ 282 | UNM_HW_I2C1_CRB_AGT_ADR) 283 284 #define UNM_HW_CRB_HUB_AGT_ADR_SRE ((UNM_HW_H3_CH_HUB_ADR << 7) \ 285 | UNM_HW_SRE_CRB_AGT_ADR) 286 #define UNM_HW_CRB_HUB_AGT_ADR_EG ((UNM_HW_H3_CH_HUB_ADR << 7) \ 287 | UNM_HW_EG_CRB_AGT_ADR) 288 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX0 ((UNM_HW_H3_CH_HUB_ADR << 7) \ 289 | UNM_HW_RPMX0_CRB_AGT_ADR) 290 #define UNM_HW_CRB_HUB_AGT_ADR_QMN ((UNM_HW_H3_CH_HUB_ADR << 7) \ 291 | UNM_HW_QM_CRB_AGT_ADR) 292 #define UNM_HW_CRB_HUB_AGT_ADR_SQN0 ((UNM_HW_H3_CH_HUB_ADR << 7) \ 293 | UNM_HW_SQG0_CRB_AGT_ADR) 294 #define UNM_HW_CRB_HUB_AGT_ADR_SQN1 ((UNM_HW_H3_CH_HUB_ADR << 7) \ 295 | UNM_HW_SQG1_CRB_AGT_ADR) 296 #define UNM_HW_CRB_HUB_AGT_ADR_SQN2 ((UNM_HW_H3_CH_HUB_ADR << 7) \ 297 | UNM_HW_SQG2_CRB_AGT_ADR) 298 #define UNM_HW_CRB_HUB_AGT_ADR_SQN3 ((UNM_HW_H3_CH_HUB_ADR << 7) \ 299 | UNM_HW_SQG3_CRB_AGT_ADR) 300 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX1 ((UNM_HW_H3_CH_HUB_ADR << 7) \ 301 | UNM_HW_RPMX1_CRB_AGT_ADR) 302 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX5 ((UNM_HW_H3_CH_HUB_ADR << 7) \ 303 | UNM_HW_RPMX5_CRB_AGT_ADR) 304 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX6 ((UNM_HW_H3_CH_HUB_ADR << 7) \ 305 | UNM_HW_RPMX6_CRB_AGT_ADR) 306 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX8 ((UNM_HW_H3_CH_HUB_ADR << 7) \ 307 | UNM_HW_RPMX8_CRB_AGT_ADR) 308 #define UNM_HW_CRB_HUB_AGT_ADR_CAS0 ((UNM_HW_H3_CH_HUB_ADR << 7) \ 309 | UNM_HW_CAS0_CRB_AGT_ADR) 310 #define UNM_HW_CRB_HUB_AGT_ADR_CAS1 ((UNM_HW_H3_CH_HUB_ADR << 7) \ 311 | UNM_HW_CAS1_CRB_AGT_ADR) 312 #define UNM_HW_CRB_HUB_AGT_ADR_CAS2 ((UNM_HW_H3_CH_HUB_ADR << 7) \ 313 | UNM_HW_CAS2_CRB_AGT_ADR) 314 #define UNM_HW_CRB_HUB_AGT_ADR_CAS3 ((UNM_HW_H3_CH_HUB_ADR << 7) \ 315 | UNM_HW_CAS3_CRB_AGT_ADR) 316 317 #define UNM_HW_CRB_HUB_AGT_ADR_PGNI ((UNM_HW_H4_CH_HUB_ADR << 7) \ 318 | UNM_HW_PEGNI_CRB_AGT_ADR) 319 #define UNM_HW_CRB_HUB_AGT_ADR_PGND ((UNM_HW_H4_CH_HUB_ADR << 7) \ 320 | UNM_HW_PEGND_CRB_AGT_ADR) 321 #define UNM_HW_CRB_HUB_AGT_ADR_PGN0 ((UNM_HW_H4_CH_HUB_ADR << 7) \ 322 | UNM_HW_PEGN0_CRB_AGT_ADR) 323 #define UNM_HW_CRB_HUB_AGT_ADR_PGN1 ((UNM_HW_H4_CH_HUB_ADR << 7) \ 324 | UNM_HW_PEGN1_CRB_AGT_ADR) 325 #define UNM_HW_CRB_HUB_AGT_ADR_PGN2 ((UNM_HW_H4_CH_HUB_ADR << 7) \ 326 | UNM_HW_PEGN2_CRB_AGT_ADR) 327 #define UNM_HW_CRB_HUB_AGT_ADR_PGN3 ((UNM_HW_H4_CH_HUB_ADR << 7) \ 328 | UNM_HW_PEGN3_CRB_AGT_ADR) 329 #define UNM_HW_CRB_HUB_AGT_ADR_PGN4 ((UNM_HW_H4_CH_HUB_ADR << 7) \ 330 | UNM_HW_PEGN4_CRB_AGT_ADR) 331 332 #define UNM_HW_CRB_HUB_AGT_ADR_PGNC ((UNM_HW_H4_CH_HUB_ADR << 7) \ 333 | UNM_HW_PEGNC_CRB_AGT_ADR) 334 #define UNM_HW_CRB_HUB_AGT_ADR_PGR0 ((UNM_HW_H4_CH_HUB_ADR << 7) \ 335 | UNM_HW_PEGR0_CRB_AGT_ADR) 336 #define UNM_HW_CRB_HUB_AGT_ADR_PGR1 ((UNM_HW_H4_CH_HUB_ADR << 7) \ 337 | UNM_HW_PEGR1_CRB_AGT_ADR) 338 #define UNM_HW_CRB_HUB_AGT_ADR_PGR2 ((UNM_HW_H4_CH_HUB_ADR << 7) \ 339 | UNM_HW_PEGR2_CRB_AGT_ADR) 340 #define UNM_HW_CRB_HUB_AGT_ADR_PGR3 ((UNM_HW_H4_CH_HUB_ADR << 7) \ 341 | UNM_HW_PEGR3_CRB_AGT_ADR) 342 343 #define UNM_HW_CRB_HUB_AGT_ADR_PGSI ((UNM_HW_H5_CH_HUB_ADR << 7) \ 344 | UNM_HW_PEGSI_CRB_AGT_ADR) 345 #define UNM_HW_CRB_HUB_AGT_ADR_PGSD ((UNM_HW_H5_CH_HUB_ADR << 7) \ 346 | UNM_HW_PEGSD_CRB_AGT_ADR) 347 #define UNM_HW_CRB_HUB_AGT_ADR_PGS0 ((UNM_HW_H5_CH_HUB_ADR << 7) \ 348 | UNM_HW_PEGS0_CRB_AGT_ADR) 349 #define UNM_HW_CRB_HUB_AGT_ADR_PGS1 ((UNM_HW_H5_CH_HUB_ADR << 7) \ 350 | UNM_HW_PEGS1_CRB_AGT_ADR) 351 #define UNM_HW_CRB_HUB_AGT_ADR_PGS2 ((UNM_HW_H5_CH_HUB_ADR << 7) \ 352 | UNM_HW_PEGS2_CRB_AGT_ADR) 353 #define UNM_HW_CRB_HUB_AGT_ADR_PGS3 ((UNM_HW_H5_CH_HUB_ADR << 7) \ 354 | UNM_HW_PEGS3_CRB_AGT_ADR) 355 #define UNM_HW_CRB_HUB_AGT_ADR_PGSC ((UNM_HW_H5_CH_HUB_ADR << 7) \ 356 | UNM_HW_PEGSC_CRB_AGT_ADR) 357 358 #define UNM_HW_CRB_HUB_AGT_ADR_CAM ((UNM_HW_H6_CH_HUB_ADR << 7) \ 359 | UNM_HW_NCM_CRB_AGT_ADR) 360 #define UNM_HW_CRB_HUB_AGT_ADR_TIMR ((UNM_HW_H6_CH_HUB_ADR << 7) \ 361 | UNM_HW_TMR_CRB_AGT_ADR) 362 #define UNM_HW_CRB_HUB_AGT_ADR_XDMA ((UNM_HW_H6_CH_HUB_ADR << 7) \ 363 | UNM_HW_XDMA_CRB_AGT_ADR) 364 #define UNM_HW_CRB_HUB_AGT_ADR_SN ((UNM_HW_H6_CH_HUB_ADR << 7) \ 365 | UNM_HW_SN_CRB_AGT_ADR) 366 #define UNM_HW_CRB_HUB_AGT_ADR_I2Q ((UNM_HW_H6_CH_HUB_ADR << 7) \ 367 | UNM_HW_I2Q_CRB_AGT_ADR) 368 #define UNM_HW_CRB_HUB_AGT_ADR_ROMUSB ((UNM_HW_H6_CH_HUB_ADR << 7) \ 369 | UNM_HW_ROMUSB_CRB_AGT_ADR) 370 #define UNM_HW_CRB_HUB_AGT_ADR_OCM0 ((UNM_HW_H6_CH_HUB_ADR << 7) \ 371 | UNM_HW_OCM0_CRB_AGT_ADR) 372 #define UNM_HW_CRB_HUB_AGT_ADR_OCM1 ((UNM_HW_H6_CH_HUB_ADR << 7) \ 373 | UNM_HW_OCM1_CRB_AGT_ADR) 374 #define UNM_HW_CRB_HUB_AGT_ADR_LPC ((UNM_HW_H6_CH_HUB_ADR << 7) \ 375 | UNM_HW_LPC_CRB_AGT_ADR) 376 377 /* 378 * ROM USB CRB space is divided into 4 regions depending on decode of 379 * address bits [19:16] 380 */ 381 #define ROMUSB_GLB (UNM_CRB_ROMUSB + 0x00000) 382 #define ROMUSB_ROM (UNM_CRB_ROMUSB + 0x10000) 383 #define ROMUSB_USB (UNM_CRB_ROMUSB + 0x20000) 384 #define ROMUSB_DIRECT_ROM (UNM_CRB_ROMUSB + 0x30000) 385 #define ROMUSB_TAP (UNM_CRB_ROMUSB + 0x40000) 386 387 /* ROMUSB GLB register definitions */ 388 #define UNM_ROMUSB_GLB_CONTROL (ROMUSB_GLB + 0x0000) 389 #define UNM_ROMUSB_GLB_STATUS (ROMUSB_GLB + 0x0004) 390 #define UNM_ROMUSB_GLB_SW_RESET (ROMUSB_GLB + 0x0008) 391 #define UNM_ROMUSB_GLB_PAD_GPIO_I (ROMUSB_GLB + 0x000c) 392 #define UNM_ROMUSB_GLB_RNG_PLL_CTL (ROMUSB_GLB + 0x0010) 393 #define UNM_ROMUSB_GLB_TEST_MUX_O (ROMUSB_GLB + 0x0014) 394 #define UNM_ROMUSB_GLB_PLL0_CTRL (ROMUSB_GLB + 0x0018) 395 #define UNM_ROMUSB_GLB_PLL1_CTRL (ROMUSB_GLB + 0x001c) 396 #define UNM_ROMUSB_GLB_PLL2_CTRL (ROMUSB_GLB + 0x0020) 397 #define UNM_ROMUSB_GLB_PLL3_CTRL (ROMUSB_GLB + 0x0024) 398 #define UNM_ROMUSB_GLB_PLL_LOCK (ROMUSB_GLB + 0x0028) 399 #define UNM_ROMUSB_GLB_EXTERN_INT (ROMUSB_GLB + 0x002c) 400 #define UNM_ROMUSB_GLB_PH_RST (ROMUSB_GLB + 0x0030) 401 #define UNM_ROMUSB_GLB_PS_RST (ROMUSB_GLB + 0x0034) 402 #define UNM_ROMUSB_GLB_CAS_RST (ROMUSB_GLB + 0x0038) 403 #define UNM_ROMUSB_GLB_MIU_RST (ROMUSB_GLB + 0x003c) 404 #define UNM_ROMUSB_GLB_CRB_RST (ROMUSB_GLB + 0x0040) 405 #define UNM_ROMUSB_GLB_TEST_MUX_SEL (ROMUSB_GLB + 0x0044) 406 #define UNM_ROMUSB_GLB_MN_COM_A2T (ROMUSB_GLB + 0x0050) 407 #define UNM_ROMUSB_GLB_REV_ID (ROMUSB_GLB + 0x0054) 408 #define UNM_ROMUSB_GLB_PEGTUNE_DONE (ROMUSB_GLB + 0x005c) 409 #define UNM_ROMUSB_GLB_VENDOR_DEV_ID (ROMUSB_GLB + 0x0058) 410 #define UNM_ROMUSB_GLB_CHIP_CLK_CTRL (ROMUSB_GLB + 0x00a8) 411 412 #define UNM_ROMUSB_GPIO(n) ((n) <= 15 ? (ROMUSB_GLB + 0x60 + (4 * (n))): \ 413 ((n) <= 18)?(ROMUSB_GLB + 0x70 + (4 * (n))): \ 414 (ROMUSB_GLB + 0x70 + (4 * (19)))) 415 416 #define UNM_ROMUSB_ROM_CONTROL (ROMUSB_ROM + 0x0000) 417 #define UNM_ROMUSB_ROM_INSTR_OPCODE (ROMUSB_ROM + 0x0004) 418 #define UNM_ROMUSB_ROM_ADDRESS (ROMUSB_ROM + 0x0008) 419 #define UNM_ROMUSB_ROM_WDATA (ROMUSB_ROM + 0x000c) 420 #define UNM_ROMUSB_ROM_ABYTE_CNT (ROMUSB_ROM + 0x0010) 421 #define UNM_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014) 422 #define UNM_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018) 423 #define UNM_ROMUSB_ROM_AGT_TAG (ROMUSB_ROM + 0x001c) 424 #define UNM_ROMUSB_ROM_TIME_PARM (ROMUSB_ROM + 0x0020) 425 #define UNM_ROMUSB_ROM_CLK_DIV (ROMUSB_ROM + 0x0024) 426 #define UNM_ROMUSB_ROM_MISS_INSTR (ROMUSB_ROM + 0x0028) 427 428 /* Lock IDs for ROM lock */ 429 #define ROM_LOCK_DRIVER 0x0d417340 430 431 /* Lock IDs for PHY lock */ 432 #define PHY_LOCK_DRIVER 0x44524956 433 434 #define UNM_PCI_CRB_WINDOWSIZE 0x00100000 /* all are 1MB windows */ 435 #define UNM_PCI_CRB_WINDOW(A) (UNM_PCI_CRBSPACE + (A)*UNM_PCI_CRB_WINDOWSIZE) 436 #define UNM_CRB_C2C_0 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_C2C0) 437 #define UNM_CRB_C2C_1 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_C2C1) 438 #define UNM_CRB_C2C_2 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_C2C2) 439 #define UNM_CRB_CAM UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_CAM) 440 #define UNM_CRB_CASPER UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_CAS) 441 #define UNM_CRB_CASPER_0 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_CAS0) 442 #define UNM_CRB_CASPER_1 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_CAS1) 443 #define UNM_CRB_CASPER_2 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_CAS2) 444 #define UNM_CRB_DDR_MD UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_MS) 445 #define UNM_CRB_DDR_NET UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_MN) 446 #define UNM_CRB_EPG UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_EG) 447 #define UNM_CRB_I2Q UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_I2Q) 448 #define UNM_CRB_NIU UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_NIU) 449 /* HACK upon HACK upon HACK (for PCIE builds) */ 450 #define UNM_CRB_PCIX_HOST UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PH) 451 #define UNM_CRB_PCIX_HOST2 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PH2) 452 #define UNM_CRB_PCIX_MD UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PS) 453 #define UNM_CRB_PCIE UNM_CRB_PCIX_MD 454 // window 1 pcie slot 455 #define UNM_CRB_PCIE2 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PS2) 456 457 #define UNM_CRB_PEG_MD_0 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGS0) 458 #define UNM_CRB_PEG_MD_1 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGS1) 459 #define UNM_CRB_PEG_MD_2 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGS2) 460 #define UNM_CRB_PEG_MD_3 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGS3) 461 #define UNM_CRB_PEG_MD_D UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGSD) 462 #define UNM_CRB_PEG_MD_I UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGSI) 463 #define UNM_CRB_PEG_NET_0 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGN0) 464 #define UNM_CRB_PEG_NET_1 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGN1) 465 #define UNM_CRB_PEG_NET_2 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGN2) 466 #define UNM_CRB_PEG_NET_3 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGN3) 467 #define UNM_CRB_PEG_NET_D UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGND) 468 #define UNM_CRB_PEG_NET_I UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGNI) 469 #define UNM_CRB_PQM_MD UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_QMS) 470 #define UNM_CRB_PQM_NET UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_QMN) 471 #define UNM_CRB_QDR_MD UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SS) 472 #define UNM_CRB_QDR_NET UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SN) 473 #define UNM_CRB_ROMUSB UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_ROMUSB) 474 #define UNM_CRB_RPMX_0 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_RPMX0) 475 #define UNM_CRB_RPMX_1 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_RPMX1) 476 #define UNM_CRB_RPMX_2 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_RPMX2) 477 #define UNM_CRB_RPMX_3 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_RPMX3) 478 #define UNM_CRB_RPMX_4 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_RPMX4) 479 #define UNM_CRB_RPMX_5 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_RPMX5) 480 #define UNM_CRB_RPMX_6 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_RPMX6) 481 #define UNM_CRB_RPMX_7 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_RPMX7) 482 #define UNM_CRB_SQM_MD_0 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SQS0) 483 #define UNM_CRB_SQM_MD_1 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SQS1) 484 #define UNM_CRB_SQM_MD_2 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SQS2) 485 #define UNM_CRB_SQM_MD_3 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SQS3) 486 #define UNM_CRB_SQM_NET_0 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SQN0) 487 #define UNM_CRB_SQM_NET_1 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SQN1) 488 #define UNM_CRB_SQM_NET_2 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SQN2) 489 #define UNM_CRB_SQM_NET_3 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SQN3) 490 #define UNM_CRB_SRE UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SRE) 491 #define UNM_CRB_TIMER UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_TIMR) 492 #define UNM_CRB_XDMA UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_XDMA) 493 #define UNM_CRB_I2C0 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_I2C0) 494 #define UNM_CRB_I2C1 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_I2C1) 495 #define UNM_CRB_OCM0 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_OCM0) 496 #define UNM_CRB_SMB UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SMB) 497 498 #define UNM_CRB_MAX UNM_PCI_CRB_WINDOW(64) 499 500 /* 501 * ====================== BASE ADDRESSES ON-CHIP ====================== 502 * Base addresses of major components on-chip. 503 * ====================== BASE ADDRESSES ON-CHIP ====================== 504 */ 505 #define UNM_ADDR_DDR_NET (0x0000000000000000ULL) 506 #define UNM_ADDR_DDR_NET_MAX (0x000000000fffffffULL) 507 508 /* 509 * Imbus address bit used to indicate a host address. This bit is 510 * eliminated by the pcie bar and bar select before presentation 511 * over pcie. 512 */ 513 /* host memory via IMBUS */ 514 #define NX_P2_ADDR_PCIE (0x0000000800000000ULL) 515 #define NX_P3_ADDR_PCIE (0x0000008000000000ULL) 516 517 #define UNM_ADDR_PCIE_MAX (0x0000000FFFFFFFFFULL) 518 #define UNM_ADDR_OCM0 (0x0000000200000000ULL) 519 #define UNM_ADDR_OCM0_MAX (0x00000002000fffffULL) 520 #define UNM_ADDR_OCM1 (0x0000000200400000ULL) 521 #define UNM_ADDR_OCM1_MAX (0x00000002004fffffULL) 522 #define UNM_ADDR_QDR_NET (0x0000000300000000ULL) 523 524 #define NX_P2_ADDR_QDR_NET_MAX (0x00000003001fffffULL) 525 #define NX_P3_ADDR_QDR_NET_MAX (0x0000000303ffffffULL) 526 /* 527 * The ifdef at the bottom should go. All drivers should start using the 528 * above 2 defines. 529 */ 530 #ifdef P3 531 #define UNM_ADDR_QDR_NET_MAX NX_P3_ADDR_QDR_NET_MAX 532 #else 533 #define UNM_ADDR_QDR_NET_MAX NX_P2_ADDR_QDR_NET_MAX 534 #endif 535 536 #define D3_CRB_REG_FUN0 (UNM_PCIX_PS_REG(0x0084)) 537 #define D3_CRB_REG_FUN1 (UNM_PCIX_PS_REG(0x1084)) 538 #define D3_CRB_REG_FUN2 (UNM_PCIX_PS_REG(0x2084)) 539 #define D3_CRB_REG_FUN3 (UNM_PCIX_PS_REG(0x3084)) 540 541 542 #define ISR_I2Q_CLR_PCI_LO (UNM_PCIX_PS_REG(UNM_I2Q_CLR_PCI_LO)) 543 #define ISR_I2Q_CLR_PCI_HI (UNM_PCIX_PS_REG(UNM_I2Q_CLR_PCI_HI)) 544 #define UNM_PCI_ARCH_CRB_BASE (UNM_PCI_DIRECT_CRB) 545 546 /* we're mapping 128MB of mem on the PCI bus */ 547 #define UNM_PCI_MAPSIZE 128 548 #define UNM_PCI_DDR_NET (unsigned long)0x00000000 549 #define UNM_PCI_DDR_NET_MAX (unsigned long)0x01ffffff 550 #define UNM_PCI_DDR_MD (unsigned long)0x02000000 551 #define UNM_PCI_DDR_MD_MAX (unsigned long)0x03ffffff 552 #define UNM_PCI_QDR_NET (unsigned long)0x04000000 553 #define UNM_PCI_QDR_NET_MAX (unsigned long)0x043fffff 554 #define UNM_PCI_DIRECT_CRB (unsigned long)0x04400000 555 #define UNM_PCI_DIRECT_CRB_MAX (unsigned long)0x047fffff 556 #define UNM_PCI_CAMQM (unsigned long)0x04800000 557 #define UNM_PCI_CAMQM_MAX (unsigned long)0x04ffffff 558 #define UNM_PCI_OCM0 (unsigned long)0x05000000 559 #define UNM_PCI_OCM0_MAX (unsigned long)0x050fffff 560 #define UNM_PCI_OCM1 (unsigned long)0x05100000 561 #define UNM_PCI_OCM1_MAX (unsigned long)0x051fffff 562 #define UNM_PCI_CRBSPACE (unsigned long)0x06000000 563 #define UNM_PCI_CRBSPACE_MAX (unsigned long)0x07ffffff 564 #define UNM_PCI_128MB_SIZE (unsigned long)0x08000000 565 #define UNM_PCI_32MB_SIZE (unsigned long)0x02000000 566 #define UNM_PCI_2MB_SIZE (unsigned long)0x00200000 567 568 /* 569 * The basic unit of access when reading/writing control registers. 570 */ 571 typedef long native_t; /* most efficient integer on h/w */ 572 typedef __uint64_t unm_dataword_t; /* single word in data space */ 573 typedef __uint64_t unm64ptr_t; /* a pointer that occupies 64 bits */ 574 #define UNM64PTR(P) ((unm64ptr_t)((native_t)(P))) /* convert for us */ 575 576 typedef __uint32_t unm_crbword_t; /* single word in CRB space */ 577 578 /* 579 * Definitions relating to access/control of the Network Interface Unit 580 * h/w block. 581 */ 582 /* 583 * Configuration registers. 584 */ 585 #define UNM_NIU_MODE (UNM_CRB_NIU + 0x00000) 586 587 #define UNM_NIU_XG_SINGLE_TERM (UNM_CRB_NIU + 0x00004) 588 #define UNM_NIU_XG_DRIVE_HI (UNM_CRB_NIU + 0x00008) 589 #define UNM_NIU_XG_DRIVE_LO (UNM_CRB_NIU + 0x0000c) 590 #define UNM_NIU_XG_DTX (UNM_CRB_NIU + 0x00010) 591 #define UNM_NIU_XG_DEQ (UNM_CRB_NIU + 0x00014) 592 #define UNM_NIU_XG_WORD_ALIGN (UNM_CRB_NIU + 0x00018) 593 #define UNM_NIU_XG_RESET (UNM_CRB_NIU + 0x0001c) 594 #define UNM_NIU_XG_POWER_DOWN (UNM_CRB_NIU + 0x00020) 595 #define UNM_NIU_XG_RESET_PLL (UNM_CRB_NIU + 0x00024) 596 #define UNM_NIU_XG_SERDES_LOOPBACK (UNM_CRB_NIU + 0x00028) 597 #define UNM_NIU_XG_DO_BYTE_ALIGN (UNM_CRB_NIU + 0x0002c) 598 #define UNM_NIU_XG_TX_ENABLE (UNM_CRB_NIU + 0x00030) 599 #define UNM_NIU_XG_RX_ENABLE (UNM_CRB_NIU + 0x00034) 600 #define UNM_NIU_XG_STATUS (UNM_CRB_NIU + 0x00038) 601 #define UNM_NIU_XG_PAUSE_THRESHOLD (UNM_CRB_NIU + 0x0003c) 602 #define UNM_NIU_INT_MASK (UNM_CRB_NIU + 0x00040) 603 #define UNM_NIU_ACTIVE_INT (UNM_CRB_NIU + 0x00044) 604 #define UNM_NIU_MASKABLE_INT (UNM_CRB_NIU + 0x00048) 605 #define UNM_NIU_TEST_MUX_CTL (UNM_CRB_NIU + 0x00094) 606 #define UNM_NIU_XG_PAUSE_CTL (UNM_CRB_NIU + 0x00098) 607 #define UNM_NIU_XG_PAUSE_LEVEL (UNM_CRB_NIU + 0x000dc) 608 #define UNM_NIU_XG_SEL (UNM_CRB_NIU + 0x00128) 609 #define UNM_NIU_GB_PAUSE_CTL (UNM_CRB_NIU + 0x0030c) 610 #define UNM_NIU_FULL_LEVEL_XG (UNM_CRB_NIU + 0x00450) 611 612 613 #define UNM_NIU_XG1_RESET (UNM_CRB_NIU + 0x0011c) 614 #define UNM_NIU_XG1_POWER_DOWN (UNM_CRB_NIU + 0x00120) 615 #define UNM_NIU_XG1_RESET_PLL (UNM_CRB_NIU + 0x00124) 616 617 #define UNM_NIU_STRAP_VALUE_SAVE_HIGHER (UNM_CRB_NIU + 0x0004c) 618 619 #define UNM_NIU_GB_SERDES_RESET (UNM_CRB_NIU + 0x00050) 620 #define UNM_NIU_GB0_GMII_MODE (UNM_CRB_NIU + 0x00054) 621 #define UNM_NIU_GB0_MII_MODE (UNM_CRB_NIU + 0x00058) 622 #define UNM_NIU_GB1_GMII_MODE (UNM_CRB_NIU + 0x0005c) 623 #define UNM_NIU_GB1_MII_MODE (UNM_CRB_NIU + 0x00060) 624 #define UNM_NIU_GB2_GMII_MODE (UNM_CRB_NIU + 0x00064) 625 #define UNM_NIU_GB2_MII_MODE (UNM_CRB_NIU + 0x00068) 626 #define UNM_NIU_GB3_GMII_MODE (UNM_CRB_NIU + 0x0006c) 627 #define UNM_NIU_GB3_MII_MODE (UNM_CRB_NIU + 0x00070) 628 #define UNM_NIU_REMOTE_LOOPBACK (UNM_CRB_NIU + 0x00074) 629 #define UNM_NIU_GB0_HALF_DUPLEX (UNM_CRB_NIU + 0x00078) 630 #define UNM_NIU_GB1_HALF_DUPLEX (UNM_CRB_NIU + 0x0007c) 631 #define UNM_NIU_GB2_HALF_DUPLEX (UNM_CRB_NIU + 0x00080) 632 #define UNM_NIU_GB3_HALF_DUPLEX (UNM_CRB_NIU + 0x00084) 633 #define UNM_NIU_RESET_SYS_FIFOS (UNM_CRB_NIU + 0x00088) 634 #define UNM_NIU_GB_CRC_DROP (UNM_CRB_NIU + 0x0008c) 635 #define UNM_NIU_GB_DROP_WRONGADDR (UNM_CRB_NIU + 0x00090) 636 #define UNM_NIU_TEST_MUX_CTL (UNM_CRB_NIU + 0x00094) 637 #define UNM_NIU_XG_PAUSE_CTL (UNM_CRB_NIU + 0x00098) 638 #define UNM_NIU_GB0_PAUSE_LEVEL (UNM_CRB_NIU + 0x000cc) 639 #define UNM_NIU_GB1_PAUSE_LEVEL (UNM_CRB_NIU + 0x000d0) 640 #define UNM_NIU_GB2_PAUSE_LEVEL (UNM_CRB_NIU + 0x000d4) 641 #define UNM_NIU_GB3_PAUSE_LEVEL (UNM_CRB_NIU + 0x000d8) 642 #define UNM_NIU_XG_PAUSE_LEVEL (UNM_CRB_NIU + 0x000dc) 643 #define UNM_NIU_FRAME_COUNT_SELECT (UNM_CRB_NIU + 0x000ac) 644 #define UNM_NIU_FRAME_COUNT (UNM_CRB_NIU + 0x000b0) 645 #define UNM_NIU_XG_SE (UNM_CRB_NIU + 0x00128) 646 #define UNM_NIU_FULL_LEVEL_XG (UNM_CRB_NIU + 0x00450) 647 648 #define UNM_NIU_FC_RX_STATUS(I) (UNM_CRB_NIU + 0x10000 + (I)*0x10000) 649 #define UNM_NIU_FC_RX_COMMA_DETECT(I) (UNM_CRB_NIU + 0x10004 + (I)*0x10000) 650 #define UNM_NIU_FC_LASER_UNSAFE(I) (UNM_CRB_NIU + 0x10008 + (I)*0x10000) 651 #define UNM_NIU_FC_TX_CONTROL(I) (UNM_CRB_NIU + 0x1000c + (I)*0x10000) 652 #define UNM_NIU_FC_ON_OFFLINE_CTL(I) (UNM_CRB_NIU + 0x10010 + (I)*0x10000) 653 #define UNM_NIU_FC_PORT_ACTIVE_STAT(I) (UNM_CRB_NIU + 0x10014 + (I)*0x10000) 654 #define UNM_NIU_FC_PORT_INACTIVE_STAT(I)(UNM_CRB_NIU + 0x10018 + (I)*0x10000) 655 #define UNM_NIU_FC_LINK_FAILURE_CNT(I) (UNM_CRB_NIU + 0x1001c + (I)*0x10000) 656 #define UNM_NIU_FC_LOSS_SYNC_CNT(I) (UNM_CRB_NIU + 0x10020 + (I)*0x10000) 657 #define UNM_NIU_FC_LOSS_SIGNAL_CNT(I) (UNM_CRB_NIU + 0x10024 + (I)*0x10000) 658 #define UNM_NIU_FC_PRIM_SEQ_ERR_CNT(I) (UNM_CRB_NIU + 0x10028 + (I)*0x10000) 659 #define UNM_NIU_FC_INVLD_TX_WORD_CNT(I) (UNM_CRB_NIU + 0x1002c + (I)*0x10000) 660 #define UNM_NIU_FC_INVLD_CRC_CNT(I) (UNM_CRB_NIU + 0x10030 + (I)*0x10000) 661 #define UNM_NIU_FC_RX_CELL_CNT(I) (UNM_CRB_NIU + 0x10034 + (I)*0x10000) 662 #define UNM_NIU_FC_TX_CELL_CNT(I) (UNM_CRB_NIU + 0x10038 + (I)*0x10000) 663 #define UNM_NIU_FC_B2B_CREDIT(I) (UNM_CRB_NIU + 0x1003c + (I)*0x10000) 664 #define UNM_NIU_FC_LOGIN_DONE(I) (UNM_CRB_NIU + 0x10040 + (I)*0x10000) 665 #define UNM_NIU_FC_OPERATING_SPEED(I) (UNM_CRB_NIU + 0x10044 + (I)*0x10000) 666 667 #define UNM_NIU_GB_MAC_CONFIG_0(I) (UNM_CRB_NIU + 0x30000 + (I)*0x10000) 668 #define UNM_NIU_GB_MAC_CONFIG_1(I) (UNM_CRB_NIU + 0x30004 + (I)*0x10000) 669 #define UNM_NIU_GB_MAC_IPG_IFG(I) (UNM_CRB_NIU + 0x30008 + (I)*0x10000) 670 #define UNM_NIU_GB_HALF_DUPLEX_CTRL(I) (UNM_CRB_NIU + 0x3000c + (I)*0x10000) 671 #define UNM_NIU_GB_MAX_FRAME_SIZE(I) (UNM_CRB_NIU + 0x30010 + (I)*0x10000) 672 #define UNM_NIU_GB_TEST_REG(I) (UNM_CRB_NIU + 0x3001c + (I)*0x10000) 673 #define UNM_NIU_GB_MII_MGMT_CONFIG(I) (UNM_CRB_NIU + 0x30020 + (I)*0x10000) 674 #define UNM_NIU_GB_MII_MGMT_COMMAND(I) (UNM_CRB_NIU + 0x30024 + (I)*0x10000) 675 #define UNM_NIU_GB_MII_MGMT_ADDR(I) (UNM_CRB_NIU + 0x30028 + (I)*0x10000) 676 #define UNM_NIU_GB_MII_MGMT_CTRL(I) (UNM_CRB_NIU + 0x3002c + (I)*0x10000) 677 #define UNM_NIU_GB_MII_MGMT_STATUS(I) (UNM_CRB_NIU + 0x30030 + (I)*0x10000) 678 #define UNM_NIU_GB_MII_MGMT_INDICATE(I) (UNM_CRB_NIU + 0x30034 + (I)*0x10000) 679 #define UNM_NIU_GB_INTERFACE_CTRL(I) (UNM_CRB_NIU + 0x30038 + (I)*0x10000) 680 #define UNM_NIU_GB_INTERFACE_STATUS(I) (UNM_CRB_NIU + 0x3003c + (I)*0x10000) 681 #define UNM_NIU_GB_STATION_ADDR_0(I) (UNM_CRB_NIU + 0x30040 + (I)*0x10000) 682 #define UNM_NIU_GB_STATION_ADDR_1(I) (UNM_CRB_NIU + 0x30044 + (I)*0x10000) 683 684 #define UNM_NIU_XGE_CONFIG_0 (UNM_CRB_NIU + 0x70000) 685 #define UNM_NIU_XGE_CONFIG_1 (UNM_CRB_NIU + 0x70004) 686 #define UNM_NIU_XGE_IPG (UNM_CRB_NIU + 0x70008) 687 #define UNM_NIU_XGE_STATION_ADDR_0_HI (UNM_CRB_NIU + 0x7000c) 688 #define UNM_NIU_XGE_STATION_ADDR_0_1 (UNM_CRB_NIU + 0x70010) 689 #define UNM_NIU_XGE_STATION_ADDR_1_LO (UNM_CRB_NIU + 0x70014) 690 #define UNM_NIU_XGE_STATUS (UNM_CRB_NIU + 0x70018) 691 #define UNM_NIU_XGE_MAX_FRAME_SIZE (UNM_CRB_NIU + 0x7001c) 692 #define UNM_NIU_XGE_PAUSE_FRAME_VALUE (UNM_CRB_NIU + 0x70020) 693 #define UNM_NIU_XGE_TX_BYTE_CNT (UNM_CRB_NIU + 0x70024) 694 #define UNM_NIU_XGE_TX_FRAME_CNT (UNM_CRB_NIU + 0x70028) 695 #define UNM_NIU_XGE_RX_BYTE_CNT (UNM_CRB_NIU + 0x7002c) 696 #define UNM_NIU_XGE_RX_FRAME_CNT (UNM_CRB_NIU + 0x70030) 697 #define UNM_NIU_XGE_AGGR_ERROR_CNT (UNM_CRB_NIU + 0x70034) 698 #define UNM_NIU_XGE_MULTICAST_FRAME_CNT (UNM_CRB_NIU + 0x70038) 699 #define UNM_NIU_XGE_UNICAST_FRAME_CNT (UNM_CRB_NIU + 0x7003c) 700 #define UNM_NIU_XGE_CRC_ERROR_CNT (UNM_CRB_NIU + 0x70040) 701 #define UNM_NIU_XGE_OVERSIZE_FRAME_ERR (UNM_CRB_NIU + 0x70044) 702 #define UNM_NIU_XGE_UNDERSIZE_FRAME_ERR (UNM_CRB_NIU + 0x70048) 703 #define UNM_NIU_XGE_LOCAL_ERROR_CNT (UNM_CRB_NIU + 0x7004c) 704 #define UNM_NIU_XGE_REMOTE_ERROR_CNT (UNM_CRB_NIU + 0x70050) 705 #define UNM_NIU_XGE_CONTROL_CHAR_CNT (UNM_CRB_NIU + 0x70054) 706 #define UNM_NIU_XGE_PAUSE_FRAME_CNT (UNM_CRB_NIU + 0x70058) 707 #define UNM_NIU_XG1_CONFIG_0 (UNM_CRB_NIU + 0x80000) 708 #define UNM_NIU_XG1_CONFIG_1 (UNM_CRB_NIU + 0x80004) 709 #define UNM_NIU_XG1_IPG (UNM_CRB_NIU + 0x80008) 710 #define UNM_NIU_XG1_STATION_ADDR_0_HI (UNM_CRB_NIU + 0x8000c) 711 #define UNM_NIU_XG1_STATION_ADDR_0_1 (UNM_CRB_NIU + 0x80010) 712 #define UNM_NIU_XG1_STATION_ADDR_1_LO (UNM_CRB_NIU + 0x80014) 713 #define UNM_NIU_XG1_STATUS (UNM_CRB_NIU + 0x80018) 714 #define UNM_NIU_XG1_MAX_FRAME_SIZE (UNM_CRB_NIU + 0x8001c) 715 #define UNM_NIU_XG1_PAUSE_FRAME_VALUE (UNM_CRB_NIU + 0x80020) 716 #define UNM_NIU_XG1_TX_BYTE_CNT (UNM_CRB_NIU + 0x80024) 717 #define UNM_NIU_XG1_TX_FRAME_CNT (UNM_CRB_NIU + 0x80028) 718 #define UNM_NIU_XG1_RX_BYTE_CNT (UNM_CRB_NIU + 0x8002c) 719 #define UNM_NIU_XG1_RX_FRAME_CNT (UNM_CRB_NIU + 0x80030) 720 #define UNM_NIU_XG1_AGGR_ERROR_CNT (UNM_CRB_NIU + 0x80034) 721 #define UNM_NIU_XG1_MULTICAST_FRAME_CNT (UNM_CRB_NIU + 0x80038) 722 #define UNM_NIU_XG1_UNICAST_FRAME_CNT (UNM_CRB_NIU + 0x8003c) 723 #define UNM_NIU_XG1_CRC_ERROR_CNT (UNM_CRB_NIU + 0x80040) 724 #define UNM_NIU_XG1_OVERSIZE_FRAME_ERR (UNM_CRB_NIU + 0x80044) 725 #define UNM_NIU_XG1_UNDERSIZE_FRAME_ERR (UNM_CRB_NIU + 0x80048) 726 #define UNM_NIU_XG1_LOCAL_ERROR_CNT (UNM_CRB_NIU + 0x8004c) 727 #define UNM_NIU_XG1_REMOTE_ERROR_CNT (UNM_CRB_NIU + 0x80050) 728 #define UNM_NIU_XG1_CONTROL_CHAR_CNT (UNM_CRB_NIU + 0x80054) 729 #define UNM_NIU_XG1_PAUSE_FRAME_CNT (UNM_CRB_NIU + 0x80058) 730 731 #define UNM_TIMER_GT_TICKCTL (UNM_CRB_TIMER + 0x00200) 732 #define UNM_TIMER_GLOBAL_TIMESTAMP_LO (UNM_CRB_TIMER + 0x00220) 733 #define UNM_TIMER_TIMESTAMP (UNM_CRB_TIMER + 0x00208) 734 735 #define UNM_PEXQ_REQ_HDR_LO (UNM_CRB_XDMA + 0x00110) 736 #define UNM_PEXQ_REQ_HDR_HI (UNM_CRB_XDMA + 0x00114) 737 738 /* P3 802.3ap */ 739 #define UNM_NIU_AP_MAC_CONFIG_0(I) (UNM_CRB_NIU + 0xa0000 + (I)*0x10000) 740 #define UNM_NIU_AP_MAC_CONFIG_1(I) (UNM_CRB_NIU + 0xa0004 + (I)*0x10000) 741 #define UNM_NIU_AP_MAC_IPG_IFG(I) (UNM_CRB_NIU + 0xa0008 + (I)*0x10000) 742 #define UNM_NIU_AP_HALF_DUPLEX_CTRL(I) (UNM_CRB_NIU + 0xa000c + (I)*0x10000) 743 #define UNM_NIU_AP_MAX_FRAME_SIZE(I) (UNM_CRB_NIU + 0xa0010 + (I)*0x10000) 744 #define UNM_NIU_AP_TEST_REG(I) (UNM_CRB_NIU + 0xa001c + (I)*0x10000) 745 #define UNM_NIU_AP_MII_MGMT_CONFIG(I) (UNM_CRB_NIU + 0xa0020 + (I)*0x10000) 746 #define UNM_NIU_AP_MII_MGMT_COMMAND(I) (UNM_CRB_NIU + 0xa0024 + (I)*0x10000) 747 #define UNM_NIU_AP_MII_MGMT_ADDR(I) (UNM_CRB_NIU + 0xa0028 + (I)*0x10000) 748 #define UNM_NIU_AP_MII_MGMT_CTRL(I) (UNM_CRB_NIU + 0xa002c + (I)*0x10000) 749 #define UNM_NIU_AP_MII_MGMT_STATUS(I) (UNM_CRB_NIU + 0xa0030 + (I)*0x10000) 750 #define UNM_NIU_AP_MII_MGMT_INDICATE(I) (UNM_CRB_NIU + 0xa0034 + (I)*0x10000) 751 #define UNM_NIU_AP_INTERFACE_CTRL(I) (UNM_CRB_NIU + 0xa0038 + (I)*0x10000) 752 #define UNM_NIU_AP_INTERFACE_STATUS(I) (UNM_CRB_NIU + 0xa003c + (I)*0x10000) 753 #define UNM_NIU_AP_STATION_ADDR_0(I) (UNM_CRB_NIU + 0xa0040 + (I)*0x10000) 754 #define UNM_NIU_AP_STATION_ADDR_1(I) (UNM_CRB_NIU + 0xa0044 + (I)*0x10000) 755 756 /* 757 * Register offsets for MN 758 */ 759 #define MIU_CONTROL (0x000) 760 #define MIU_TAG (0x004) 761 #define MIU_TEST_AGT_CTRL (0x090) 762 #define MIU_TEST_AGT_ADDR_LO (0x094) 763 #define MIU_TEST_AGT_ADDR_HI (0x098) 764 #define MIU_TEST_AGT_WRDATA_LO (0x0a0) 765 #define MIU_TEST_AGT_WRDATA_HI (0x0a4) 766 #define MIU_TEST_AGT_WRDATA(i) (0x0a0+(4*(i))) 767 #define MIU_TEST_AGT_RDDATA_LO (0x0a8) 768 #define MIU_TEST_AGT_RDDATA_HI (0x0ac) 769 #define MIU_TEST_AGT_RDDATA(i) (0x0a8+(4*(i))) 770 #define MIU_TEST_AGT_ADDR_MASK 0xfffffff8 771 #define MIU_TEST_AGT_UPPER_ADDR(off) (0) 772 773 /* MIU_TEST_AGT_CTRL flags. work for SIU as well */ 774 #define MIU_TA_CTL_START 1 775 #define MIU_TA_CTL_ENABLE 2 776 #define MIU_TA_CTL_WRITE 4 777 #define MIU_TA_CTL_BUSY 8 778 779 #define SIU_TEST_AGT_CTRL (0x060) 780 #define SIU_TEST_AGT_ADDR_LO (0x064) 781 #define SIU_TEST_AGT_ADDR_HI (0x078) 782 #define SIU_TEST_AGT_WRDATA_LO (0x068) 783 #define SIU_TEST_AGT_WRDATA_HI (0x06c) 784 #define SIU_TEST_AGT_WRDATA(i) (0x068+(4*(i))) 785 #define SIU_TEST_AGT_RDDATA_LO (0x070) 786 #define SIU_TEST_AGT_RDDATA_HI (0x074) 787 #define SIU_TEST_AGT_RDDATA(i) (0x070+(4*(i))) 788 789 #define SIU_TEST_AGT_ADDR_MASK 0x3ffff8 790 #define SIU_TEST_AGT_UPPER_ADDR(off) ((off)>>22) 791 792 /* XG Link status */ 793 #define XG_LINK_UP 0x10 794 795 796 /* ====================== Configuration Constants ======================== */ 797 #define UNM_NIU_PHY_WAITLEN 200000 /* 200ms delay in each loop */ 798 #define UNM_NIU_PHY_WAITMAX 50 /* 10 seconds before we give up */ 799 #define UNM_NIU_MAX_GBE_PORTS 4 800 #define UNM_NIU_MAX_XG_PORTS 2 801 802 typedef __uint8_t unm_ethernet_macaddr_t[6]; 803 804 #define MIN_CORE_CLK_SPEED 200 805 #define MAX_CORE_CLK_SPEED 400 806 #define ACCEPTABLE_CORE_CLK_RANGE(speed) \ 807 ((speed >= MIN_CORE_CLK_SPEED) && (speed <= MAX_CORE_CLK_SPEED)) 808 809 #define P2_TICKS_PER_SEC 2048 810 #define P2_MIN_TICKS_PER_SEC (P2_TICKS_PER_SEC-10) 811 #define P2_MAX_TICKS_PER_SEC (P2_TICKS_PER_SEC+10) 812 #define CHECK_TICKS_PER_SEC(ticks) \ 813 ((ticks >= P2_MIN_TICKS_PER_SEC) && (ticks <= P2_MAX_TICKS_PER_SEC)) 814 815 /* ============================= 1GbE =============================== */ 816 /* Nibble or Byte mode for phy interface (GbE mode only) */ 817 typedef enum { 818 UNM_NIU_10_100_MB = 0, 819 UNM_NIU_1000_MB 820 } unm_niu_gbe_ifmode_t; 821 822 /* Promiscous mode options (GbE mode only) */ 823 typedef enum { 824 UNM_NIU_PROMISCOUS_MODE = 0, 825 UNM_NIU_NON_PROMISCOUS_MODE 826 } unm_niu_prom_mode_t; 827 828 /* 829 * NIU GB Drop CRC Register 830 */ 831 typedef struct { 832 unm_crbword_t 833 drop_gb0:1, /* 1:drop pkts with bad CRCs, 0:pass them on */ 834 drop_gb1:1, /* 1:drop pkts with bad CRCs, 0:pass them on */ 835 drop_gb2:1, /* 1:drop pkts with bad CRCs, 0:pass them on */ 836 drop_gb3:1, /* 1:drop pkts with bad CRCs, 0:pass them on */ 837 rsvd:28; 838 } unm_niu_gb_drop_crc_t; 839 840 /* 841 * NIU GB GMII Mode Register (applies to GB0, GB1, GB2, GB3) 842 * To change the mode, turn off the existing mode, then turn on the new mode. 843 */ 844 typedef struct { 845 unm_crbword_t 846 gmiimode:1, /* 1:GMII mode, 0:xmit clk taken from SERDES */ 847 rsvd:29; 848 } unm_niu_gb_gmii_mode_t; 849 850 /* 851 * NIU GB MII Mode Register (applies to GB0, GB1, GB2, GB3) 852 * To change the mode, turn off the existing mode, then turn on the new mode. 853 */ 854 typedef struct { 855 unm_crbword_t 856 miimode:1, /* 1:MII mode, 0:xmit clk provided to SERDES */ 857 rsvd:29; 858 } unm_niu_gb_mii_mode_t; 859 860 /* 861 * NIU GB MAC Config Register 0 (applies to GB0, GB1, GB2, GB3) 862 */ 863 typedef struct { 864 unm_crbword_t 865 tx_enable:1, /* 1:enable frame xmit, 0:disable */ 866 tx_synched:1, /* R/O: xmit enable synched to xmit stream */ 867 rx_enable:1, /* 1:enable frame recv, 0:disable */ 868 rx_synched:1, /* R/O: recv enable synched to recv stream */ 869 tx_flowctl:1, /* 1:enable pause frame generation, 0:disable */ 870 rx_flowctl:1, /* 1:act on recv'd pause frames, 0:ignore */ 871 rsvd1:2, 872 loopback:1, /* 1:loop MAC xmits to MAC recvs, 0:normal */ 873 rsvd2:7, 874 tx_reset_pb:1, /* 1:reset frame xmit protocol blk, 0:no-op */ 875 rx_reset_pb:1, /* 1:reset frame recv protocol blk, 0:no-op */ 876 tx_reset_mac:1, /* 1:reset data/ctl multiplexer blk, 0:no-op */ 877 rx_reset_mac:1, /* 1:reset ctl frames & timers blk, 0:no-op */ 878 rsvd3:11, 879 soft_reset:1; /* 1:reset the MAC and the SERDES, 0:no-op */ 880 } unm_niu_gb_mac_config_0_t; 881 882 /* 883 * NIU GB MAC Config Register 1 (applies to GB0, GB1, GB2, GB3) 884 */ 885 typedef struct { 886 unm_crbword_t 887 duplex:1, /* 1:full duplex mode, 0:half duplex */ 888 crc_enable:1, /* 1:append CRC to xmit frames, 0:dont append */ 889 padshort:1, /* 1:pad short frames and add CRC, 0:dont pad */ 890 rsvd1:1, 891 checklength:1, /* 1:check framelen with actual, 0:dont check */ 892 hugeframes:1, /* 1:allow oversize xmit frames, 0:dont allow */ 893 rsvd2:2, 894 intfmode:2, /* 01:nibble (10/100), 10:byte (1000) */ 895 rsvd3:2, 896 preamblelen:4, /* preamble field length in bytes, default 7 */ 897 rsvd4:16; 898 } unm_niu_gb_mac_config_1_t; 899 900 /* 901 * NIU XG Pause Ctl Register 902 */ 903 typedef struct { 904 unm_crbword_t 905 xg0_mask:1, /* 1:disable tx pause frames */ 906 xg0_request:1, /* request single pause frame */ 907 xg0_on_off:1, /* 1:req is pause on, 0:off */ 908 xg1_mask:1, /* 1:disable tx pause frames */ 909 xg1_request:1, /* request single pause frame */ 910 xg1_on_off:1, /* 1:req is pause on, 0:off */ 911 rsvd:26; 912 } unm_niu_xg_pause_ctl_t; 913 914 /* 915 * NIU GBe Pause Ctl Register 916 */ 917 typedef struct { 918 unm_crbword_t 919 gb0_mask:1, /* 1:disable tx pause frames */ 920 gb0_pause_req:1, /* 1: send pause on, 0: send pause off */ 921 gb1_mask:1, /* 1:disable tx pause frames */ 922 gb1_pause_req:1, /* 1: send pause on, 0: send pause off */ 923 gb2_mask:1, /* 1:disable tx pause frames */ 924 gb2_pause_req:1, /* 1: send pause on, 0: send pause off */ 925 gb3_mask:1, /* 1:disable tx pause frames */ 926 gb3_pause_req:1, /* 1: send pause on, 0: send pause off */ 927 rsvd:24; 928 } unm_niu_gb_pause_ctl_t; 929 930 931 /* 932 * NIU XG MAC Config Register 933 */ 934 typedef struct { 935 unm_crbword_t 936 tx_enable:1, /* 1:enable frame xmit, 0:disable */ 937 rsvd1:1, 938 rx_enable:1, /* 1:enable frame recv, 0:disable */ 939 rsvd2:1, 940 soft_reset:1, /* 1:reset the MAC , 0:no-op */ 941 rsvd3:22, 942 xaui_framer_reset:1, 943 xaui_rx_reset:1, 944 xaui_tx_reset:1, 945 xg_ingress_afifo_reset:1, 946 xg_egress_afifo_reset:1; 947 } unm_niu_xg_mac_config_0_t; 948 949 /* 950 * NIU GB MII Mgmt Config Register (applies to GB0, GB1, GB2, GB3) 951 */ 952 typedef struct { 953 unm_crbword_t 954 clockselect:3, /* 0:clk/4, 1:clk/4, 2:clk/6, 3:clk/8 */ 955 /* 4:clk/10, 5:clk/14, 6:clk/20, 7:clk/28 */ 956 rsvd1:1, 957 nopreamble:1, /* 1:suppress preamble generation, 0:normal */ 958 scanauto:1, /* ???? */ 959 rsvd2:25, 960 reset:1; /* 1:reset MII mgmt, 0:no-op */ 961 } unm_niu_gb_mii_mgmt_config_t; 962 963 /* 964 * NIU GB MII Mgmt Command Register (applies to GB0, GB1, GB2, GB3) 965 */ 966 typedef struct { 967 unm_crbword_t 968 read_cycle:1, /* 1:perform single read cycle, 0:no-op */ 969 scan_cycle:1, /* 1:perform continuous read cycles, 0:no-op */ 970 rsvd:30; 971 } unm_niu_gb_mii_mgmt_command_t; 972 973 /* 974 * NIU GB MII Mgmt Address Register (applies to GB0, GB1, GB2, GB3) 975 */ 976 typedef struct { 977 unm_crbword_t 978 reg_addr:5, /* which mgmt register we want to talk to */ 979 rsvd1:3, 980 phy_addr:5, /* which PHY to talk to (0 is reserved) */ 981 rsvd:19; 982 } unm_niu_gb_mii_mgmt_address_t; 983 984 /* 985 * NIU GB MII Mgmt Indicators Register (applies to GB0, GB1, GB2, GB3) 986 * Read-only register. 987 */ 988 typedef struct { 989 unm_crbword_t 990 busy:1, /* 1:performing an MII mgmt cycle, 0:idle */ 991 scanning:1, /* 1:scan operation in progress, 0:idle */ 992 notvalid:1, /* 1:mgmt result data not yet valid, 0:idle */ 993 rsvd:29; 994 } unm_niu_gb_mii_mgmt_indicators_t; 995 996 /* 997 * NIU GB Station Address High Register 998 * NOTE: this value is in network byte order. 999 */ 1000 typedef struct { 1001 unm_crbword_t 1002 address:32; /* station address [47:16] */ 1003 } unm_niu_gb_station_address_high_t; 1004 1005 /* 1006 * NIU GB Station Address Low Register 1007 * NOTE: this value is in network byte order. 1008 */ 1009 typedef struct { 1010 unm_crbword_t 1011 rsvd:16, 1012 address:16; /* station address [15:0] */ 1013 } unm_niu_gb_station_address_low_t; 1014 1015 /* ============================ PHY Definitions ========================== */ 1016 /* 1017 * PHY-Specific MII control/status registers. 1018 */ 1019 typedef enum { 1020 UNM_NIU_GB_MII_MGMT_ADDR_CONTROL = 0, 1021 UNM_NIU_GB_MII_MGMT_ADDR_STATUS = 1, 1022 UNM_NIU_GB_MII_MGMT_ADDR_PHY_ID_0 = 2, 1023 UNM_NIU_GB_MII_MGMT_ADDR_PHY_ID_1 = 3, 1024 UNM_NIU_GB_MII_MGMT_ADDR_AUTONEG = 4, 1025 UNM_NIU_GB_MII_MGMT_ADDR_LNKPART = 5, 1026 UNM_NIU_GB_MII_MGMT_ADDR_AUTONEG_MORE = 6, 1027 UNM_NIU_GB_MII_MGMT_ADDR_NEXTPAGE_XMIT = 7, 1028 UNM_NIU_GB_MII_MGMT_ADDR_LNKPART_NEXTPAGE = 8, 1029 UNM_NIU_GB_MII_MGMT_ADDR_1000BT_CONTROL = 9, 1030 UNM_NIU_GB_MII_MGMT_ADDR_1000BT_STATUS = 10, 1031 UNM_NIU_GB_MII_MGMT_ADDR_EXTENDED_STATUS = 15, 1032 UNM_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL = 16, 1033 UNM_NIU_GB_MII_MGMT_ADDR_PHY_STATUS = 17, 1034 UNM_NIU_GB_MII_MGMT_ADDR_INT_ENABLE = 18, 1035 UNM_NIU_GB_MII_MGMT_ADDR_INT_STATUS = 19, 1036 UNM_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL_MORE = 20, 1037 UNM_NIU_GB_MII_MGMT_ADDR_RECV_ERROR_COUNT = 21, 1038 UNM_NIU_GB_MII_MGMT_ADDR_LED_CONTROL = 24, 1039 UNM_NIU_GB_MII_MGMT_ADDR_LED_OVERRIDE = 25, 1040 UNM_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL_MORE_YET = 26, 1041 UNM_NIU_GB_MII_MGMT_ADDR_PHY_STATUS_MORE = 27 1042 } unm_niu_phy_register_t; 1043 1044 /* 1045 * PHY-Specific Status Register (reg 17). 1046 */ 1047 typedef struct { 1048 unm_crbword_t 1049 jabber:1, /* 1:jabber detected, 0:not */ 1050 polarity:1, /* 1:polarity reversed, 0:normal */ 1051 recvpause:1, /* 1:receive pause enabled, 0:disabled */ 1052 xmitpause:1, /* 1:transmit pause enabled, 0:disabled */ 1053 energydetect:1, /* 1:sleep, 0:active */ 1054 downshift:1, /* 1:downshift, 0:no downshift */ 1055 crossover:1, /* 1:MDIX (crossover), 0:MDI (no crossover) */ 1056 cablelen:3, /* not valid in 10Mb/s mode */ 1057 /* 0:<50m, 1:50-80m, 2:80-110m, 3:110-140m, 4:>140m */ 1058 link:1, /* 1:link up, 0:link down */ 1059 resolved:1, /* 1:speed and duplex resolved, 0:not yet */ 1060 pagercvd:1, /* 1:page received, 0:page not received */ 1061 duplex:1, /* 1:full duplex, 0:half duplex */ 1062 speed:2, /* 0:10Mb/s, 1:100Mb/s, 2:1000Mb/s, 3:rsvd */ 1063 rsvd:16; 1064 } unm_niu_phy_status_t; 1065 1066 /* 1067 * Interrupt Register definition 1068 * This definition applies to registers 18 and 19 (int enable and int status). 1069 */ 1070 typedef struct { 1071 unm_crbword_t 1072 jabber:1, 1073 polarity_changed:1, 1074 reserved:2, 1075 energy_detect:1, 1076 downshift:1, 1077 mdi_xover_changed:1, 1078 fifo_over_underflow:1, 1079 false_carrier:1, 1080 symbol_error:1, 1081 link_status_changed:1, 1082 autoneg_completed:1, 1083 page_received:1, 1084 duplex_changed:1, 1085 speed_changed:1, 1086 autoneg_error:1, 1087 rsvd:16; 1088 } unm_niu_phy_interrupt_t; 1089 1090 /* ============================= 10GbE =============================== */ 1091 /* 1092 * NIU Mode Register. 1093 */ 1094 typedef struct { 1095 unm_crbword_t 1096 enable_fc:1, /* enable FibreChannel */ 1097 enable_ge:1, /* enable 10/100/1000 Ethernet */ 1098 enable_xgb:1, /* enable 10Gb Ethernet */ 1099 rsvd:29; 1100 } unm_niu_control_t; 1101 1102 /* ========================== Interface Functions ======================= */ 1103 1104 /* Generic enable for GbE ports. Will detect the speed of the link. */ 1105 long unm_niu_gbe_init_port(long port); 1106 1107 /* XG Link status */ 1108 #define XG_LINK_UP 0x10 1109 #define XG_LINK_DOWN 0x20 1110 1111 #define XG_LINK_UP_P3 0x1 1112 #define XG_LINK_DOWN_P3 0x2 1113 #define XG_LINK_UNKNOWN_P3 0 1114 1115 #define XG_LINK_STATE_P3_MASK 0xf 1116 #define XG_LINK_STATE_P3(pcifn, val) \ 1117 (((val) >> ((pcifn) * 4)) & XG_LINK_STATE_P3_MASK) 1118 1119 #define MTU_MARGIN 100 1120 1121 #define PF_LINK_SPEED_MHZ 100 1122 #define PF_LINK_SPEED_REG(pcifn) (CRB_PF_LINK_SPEED_1 + (((pcifn)/4)* 4)) 1123 #define PF_LINK_SPEED_MASK 0xff 1124 #define PF_LINK_SPEED_VAL(pcifn, reg) \ 1125 (((reg) >> (8 * ((pcifn) & 0x3))) & PF_LINK_SPEED_MASK) 1126 1127 1128 1129 /* 1130 * Definitions relating to access/control of the CAM RAM 1131 */ 1132 1133 typedef union { 1134 struct { 1135 /* 1136 * =1 if watchdog is active. 1137 * =0 if watchdog is inactive 1138 * This is read-only for anyone 1139 * but the watchdog itself. 1140 */ 1141 unsigned int enabled: 1, 1142 /* 1143 * Set this to 1 to send disable 1144 * request to watchdog . Watchdog 1145 * will complete the shutdown 1146 * process and acknowledge it 1147 * by clearing this bit and the 1148 * "enable" bit. 1149 */ 1150 disable_request: 1, 1151 /* 1152 * Set this to 1 to send enable 1153 * request to watchdog . Watchdog 1154 * will complete the enable 1155 * process and acknowledge it 1156 * by clearing this bit and 1157 * setting the "enable" bit. 1158 */ 1159 enable_request: 1, 1160 unused: 29; 1161 } s1; 1162 unm_crbword_t word; 1163 } dma_watchdog_ctrl_t; 1164 1165 #define UNM_CAM_RAM_BASE (UNM_CRB_CAM + 0x02000) 1166 #define UNM_CAM_RAM(reg) (UNM_CAM_RAM_BASE + (reg)) 1167 1168 #define UNM_PORT_MODE_NONE 0 1169 #define UNM_PORT_MODE_XG 1 1170 #define UNM_PORT_MODE_GB 2 1171 #define UNM_PORT_MODE_802_3_AP 3 1172 #define UNM_PORT_MODE_AUTO_NEG 4 1173 #define UNM_PORT_MODE_AUTO_NEG_1G 5 1174 #define UNM_PORT_MODE_AUTO_NEG_XG 6 1175 #define UNM_PORT_MODE_ADDR (UNM_CAM_RAM(0x24)) 1176 #define UNM_WOL_PORT_MODE (UNM_CAM_RAM(0x198)) 1177 1178 #define UNM_ROM_LOCK_ID (UNM_CAM_RAM(0x100)) 1179 #define UNM_I2C_ROM_LOCK_ID (UNM_CAM_RAM(0x104)) 1180 #define UNM_PHY_LOCK_ID (UNM_CAM_RAM(0x120)) 1181 #define UNM_CRB_WIN_LOCK_ID (UNM_CAM_RAM(0x124)) 1182 #define CAM_RAM_DMA_WATCHDOG_CTRL 0x14 /* See dma_watchdog_ctrl_t */ 1183 #define UNM_EFUSE_CHIP_ID (UNM_CAM_RAM(0x18)) 1184 1185 #define UNM_FW_VERSION_MAJOR (UNM_CAM_RAM(0x150)) 1186 #define UNM_FW_VERSION_MINOR (UNM_CAM_RAM(0x154)) 1187 #define UNM_FW_VERSION_BUILD (UNM_CAM_RAM(0x168)) 1188 #define UNM_FW_VERSION_SUB (UNM_CAM_RAM(0x158)) 1189 #define UNM_TCP_FW_VERSION_MAJOR_ADDR (UNM_CAM_RAM(0x15c)) 1190 #define UNM_TCP_FW_VERSION_MINOR_ADDR (UNM_CAM_RAM(0x160)) 1191 #define UNM_TCP_FW_VERSION_SUB_ADDR (UNM_CAM_RAM(0x164)) 1192 #define UNM_PCIE_REG(reg) (UNM_CRB_PCIE + (reg)) 1193 1194 #define PCIE_DCR (0x00d8) 1195 #define PCIE_DB_DATA2 (0x10070) 1196 #define PCIE_DB_CTRL (0x100a0) 1197 #define PCIE_DB_ADDR (0x100a4) 1198 #define PCIE_DB_DATA (0x100a8) 1199 #define PCIE_IMBUS_CONTROL (0x101b8) 1200 #define PCIE_SETUP_FUNCTION (0x12040) 1201 #define PCIE_SETUP_FUNCTION2 (0x12048) 1202 #define PCIE_TGT_SPLIT_CHICKEN (0x12080) 1203 #define PCIE_CHICKEN3 (0x120c8) 1204 #define PCIE_MAX_MASTER_SPLIT (0x14048) 1205 #define PCIE_MAX_DMA_XFER_SIZE (0x1404c) 1206 1207 #define UNM_WOL_WAKE (UNM_CAM_RAM(0x180)) 1208 #define UNM_WOL_CONFIG_NV (UNM_CAM_RAM(0x184)) 1209 #define UNM_WOL_CONFIG (UNM_CAM_RAM(0x188)) 1210 #define UNM_PRE_WOL_RX_ENABLE (UNM_CAM_RAM(0x18c)) 1211 1212 /* 1213 * Following define address space withing PCIX CRB space to talk with 1214 * devices on the storage side PCI bus. 1215 */ 1216 #define PCIX_PS_MEM_SPACE (0x90000) 1217 1218 #define UNM_PCIX_PH_REG(reg) (UNM_CRB_PCIE + (reg)) 1219 1220 /* 1221 * Configuration registers. These are the same offsets on both host and 1222 * storage side PCI blocks. 1223 */ 1224 /* Used for PS PCI Memory access */ 1225 #define PCIX_PS_OP_ADDR_LO (0x10000) 1226 #define PCIX_PS_OP_ADDR_HI (0x10004) /* via CRB (PS side only) */ 1227 1228 #define PCIX_MS_WINDOW (0x10204) /* UNUSED */ 1229 1230 #define PCIX_CRB_WINDOW (0x10210) 1231 #define PCIX_CRB_WINDOW_F0 (0x10210) 1232 #define PCIX_CRB_WINDOW_F1 (0x10230) 1233 #define PCIX_CRB_WINDOW_F2 (0x10250) 1234 #define PCIX_CRB_WINDOW_F3 (0x10270) 1235 #define PCIX_CRB_WINDOW_F4 (0x102ac) 1236 #define PCIX_CRB_WINDOW_F5 (0x102bc) 1237 #define PCIX_CRB_WINDOW_F6 (0x102cc) 1238 #define PCIX_CRB_WINDOW_F7 (0x102dc) 1239 #define PCIE_CRB_WINDOW_REG(func) (((func) < 4) ? \ 1240 (PCIX_CRB_WINDOW_F0 + (0x20 * (func))) :\ 1241 (PCIX_CRB_WINDOW_F4 + (0x10 * ((func)-4)))) 1242 1243 #define PCIX_MN_WINDOW (0x10200) 1244 #define PCIX_MN_WINDOW_F0 (0x10200) 1245 #define PCIX_MN_WINDOW_F1 (0x10220) 1246 #define PCIX_MN_WINDOW_F2 (0x10240) 1247 #define PCIX_MN_WINDOW_F3 (0x10260) 1248 #define PCIX_MN_WINDOW_F4 (0x102a0) 1249 #define PCIX_MN_WINDOW_F5 (0x102b0) 1250 #define PCIX_MN_WINDOW_F6 (0x102c0) 1251 #define PCIX_MN_WINDOW_F7 (0x102d0) 1252 #define PCIE_MN_WINDOW_REG(func) (((func) < 4) ? \ 1253 (PCIX_MN_WINDOW_F0 + (0x20 * (func))) :\ 1254 (PCIX_MN_WINDOW_F4 + (0x10 * ((func)-4)))) 1255 1256 #define PCIX_SN_WINDOW (0x10208) 1257 #define PCIX_SN_WINDOW_F0 (0x10208) 1258 #define PCIX_SN_WINDOW_F1 (0x10228) 1259 #define PCIX_SN_WINDOW_F2 (0x10248) 1260 #define PCIX_SN_WINDOW_F3 (0x10268) 1261 #define PCIX_SN_WINDOW_F4 (0x102a8) 1262 #define PCIX_SN_WINDOW_F5 (0x102b8) 1263 #define PCIX_SN_WINDOW_F6 (0x102c8) 1264 #define PCIX_SN_WINDOW_F7 (0x102d8) 1265 #define PCIE_SN_WINDOW_REG(func) (((func) < 4) ? \ 1266 (PCIX_SN_WINDOW_F0 + (0x20 * (func))) :\ 1267 (PCIX_SN_WINDOW_F4 + (0x10 * ((func)-4)))) 1268 1269 #define UNM_PCIX_PS_REG(reg) (UNM_CRB_PCIX_MD + (reg)) 1270 #define UNM_PCIX_PS2_REG(reg) (UNM_CRB_PCIE2 + (reg)) 1271 #define MANAGEMENT_COMMAND_REG (UNM_CRB_PCIE + (4)) 1272 1273 #define UNM_PH_INT_MASK (UNM_CRB_PCIE + PCIX_INT_MASK) 1274 1275 /* 1276 * CRB window register. 1277 */ 1278 typedef struct { 1279 unm_crbword_t rsvd1:25, 1280 addrbit:1, /* bit 25 of CRB address */ 1281 rsvd2:6; 1282 } unm_pcix_crb_window_t; 1283 1284 /* 1285 * Tell which interrupt source we want to operate on. 1286 */ 1287 typedef enum { 1288 UNM_PCIX_INT_SRC_UNDEFINED = 0, 1289 UNM_PCIX_INT_SRC_DMA0, /* DMA engine 0 */ 1290 UNM_PCIX_INT_SRC_DMA1, /* DMA engine 1 */ 1291 UNM_PCIX_INT_SRC_I2Q /* I2Q block */ 1292 } unm_pcix_int_source_t; 1293 1294 typedef enum { 1295 UNM_PCIX_INT_SRC_UNDEFINEDSTATE = 0, 1296 UNM_PCIX_INT_SRC_ALLOW, /* Allow this src to int. the host */ 1297 UNM_PCIX_INT_SRC_MASK /* Mask this src */ 1298 } unm_pcix_int_state_t; 1299 1300 /* 1301 * PCIX Interrupt Mask Register. 1302 */ 1303 typedef struct { 1304 /* 0=DMA0 not masked, 1=masked */ 1305 unm_crbword_t dma0:1, 1306 /* 0=DMA1 not masked, 1=masked */ 1307 dma1:1, 1308 /* 0=I2Q not masked, 1=masked */ 1309 i2q:1, 1310 dma0_err:1, 1311 dma1_err:1, 1312 target_status:1, 1313 mega_err:1, 1314 ps_serr_int:1, 1315 split_discard:1, 1316 io_write_func0:1, 1317 io_write_func1:1, 1318 io_write_func2:1, 1319 io_write_func3:1, 1320 msi_write_func0:1, 1321 msi_write_func1:1, 1322 msi_write_func2:1, 1323 msi_write_func3:1, 1324 rsvd:15; 1325 } unm_pcix_int_mask_t; 1326 1327 int unm_pcix_int_control(unm_pcix_int_source_t src, 1328 unm_pcix_int_state_t state); 1329 1330 #define UNM_SRE_INT_STATUS (UNM_CRB_SRE + 0x00034) 1331 #define UNM_SRE_BUF_CTL (UNM_CRB_SRE + 0x01000) 1332 #define UNM_SRE_PBI_ACTIVE_STATUS (UNM_CRB_SRE + 0x01014) 1333 #define UNM_SRE_SCRATCHPAD (UNM_CRB_SRE + 0x01018) 1334 #define UNM_SRE_L1RE_CTL (UNM_CRB_SRE + 0x03000) 1335 #define UNM_SRE_L2RE_CTL (UNM_CRB_SRE + 0x05000) 1336 1337 // These are offset to a particular Peg's CRB base address 1338 #define CRB_REG_EX_PC 0x3c 1339 1340 #define PEG_NETWORK_BASE(N) (UNM_CRB_PEG_NET_0 + (((N)&3) << 20)) 1341 1342 /* 1343 * Definitions relating to enqueue/dequeue/control of the Queue Operations 1344 * to either the Primary Queue Manager or the Secondary Queue Manager. 1345 */ 1346 1347 /* 1348 * General configuration constants. 1349 */ 1350 #define UNM_QM_MAX_SIDE 1 1351 1352 /* 1353 * Data movement registers (differs based on processor). 1354 */ 1355 #define UNM_QM_COMMAND (UNM_PCI_CAMQM + 0x00000) 1356 #define UNM_QM_STATUS (UNM_PCI_CAMQM + 0x00008) 1357 #define UNM_QM_DATA(W, P) (UNM_PCI_CAMQM + 0x00010 + \ 1358 (W)*sizeof (unm_dataword_t)) 1359 #define UNM_QM_REPLY(W, P)(UNM_PCI_CAMQM + 0x00050 + \ 1360 (W)*sizeof (unm_dataword_t)) 1361 1362 /* 1363 * Control commands to the QM block. 1364 */ 1365 #define UNM_QM_CMD_READ 0x0 /* interpret "readop" field */ 1366 1367 /* 1368 * Platform-specific fields in the queue command word 1369 */ 1370 #define UNM_QM_CMD_SIDE 0 1371 /* Casper and Peg need this bit. PCI interface does not */ 1372 #define UNM_QM_CMD_START 1 1373 1374 1375 /* 1376 * Pegasus has two QM ports. This is the default one to use (unless 1377 * QM async interface is called explicitly with other port). 1378 */ 1379 #define UNM_QM_DEFAULT_PORT 0 1380 1381 /* 1382 * Status result returned to caller of unm_qm_request_status() 1383 */ 1384 typedef enum { 1385 /* error in HW - most likely PCI bug. retry */ 1386 unm_qm_status_unknown = 0, 1387 unm_qm_status_done, /* done with last command */ 1388 unm_qm_status_busy, /* busy */ 1389 unm_qm_status_notfound, /* queue is empty to read or full to write */ 1390 unm_qm_status_error /* error (e.g. timeout) encountered */ 1391 } unm_qm_result_t; 1392 1393 /* 1394 * Definitions relating to access/control of the I2Q h/w block. 1395 */ 1396 /* 1397 * Configuration registers. 1398 */ 1399 #define UNM_I2Q_CONFIG (UNM_CRB_I2Q + 0x00000) 1400 #define UNM_I2Q_ENA_PCI_LO (UNM_CRB_I2Q + 0x00010) 1401 #define UNM_I2Q_ENA_PCI_HI (UNM_CRB_I2Q + 0x00014) 1402 #define UNM_I2Q_ENA_CASPER_LO (UNM_CRB_I2Q + 0x00018) 1403 #define UNM_I2Q_ENA_CASPER_HI (UNM_CRB_I2Q + 0x0001c) 1404 #define UNM_I2Q_ENA_QM_LO (UNM_CRB_I2Q + 0x00020) 1405 #define UNM_I2Q_ENA_QM_HI (UNM_CRB_I2Q + 0x00024) 1406 #define UNM_I2Q_CLR_PCI_LO (UNM_CRB_I2Q + 0x00030) 1407 #define UNM_I2Q_CLR_PCI_HI (UNM_CRB_I2Q + 0x00034) 1408 #define UNM_I2Q_CLR_CASPER_LO (UNM_CRB_I2Q + 0x00038) 1409 #define UNM_I2Q_CLR_CASPER_HI (UNM_CRB_I2Q + 0x0003c) 1410 #define UNM_I2Q_MSG_HDR_LO(I) (UNM_CRB_I2Q + 0x00100 + (I)*0x8) 1411 #define UNM_I2Q_MSG_HDR_HI(I) (UNM_CRB_I2Q + 0x00104 + (I)*0x8) 1412 1413 /* 1414 * List the bit positions in the registers of the interrupt sources. 1415 */ 1416 typedef enum { 1417 UNM_I2Q_SRC_PCI32 = 0, /* PCI32 block */ 1418 UNM_I2Q_SRC_PCIE = 1, /* PCI-Express block */ 1419 UNM_I2Q_SRC_CASPER = 2, /* Casper */ 1420 UNM_I2Q_SRC_CASPER_ERR = 3, /* Casper error */ 1421 UNM_I2Q_SRC_PEG_0 = 4, /* Peg 0 */ 1422 UNM_I2Q_SRC_PEG_1 = 5, /* Peg 1 */ 1423 UNM_I2Q_SRC_PEG_2 = 6, /* Peg 2 */ 1424 UNM_I2Q_SRC_PEG_3 = 7, /* Peg 3 */ 1425 UNM_I2Q_SRC_PEG_DCACHE = 8, /* Peg Data cache */ 1426 UNM_I2Q_SRC_PEG_ICACHE = 9, /* Peg Instruction cache */ 1427 UNM_I2Q_SRC_DMA0 = 10, /* DMA engine 0 */ 1428 UNM_I2Q_SRC_DMA1 = 11, /* DMA engine 1 */ 1429 UNM_I2Q_SRC_DMA2 = 12, /* DMA engine 2 */ 1430 NM_I2Q_SRC_DMA3 = 13, /* DMA engine 3 */ 1431 UNM_I2Q_SRC_LPC = 14, /* */ 1432 UNM_I2Q_SRC_SMB = 15, /* */ 1433 UNM_I2Q_SRC_TIMER = 16, /* One of the global timers */ 1434 UNM_I2Q_SRC_SQG0 = 17, /* SQM SQG0 empty->non-empty */ 1435 UNM_I2Q_SRC_SQG1 = 18, /* SQM SQG1 empty->non-empty */ 1436 UNM_I2Q_SRC_SQG2 = 19, /* SQM SQG2 empty->non-empty */ 1437 UNM_I2Q_SRC_SQG3 = 20, /* SQM SQG3 empty->non-empty */ 1438 UNM_I2Q_SRC_SQG0_LW = 21, /* SQM SQG0 low on free buffers */ 1439 UNM_I2Q_SRC_SQG1_LW = 22, /* SQM SQG1 low on free buffers */ 1440 UNM_I2Q_SRC_SQG2_LW = 23, /* SQM SQG2 low on free buffers */ 1441 UNM_I2Q_SRC_SQG3_LW = 24, /* SQM SQG3 low on free buffers */ 1442 UNM_I2Q_SRC_PQM_0 = 25, /* PQM group 0 */ 1443 UNM_I2Q_SRC_PQM_1 = 26, /* PQM group 1 */ 1444 UNM_I2Q_SRC_PQM_2 = 27, /* PQM group 2 */ 1445 UNM_I2Q_SRC_PQM_3 = 28, /* PQM group 3 */ 1446 /* [29:31] reserved */ 1447 UNM_I2Q_SRC_SW_0 = 32, /* SW INT 0 */ 1448 UNM_I2Q_SRC_SW_1 = 33, /* SW INT 1 */ 1449 UNM_I2Q_SRC_SW_2 = 34, /* SW INT 2 */ 1450 UNM_I2Q_SRC_SW_3 = 35, /* SW INT 3 */ 1451 UNM_I2Q_SRC_SW_4 = 36, /* SW INT 4 */ 1452 UNM_I2Q_SRC_SW_5 = 37, /* SW INT 5 */ 1453 UNM_I2Q_SRC_SW_6 = 38, /* SW INT 6 */ 1454 UNM_I2Q_SRC_SW_7 = 39, /* SW INT 7 */ 1455 UNM_I2Q_SRC_SRE_EPG = 40, /* SRE/EPG aggregate interrupt */ 1456 UNM_I2Q_SRC_XDMA = 41, /* XDMA engine */ 1457 UNM_I2Q_SRC_MN = 42, /* DDR interface unit */ 1458 UNM_I2Q_SRC_NIU = 43, /* Network interface unit */ 1459 UNM_I2Q_SRC_SN = 44, /* QDR interface unit */ 1460 UNM_I2Q_SRC_CAM = 45, /* CAM */ 1461 UNM_I2Q_SRC_EXT1 = 46, /* External 1 */ 1462 UNM_I2Q_SRC_EXT2 = 47, /* External 2 */ 1463 /* [48:63] reserved */ 1464 UNM_I2Q_SRC_MAX = 47, /* max used interrupt line */ 1465 UNM_I2Q_SRC_MAX_LO = 32, /* max bits in "lo" register */ 1466 } unm_i2q_source_t; 1467 1468 /* 1469 * Interrupt Source Enable/Clear registers for the I2Q. 1470 */ 1471 typedef struct { 1472 unm_crbword_t source:32; /* int enable/status bits */ 1473 } unm_i2q_source_lo_t; 1474 1475 typedef struct { 1476 unm_crbword_t source:16, /* int enable/status bits */ 1477 rsvd:16; 1478 } unm_i2q_source_hi_t; 1479 1480 /* 1481 * List the possible interrupt sources and the 1482 * control operations to be performed for each. 1483 */ 1484 typedef enum { 1485 UNM_I2Q_CTL_SRCUNKNOWN = 0, /* undefined */ 1486 UNM_I2Q_CTL_PCI, /* PCI block */ 1487 UNM_I2Q_CTL_CASPER, /* Casper */ 1488 UNM_I2Q_CTL_QM /* Queue Manager */ 1489 } unm_i2q_ctl_src_t; 1490 1491 typedef enum { 1492 UNM_I2Q_CTL_OPUNKNOWN = 0, /* undefined */ 1493 UNM_I2Q_CTL_ADD, /* add int'ing for that source */ 1494 UNM_I2Q_CTL_DEL /* stop int'ing for that source */ 1495 } unm_i2q_ctl_op_t; 1496 1497 /* 1498 * Definitions relating to access/control of the Secondary Queue Manager 1499 * h/w block. 1500 */ 1501 /* 1502 * Configuration registers. 1503 */ 1504 #define UNM_SQM_BASE(G) \ 1505 ((G) == 0 ? UNM_CRB_SQM_NET_0 : \ 1506 ((G) == 1 ? UNM_CRB_SQM_NET_1 : \ 1507 ((G) == 2 ? UNM_CRB_SQM_NET_2 : UNM_CRB_SQM_NET_3))) 1508 1509 #define UNM_SQM_INT_ENABLE(G) (UNM_SQM_BASE(G) + 0x00018) 1510 #define UNM_SQM_INT_STATUS(G) (UNM_SQM_BASE(G) + 0x0001c) 1511 #define UNN_SQM_SCRATCHPAD(G) (UNM_SQM_BASE(G) + 0x01000) 1512 1513 #define UNM_SQM_MAX_GRP 4 /* num groups per side */ 1514 #define UNM_SQM_MAX_SUBQ 16 /* num Q's per type-0 group */ 1515 #define UNM_SQM_MAX_SUBGRP 4 /* subgrps per type-1 group */ 1516 1517 #define UNM_SQM_MAX_TYPE_1_NUM (256*1024) 1518 1519 /* 1520 * Interrupt enables and interrupt status for all 16 queues in a group. 1521 */ 1522 typedef struct { 1523 unm_crbword_t queues:16, /* enable/status: 0x1=Q0, 0x8000=Q15 */ 1524 rsvd:16; 1525 } unm_sqm_int_enstat_t; 1526 1527 /* 1528 * Control operation for an SQM Group interrupt. 1529 */ 1530 typedef enum { 1531 UNM_SQM_INTOP_OPUNKNOWN = 0, /* undefined */ 1532 UNM_SQM_INTOP_GET, /* return all bits for that group */ 1533 UNM_SQM_INTOP_SET, /* assign all bits for that group */ 1534 UNM_SQM_INTOP_ADD, /* set one bit for that group */ 1535 UNM_SQM_INTOP_DEL /* clear one bit for that group */ 1536 } unm_sqm_int_op_t; 1537 typedef enum { 1538 UNM_SQM_INTARG_ARGUNKNOWN = 0, /* undefined */ 1539 UNM_SQM_INTARG_ENABLE, /* affect the 'enable' register */ 1540 UNM_SQM_INTARG_STATUS /* affect the 'status' register */ 1541 } unm_sqm_int_arg_t; 1542 1543 int unm_sqm_int_control(unm_sqm_int_op_t op, unm_sqm_int_arg_t arg, 1544 int side, int group, int queue, int *image); 1545 1546 1547 int unm_crb_read(unsigned long off, void *data); 1548 native_t unm_crb_read_val(unsigned long off); 1549 int unm_crb_write(unsigned long off, void *data); 1550 int unm_crb_writelit(unsigned long off, int data); 1551 int unm_imb_read(unsigned long off, void *data); 1552 int unm_imb_write(unsigned long off, void *data); 1553 int unm_imb_writelit64(unsigned long off, __uint64_t data); 1554 1555 unsigned long unm_xport_lock(void); 1556 void unm_xport_unlock(unsigned long); 1557 1558 #define UNM_CRB_READ_VAL(ADDR) unm_crb_read_val((ADDR)) 1559 #define UNM_CRB_READ(ADDR, VALUE) unm_crb_read((ADDR), (unm_crbword_t *)(VALUE)) 1560 #define UNM_CRB_READ_CHECK(ADDR, VALUE) \ 1561 do { \ 1562 if (unm_crb_read(ADDR, VALUE)) \ 1563 return (-1); \ 1564 } while (0) 1565 #define UNM_CRB_WRITE_CHECK(ADDR, VALUE) \ 1566 do { \ 1567 if (unm_crb_write(ADDR, VALUE)) \ 1568 return (-1); \ 1569 } while (0) 1570 #define UNM_CRB_WRITELIT(ADDR, VALUE) \ 1571 do { \ 1572 unm_crb_writelit(ADDR, VALUE); \ 1573 } while (0) 1574 #define UNM_CRB_WRITE(ADDR, VALUE) \ 1575 do { \ 1576 unm_crb_write(ADDR, VALUE); \ 1577 } while (0) 1578 #define UNM_CRB_WRITELIT_CHECK(ADDR, VALUE) \ 1579 do { \ 1580 if (unm_crb_writelit(ADDR, VALUE)) \ 1581 return (-1); \ 1582 } while (0) 1583 1584 #define UNM_IMB_READ_CHECK(ADDR, VALUE) \ 1585 do { \ 1586 if (unm_imb_read(ADDR, VALUE)) \ 1587 return (-1); \ 1588 } while (0) 1589 #define UNM_IMB_WRITE_CHECK(ADDR, VALUE) \ 1590 do { \ 1591 if (unm_imb_write(ADDR, VALUE)) \ 1592 return (-1); \ 1593 } while (0) 1594 #define UNM_IMB_WRITELIT_CHECK(ADDR, VALUE) \ 1595 do { \ 1596 if (unm_imb_writelit64(ADDR, VALUE)) \ 1597 return (-1); \ 1598 } while (0) 1599 1600 /* 1601 * Configuration registers. 1602 */ 1603 #ifdef PCIX 1604 #define UNM_DMA_BASE(U) (UNM_CRB_PCIX_HOST + 0x20000 + ((U)<<16)) 1605 #else 1606 #define UNM_DMA_BASE(U) (UNM_CRB_PCIX_MD + 0x20000 + ((U)<<16)) 1607 #endif 1608 #define UNM_DMA_COMMAND(U) (UNM_DMA_BASE(U) + 0x00008) 1609 1610 1611 #define PCIE_SEM2_LOCK (0x1c010) /* Flash lock */ 1612 #define PCIE_SEM2_UNLOCK (0x1c014) /* Flash unlock */ 1613 #define PCIE_SEM3_LOCK (0x1c018) /* Phy lock */ 1614 #define PCIE_SEM3_UNLOCK (0x1c01c) /* Phy unlock */ 1615 #define PCIE_SEM4_LOCK (0x1c020) /* I2C lock */ 1616 #define PCIE_SEM4_UNLOCK (0x1c024) /* I2C unlock */ 1617 #define PCIE_SEM5_LOCK (0x1c028) /* API lock */ 1618 #define PCIE_SEM5_UNLOCK (0x1c02c) /* API unlock */ 1619 #define PCIE_SEM6_LOCK (0x1c030) /* sw lock */ 1620 #define PCIE_SEM6_UNLOCK (0x1c034) /* sw unlock */ 1621 #define PCIE_SEM7_LOCK (0x1c038) /* crb win lock */ 1622 #define PCIE_SEM7_UNLOCK (0x1c03c) /* crbwin unlock */ 1623 1624 1625 #define PCIE_PS_STRAP_RESET (0x18000) 1626 1627 #define M25P_INSTR_WREN 0x06 1628 #define M25P_INSTR_RDSR 0x05 1629 #define M25P_INSTR_PP 0x02 1630 #define M25P_INSTR_SE 0xd8 1631 #define CAM_RAM_P2I_ENABLE 0xc 1632 #define CAM_RAM_P2D_ENABLE 0x8 1633 #define PCIX_IMBTAG (0x18004) 1634 #define UNM_MAC_ADDR_CNTL_REG (UNM_CRB_NIU + 0x1000) 1635 1636 #define UNM_MULTICAST_ADDR_HI_0 (UNM_CRB_NIU + 0x1010) 1637 #define UNM_MULTICAST_ADDR_HI_1 (UNM_CRB_NIU + 0x1014) 1638 #define UNM_MULTICAST_ADDR_HI_2 (UNM_CRB_NIU + 0x1018) 1639 #define UNM_MULTICAST_ADDR_HI_3 (UNM_CRB_NIU + 0x101c) 1640 1641 #define M_UNICAST_ADDR_BASE (UNM_CRB_NIU + 0x1080) 1642 1643 #define UNM_UNICAST_ADDR_LO_0_0 (UNM_CRB_NIU + 0x1080) // port 0 1644 #define UNM_UNICAST_ADDR_HI_0_0 (UNM_CRB_NIU + 0x1084) 1645 #define UNM_UNICAST_ADDR_LO_0_1 (UNM_CRB_NIU + 0x1088) 1646 #define UNM_UNICAST_ADDR_HI_0_1 (UNM_CRB_NIU + 0x108c) 1647 #define UNM_UNICAST_ADDR_LO_0_2 (UNM_CRB_NIU + 0x1090) 1648 #define UNM_UNICAST_ADDR_HI_0_2 (UNM_CRB_NIU + 0x1084) 1649 #define UNM_UNICAST_ADDR_LO_0_3 (UNM_CRB_NIU + 0x1098) 1650 #define UNM_UNICAST_ADDR_HI_0_3 (UNM_CRB_NIU + 0x109c) 1651 1652 #define UNM_UNICAST_ADDR_LO_1_0 (UNM_CRB_NIU + 0x10a0) 1653 #define UNM_UNICAST_ADDR_HI_1_0 (UNM_CRB_NIU + 0x10a4) 1654 #define UNM_UNICAST_ADDR_LO_1_1 (UNM_CRB_NIU + 0x10a8) 1655 #define UNM_UNICAST_ADDR_HI_1_1 (UNM_CRB_NIU + 0x10ac) 1656 #define UNM_UNICAST_ADDR_LO_1_2 (UNM_CRB_NIU + 0x10b0) 1657 #define UNM_UNICAST_ADDR_HI_1_2 (UNM_CRB_NIU + 0x10b4) 1658 #define UNM_UNICAST_ADDR_LO_1_3 (UNM_CRB_NIU + 0x10b8) 1659 #define UNM_UNICAST_ADDR_HI_1_3 (UNM_CRB_NIU + 0x10bc) 1660 1661 #define UNM_UNICAST_ADDR_LO_2_0 (UNM_CRB_NIU + 0x10c0) 1662 #define UNM_UNICAST_ADDR_HI_2_0 (UNM_CRB_NIU + 0x10c4) 1663 #define UNM_UNICAST_ADDR_LO_2_1 (UNM_CRB_NIU + 0x10c8) 1664 #define UNM_UNICAST_ADDR_HI_2_1 (UNM_CRB_NIU + 0x10cc) 1665 #define UNM_UNICAST_ADDR_LO_2_2 (UNM_CRB_NIU + 0x10d0) 1666 #define UNM_UNICAST_ADDR_HI_2_2 (UNM_CRB_NIU + 0x10d4) 1667 #define UNM_UNICAST_ADDR_LO_2_3 (UNM_CRB_NIU + 0x10d8) 1668 #define UNM_UNICAST_ADDR_HI_2_3 (UNM_CRB_NIU + 0x10dc) 1669 1670 #define UNM_UNICAST_ADDR_LO_3_0 (UNM_CRB_NIU + 0x10e0) 1671 #define UNM_UNICAST_ADDR_HI_3_0 (UNM_CRB_NIU + 0x10e4) 1672 #define UNM_UNICAST_ADDR_LO_3_1 (UNM_CRB_NIU + 0x10e8) 1673 #define UNM_UNICAST_ADDR_HI_3_1 (UNM_CRB_NIU + 0x10ec) 1674 #define UNM_UNICAST_ADDR_LO_3_2 (UNM_CRB_NIU + 0x10f0) 1675 #define UNM_UNICAST_ADDR_HI_3_2 (UNM_CRB_NIU + 0x10f4) 1676 #define UNM_UNICAST_ADDR_LO_3_3 (UNM_CRB_NIU + 0x10f8) 1677 #define UNM_UNICAST_ADDR_HI_3_3 (UNM_CRB_NIU + 0x10fc) 1678 1679 #define UNM_MULTICAST_ADDR_BASE (UNM_CRB_NIU + 0x1100) 1680 1681 // BASE ADDRESS FOR POOL/PORT 0 1682 #define UNM_MULTICAST_ADDR_LO_0 (UNM_CRB_NIU + 0x1100) 1683 // FOR PORT 1 1684 #define UNM_MULTICAST_ADDR_LO_1 (UNM_CRB_NIU + 0x1180) 1685 // FOR PORT 2 1686 #define UNM_MULTICAST_ADDR_LO_2 (UNM_CRB_NIU + 0x1200) 1687 // PORT 3 1688 #define UNM_MULTICAST_ADDR_LO_3 (UNM_CRB_NIU + 0x1280) 1689 1690 #define PHAN_VENDOR_ID 0x4040 1691 1692 #define CAM_RAM_PEG_ENABLES 0x4 1693 1694 /* 1695 * The PCI VendorID and DeviceID for our board. 1696 */ 1697 #define PCI_VENDOR_ID_NX 0x4040 1698 #define PCI_DEVICE_ID_NX_XG 0x0001 1699 #define PCI_DEVICE_ID_NX_CX4 0x0002 1700 #define PCI_DEVICE_ID_NX_QG 0x0003 1701 #define PCI_DEVICE_ID_NX_IMEZ 0x0004 1702 #define PCI_DEVICE_ID_NX_HMEZ 0x0005 1703 #define PCI_DEVICE_ID_NX_IMEZ_DUP 0x0024 1704 #define PCI_DEVICE_ID_NX_HMEZ_DUP 0x0025 1705 #define PCI_DEVICE_ID_NX_P3_XG 0x0100 1706 1707 /* 1708 * Time base tick control registers (global and per-flow). 1709 */ 1710 1711 typedef struct { 1712 /* half period of time cycle */ 1713 /* global: in units of core clock */ 1714 /* per-flow: in units of global ticks */ 1715 unm_crbword_t count:16, 1716 rsvd:15, 1717 enable:1; /* 0=disable, 1=enable */ 1718 } unm_timer_tickctl_t; 1719 1720 1721 typedef struct 1722 { 1723 unm_crbword_t 1724 id_pool_0:2, 1725 enable_xtnd_0:1, 1726 rsvd1:1, 1727 id_pool_1:2, 1728 enable_xtnd_1:1, 1729 rsvd2:1, 1730 id_pool_2:2, 1731 enable_xtnd_2:1, 1732 rsvd3:1, 1733 id_pool_3:2, 1734 enable_xtnd_3:1, 1735 rsvd4:9, 1736 mode_select:2, 1737 rsvd5:2, 1738 enable_pool:4; 1739 } unm_mac_addr_cntl_t; 1740 1741 typedef struct { 1742 unm_crbword_t start:1, 1743 enable:1, 1744 command:1, 1745 busy:1, 1746 rsvd:28; 1747 } unm_miu_test_agt_ctrl_t; 1748 1749 #define UNM_MIU_TEST_AGENT_CMD_READ 0 1750 #define UNM_MIU_TEST_AGENT_CMD_WRITE 1 1751 #define UNM_MIU_TEST_AGENT_BUSY 1 1752 #define UNM_MIU_TEST_AGENT_ENABLE 1 1753 #define UNM_MIU_TEST_AGENT_START 1 1754 1755 #define UNM_MIU_MN_CONTROL (UNM_CRB_DDR_NET + MIU_CONTROL) 1756 #define UNM_MIU_MN_TAG (UNM_CRB_DDR_NET + MIU_TAG) 1757 #define UNM_MIU_MN_TEST_AGT_ADDR_LO (UNM_CRB_DDR_NET + MIU_TEST_AGT_ADDR_LO) 1758 #define UNM_MIU_MN_TEST_AGT_ADDR_HI (UNM_CRB_DDR_NET + MIU_TEST_AGT_ADDR_HI) 1759 #define UNM_MIU_MN_TEST_AGT_WRDATA_LO (UNM_CRB_DDR_NET + MIU_TEST_AGT_WRDATA_LO) 1760 #define UNM_MIU_MN_TEST_AGT_WRDATA_HI (UNM_CRB_DDR_NET + MIU_TEST_AGT_WRDATA_HI) 1761 #define UNM_MIU_MN_TEST_AGT_CTRL (UNM_CRB_DDR_NET + MIU_TEST_AGT_CTRL) 1762 #define UNM_MIU_MN_TEST_AGT_RDDATA_LO (UNM_CRB_DDR_NET + MIU_TEST_AGT_RDDATA_LO) 1763 #define UNM_MIU_MN_TEST_AGT_RDDATA_HI (UNM_CRB_DDR_NET + MIU_TEST_AGT_RDDATA_HI) 1764 1765 #define UNM_SIU_SN_TEST_AGT_ADDR_LO (UNM_CRB_QDR_NET + SIU_TEST_AGT_ADDR_LO) 1766 #define UNM_SIU_SN_TEST_AGT_ADDR_HI (UNM_CRB_QDR_NET + SIU_TEST_AGT_ADDR_HI) 1767 #define UNM_SIU_SN_TEST_AGT_WRDATA_LO (UNM_CRB_QDR_NET + SIU_TEST_AGT_WRDATA_LO) 1768 #define UNM_SIU_SN_TEST_AGT_WRDATA_HI (UNM_CRB_QDR_NET + SIU_TEST_AGT_WRDATA_HI) 1769 #define UNM_SIU_SN_TEST_AGT_CTRL (UNM_CRB_QDR_NET + SIU_TEST_AGT_CTRL) 1770 #define UNM_SIU_SN_TEST_AGT_RDDATA_LO (UNM_CRB_QDR_NET + SIU_TEST_AGT_RDDATA_LO) 1771 #define UNM_SIU_SN_TEST_AGT_RDDATA_HI (UNM_CRB_QDR_NET + SIU_TEST_AGT_RDDATA_HI) 1772 1773 #define NX_IS_SYSTEM_CUT_THROUGH(MIU_CTRL) (((MIU_CTRL) & 0x4) ? 1 : 0) 1774 #define NX_SET_SYSTEM_LEGACY(MIU_CTRL) {(MIU_CTRL) &= ~0x4; } 1775 #define NX_SET_SYSTEM_CUT_THROUGH(MIU_CTRL) {(MIU_CTRL) |= 0x4; } 1776 1777 #endif /* __UNM_INC_H */ 1778